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-rw-r--r--arch/arm/plat-mxc/include/mach/common.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S7
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h27
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/io.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h283
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h256
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h2
16 files changed, 52 insertions, 626 deletions
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a22ebe11a60..da7991832af 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -23,7 +23,6 @@ extern void mx35_map_io(void);
23extern void mx50_map_io(void); 23extern void mx50_map_io(void);
24extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void); 25extern void mx53_map_io(void);
26extern void mxc91231_map_io(void);
27extern void imx1_init_early(void); 26extern void imx1_init_early(void);
28extern void imx21_init_early(void); 27extern void imx21_init_early(void);
29extern void imx25_init_early(void); 28extern void imx25_init_early(void);
@@ -33,7 +32,6 @@ extern void imx35_init_early(void);
33extern void imx50_init_early(void); 32extern void imx50_init_early(void);
34extern void imx51_init_early(void); 33extern void imx51_init_early(void);
35extern void imx53_init_early(void); 34extern void imx53_init_early(void);
36extern void mxc91231_init_early(void);
37extern void mxc_init_irq(void __iomem *); 35extern void mxc_init_irq(void __iomem *);
38extern void tzic_init_irq(void __iomem *); 36extern void tzic_init_irq(void __iomem *);
39extern void mx1_init_irq(void); 37extern void mx1_init_irq(void);
@@ -45,7 +43,6 @@ extern void mx35_init_irq(void);
45extern void mx50_init_irq(void); 43extern void mx50_init_irq(void);
46extern void mx51_init_irq(void); 44extern void mx51_init_irq(void);
47extern void mx53_init_irq(void); 45extern void mx53_init_irq(void);
48extern void mxc91231_init_irq(void);
49extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 46extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
50extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 47extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
51extern int mx1_clocks_init(unsigned long fref); 48extern int mx1_clocks_init(unsigned long fref);
@@ -58,14 +55,11 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
58 unsigned long ckih1, unsigned long ckih2); 55 unsigned long ckih1, unsigned long ckih2);
59extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 56extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
60 unsigned long ckih1, unsigned long ckih2); 57 unsigned long ckih1, unsigned long ckih2);
61extern int mxc91231_clocks_init(unsigned long fref);
62extern int mxc_register_gpios(void); 58extern int mxc_register_gpios(void);
63extern int mxc_register_device(struct platform_device *pdev, void *data); 59extern int mxc_register_device(struct platform_device *pdev, void *data);
64extern void mxc_set_cpu_type(unsigned int type); 60extern void mxc_set_cpu_type(unsigned int type);
65extern void mxc_arch_reset_init(void __iomem *); 61extern void mxc_arch_reset_init(void __iomem *);
66extern void mxc91231_power_off(void);
67extern void mxc91231_arch_reset(int, const char *);
68extern void mxc91231_prepare_idle(void);
69extern void mx51_efikamx_reset(void); 62extern void mx51_efikamx_reset(void);
70extern int mx53_revision(void); 63extern int mx53_revision(void);
64extern int mx53_display_revision(void);
71#endif 65#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 3b3a37c25c5..8e8d175e507 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,13 +44,6 @@
44#define UART_PADDR MX51_UART1_BASE_ADDR 44#define UART_PADDR MX51_UART1_BASE_ADDR
45#endif 45#endif
46 46
47#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
50#endif
51#define UART_PADDR MXC91231_UART2_BASE_ADDR
52#endif
53
54#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) 47#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
55 48
56 .macro addruart, rp, rv 49 .macro addruart, rp, rv
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8658c9caa65..fa8477337f9 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -166,6 +166,24 @@ struct platform_device *__init imx_add_imx_udc(
166 const struct imx_imx_udc_data *data, 166 const struct imx_imx_udc_data *data,
167 const struct imxusb_platform_data *pdata); 167 const struct imxusb_platform_data *pdata);
168 168
169#include <mach/ipu.h>
170#include <mach/mx3fb.h>
171#include <mach/mx3_camera.h>
172struct imx_ipu_core_data {
173 resource_size_t iobase;
174 resource_size_t synirq;
175 resource_size_t errirq;
176};
177struct platform_device *__init imx_add_ipu_core(
178 const struct imx_ipu_core_data *data,
179 const struct ipu_platform_data *pdata);
180struct platform_device *__init imx_alloc_mx3_camera(
181 const struct imx_ipu_core_data *data,
182 const struct mx3_camera_pdata *pdata);
183struct platform_device *__init imx_add_mx3_sdc_fb(
184 const struct imx_ipu_core_data *data,
185 struct mx3fb_platform_data *pdata);
186
169#include <mach/mx1_camera.h> 187#include <mach/mx1_camera.h>
170struct imx_mx1_camera_data { 188struct imx_mx1_camera_data {
171 resource_size_t iobase; 189 resource_size_t iobase;
@@ -237,6 +255,15 @@ struct imx_mxc_pwm_data {
237struct platform_device *__init imx_add_mxc_pwm( 255struct platform_device *__init imx_add_mxc_pwm(
238 const struct imx_mxc_pwm_data *data); 256 const struct imx_mxc_pwm_data *data);
239 257
258/* mxc_rtc */
259struct imx_mxc_rtc_data {
260 resource_size_t iobase;
261 resource_size_t irq;
262};
263struct platform_device *__init imx_add_mxc_rtc(
264 const struct imx_mxc_rtc_data *data);
265
266/* mxc_w1 */
240struct imx_mxc_w1_data { 267struct imx_mxc_w1_data {
241 resource_size_t iobase; 268 resource_size_t iobase;
242}; 269};
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 26bb1bab4ae..67d3e2bed06 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -86,15 +86,6 @@
86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
89 * mxc91231:
90 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
91 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
92 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
93 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
94 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
95 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
96 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
97 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
98 */ 89 */
99#define IMX_IO_P2V(x) ( \ 90#define IMX_IO_P2V(x) ( \
100 0xf4000000 + \ 91 0xf4000000 + \
@@ -104,6 +95,8 @@
104 95
105#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) 96#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
106 97
98#include <mach/mxc.h>
99
107#ifdef CONFIG_ARCH_MX5 100#ifdef CONFIG_ARCH_MX5
108#include <mach/mx50.h> 101#include <mach/mx50.h>
109#include <mach/mx51.h> 102#include <mach/mx51.h>
@@ -134,12 +127,6 @@
134# include <mach/mx25.h> 127# include <mach/mx25.h>
135#endif 128#endif
136 129
137#ifdef CONFIG_ARCH_MXC91231
138# include <mach/mxc91231.h>
139#endif
140
141#include <mach/mxc.h>
142
143#define imx_map_entry(soc, name, _type) { \ 130#define imx_map_entry(soc, name, _type) { \
144 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 131 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
145 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ 132 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index b4f2de76946..4347a87d2bb 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,19 +14,26 @@
14/* Allow IO space to be anywhere in the memory */ 14/* Allow IO space to be anywhere in the memory */
15#define IO_SPACE_LIMIT 0xffffffff 15#define IO_SPACE_LIMIT 0xffffffff
16 16
17#ifdef CONFIG_ARCH_MX3 17#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
18#define __arch_ioremap __mx3_ioremap 18#include <mach/hardware.h>
19
20#define __arch_ioremap __imx_ioremap
19#define __arch_iounmap __iounmap 21#define __arch_iounmap __iounmap
20 22
23#define addr_in_module(addr, mod) \
24 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
25
21static inline void __iomem * 26static inline void __iomem *
22__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) 27__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
23{ 28{
24 if (mtype == MT_DEVICE) { 29 if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
25 /* Access all peripherals below 0x80000000 as nonshared device 30 /*
26 * but leave l2cc alone. 31 * Access all peripherals below 0x80000000 as nonshared device
32 * on mx3, but leave l2cc alone. Otherwise cache corruptions
33 * can occur.
27 */ 34 */
28 if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || 35 if (phys_addr < 0x80000000 &&
29 (phys_addr >= 0x30000000 + SZ_1M))) 36 !addr_in_module(phys_addr, MX3x_L2CC))
30 mtype = MT_DEVICE_NONSHARED; 37 mtype = MT_DEVICE_NONSHARED;
31 } 38 }
32 39
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index d7f52c91f82..2e5244de7ff 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -89,13 +89,16 @@
89#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) 89#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
90 90
91#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) 91#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
92#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
92#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) 93#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
93 94
94#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) 95#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
96#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
95#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) 97#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
96#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) 98#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
97 99
98#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) 100#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
101#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
99#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) 102#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
100#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) 103#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
101 104
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
deleted file mode 100644
index bf28df0d58b..00000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_IOMUX_MXC91231_H__
18#define __MACH_IOMUX_MXC91231_H__
19
20/*
21 * various IOMUX output functions
22 */
23
24#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
25#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
26#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
27#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
28#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
29#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
30#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
31#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
32#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
33#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
34#define IOMUX_ICONFIG_FUNC 2 /* used as function */
35#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
36#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
37
38#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
39#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
40#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
41#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
42
43/*
44 * setups a single pin:
45 * - reserves the pin so that it is not claimed by another driver
46 * - setups the iomux according to the configuration
47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
48 */
49int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
50/*
51 * setups mutliple pins
52 * convenient way to call the above function with tables
53 */
54int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
55 const char *label);
56
57/*
58 * releases a single pin:
59 * - make it available for a future use by another driver
60 * - frees the GPIO if the pin was configured as GPIO
61 * - DOES NOT reconfigure the IOMUX in its reset state
62 */
63void mxc_iomux_release_pin(unsigned int pin_mode);
64/*
65 * releases multiple pins
66 * convenvient way to call the above function with tables
67 */
68void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
69
70#define MUX_SIDE_AP (0)
71#define MUX_SIDE_SP (1)
72
73#define MUX_SIDE_SHIFT (26)
74#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
75
76#define MUX_GPIO_PORT_SHIFT (23)
77#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
78
79#define MUX_GPIO_PIN_SHIFT (20)
80#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
81
82#define MUX_REG_SHIFT (15)
83#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
84
85#define MUX_FIELD_SHIFT (13)
86#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
87
88#define MUX_PADGRP_SHIFT (8)
89#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
90
91#define MUX_PIN_MASK (0xffffff << 8)
92
93#define GPIO_PORT_MAX (3)
94
95#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
96 (((side) << MUX_SIDE_SHIFT) | \
97 (gport << MUX_GPIO_PORT_SHIFT) | \
98 ((gpin) << MUX_GPIO_PIN_SHIFT) | \
99 ((ctlreg) << MUX_REG_SHIFT) | \
100 ((ctlfield) << MUX_FIELD_SHIFT) | \
101 ((padgrp) << MUX_PADGRP_SHIFT))
102
103#define MUX_MODE_OUT_SHIFT (4)
104#define MUX_MODE_IN_SHIFT (0)
105#define MUX_MODE_SHIFT (0)
106#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
107
108#define IOMUX_MODE(pin, mode) \
109 (pin | (mode << MUX_MODE_SHIFT))
110
111enum iomux_pins {
112 /* AP Side pins */
113 MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
114 MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
115 MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
116 MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
117 MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
118 MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
119 MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
120 MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
121 MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
122 MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
123 MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
124 MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
125 MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
126 MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
127 MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
128 MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
129 MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
130 MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
131 MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
132 MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
133 MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
134 MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
135 MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
136 MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
137 MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
138 MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
139 MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
140 MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
141 MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
142 MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
143 MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
144 MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
145 MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
146 MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
147 MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
148 MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
149 MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
150 MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
151 MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
152 MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
153 MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
154 MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
155 MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
156 MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
157 MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
158 MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
159 MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
160 MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
161 MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
162 MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
163 MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
164 MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
165 MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
166 MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
167 MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
168 MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
169 MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
170 MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
171 MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
172 MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
173 MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
174 MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
175 MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
176 MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
177 MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
178 MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
179 MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
180 MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
181 MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
182 MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
183 MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
184 MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
185 MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
186 MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
187 MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
188 MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
189 MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
190 MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
191 MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
192 MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
193 MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
194 MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
195 MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
196 MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
197 MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
198 MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
199 MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
200 MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
201 MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
202 MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
203 MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
204 MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
205 MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
206 MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
207 MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
208 MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
209 MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
210 MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
211 MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
212 MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
213 MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
214 MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
215 MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
216 MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
217
218 /* Shared pins */
219 MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
220 MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
221 MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
222 MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
223 MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
224 MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
225 MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
226 MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
227 MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
228 MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
229 MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
230 MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
231 MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
232 MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
233 MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
234 MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
235 MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
236 MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
237 MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
238 MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
239 MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
240 MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
241 MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
242 MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
243 MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
244 MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
245 MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
246 MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
247 MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
248 MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
249 MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
250 MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
251 MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
252 MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
253 MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
254 MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
255 MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
256 MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
257 MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
258 MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
259 MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
260};
261
262#define PIN_AP_MAX (104)
263#define PIN_SP_MAX (41)
264
265#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
266
267/*
268 * Convenience values for use with mxc_iomux_mode()
269 *
270 * Format here is MXC91231_PIN_(pin name)__(function)
271 */
272
273#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
274 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
275#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
276 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
277#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
278 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
279#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
280 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
281
282
283#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3d930d3e65..35c89bcdf75 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -35,8 +35,6 @@
35#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_SOC_IMX51 36#elif defined CONFIG_SOC_IMX51
37#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
38#elif defined CONFIG_ARCH_MXC91231
39#define MXC_GPIO_IRQS (32 * 4)
40#elif defined CONFIG_ARCH_MX3 38#elif defined CONFIG_ARCH_MX3
41#define MXC_GPIO_IRQS (32 * 3) 39#define MXC_GPIO_IRQS (32 * 3)
42#endif 40#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 5d51cbb9889..11be5cdbdd1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -19,7 +19,6 @@
19#define MX50_PHYS_OFFSET UL(0x70000000) 19#define MX50_PHYS_OFFSET UL(0x70000000)
20#define MX51_PHYS_OFFSET UL(0x90000000) 20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000) 21#define MX53_PHYS_OFFSET UL(0x70000000)
22#define MXC91231_PHYS_OFFSET UL(0x90000000)
23 22
24#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
25# if defined CONFIG_ARCH_MX1 24# if defined CONFIG_ARCH_MX1
@@ -32,8 +31,6 @@
32# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET 31# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MX3 32# elif defined CONFIG_ARCH_MX3
34# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET 33# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MXC91231
36# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET
37# elif defined CONFIG_ARCH_MX50 34# elif defined CONFIG_ARCH_MX50
38# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET 35# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
39# elif defined CONFIG_ARCH_MX51 36# elif defined CONFIG_ARCH_MX51
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index cbc43ad5ef4..1dc1c522601 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -60,8 +60,8 @@
60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) 60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) 61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) 62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
63#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) 63#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
64#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) 64#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
65#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) 65#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
66#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) 66#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
67#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) 67#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index ace17864575..9d2a1ef84de 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -337,17 +337,4 @@
337#define MX53_INT_GPIO7_LOW 107 337#define MX53_INT_GPIO7_LOW 107
338#define MX53_INT_GPIO7_HIGH 108 338#define MX53_INT_GPIO7_HIGH 108
339 339
340/* silicon revisions specific to i.MX53 */
341#define MX53_CHIP_REV_1_0 0x10
342#define MX53_CHIP_REV_1_1 0x11
343#define MX53_CHIP_REV_1_2 0x12
344#define MX53_CHIP_REV_1_3 0x13
345#define MX53_CHIP_REV_2_0 0x20
346#define MX53_CHIP_REV_2_1 0x21
347#define MX53_CHIP_REV_2_2 0x22
348#define MX53_CHIP_REV_2_3 0x23
349#define MX53_CHIP_REV_3_0 0x30
350#define MX53_CHIP_REV_3_1 0x31
351#define MX53_CHIP_REV_3_2 0x32
352
353#endif /* ifndef __MACH_MX53_H__ */ 340#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 1aea818d9d3..4ac53ce97c2 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -35,7 +35,6 @@
35#define MXC_CPU_MX50 50 35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51 36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53 37#define MXC_CPU_MX53 53
38#define MXC_CPU_MXC91231 91231
39 38
40#define IMX_CHIP_REVISION_1_0 0x10 39#define IMX_CHIP_REVISION_1_0 0x10
41#define IMX_CHIP_REVISION_1_1 0x11 40#define IMX_CHIP_REVISION_1_1 0x11
@@ -177,18 +176,6 @@ extern unsigned int __mxc_cpu_type;
177# define cpu_is_mx53() (0) 176# define cpu_is_mx53() (0)
178#endif 177#endif
179 178
180#ifdef CONFIG_ARCH_MXC91231
181# ifdef mxc_cpu_type
182# undef mxc_cpu_type
183# define mxc_cpu_type __mxc_cpu_type
184# else
185# define mxc_cpu_type MXC_CPU_MXC91231
186# endif
187# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
188#else
189# define cpu_is_mxc91231() (0)
190#endif
191
192#ifndef __ASSEMBLY__ 179#ifndef __ASSEMBLY__
193 180
194struct cpu_op { 181struct cpu_op {
@@ -207,14 +194,7 @@ enum mxc_cpu_pwr_mode {
207extern struct cpu_op *(*get_cpu_op)(int *op); 194extern struct cpu_op *(*get_cpu_op)(int *op);
208#endif 195#endif
209 196
210#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 197#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
211/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
212#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
213#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
214#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
215#endif
216
217#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
218#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) 198#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
219 199
220#endif /* __ASM_ARCH_MXC_H__ */ 200#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
deleted file mode 100644
index 765190fe633..00000000000
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * - Platform specific register memory map
4 *
5 * Copyright 2005-2007 Motorola, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#ifndef __MACH_MXC91231_H__
18#define __MACH_MXC91231_H__
19
20/*
21 * L2CC
22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_SIZE SZ_64K
25
26/*
27 * AIPS 1
28 */
29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
30#define MXC91231_AIPS1_SIZE SZ_1M
31
32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
33#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
34#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
35#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
36#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
37#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
38#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
39#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
40#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
41#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
42#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
43#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
44#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
45#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
46#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
47#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
48#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
49
50/*
51 * AIPS 2
52 */
53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
54#define MXC91231_AIPS2_SIZE SZ_1M
55
56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
57#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
58#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
59#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
60#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
61#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
62#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
63#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
64#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
65#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
66#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
67#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
68#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
69#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
70#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
71#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
72#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
73#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
74
75/*
76 * SPBA global module 0
77 */
78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
79#define MXC91231_SPBA0_SIZE SZ_1M
80
81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
82#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
83#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
84#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
85#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
86#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
87#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
88#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
89#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
90#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
91#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
92#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
93#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
94#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
95#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
96#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
97#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
98#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
99#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
100#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
101#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
102#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
103
104/*
105 * SPBA global module 1
106 */
107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
108#define MXC91231_SPBA1_SIZE SZ_1M
109
110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
111#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
112
113/*!
114 * Defines for SPBA modules
115 */
116#define MXC91231_SPBA_SDHC1 0x04
117#define MXC91231_SPBA_SDHC2 0x08
118#define MXC91231_SPBA_UART3 0x0C
119#define MXC91231_SPBA_CSPI2 0x10
120#define MXC91231_SPBA_SSI2 0x14
121#define MXC91231_SPBA_SIM 0x18
122#define MXC91231_SPBA_IIM 0x1C
123#define MXC91231_SPBA_CTI_SDMA 0x20
124#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
125#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
126#define MXC91231_SPBA_CSPI1 0x30
127#define MXC91231_SPBA_MQSPI 0x34
128#define MXC91231_SPBA_EL1T 0x38
129#define MXC91231_SPBA_IOMUX 0x40
130#define MXC91231_SPBA_CRM_COM 0x44
131#define MXC91231_SPBA_CRM_AP 0x48
132#define MXC91231_SPBA_PLL0 0x4C
133#define MXC91231_SPBA_PLL1 0x50
134#define MXC91231_SPBA_PLL2 0x54
135#define MXC91231_SPBA_GPIO4 0x58
136#define MXC91231_SPBA_SAHARA 0x5C
137
138/*
139 * ROMP and AVIC
140 */
141#define MXC91231_ROMP_BASE_ADDR 0x60000000
142#define MXC91231_ROMP_SIZE SZ_64K
143
144#define MXC91231_AVIC_BASE_ADDR 0x68000000
145#define MXC91231_AVIC_SIZE SZ_64K
146
147/*
148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
149 */
150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
151#define MXC91231_X_MEMC_SIZE SZ_64K
152
153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
154#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
155#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
156#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
157#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
158
159/*
160 * Memory regions and CS
161 * CPLD is connected on CS4
162 * CS5 is TP1021 or it is not connected
163 * */
164#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
165#define MXC91231_FB_RAM_SIZE SZ_256K
166#define MXC91231_CSD0_BASE_ADDR 0x80000000
167#define MXC91231_CSD1_BASE_ADDR 0x90000000
168#define MXC91231_CS0_BASE_ADDR 0xA0000000
169#define MXC91231_CS1_BASE_ADDR 0xA8000000
170#define MXC91231_CS2_BASE_ADDR 0xB0000000
171#define MXC91231_CS3_BASE_ADDR 0xB2000000
172#define MXC91231_CS4_BASE_ADDR 0xB4000000
173#define MXC91231_CS5_BASE_ADDR 0xB6000000
174
175/*
176 * This macro defines the physical to virtual address mapping for all the
177 * peripheral modules. It is used by passing in the physical address as x
178 * and returning the virtual address.
179 */
180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
182
183/*
184 * Interrupt numbers
185 */
186#define MXC91231_INT_GPIO3 0
187#define MXC91231_INT_EL1T_CI 1
188#define MXC91231_INT_EL1T_RFCI 2
189#define MXC91231_INT_EL1T_RFI 3
190#define MXC91231_INT_EL1T_MCU 4
191#define MXC91231_INT_EL1T_IPI 5
192#define MXC91231_INT_MU_GEN 6
193#define MXC91231_INT_GPIO4 7
194#define MXC91231_INT_MMC_SDHC2 8
195#define MXC91231_INT_MMC_SDHC1 9
196#define MXC91231_INT_I2C 10
197#define MXC91231_INT_SSI2 11
198#define MXC91231_INT_SSI1 12
199#define MXC91231_INT_CSPI2 13
200#define MXC91231_INT_CSPI1 14
201#define MXC91231_INT_RTIC 15
202#define MXC91231_INT_SAHARA 15
203#define MXC91231_INT_HAC 15
204#define MXC91231_INT_UART3_RX 16
205#define MXC91231_INT_UART3_TX 17
206#define MXC91231_INT_UART3_MINT 18
207#define MXC91231_INT_ECT 19
208#define MXC91231_INT_SIM_IPB 20
209#define MXC91231_INT_SIM_DATA 21
210#define MXC91231_INT_RNGA 22
211#define MXC91231_INT_DSM_AP 23
212#define MXC91231_INT_KPP 24
213#define MXC91231_INT_RTC 25
214#define MXC91231_INT_PWM 26
215#define MXC91231_INT_GEMK_AP 27
216#define MXC91231_INT_EPIT 28
217#define MXC91231_INT_GPT 29
218#define MXC91231_INT_UART2_RX 30
219#define MXC91231_INT_UART2_TX 31
220#define MXC91231_INT_UART2_MINT 32
221#define MXC91231_INT_NANDFC 33
222#define MXC91231_INT_SDMA 34
223#define MXC91231_INT_USB_WAKEUP 35
224#define MXC91231_INT_USB_SOF 36
225#define MXC91231_INT_PMU_EVTMON 37
226#define MXC91231_INT_USB_FUNC 38
227#define MXC91231_INT_USB_DMA 39
228#define MXC91231_INT_USB_CTRL 40
229#define MXC91231_INT_IPU_ERR 41
230#define MXC91231_INT_IPU_SYN 42
231#define MXC91231_INT_UART1_RX 43
232#define MXC91231_INT_UART1_TX 44
233#define MXC91231_INT_UART1_MINT 45
234#define MXC91231_INT_IIM 46
235#define MXC91231_INT_MU_RX_OR 47
236#define MXC91231_INT_MU_TX_OR 48
237#define MXC91231_INT_SCC_SCM 49
238#define MXC91231_INT_SCC_SMN 50
239#define MXC91231_INT_GPIO2 51
240#define MXC91231_INT_GPIO1 52
241#define MXC91231_INT_MQSPI1 53
242#define MXC91231_INT_MQSPI2 54
243#define MXC91231_INT_WDOG2 55
244#define MXC91231_INT_EXT_INT7 56
245#define MXC91231_INT_EXT_INT6 57
246#define MXC91231_INT_EXT_INT5 58
247#define MXC91231_INT_EXT_INT4 59
248#define MXC91231_INT_EXT_INT3 60
249#define MXC91231_INT_EXT_INT2 61
250#define MXC91231_INT_EXT_INT1 62
251#define MXC91231_INT_EXT_INT0 63
252
253#define MXC91231_MAX_INT_LINES 63
254#define MXC91231_MAX_EXT_LINES 8
255
256#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 0417da9f710..51f02a9d41a 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -24,12 +24,6 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
24 24
25static inline void arch_idle(void) 25static inline void arch_idle(void)
26{ 26{
27#ifdef CONFIG_ARCH_MXC91231
28 if (cpu_is_mxc91231()) {
29 /* Need this to set DSM low-power mode */
30 mxc91231_prepare_idle();
31 }
32#endif
33 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ 27 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
34 if (cpu_is_mx31() || cpu_is_mx35()) { 28 if (cpu_is_mx31() || cpu_is_mx35()) {
35 unsigned long reg = 0; 29 unsigned long reg = 0;
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 2d9624697cc..d61d5c74817 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,8 +26,6 @@
26#define CLOCK_TICK_RATE 16000000 26#define CLOCK_TICK_RATE 16000000
27#elif defined CONFIG_ARCH_MX5 27#elif defined CONFIG_ARCH_MX5
28#define CLOCK_TICK_RATE 8000000 28#define CLOCK_TICK_RATE 8000000
29#elif defined CONFIG_ARCH_MXC91231
30#define CLOCK_TICK_RATE 13000000
31#endif 29#endif
32 30
33#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ 31#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4864b0afd44..d85e2d1c032 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -21,7 +21,7 @@
21 21
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23 23
24static unsigned long uart_base; 24unsigned long uart_base;
25 25
26#define UART(x) (*(volatile unsigned long *)(uart_base + (x))) 26#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
27 27
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 20:23:17 -0400