diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mxc.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc.h | 200 |
1 files changed, 200 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h new file mode 100644 index 00000000000..09879235a9f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
@@ -0,0 +1,200 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version 2 | ||
8 | * of the License, or (at your option) any later version. | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
17 | * MA 02110-1301, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASM_ARCH_MXC_H__ | ||
21 | #define __ASM_ARCH_MXC_H__ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | |||
25 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
26 | #error "Do not include directly." | ||
27 | #endif | ||
28 | |||
29 | #define MXC_CPU_MX1 1 | ||
30 | #define MXC_CPU_MX21 21 | ||
31 | #define MXC_CPU_MX25 25 | ||
32 | #define MXC_CPU_MX27 27 | ||
33 | #define MXC_CPU_MX31 31 | ||
34 | #define MXC_CPU_MX35 35 | ||
35 | #define MXC_CPU_MX50 50 | ||
36 | #define MXC_CPU_MX51 51 | ||
37 | #define MXC_CPU_MX53 53 | ||
38 | |||
39 | #define IMX_CHIP_REVISION_1_0 0x10 | ||
40 | #define IMX_CHIP_REVISION_1_1 0x11 | ||
41 | #define IMX_CHIP_REVISION_1_2 0x12 | ||
42 | #define IMX_CHIP_REVISION_1_3 0x13 | ||
43 | #define IMX_CHIP_REVISION_2_0 0x20 | ||
44 | #define IMX_CHIP_REVISION_2_1 0x21 | ||
45 | #define IMX_CHIP_REVISION_2_2 0x22 | ||
46 | #define IMX_CHIP_REVISION_2_3 0x23 | ||
47 | #define IMX_CHIP_REVISION_3_0 0x30 | ||
48 | #define IMX_CHIP_REVISION_3_1 0x31 | ||
49 | #define IMX_CHIP_REVISION_3_2 0x32 | ||
50 | #define IMX_CHIP_REVISION_3_3 0x33 | ||
51 | #define IMX_CHIP_REVISION_UNKNOWN 0xff | ||
52 | |||
53 | #define IMX_CHIP_REVISION_1_0_STRING "1.0" | ||
54 | #define IMX_CHIP_REVISION_1_1_STRING "1.1" | ||
55 | #define IMX_CHIP_REVISION_1_2_STRING "1.2" | ||
56 | #define IMX_CHIP_REVISION_1_3_STRING "1.3" | ||
57 | #define IMX_CHIP_REVISION_2_0_STRING "2.0" | ||
58 | #define IMX_CHIP_REVISION_2_1_STRING "2.1" | ||
59 | #define IMX_CHIP_REVISION_2_2_STRING "2.2" | ||
60 | #define IMX_CHIP_REVISION_2_3_STRING "2.3" | ||
61 | #define IMX_CHIP_REVISION_3_0_STRING "3.0" | ||
62 | #define IMX_CHIP_REVISION_3_1_STRING "3.1" | ||
63 | #define IMX_CHIP_REVISION_3_2_STRING "3.2" | ||
64 | #define IMX_CHIP_REVISION_3_3_STRING "3.3" | ||
65 | #define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" | ||
66 | |||
67 | #ifndef __ASSEMBLY__ | ||
68 | extern unsigned int __mxc_cpu_type; | ||
69 | #endif | ||
70 | |||
71 | #ifdef CONFIG_SOC_IMX1 | ||
72 | # ifdef mxc_cpu_type | ||
73 | # undef mxc_cpu_type | ||
74 | # define mxc_cpu_type __mxc_cpu_type | ||
75 | # else | ||
76 | # define mxc_cpu_type MXC_CPU_MX1 | ||
77 | # endif | ||
78 | # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) | ||
79 | #else | ||
80 | # define cpu_is_mx1() (0) | ||
81 | #endif | ||
82 | |||
83 | #ifdef CONFIG_SOC_IMX21 | ||
84 | # ifdef mxc_cpu_type | ||
85 | # undef mxc_cpu_type | ||
86 | # define mxc_cpu_type __mxc_cpu_type | ||
87 | # else | ||
88 | # define mxc_cpu_type MXC_CPU_MX21 | ||
89 | # endif | ||
90 | # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) | ||
91 | #else | ||
92 | # define cpu_is_mx21() (0) | ||
93 | #endif | ||
94 | |||
95 | #ifdef CONFIG_SOC_IMX25 | ||
96 | # ifdef mxc_cpu_type | ||
97 | # undef mxc_cpu_type | ||
98 | # define mxc_cpu_type __mxc_cpu_type | ||
99 | # else | ||
100 | # define mxc_cpu_type MXC_CPU_MX25 | ||
101 | # endif | ||
102 | # define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) | ||
103 | #else | ||
104 | # define cpu_is_mx25() (0) | ||
105 | #endif | ||
106 | |||
107 | #ifdef CONFIG_SOC_IMX27 | ||
108 | # ifdef mxc_cpu_type | ||
109 | # undef mxc_cpu_type | ||
110 | # define mxc_cpu_type __mxc_cpu_type | ||
111 | # else | ||
112 | # define mxc_cpu_type MXC_CPU_MX27 | ||
113 | # endif | ||
114 | # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) | ||
115 | #else | ||
116 | # define cpu_is_mx27() (0) | ||
117 | #endif | ||
118 | |||
119 | #ifdef CONFIG_SOC_IMX31 | ||
120 | # ifdef mxc_cpu_type | ||
121 | # undef mxc_cpu_type | ||
122 | # define mxc_cpu_type __mxc_cpu_type | ||
123 | # else | ||
124 | # define mxc_cpu_type MXC_CPU_MX31 | ||
125 | # endif | ||
126 | # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) | ||
127 | #else | ||
128 | # define cpu_is_mx31() (0) | ||
129 | #endif | ||
130 | |||
131 | #ifdef CONFIG_SOC_IMX35 | ||
132 | # ifdef mxc_cpu_type | ||
133 | # undef mxc_cpu_type | ||
134 | # define mxc_cpu_type __mxc_cpu_type | ||
135 | # else | ||
136 | # define mxc_cpu_type MXC_CPU_MX35 | ||
137 | # endif | ||
138 | # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) | ||
139 | #else | ||
140 | # define cpu_is_mx35() (0) | ||
141 | #endif | ||
142 | |||
143 | #ifdef CONFIG_SOC_IMX50 | ||
144 | # ifdef mxc_cpu_type | ||
145 | # undef mxc_cpu_type | ||
146 | # define mxc_cpu_type __mxc_cpu_type | ||
147 | # else | ||
148 | # define mxc_cpu_type MXC_CPU_MX50 | ||
149 | # endif | ||
150 | # define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) | ||
151 | #else | ||
152 | # define cpu_is_mx50() (0) | ||
153 | #endif | ||
154 | |||
155 | #ifdef CONFIG_SOC_IMX51 | ||
156 | # ifdef mxc_cpu_type | ||
157 | # undef mxc_cpu_type | ||
158 | # define mxc_cpu_type __mxc_cpu_type | ||
159 | # else | ||
160 | # define mxc_cpu_type MXC_CPU_MX51 | ||
161 | # endif | ||
162 | # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) | ||
163 | #else | ||
164 | # define cpu_is_mx51() (0) | ||
165 | #endif | ||
166 | |||
167 | #ifdef CONFIG_SOC_IMX53 | ||
168 | # ifdef mxc_cpu_type | ||
169 | # undef mxc_cpu_type | ||
170 | # define mxc_cpu_type __mxc_cpu_type | ||
171 | # else | ||
172 | # define mxc_cpu_type MXC_CPU_MX53 | ||
173 | # endif | ||
174 | # define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) | ||
175 | #else | ||
176 | # define cpu_is_mx53() (0) | ||
177 | #endif | ||
178 | |||
179 | #ifndef __ASSEMBLY__ | ||
180 | |||
181 | struct cpu_op { | ||
182 | u32 cpu_rate; | ||
183 | }; | ||
184 | |||
185 | int tzic_enable_wake(int is_idle); | ||
186 | enum mxc_cpu_pwr_mode { | ||
187 | WAIT_CLOCKED, /* wfi only */ | ||
188 | WAIT_UNCLOCKED, /* WAIT */ | ||
189 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | ||
190 | STOP_POWER_ON, /* just STOP */ | ||
191 | STOP_POWER_OFF, /* STOP + SRPG */ | ||
192 | }; | ||
193 | |||
194 | extern struct cpu_op *(*get_cpu_op)(int *op); | ||
195 | #endif | ||
196 | |||
197 | #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) | ||
198 | #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) | ||
199 | |||
200 | #endif /* __ASM_ARCH_MXC_H__ */ | ||