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Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx51.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h73
1 files changed, 11 insertions, 62 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 2af7a1056fc..873807f96d7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -2,31 +2,6 @@
2#define __MACH_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * fa200000 60000000 1M DEBUG
14 * fb100000 70000000 1M SPBA 0
15 * fb000000 73f00000 1M AIPS 1
16 * fb200000 83f00000 1M AIPS 2
17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * a0000000 256M CSD1 SDRAM/DDR
20 * b0000000 128M CS0 Flash
21 * b8000000 128M CS1 Flash
22 * c0000000 128M CS2 Flash
23 * c8000000 64M CS3 Flash
24 * cc000000 32M CS4 SRAM
25 * ce000000 32M CS5 SRAM
26 * cfff0000 64K NFC (NAND Flash AXI)
27 */
28
29/*
30 * IROM 5 * IROM
31 */ 6 */
32#define MX51_IROM_BASE_ADDR 0x0 7#define MX51_IROM_BASE_ADDR 0x0
@@ -36,7 +11,6 @@
36 * IRAM 11 * IRAM
37 */ 12 */
38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ 13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
40#define MX51_IRAM_PARTITIONS 16 14#define MX51_IRAM_PARTITIONS 16
41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
42 16
@@ -45,7 +19,6 @@
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46 20
47#define MX51_DEBUG_BASE_ADDR 0x60000000 21#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M 22#define MX51_DEBUG_SIZE SZ_1M
50 23
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) 24#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
@@ -61,7 +34,6 @@
61 * SPBA global module enabled #0 34 * SPBA global module enabled #0
62 */ 35 */
63#define MX51_SPBA0_BASE_ADDR 0x70000000 36#define MX51_SPBA0_BASE_ADDR 0x70000000
64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M 37#define MX51_SPBA0_SIZE SZ_1M
66 38
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 39#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
@@ -81,7 +53,6 @@
81 * AIPS 1 53 * AIPS 1
82 */ 54 */
83#define MX51_AIPS1_BASE_ADDR 0x73f00000 55#define MX51_AIPS1_BASE_ADDR 0x73f00000
84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
85#define MX51_AIPS1_SIZE SZ_1M 56#define MX51_AIPS1_SIZE SZ_1M
86 57
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) 58#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
@@ -90,7 +61,7 @@
90#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) 61#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
91#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) 62#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
92#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) 63#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
93#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) 64#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
94#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) 65#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
95#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) 66#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
96#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) 67#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
@@ -109,7 +80,6 @@
109 * AIPS 2 80 * AIPS 2
110 */ 81 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000 82#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M 83#define MX51_AIPS2_SIZE SZ_1M
114 84
115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) 85#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
@@ -139,7 +109,7 @@
139#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) 109#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
140#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) 110#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
141#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) 111#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
142#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) 112#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
143#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) 113#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
144#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) 114#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
145#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) 115#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
@@ -163,16 +133,8 @@
163#define MX51_GPU2D_BASE_ADDR 0xd0000000 133#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000 134#define MX51_TZIC_BASE_ADDR 0xe0000000
165 135
166#define MX51_IO_ADDRESS(x) ( \ 136#define MX51_IO_P2V(x) IMX_IO_P2V(x)
167 IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ 137#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
168 IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
169 IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
170 IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
171 IMX_IO_ADDRESS(x, MX51_AIPS2))
172
173/* This is currently used in <mach/debug-macro.S>, but should go away */
174#define MX51_AIPS1_IO_ADDRESS(x) \
175 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
176 138
177/* 139/*
178 * defines for SPBA modules 140 * defines for SPBA modules
@@ -261,9 +223,9 @@
261#define MX51_DMA_REQ_EMI_WR 32 223#define MX51_DMA_REQ_EMI_WR 32
262#define MX51_DMA_REQ_CTI2_1 33 224#define MX51_DMA_REQ_CTI2_1 33
263#define MX51_DMA_REQ_EPIT2 34 225#define MX51_DMA_REQ_EPIT2 34
264#define MX51_DMA_REQ_SSI3_RX2 35 226#define MX51_DMA_REQ_SSI3_RX1 35
265#define MX51_DMA_REQ_IPU 36 227#define MX51_DMA_REQ_IPU 36
266#define MX51_DMA_REQ_SSI3_TX2 37 228#define MX51_DMA_REQ_SSI3_TX1 37
267#define MX51_DMA_REQ_CSPI_RX 38 229#define MX51_DMA_REQ_CSPI_RX 38
268#define MX51_DMA_REQ_CSPI_TX 39 230#define MX51_DMA_REQ_CSPI_TX 39
269#define MX51_DMA_REQ_SDHC3 40 231#define MX51_DMA_REQ_SDHC3 40
@@ -272,8 +234,8 @@
272#define MX51_DMA_REQ_UART3_RX 43 234#define MX51_DMA_REQ_UART3_RX 43
273#define MX51_DMA_REQ_UART3_TX 44 235#define MX51_DMA_REQ_UART3_TX 44
274#define MX51_DMA_REQ_SPDIF 45 236#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_SSI3_RX1 46 237#define MX51_DMA_REQ_SSI3_RX0 46
276#define MX51_DMA_REQ_SSI3_TX1 47 238#define MX51_DMA_REQ_SSI3_TX0 47
277 239
278/* 240/*
279 * Interrupt numbers 241 * Interrupt numbers
@@ -289,8 +251,8 @@
289#define MX51_MXC_INT_IOMUX 7 251#define MX51_MXC_INT_IOMUX 7
290#define MX51_INT_NFC 8 252#define MX51_INT_NFC 8
291#define MX51_MXC_INT_VPU 9 253#define MX51_MXC_INT_VPU 9
292#define MX51_MXC_INT_IPU_ERR 10 254#define MX51_INT_IPU_ERR 10
293#define MX51_MXC_INT_IPU_SYN 11 255#define MX51_INT_IPU_SYN 11
294#define MX51_MXC_INT_GPU 12 256#define MX51_MXC_INT_GPU 12
295#define MX51_MXC_INT_RESV13 13 257#define MX51_MXC_INT_RESV13 13
296#define MX51_MXC_INT_USB_H1 14 258#define MX51_MXC_INT_USB_H1 14
@@ -375,7 +337,7 @@
375#define MX51_MXC_INT_FIRI 93 337#define MX51_MXC_INT_FIRI 93
376#define MX51_MXC_INT_PWM2 94 338#define MX51_MXC_INT_PWM2 94
377#define MX51_MXC_INT_SLIM_EXP 95 339#define MX51_MXC_INT_SLIM_EXP 95
378#define MX51_MXC_INT_SSI3 96 340#define MX51_INT_SSI3 96
379#define MX51_MXC_INT_EMI_BOOT 97 341#define MX51_MXC_INT_EMI_BOOT 97
380#define MX51_MXC_INT_CTI1_TG3 98 342#define MX51_MXC_INT_CTI1_TG3 98
381#define MX51_MXC_INT_SMC_RX 99 343#define MX51_MXC_INT_SMC_RX 99
@@ -383,19 +345,6 @@
383#define MX51_MXC_INT_EMI_NFC 101 345#define MX51_MXC_INT_EMI_NFC 101
384#define MX51_MXC_INT_GPU_IDLE 102 346#define MX51_MXC_INT_GPU_IDLE 102
385 347
386/* silicon revisions specific to i.MX51 */
387#define MX51_CHIP_REV_1_0 0x10
388#define MX51_CHIP_REV_1_1 0x11
389#define MX51_CHIP_REV_1_2 0x12
390#define MX51_CHIP_REV_1_3 0x13
391#define MX51_CHIP_REV_2_0 0x20
392#define MX51_CHIP_REV_2_1 0x21
393#define MX51_CHIP_REV_2_2 0x22
394#define MX51_CHIP_REV_2_3 0x23
395#define MX51_CHIP_REV_3_0 0x30
396#define MX51_CHIP_REV_3_1 0x31
397#define MX51_CHIP_REV_3_2 0x32
398
399#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 348#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
400extern int mx51_revision(void); 349extern int mx51_revision(void);
401#endif 350#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 16:32:45 -0400