diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx21.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx21.h | 50 |
1 files changed, 8 insertions, 42 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc59720b6e..6cd049ebbd8 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
@@ -26,7 +26,6 @@ | |||
26 | #define __MACH_MX21_H__ | 26 | #define __MACH_MX21_H__ |
27 | 27 | ||
28 | #define MX21_AIPI_BASE_ADDR 0x10000000 | 28 | #define MX21_AIPI_BASE_ADDR 0x10000000 |
29 | #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
30 | #define MX21_AIPI_SIZE SZ_1M | 29 | #define MX21_AIPI_SIZE SZ_1M |
31 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) | 30 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) |
32 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) | 31 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) |
@@ -49,6 +48,12 @@ | |||
49 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | 48 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) |
50 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | 49 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) |
51 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | 50 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) |
51 | #define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) | ||
52 | #define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) | ||
53 | #define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) | ||
54 | #define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) | ||
55 | #define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) | ||
56 | #define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) | ||
52 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) | 57 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) |
53 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | 58 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) |
54 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | 59 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) |
@@ -64,7 +69,6 @@ | |||
64 | #define MX21_AVIC_BASE_ADDR 0x10040000 | 69 | #define MX21_AVIC_BASE_ADDR 0x10040000 |
65 | 70 | ||
66 | #define MX21_SAHB1_BASE_ADDR 0x80000000 | 71 | #define MX21_SAHB1_BASE_ADDR 0x80000000 |
67 | #define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
68 | #define MX21_SAHB1_SIZE SZ_1M | 72 | #define MX21_SAHB1_SIZE SZ_1M |
69 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | 73 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
70 | 74 | ||
@@ -82,7 +86,6 @@ | |||
82 | 86 | ||
83 | /* NAND, SDRAM, WEIM etc controllers */ | 87 | /* NAND, SDRAM, WEIM etc controllers */ |
84 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 | 88 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 |
85 | #define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | ||
86 | #define MX21_X_MEMC_SIZE SZ_256K | 89 | #define MX21_X_MEMC_SIZE SZ_256K |
87 | 90 | ||
88 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) | 91 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) |
@@ -92,10 +95,8 @@ | |||
92 | 95 | ||
93 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ | 96 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ |
94 | 97 | ||
95 | #define MX21_IO_ADDRESS(x) ( \ | 98 | #define MX21_IO_P2V(x) IMX_IO_P2V(x) |
96 | IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ | 99 | #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) |
97 | IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ | ||
98 | IMX_IO_ADDRESS(x, MX21_X_MEMC)) | ||
99 | 100 | ||
100 | /* fixed interrupt numbers */ | 101 | /* fixed interrupt numbers */ |
101 | #define MX21_INT_CSPI3 6 | 102 | #define MX21_INT_CSPI3 6 |
@@ -184,39 +185,4 @@ | |||
184 | #define MX21_DMA_REQ_CSI_STAT 30 | 185 | #define MX21_DMA_REQ_CSI_STAT 30 |
185 | #define MX21_DMA_REQ_CSI_RX 31 | 186 | #define MX21_DMA_REQ_CSI_RX 31 |
186 | 187 | ||
187 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
188 | /* these should go away */ | ||
189 | #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR | ||
190 | #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR | ||
191 | #define CS0_BASE_ADDR MX21_CS0_BASE_ADDR | ||
192 | #define CS1_BASE_ADDR MX21_CS1_BASE_ADDR | ||
193 | #define CS2_BASE_ADDR MX21_CS2_BASE_ADDR | ||
194 | #define CS3_BASE_ADDR MX21_CS3_BASE_ADDR | ||
195 | #define CS4_BASE_ADDR MX21_CS4_BASE_ADDR | ||
196 | #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR | ||
197 | #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR | ||
198 | #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR | ||
199 | #define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT | ||
200 | #define X_MEMC_SIZE MX21_X_MEMC_SIZE | ||
201 | #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR | ||
202 | #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR | ||
203 | #define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR | ||
204 | #define NFC_BASE_ADDR MX21_NFC_BASE_ADDR | ||
205 | #define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR | ||
206 | #define MXC_INT_FIRI MX21_INT_FIRI | ||
207 | #define MXC_INT_BMI MX21_INT_BMI | ||
208 | #define MXC_INT_EMMAENC MX21_INT_EMMAENC | ||
209 | #define MXC_INT_EMMADEC MX21_INT_EMMADEC | ||
210 | #define MXC_INT_USBWKUP MX21_INT_USBWKUP | ||
211 | #define MXC_INT_USBDMA MX21_INT_USBDMA | ||
212 | #define MXC_INT_USBHOST MX21_INT_USBHOST | ||
213 | #define MXC_INT_USBFUNC MX21_INT_USBFUNC | ||
214 | #define MXC_INT_USBMNP MX21_INT_USBMNP | ||
215 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
216 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
217 | #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX | ||
218 | #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX | ||
219 | #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX | ||
220 | #endif | ||
221 | |||
222 | #endif /* ifndef __MACH_MX21_H__ */ | 188 | #endif /* ifndef __MACH_MX21_H__ */ |