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-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h173
1 files changed, 173 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
new file mode 100644
index 00000000000..97b19e7800b
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+++ b/arch/arm/plat-mxc/include/mach/mx1.h
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1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_MX1_H__
13#define __MACH_MX1_H__
14
15#include <mach/vmalloc.h>
16
17/*
18 * Memory map
19 */
20#define MX1_IO_BASE_ADDR 0x00200000
21#define MX1_IO_SIZE SZ_1M
22
23#define MX1_CS0_PHYS 0x10000000
24#define MX1_CS0_SIZE 0x02000000
25
26#define MX1_CS1_PHYS 0x12000000
27#define MX1_CS1_SIZE 0x01000000
28
29#define MX1_CS2_PHYS 0x13000000
30#define MX1_CS2_SIZE 0x01000000
31
32#define MX1_CS3_PHYS 0x14000000
33#define MX1_CS3_SIZE 0x01000000
34
35#define MX1_CS4_PHYS 0x15000000
36#define MX1_CS4_SIZE 0x01000000
37
38#define MX1_CS5_PHYS 0x16000000
39#define MX1_CS5_SIZE 0x01000000
40
41/*
42 * Register BASEs, based on OFFSETs
43 */
44#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
45#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
46#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
47#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
48#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
49#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
50#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
51#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
52#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
53#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
54#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
55#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
56#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
57#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
58#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
59#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
60#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
61#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
62#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
63#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
64#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
67#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
70#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
71#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
72#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
73#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
74#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
75#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
76#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
77
78/* macro to get at IO space when running virtually */
79#define MX1_IO_P2V(x) IMX_IO_P2V(x)
80#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
81
82/* fixed interrput numbers */
83#define MX1_INT_SOFTINT 0
84#define MX1_INT_CSI 6
85#define MX1_DSPA_MAC_INT 7
86#define MX1_DSPA_INT 8
87#define MX1_COMP_INT 9
88#define MX1_MSHC_XINT 10
89#define MX1_GPIO_INT_PORTA 11
90#define MX1_GPIO_INT_PORTB 12
91#define MX1_GPIO_INT_PORTC 13
92#define MX1_INT_LCDC 14
93#define MX1_SIM_INT 15
94#define MX1_SIM_DATA_INT 16
95#define MX1_RTC_INT 17
96#define MX1_RTC_SAMINT 18
97#define MX1_INT_UART2PFERR 19
98#define MX1_INT_UART2RTS 20
99#define MX1_INT_UART2DTR 21
100#define MX1_INT_UART2UARTC 22
101#define MX1_INT_UART2TX 23
102#define MX1_INT_UART2RX 24
103#define MX1_INT_UART1PFERR 25
104#define MX1_INT_UART1RTS 26
105#define MX1_INT_UART1DTR 27
106#define MX1_INT_UART1UARTC 28
107#define MX1_INT_UART1TX 29
108#define MX1_INT_UART1RX 30
109#define MX1_VOICE_DAC_INT 31
110#define MX1_VOICE_ADC_INT 32
111#define MX1_PEN_DATA_INT 33
112#define MX1_PWM_INT 34
113#define MX1_SDHC_INT 35
114#define MX1_INT_I2C 39
115#define MX1_INT_CSPI2 40
116#define MX1_INT_CSPI1 41
117#define MX1_SSI_TX_INT 42
118#define MX1_SSI_TX_ERR_INT 43
119#define MX1_SSI_RX_INT 44
120#define MX1_SSI_RX_ERR_INT 45
121#define MX1_TOUCH_INT 46
122#define MX1_INT_USBD0 47
123#define MX1_INT_USBD1 48
124#define MX1_INT_USBD2 49
125#define MX1_INT_USBD3 50
126#define MX1_INT_USBD4 51
127#define MX1_INT_USBD5 52
128#define MX1_INT_USBD6 53
129#define MX1_BTSYS_INT 55
130#define MX1_BTTIM_INT 56
131#define MX1_BTWUI_INT 57
132#define MX1_TIM2_INT 58
133#define MX1_TIM1_INT 59
134#define MX1_DMA_ERR 60
135#define MX1_DMA_INT 61
136#define MX1_GPIO_INT_PORTD 62
137#define MX1_WDT_INT 63
138
139/* DMA */
140#define MX1_DMA_REQ_UART3_T 2
141#define MX1_DMA_REQ_UART3_R 3
142#define MX1_DMA_REQ_SSI2_T 4
143#define MX1_DMA_REQ_SSI2_R 5
144#define MX1_DMA_REQ_CSI_STAT 6
145#define MX1_DMA_REQ_CSI_R 7
146#define MX1_DMA_REQ_MSHC 8
147#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
148#define MX1_DMA_REQ_DSPA_DCT_DIN 10
149#define MX1_DMA_REQ_DSPA_MAC 11
150#define MX1_DMA_REQ_EXT 12
151#define MX1_DMA_REQ_SDHC 13
152#define MX1_DMA_REQ_SPI1_R 14
153#define MX1_DMA_REQ_SPI1_T 15
154#define MX1_DMA_REQ_SSI_T 16
155#define MX1_DMA_REQ_SSI_R 17
156#define MX1_DMA_REQ_ASP_DAC 18
157#define MX1_DMA_REQ_ASP_ADC 19
158#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
159#define MX1_DMA_REQ_SPI2_R 26
160#define MX1_DMA_REQ_SPI2_T 27
161#define MX1_DMA_REQ_UART2_T 28
162#define MX1_DMA_REQ_UART2_R 29
163#define MX1_DMA_REQ_UART1_T 30
164#define MX1_DMA_REQ_UART1_R 31
165
166/*
167 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
168 * to not break drivers/usb/gadget/imx_udc. Should go
169 * away after this driver uses the new name.
170 */
171#define USBD_INT0 MX1_INT_USBD0
172
173#endif /* ifndef __MACH_MX1_H__ */