diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/irqs.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/irqs.h | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h new file mode 100644 index 00000000000..00e812bbd81 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/irqs.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_MXC_IRQS_H__ | ||
12 | #define __ASM_ARCH_MXC_IRQS_H__ | ||
13 | |||
14 | #include <asm-generic/gpio.h> | ||
15 | |||
16 | /* | ||
17 | * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 | ||
18 | */ | ||
19 | #ifdef CONFIG_MXC_TZIC | ||
20 | #define MXC_INTERNAL_IRQS 128 | ||
21 | #else | ||
22 | #define MXC_INTERNAL_IRQS 64 | ||
23 | #endif | ||
24 | |||
25 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS | ||
26 | |||
27 | /* | ||
28 | * The next 16 interrupts are for board specific purposes. Since | ||
29 | * the kernel can only run on one machine at a time, we can re-use | ||
30 | * these. If you need more, increase MXC_BOARD_IRQS, but keep it | ||
31 | * within sensible limits. | ||
32 | */ | ||
33 | #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) | ||
34 | |||
35 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
36 | #define MXC_BOARD_IRQS 80 | ||
37 | #else | ||
38 | #define MXC_BOARD_IRQS 16 | ||
39 | #endif | ||
40 | |||
41 | #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) | ||
42 | |||
43 | #ifdef CONFIG_MX3_IPU_IRQS | ||
44 | #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS | ||
45 | #else | ||
46 | #define MX3_IPU_IRQS 0 | ||
47 | #endif | ||
48 | /* REVISIT: Add IPU irqs on IMX51 */ | ||
49 | |||
50 | #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) | ||
51 | |||
52 | extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); | ||
53 | |||
54 | /* all normal IRQs can be FIQs */ | ||
55 | #define FIQ_START 0 | ||
56 | /* switch between IRQ and FIQ */ | ||
57 | extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); | ||
58 | |||
59 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ | ||