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Diffstat (limited to 'arch/arm/plat-mxc/epit.c')
-rw-r--r-- | arch/arm/plat-mxc/epit.c | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c new file mode 100644 index 00000000000..d3467f818c3 --- /dev/null +++ b/arch/arm/plat-mxc/epit.c | |||
@@ -0,0 +1,225 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/plat-mxc/epit.c | ||
3 | * | ||
4 | * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version 2 | ||
9 | * of the License, or (at your option) any later version. | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
18 | * MA 02110-1301, USA. | ||
19 | */ | ||
20 | |||
21 | #define EPITCR 0x00 | ||
22 | #define EPITSR 0x04 | ||
23 | #define EPITLR 0x08 | ||
24 | #define EPITCMPR 0x0c | ||
25 | #define EPITCNR 0x10 | ||
26 | |||
27 | #define EPITCR_EN (1 << 0) | ||
28 | #define EPITCR_ENMOD (1 << 1) | ||
29 | #define EPITCR_OCIEN (1 << 2) | ||
30 | #define EPITCR_RLD (1 << 3) | ||
31 | #define EPITCR_PRESC(x) (((x) & 0xfff) << 4) | ||
32 | #define EPITCR_SWR (1 << 16) | ||
33 | #define EPITCR_IOVW (1 << 17) | ||
34 | #define EPITCR_DBGEN (1 << 18) | ||
35 | #define EPITCR_WAITEN (1 << 19) | ||
36 | #define EPITCR_RES (1 << 20) | ||
37 | #define EPITCR_STOPEN (1 << 21) | ||
38 | #define EPITCR_OM_DISCON (0 << 22) | ||
39 | #define EPITCR_OM_TOGGLE (1 << 22) | ||
40 | #define EPITCR_OM_CLEAR (2 << 22) | ||
41 | #define EPITCR_OM_SET (3 << 22) | ||
42 | #define EPITCR_CLKSRC_OFF (0 << 24) | ||
43 | #define EPITCR_CLKSRC_PERIPHERAL (1 << 24) | ||
44 | #define EPITCR_CLKSRC_REF_HIGH (1 << 24) | ||
45 | #define EPITCR_CLKSRC_REF_LOW (3 << 24) | ||
46 | |||
47 | #define EPITSR_OCIF (1 << 0) | ||
48 | |||
49 | #include <linux/interrupt.h> | ||
50 | #include <linux/irq.h> | ||
51 | #include <linux/clockchips.h> | ||
52 | #include <linux/clk.h> | ||
53 | |||
54 | #include <mach/hardware.h> | ||
55 | #include <asm/mach/time.h> | ||
56 | #include <mach/common.h> | ||
57 | |||
58 | static struct clock_event_device clockevent_epit; | ||
59 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; | ||
60 | |||
61 | static void __iomem *timer_base; | ||
62 | |||
63 | static inline void epit_irq_disable(void) | ||
64 | { | ||
65 | u32 val; | ||
66 | |||
67 | val = __raw_readl(timer_base + EPITCR); | ||
68 | val &= ~EPITCR_OCIEN; | ||
69 | __raw_writel(val, timer_base + EPITCR); | ||
70 | } | ||
71 | |||
72 | static inline void epit_irq_enable(void) | ||
73 | { | ||
74 | u32 val; | ||
75 | |||
76 | val = __raw_readl(timer_base + EPITCR); | ||
77 | val |= EPITCR_OCIEN; | ||
78 | __raw_writel(val, timer_base + EPITCR); | ||
79 | } | ||
80 | |||
81 | static void epit_irq_acknowledge(void) | ||
82 | { | ||
83 | __raw_writel(EPITSR_OCIF, timer_base + EPITSR); | ||
84 | } | ||
85 | |||
86 | static int __init epit_clocksource_init(struct clk *timer_clk) | ||
87 | { | ||
88 | unsigned int c = clk_get_rate(timer_clk); | ||
89 | |||
90 | return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, | ||
91 | clocksource_mmio_readl_down); | ||
92 | } | ||
93 | |||
94 | /* clock event */ | ||
95 | |||
96 | static int epit_set_next_event(unsigned long evt, | ||
97 | struct clock_event_device *unused) | ||
98 | { | ||
99 | unsigned long tcmp; | ||
100 | |||
101 | tcmp = __raw_readl(timer_base + EPITCNR); | ||
102 | |||
103 | __raw_writel(tcmp - evt, timer_base + EPITCMPR); | ||
104 | |||
105 | return 0; | ||
106 | } | ||
107 | |||
108 | static void epit_set_mode(enum clock_event_mode mode, | ||
109 | struct clock_event_device *evt) | ||
110 | { | ||
111 | unsigned long flags; | ||
112 | |||
113 | /* | ||
114 | * The timer interrupt generation is disabled at least | ||
115 | * for enough time to call epit_set_next_event() | ||
116 | */ | ||
117 | local_irq_save(flags); | ||
118 | |||
119 | /* Disable interrupt in GPT module */ | ||
120 | epit_irq_disable(); | ||
121 | |||
122 | if (mode != clockevent_mode) { | ||
123 | /* Set event time into far-far future */ | ||
124 | |||
125 | /* Clear pending interrupt */ | ||
126 | epit_irq_acknowledge(); | ||
127 | } | ||
128 | |||
129 | /* Remember timer mode */ | ||
130 | clockevent_mode = mode; | ||
131 | local_irq_restore(flags); | ||
132 | |||
133 | switch (mode) { | ||
134 | case CLOCK_EVT_MODE_PERIODIC: | ||
135 | printk(KERN_ERR "epit_set_mode: Periodic mode is not " | ||
136 | "supported for i.MX EPIT\n"); | ||
137 | break; | ||
138 | case CLOCK_EVT_MODE_ONESHOT: | ||
139 | /* | ||
140 | * Do not put overhead of interrupt enable/disable into | ||
141 | * epit_set_next_event(), the core has about 4 minutes | ||
142 | * to call epit_set_next_event() or shutdown clock after | ||
143 | * mode switching | ||
144 | */ | ||
145 | local_irq_save(flags); | ||
146 | epit_irq_enable(); | ||
147 | local_irq_restore(flags); | ||
148 | break; | ||
149 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
150 | case CLOCK_EVT_MODE_UNUSED: | ||
151 | case CLOCK_EVT_MODE_RESUME: | ||
152 | /* Left event sources disabled, no more interrupts appear */ | ||
153 | break; | ||
154 | } | ||
155 | } | ||
156 | |||
157 | /* | ||
158 | * IRQ handler for the timer | ||
159 | */ | ||
160 | static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) | ||
161 | { | ||
162 | struct clock_event_device *evt = &clockevent_epit; | ||
163 | |||
164 | epit_irq_acknowledge(); | ||
165 | |||
166 | evt->event_handler(evt); | ||
167 | |||
168 | return IRQ_HANDLED; | ||
169 | } | ||
170 | |||
171 | static struct irqaction epit_timer_irq = { | ||
172 | .name = "i.MX EPIT Timer Tick", | ||
173 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
174 | .handler = epit_timer_interrupt, | ||
175 | }; | ||
176 | |||
177 | static struct clock_event_device clockevent_epit = { | ||
178 | .name = "epit", | ||
179 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
180 | .shift = 32, | ||
181 | .set_mode = epit_set_mode, | ||
182 | .set_next_event = epit_set_next_event, | ||
183 | .rating = 200, | ||
184 | }; | ||
185 | |||
186 | static int __init epit_clockevent_init(struct clk *timer_clk) | ||
187 | { | ||
188 | unsigned int c = clk_get_rate(timer_clk); | ||
189 | |||
190 | clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, | ||
191 | clockevent_epit.shift); | ||
192 | clockevent_epit.max_delta_ns = | ||
193 | clockevent_delta2ns(0xfffffffe, &clockevent_epit); | ||
194 | clockevent_epit.min_delta_ns = | ||
195 | clockevent_delta2ns(0x800, &clockevent_epit); | ||
196 | |||
197 | clockevent_epit.cpumask = cpumask_of(0); | ||
198 | |||
199 | clockevents_register_device(&clockevent_epit); | ||
200 | |||
201 | return 0; | ||
202 | } | ||
203 | |||
204 | void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) | ||
205 | { | ||
206 | clk_enable(timer_clk); | ||
207 | |||
208 | timer_base = base; | ||
209 | |||
210 | /* | ||
211 | * Initialise to a known state (all timers off, and timing reset) | ||
212 | */ | ||
213 | __raw_writel(0x0, timer_base + EPITCR); | ||
214 | |||
215 | __raw_writel(0xffffffff, timer_base + EPITLR); | ||
216 | __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, | ||
217 | timer_base + EPITCR); | ||
218 | |||
219 | /* init and register the timer to the framework */ | ||
220 | epit_clocksource_init(timer_clk); | ||
221 | epit_clockevent_init(timer_clk); | ||
222 | |||
223 | /* Make irqs happen */ | ||
224 | setup_irq(irq, &epit_timer_irq); | ||
225 | } | ||