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-rw-r--r--arch/arm/mm/proc-v6.S43
1 files changed, 28 insertions, 15 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac851519..b95662dedb6 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
30#define TTB_RGN_WT (2 << 3) 30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3) 31#define TTB_RGN_WB (3 << 3)
32 32
33#ifndef CONFIG_SMP 33#define TTB_FLAGS_UP TTB_RGN_WBWA
34#define TTB_FLAGS TTB_RGN_WBWA 34#define PMD_FLAGS_UP PMD_SECT_WB
35#define PMD_FLAGS PMD_SECT_WB 35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
36#else 36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
39#endif
40 37
41ENTRY(cpu_v6_proc_init) 38ENTRY(cpu_v6_proc_init)
42 mov pc, lr 39 mov pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
97#ifdef CONFIG_MMU 94#ifdef CONFIG_MMU
98 mov r2, #0 95 mov r2, #0
99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
100 orr r0, r0, #TTB_FLAGS 97 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
98 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 99 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 100 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 101 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
156 */ 154 */
157__v6_setup: 155__v6_setup:
158#ifdef CONFIG_SMP 156#ifdef CONFIG_SMP
159 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 157 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
158 ALT_UP(nop)
160 orr r0, r0, #0x20 159 orr r0, r0, #0x20
161 mcr p15, 0, r0, c1, c0, 1 160 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
161 ALT_UP(nop)
162#endif 162#endif
163 163
164 mov r0, #0 164 mov r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
169#ifdef CONFIG_MMU 169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
172 orr r4, r4, #TTB_FLAGS 172 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
173 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
173 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 174 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
174#endif /* CONFIG_MMU */ 175#endif /* CONFIG_MMU */
175 adr r5, v6_crval 176 adr r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
225__v6_proc_info: 226__v6_proc_info:
226 .long 0x0007b000 227 .long 0x0007b000
227 .long 0x0007f000 228 .long 0x0007f000
228 .long PMD_TYPE_SECT | \ 229 ALT_SMP(.long \
230 PMD_TYPE_SECT | \
231 PMD_SECT_AP_WRITE | \
232 PMD_SECT_AP_READ | \
233 PMD_FLAGS_SMP)
234 ALT_UP(.long \
235 PMD_TYPE_SECT | \
229 PMD_SECT_AP_WRITE | \ 236 PMD_SECT_AP_WRITE | \
230 PMD_SECT_AP_READ | \ 237 PMD_SECT_AP_READ | \
231 PMD_FLAGS 238 PMD_FLAGS_UP)
232 .long PMD_TYPE_SECT | \ 239 .long PMD_TYPE_SECT | \
233 PMD_SECT_XN | \ 240 PMD_SECT_XN | \
234 PMD_SECT_AP_WRITE | \ 241 PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
249__pj4_v6_proc_info: 256__pj4_v6_proc_info:
250 .long 0x560f5810 257 .long 0x560f5810
251 .long 0xff0ffff0 258 .long 0xff0ffff0
252 .long PMD_TYPE_SECT | \ 259 ALT_SMP(.long \
260 PMD_TYPE_SECT | \
261 PMD_SECT_AP_WRITE | \
262 PMD_SECT_AP_READ | \
263 PMD_FLAGS_SMP)
264 ALT_UP(.long \
265 PMD_TYPE_SECT | \
253 PMD_SECT_AP_WRITE | \ 266 PMD_SECT_AP_WRITE | \
254 PMD_SECT_AP_READ | \ 267 PMD_SECT_AP_READ | \
255 PMD_FLAGS 268 PMD_FLAGS_UP)
256 .long PMD_TYPE_SECT | \ 269 .long PMD_TYPE_SECT | \
257 PMD_SECT_XN | \ 270 PMD_SECT_XN | \
258 PMD_SECT_AP_WRITE | \ 271 PMD_SECT_AP_WRITE | \