1 files changed, 97 insertions, 100 deletions

diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 04ea836969b..8656379a830 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,109 +23,106 @@
 
 /* typesafe io address */
 #define __io_address(n)         __io(IO_ADDRESS(n))
+/* used by some plat-nomadik code */
+#define io_p2v(n)               __io_address(n)
 
-/*
- * Base address definitions for U8500 Onchip IPs. All the
- * peripherals are contained in a single 1 Mbyte region, with
- * AHB peripherals at the bottom and APB peripherals at the
- * top of the region. PER stands for PERIPHERAL region which
- * itself divided into sub regions.
- */
-#define U8500_PER3_BASE         0x80000000
-#define U8500_PER2_BASE         0x80110000
-#define U8500_PER1_BASE         0x80120000
-#define U8500_PER4_BASE         0x80150000
-
-#define U8500_PER6_BASE         0xa03c0000
-#define U8500_PER5_BASE         0xa03e0000
-#define U8500_PER7_BASE         0xa03d0000
-
-#define U8500_SVA_BASE          0xa0100000
-#define U8500_SIA_BASE          0xa0200000
-
-#define U8500_SGA_BASE          0xa0300000
-#define U8500_MCDE_BASE         0xa0350000
-#define U8500_DMA_BASE          0xa0362000
-
-#define U8500_SCU_BASE          0xa0410000
-#define U8500_GIC_CPU_BASE      0xa0410100
-#define U8500_TWD_BASE          0xa0410600
-#define U8500_GIC_DIST_BASE     0xa0411000
-#define U8500_L2CC_BASE         0xa0412000
-
-#define U8500_TWD_SIZE          0x100
-
-/* per7 base addressess */
-#define U8500_CR_BASE           (U8500_PER7_BASE + 0x8000)
-#define U8500_MTU0_BASE         (U8500_PER7_BASE + 0xa000)
-#define U8500_MTU1_BASE         (U8500_PER7_BASE + 0xb000)
-#define U8500_TZPC0_BASE        (U8500_PER7_BASE + 0xc000)
-#define U8500_CLKRST7_BASE      (U8500_PER7_BASE + 0xf000)
-
-/* per6 base addressess */
-#define U8500_RNG_BASE          (U8500_PER6_BASE + 0x0000)
-#define U8500_PKA_BASE          (U8500_PER6_BASE + 0x1000)
-#define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x2000)
-#define U8500_CRYPTO0_BASE      (U8500_PER6_BASE + 0xa000)
-#define U8500_CRYPTO1_BASE      (U8500_PER6_BASE + 0xb000)
-#define U8500_CLKRST6_BASE      (U8500_PER6_BASE + 0xf000)
-
-/* per5 base addressess */
-#define U8500_USBOTG_BASE       (U8500_PER5_BASE + 0x00000)
-#define U8500_GPIO5_BASE        (U8500_PER5_BASE + 0x1e000)
-#define U8500_CLKRST5_BASE      (U8500_PER5_BASE + 0x1f000)
-
-/* per4 base addressess */
-#define U8500_BACKUPRAM0_BASE   (U8500_PER4_BASE + 0x0000)
-#define U8500_BACKUPRAM1_BASE   (U8500_PER4_BASE + 0x1000)
-#define U8500_RTT0_BASE         (U8500_PER4_BASE + 0x2000)
-#define U8500_RTT1_BASE         (U8500_PER4_BASE + 0x3000)
-#define U8500_RTC_BASE          (U8500_PER4_BASE + 0x4000)
-#define U8500_SCR_BASE          (U8500_PER4_BASE + 0x5000)
-#define U8500_DMC_BASE          (U8500_PER4_BASE + 0x6000)
-#define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x7000)
-
-/* per3 base addressess */
-#define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
-#define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
-#define U8500_SSP1_BASE         (U8500_PER3_BASE + 0x3000)
-#define U8500_I2C0_BASE         (U8500_PER3_BASE + 0x4000)
-#define U8500_SDI2_BASE         (U8500_PER3_BASE + 0x5000)
-#define U8500_SKE_BASE          (U8500_PER3_BASE + 0x6000)
-#define U8500_UART2_BASE        (U8500_PER3_BASE + 0x7000)
-#define U8500_SDI5_BASE         (U8500_PER3_BASE + 0x8000)
-#define U8500_GPIO3_BASE        (U8500_PER3_BASE + 0xe000)
-#define U8500_CLKRST3_BASE      (U8500_PER3_BASE + 0xf000)
-
-/* per2 base addressess */
-#define U8500_I2C3_BASE         (U8500_PER2_BASE + 0x0000)
-#define U8500_SPI2_BASE         (U8500_PER2_BASE + 0x1000)
-#define U8500_SPI1_BASE         (U8500_PER2_BASE + 0x2000)
-#define U8500_PWL_BASE          (U8500_PER2_BASE + 0x3000)
-#define U8500_SDI4_BASE         (U8500_PER2_BASE + 0x4000)
-#define U8500_MSP2_BASE         (U8500_PER2_BASE + 0x7000)
-#define U8500_SDI1_BASE         (U8500_PER2_BASE + 0x8000)
-#define U8500_SDI3_BASE         (U8500_PER2_BASE + 0x9000)
-#define U8500_SPI0_BASE         (U8500_PER2_BASE + 0xa000)
-#define U8500_HSIR_BASE         (U8500_PER2_BASE + 0xb000)
-#define U8500_HSIT_BASE         (U8500_PER2_BASE + 0xc000)
-#define U8500_GPIO2_BASE        (U8500_PER2_BASE + 0xe000)
-#define U8500_CLKRST2_BASE      (U8500_PER2_BASE + 0xf000)
-
-/* per1 base addresses */
-#define U8500_UART0_BASE        (U8500_PER1_BASE + 0x0000)
-#define U8500_UART1_BASE        (U8500_PER1_BASE + 0x1000)
-#define U8500_I2C1_BASE         (U8500_PER1_BASE + 0x2000)
-#define U8500_MSP0_BASE         (U8500_PER1_BASE + 0x3000)
-#define U8500_MSP1_BASE         (U8500_PER1_BASE + 0x4000)
-#define U8500_SDI0_BASE         (U8500_PER1_BASE + 0x6000)
-#define U8500_I2C2_BASE         (U8500_PER1_BASE + 0x8000)
-#define U8500_SPI3_BASE         (U8500_PER1_BASE + 0x9000)
-#define U8500_SLIM0_BASE        (U8500_PER1_BASE + 0xa000)
-#define U8500_GPIO1_BASE        (U8500_PER1_BASE + 0xe000)
-#define U8500_CLKRST1_BASE      (U8500_PER1_BASE + 0xf000)
+#include <mach/db8500-regs.h>
+#include <mach/db5500-regs.h>
+
+#ifdef CONFIG_UX500_SOC_DB8500
+#define UX500(periph)           U8500_##periph##_BASE
+#elif defined(CONFIG_UX500_SOC_DB5500)
+#define UX500(periph)           U5500_##periph##_BASE
+#endif
+
+#define UX500_BACKUPRAM0_BASE   UX500(BACKUPRAM0)
+#define UX500_BACKUPRAM1_BASE   UX500(BACKUPRAM1)
+#define UX500_B2R2_BASE         UX500(B2R2)
+
+#define UX500_CLKRST1_BASE      UX500(CLKRST1)
+#define UX500_CLKRST2_BASE      UX500(CLKRST2)
+#define UX500_CLKRST3_BASE      UX500(CLKRST3)
+#define UX500_CLKRST5_BASE      UX500(CLKRST5)
+#define UX500_CLKRST6_BASE      UX500(CLKRST6)
+
+#define UX500_DMA_BASE          UX500(DMA)
+#define UX500_FSMC_BASE         UX500(FSMC)
+
+#define UX500_GIC_CPU_BASE      UX500(GIC_CPU)
+#define UX500_GIC_DIST_BASE     UX500(GIC_DIST)
+
+#define UX500_I2C1_BASE         UX500(I2C1)
+#define UX500_I2C2_BASE         UX500(I2C2)
+#define UX500_I2C3_BASE         UX500(I2C3)
+
+#define UX500_L2CC_BASE         UX500(L2CC)
+#define UX500_MCDE_BASE         UX500(MCDE)
+#define UX500_MTU0_BASE         UX500(MTU0)
+#define UX500_MTU1_BASE         UX500(MTU1)
+#define UX500_PRCMU_BASE        UX500(PRCMU)
+
+#define UX500_RNG_BASE          UX500(RNG)
+#define UX500_RTC_BASE          UX500(RTC)
+
+#define UX500_SCU_BASE          UX500(SCU)
+
+#define UX500_SDI0_BASE         UX500(SDI0)
+#define UX500_SDI1_BASE         UX500(SDI1)
+#define UX500_SDI2_BASE         UX500(SDI2)
+#define UX500_SDI3_BASE         UX500(SDI3)
+#define UX500_SDI4_BASE         UX500(SDI4)
+
+#define UX500_SPI0_BASE         UX500(SPI0)
+#define UX500_SPI1_BASE         UX500(SPI1)
+#define UX500_SPI2_BASE         UX500(SPI2)
+#define UX500_SPI3_BASE         UX500(SPI3)
+
+#define UX500_SIA_BASE          UX500(SIA)
+#define UX500_SVA_BASE          UX500(SVA)
+
+#define UX500_TWD_BASE          UX500(TWD)
+
+#define UX500_UART0_BASE        UX500(UART0)
+#define UX500_UART1_BASE        UX500(UART1)
+#define UX500_UART2_BASE        UX500(UART2)
+
+#define UX500_USBOTG_BASE       UX500(USBOTG)
 
 /* ST-Ericsson modified pl022 id */
 #define SSP_PER_ID              0x01080022
 
+#ifndef __ASSEMBLY__
+
+#include <asm/cputype.h>
+
+static inline bool cpu_is_u8500(void)
+{
+#ifdef CONFIG_UX500_SOC_DB8500
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+static inline bool cpu_is_u8500ed(void)
+{
+        return cpu_is_u8500() && (read_cpuid_id() & 15) == 0;
+}
+
+static inline bool cpu_is_u8500v1(void)
+{
+        return cpu_is_u8500() && (read_cpuid_id() & 15) == 1;
+}
+
+static inline bool cpu_is_u5500(void)
+{
+#ifdef CONFIG_UX500_SOC_DB5500
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+#endif
+
 #endif                          /* __MACH_HARDWARE_H */