aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra/tegra3_dvfs.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_dvfs.c968
1 files changed, 968 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
new file mode 100644
index 00000000000..48c4384b1aa
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -0,0 +1,968 @@
1/*
2 * arch/arm/mach-tegra/tegra3_dvfs.c
3 *
4 * Copyright (C) 2010-2011 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/string.h>
20#include <linux/module.h>
21#include <linux/clk.h>
22#include <linux/kobject.h>
23#include <linux/err.h>
24
25#include "clock.h"
26#include "dvfs.h"
27#include "fuse.h"
28#include "board.h"
29#include "tegra3_emc.h"
30
31static bool tegra_dvfs_cpu_disabled;
32static bool tegra_dvfs_core_disabled;
33static struct dvfs *cpu_dvfs;
34
35static const int cpu_millivolts[MAX_DVFS_FREQS] = {
36 800, 825, 850, 875, 900, 912, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175, 1200, 1212, 1237};
37
38static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = {
39 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50};
40
41static const int core_millivolts[MAX_DVFS_FREQS] = {
42 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350};
43
44#define KHZ 1000
45#define MHZ 1000000
46
47/* VDD_CPU >= (VDD_CORE - cpu_below_core) */
48/* VDD_CORE >= min_level(VDD_CPU), see tegra3_get_core_floor_mv() below */
49#define VDD_CPU_BELOW_VDD_CORE 300
50static int cpu_below_core = VDD_CPU_BELOW_VDD_CORE;
51
52#define VDD_SAFE_STEP 100
53
54static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = {
55 .reg_id = "vdd_cpu",
56 .max_millivolts = 1250,
57 .min_millivolts = 800,
58 .step = VDD_SAFE_STEP,
59 .jmp_to_zero = true,
60};
61
62static struct dvfs_rail tegra3_dvfs_rail_vdd_core = {
63 .reg_id = "vdd_core",
64 .max_millivolts = 1350,
65 .min_millivolts = 950,
66 .step = VDD_SAFE_STEP,
67};
68
69static struct dvfs_rail *tegra3_dvfs_rails[] = {
70 &tegra3_dvfs_rail_vdd_cpu,
71 &tegra3_dvfs_rail_vdd_core,
72};
73
74static int tegra3_get_core_floor_mv(int cpu_mv)
75{
76 if (cpu_mv < 800)
77 return 950;
78 if (cpu_mv < 900)
79 return 1000;
80 if (cpu_mv < 1000)
81 return 1100;
82 if ((tegra_cpu_speedo_id() < 2) ||
83 (tegra_cpu_speedo_id() == 4) ||
84 (tegra_cpu_speedo_id() == 7) ||
85 (tegra_cpu_speedo_id() == 8))
86 return 1200;
87 if (cpu_mv < 1100)
88 return 1200;
89 if (cpu_mv <= 1250)
90 return 1300;
91 BUG();
92}
93
94/* vdd_core must be >= min_level as a function of vdd_cpu */
95static int tegra3_dvfs_rel_vdd_cpu_vdd_core(struct dvfs_rail *vdd_cpu,
96 struct dvfs_rail *vdd_core)
97{
98 int core_floor = max(vdd_cpu->new_millivolts, vdd_cpu->millivolts);
99 core_floor = tegra3_get_core_floor_mv(core_floor);
100 return max(vdd_core->new_millivolts, core_floor);
101}
102
103/* vdd_cpu must be >= (vdd_core - cpu_below_core) */
104static int tegra3_dvfs_rel_vdd_core_vdd_cpu(struct dvfs_rail *vdd_core,
105 struct dvfs_rail *vdd_cpu)
106{
107 int cpu_floor;
108
109 if (vdd_cpu->new_millivolts == 0)
110 return 0; /* If G CPU is off, core relations can be ignored */
111
112 cpu_floor = max(vdd_core->new_millivolts, vdd_core->millivolts) -
113 cpu_below_core;
114 return max(vdd_cpu->new_millivolts, cpu_floor);
115}
116
117static struct dvfs_relationship tegra3_dvfs_relationships[] = {
118 {
119 .from = &tegra3_dvfs_rail_vdd_cpu,
120 .to = &tegra3_dvfs_rail_vdd_core,
121 .solve = tegra3_dvfs_rel_vdd_cpu_vdd_core,
122 .solved_at_nominal = true,
123 },
124 {
125 .from = &tegra3_dvfs_rail_vdd_core,
126 .to = &tegra3_dvfs_rail_vdd_cpu,
127 .solve = tegra3_dvfs_rel_vdd_core_vdd_cpu,
128 },
129};
130
131#define CPU_DVFS(_clk_name, _speedo_id, _process_id, _mult, _freqs...) \
132 { \
133 .clk_name = _clk_name, \
134 .speedo_id = _speedo_id, \
135 .process_id = _process_id, \
136 .freqs = {_freqs}, \
137 .freqs_mult = _mult, \
138 .millivolts = cpu_millivolts, \
139 .auto_dvfs = true, \
140 .dvfs_rail = &tegra3_dvfs_rail_vdd_cpu, \
141 }
142
143static struct dvfs cpu_dvfs_table[] = {
144 /* Cpu voltages (mV): 800, 825, 850, 875, 900, 912, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175, 1200, 1212, 1237 */
145 CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 684, 684, 817, 817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
146 CPU_DVFS("cpu_g", 0, 1, MHZ, 1, 1, 807, 807, 948, 948, 1117, 1171, 1206, 1300),
147 CPU_DVFS("cpu_g", 0, 2, MHZ, 1, 1, 883, 883, 1039, 1039, 1178, 1206, 1300),
148 CPU_DVFS("cpu_g", 0, 3, MHZ, 1, 1, 931, 931, 1102, 1102, 1216, 1300),
149
150 CPU_DVFS("cpu_g", 1, 0, MHZ, 460, 460, 550, 550, 680, 680, 820, 970, 1040, 1080, 1150, 1200, 1280, 1300),
151 CPU_DVFS("cpu_g", 1, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1300),
152 CPU_DVFS("cpu_g", 1, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1300),
153 CPU_DVFS("cpu_g", 1, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1300),
154
155 CPU_DVFS("cpu_g", 2, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1250, 1300, 1330, 1400),
156 CPU_DVFS("cpu_g", 2, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1280, 1300, 1350, 1400),
157 CPU_DVFS("cpu_g", 2, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1300, 1350, 1400),
158
159 CPU_DVFS("cpu_g", 3, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1250, 1300, 1330, 1400),
160 CPU_DVFS("cpu_g", 3, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1280, 1300, 1350, 1400),
161 CPU_DVFS("cpu_g", 3, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1300, 1350, 1400),
162
163 CPU_DVFS("cpu_g", 4, 0, MHZ, 460, 460, 550, 550, 680, 680, 820, 970, 1040, 1080, 1150, 1200, 1240, 1280, 1320, 1360, 1360, 1500),
164 CPU_DVFS("cpu_g", 4, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1250, 1300, 1330, 1360, 1400, 1500),
165 CPU_DVFS("cpu_g", 4, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1280, 1300, 1340, 1380, 1500),
166 CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1500),
167
168 CPU_DVFS("cpu_g", 5, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
169 CPU_DVFS("cpu_g", 5, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
170
171 CPU_DVFS("cpu_g", 6, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
172 CPU_DVFS("cpu_g", 6, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
173
174 CPU_DVFS("cpu_g", 7, 0, MHZ, 460, 460, 550, 550, 680, 680, 820, 970, 1040, 1080, 1150, 1200, 1280, 1300),
175 CPU_DVFS("cpu_g", 7, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1300),
176 CPU_DVFS("cpu_g", 7, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1300),
177 CPU_DVFS("cpu_g", 7, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1300),
178 CPU_DVFS("cpu_g", 7, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1300),
179
180 CPU_DVFS("cpu_g", 8, 0, MHZ, 460, 460, 550, 550, 680, 680, 820, 970, 1040, 1080, 1150, 1200, 1280, 1300),
181 CPU_DVFS("cpu_g", 8, 1, MHZ, 480, 480, 650, 650, 780, 780, 990, 1040, 1100, 1200, 1300),
182 CPU_DVFS("cpu_g", 8, 2, MHZ, 520, 520, 700, 700, 860, 860, 1050, 1150, 1200, 1300),
183 CPU_DVFS("cpu_g", 8, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1300),
184 CPU_DVFS("cpu_g", 8, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1300),
185
186 CPU_DVFS("cpu_g", 9, -1, MHZ, 1, 1, 1, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900),
187 CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900),
188 CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600),
189
190 CPU_DVFS("cpu_g", 12, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
191 CPU_DVFS("cpu_g", 12, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
192
193 CPU_DVFS("cpu_g", 13, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
194 CPU_DVFS("cpu_g", 13, 4, MHZ, 550, 550, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
195
196 /*
197 * "Safe entry" to be used when no match for chip speedo, process
198 * corner is found (just to boot at low rate); must be the last one
199 */
200 CPU_DVFS("cpu_g", -1, -1, MHZ, 1, 1, 216, 216, 300),
201};
202
203#define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \
204 { \
205 .clk_name = _clk_name, \
206 .speedo_id = _speedo_id, \
207 .process_id = -1, \
208 .freqs = {_freqs}, \
209 .freqs_mult = _mult, \
210 .millivolts = core_millivolts, \
211 .auto_dvfs = _auto, \
212 .dvfs_rail = &tegra3_dvfs_rail_vdd_core, \
213 }
214
215static struct dvfs core_dvfs_table[] = {
216 /* Core voltages (mV): 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350 */
217 /* Clock limits for internal blocks, PLLs */
218 CORE_DVFS("cpu_lp", 0, 1, KHZ, 1, 294000, 342000, 427000, 475000, 500000, 500000, 500000, 500000),
219 CORE_DVFS("cpu_lp", 1, 1, KHZ, 204000, 294000, 342000, 427000, 475000, 500000, 500000, 500000, 500000),
220 CORE_DVFS("cpu_lp", 2, 1, KHZ, 204000, 295000, 370000, 428000, 475000, 513000, 579000, 620000, 620000),
221 CORE_DVFS("cpu_lp", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 450000, 450000, 450000),
222
223 CORE_DVFS("emc", 0, 1, KHZ, 1, 266500, 266500, 266500, 266500, 533000, 533000, 533000, 533000),
224 CORE_DVFS("emc", 1, 1, KHZ, 102000, 408000, 408000, 408000, 408000, 667000, 667000, 667000, 667000),
225 CORE_DVFS("emc", 2, 1, KHZ, 102000, 408000, 408000, 408000, 408000, 667000, 667000, 800000, 900000),
226 CORE_DVFS("emc", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 625000, 625000, 625000),
227
228 CORE_DVFS("sbus", 0, 1, KHZ, 1, 136000, 164000, 191000, 216000, 216000, 216000, 216000, 216000),
229 CORE_DVFS("sbus", 1, 1, KHZ, 51000, 205000, 205000, 227000, 227000, 267000, 267000, 267000, 267000),
230 CORE_DVFS("sbus", 2, 1, KHZ, 51000, 205000, 205000, 227000, 227000, 267000, 334000, 334000, 334000),
231 CORE_DVFS("sbus", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 378000, 378000, 378000),
232
233 CORE_DVFS("vi", 0, 1, KHZ, 1, 216000, 285000, 300000, 300000, 300000, 300000, 300000, 300000),
234 CORE_DVFS("vi", 1, 1, KHZ, 1, 216000, 267000, 300000, 371000, 409000, 409000, 409000, 409000),
235 CORE_DVFS("vi", 2, 1, KHZ, 1, 219000, 267000, 300000, 371000, 409000, 425000, 425000, 425000),
236 CORE_DVFS("vi", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 470000, 470000, 470000),
237
238 CORE_DVFS("vde", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
239 CORE_DVFS("mpe", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
240 CORE_DVFS("2d", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
241 CORE_DVFS("epp", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
242 CORE_DVFS("3d", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
243 CORE_DVFS("3d2", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
244 CORE_DVFS("se", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
245
246 CORE_DVFS("vde", 1, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
247 CORE_DVFS("mpe", 1, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
248 CORE_DVFS("2d", 1, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
249 CORE_DVFS("epp", 1, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
250 CORE_DVFS("3d", 1, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
251 CORE_DVFS("3d2", 1, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
252 CORE_DVFS("se", 1, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
253
254 CORE_DVFS("vde", 2, 1, KHZ, 1, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000),
255 CORE_DVFS("mpe", 2, 1, KHZ, 1, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
256 CORE_DVFS("2d", 2, 1, KHZ, 1, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
257 CORE_DVFS("epp", 2, 1, KHZ, 1, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
258 CORE_DVFS("3d", 2, 1, KHZ, 1, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
259 CORE_DVFS("3d2", 2, 1, KHZ, 1, 247000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
260 CORE_DVFS("se", 2, 1, KHZ, 1, 267000, 304000, 361000, 408000, 446000, 484000, 520000, 600000),
261
262 CORE_DVFS("vde", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
263 CORE_DVFS("mpe", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
264 CORE_DVFS("2d", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
265 CORE_DVFS("epp", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
266 CORE_DVFS("3d", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
267 CORE_DVFS("3d2", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
268 CORE_DVFS("se", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 625000, 625000, 625000),
269
270 CORE_DVFS("host1x", 0, 1, KHZ, 1, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 267000),
271 CORE_DVFS("host1x", 1, 1, KHZ, 1, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 267000),
272 CORE_DVFS("host1x", 2, 1, KHZ, 1, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 300000),
273 CORE_DVFS("host1x", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 242000, 242000, 242000),
274
275 CORE_DVFS("cbus", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
276 CORE_DVFS("cbus", 1, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
277 CORE_DVFS("cbus", 2, 1, KHZ, 1, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000),
278 CORE_DVFS("cbus", 3, 1, KHZ, 1, 484000, 484000, 484000, 484000, 484000, 484000, 484000, 484000),
279
280 CORE_DVFS("pll_c", -1, 1, KHZ, 533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000, 1200000),
281
282 /*
283 * PLLM dvfs is common across all speedo IDs with one special exception
284 * for T30 and T33, rev A02+, provided PLLM usage is restricted. Both
285 * common and restricted table are included, and table selection is
286 * handled by is_pllm_dvfs() below.
287 */
288 CORE_DVFS("pll_m", -1, 1, KHZ, 533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000, 1066000),
289#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
290 CORE_DVFS("pll_m", 2, 1, KHZ, 533000, 800000, 800000, 800000, 800000, 1066000, 1066000, 1066000, 1066000),
291#endif
292 /* Core voltages (mV): 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350 */
293 /* Clock limits for I/O peripherals */
294 CORE_DVFS("mipi", 0, 1, KHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1),
295 CORE_DVFS("mipi", 1, 1, KHZ, 1, 1, 1, 1, 1, 60000, 60000, 60000, 60000),
296 CORE_DVFS("mipi", 2, 1, KHZ, 1, 1, 1, 1, 1, 60000, 60000, 60000, 60000),
297 CORE_DVFS("mipi", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 1, 1, 1),
298
299 CORE_DVFS("fuse_burn", -1, 1, KHZ, 1, 1, 1, 1, 26000, 26000, 26000, 26000, 26000),
300 CORE_DVFS("sdmmc1", -1, 1, KHZ, 104000, 104000, 104000, 104000, 104000, 208000, 208000, 208000, 208000),
301 CORE_DVFS("sdmmc3", -1, 1, KHZ, 104000, 104000, 104000, 104000, 104000, 208000, 208000, 208000, 208000),
302 CORE_DVFS("ndflash", -1, 1, KHZ, 1, 120000, 120000, 120000, 200000, 200000, 200000, 200000, 200000),
303
304 CORE_DVFS("nor", 0, 1, KHZ, 1, 115000, 130000, 130000, 133000, 133000, 133000, 133000, 133000),
305 CORE_DVFS("nor", 1, 1, KHZ, 1, 115000, 130000, 130000, 133000, 133000, 133000, 133000, 133000),
306 CORE_DVFS("nor", 2, 1, KHZ, 1, 115000, 130000, 130000, 133000, 133000, 133000, 133000, 133000),
307 CORE_DVFS("nor", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 108000, 108000, 108000),
308
309 CORE_DVFS("sbc1", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
310 CORE_DVFS("sbc2", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
311 CORE_DVFS("sbc3", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
312 CORE_DVFS("sbc4", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
313 CORE_DVFS("sbc5", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
314 CORE_DVFS("sbc6", -1, 1, KHZ, 1, 52000, 60000, 60000, 60000, 100000, 100000, 100000, 100000),
315
316 CORE_DVFS("usbd", -1, 1, KHZ, 1, 480000, 480000, 480000, 480000, 480000, 480000, 480000, 480000),
317 CORE_DVFS("usb2", -1, 1, KHZ, 1, 480000, 480000, 480000, 480000, 480000, 480000, 480000, 480000),
318 CORE_DVFS("usb3", -1, 1, KHZ, 1, 480000, 480000, 480000, 480000, 480000, 480000, 480000, 480000),
319
320 CORE_DVFS("sata", -1, 1, KHZ, 1, 216000, 216000, 216000, 216000, 216000, 216000, 216000, 216000),
321 CORE_DVFS("sata_oob", -1, 1, KHZ, 1, 216000, 216000, 216000, 216000, 216000, 216000, 216000, 216000),
322 CORE_DVFS("pcie", -1, 1, KHZ, 1, 250000, 250000, 250000, 250000, 250000, 250000, 250000, 250000),
323 CORE_DVFS("afi", -1, 1, KHZ, 1, 250000, 250000, 250000, 250000, 250000, 250000, 250000, 250000),
324 CORE_DVFS("pll_e", -1, 1, KHZ, 1, 100000, 100000, 100000, 100000, 100000, 100000, 100000, 100000),
325
326 CORE_DVFS("tvdac", -1, 1, KHZ, 1, 220000, 220000, 220000, 220000, 220000, 220000, 220000, 220000),
327 CORE_DVFS("tvo", -1, 1, KHZ, 1, 1, 297000, 297000, 297000, 297000, 297000, 297000, 297000),
328 CORE_DVFS("cve", -1, 1, KHZ, 1, 1, 297000, 297000, 297000, 297000, 297000, 297000, 297000),
329 CORE_DVFS("dsia", -1, 1, KHZ, 1, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000),
330 CORE_DVFS("dsib", -1, 1, KHZ, 1, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000),
331 CORE_DVFS("hdmi", -1, 1, KHZ, 1, 148500, 148500, 148500, 148500, 148500, 148500, 148500, 148500),
332
333 /*
334 * The clock rate for the display controllers that determines the
335 * necessary core voltage depends on a divider that is internal
336 * to the display block. Disable auto-dvfs on the display clocks,
337 * and let the display driver call tegra_dvfs_set_rate manually
338 */
339 CORE_DVFS("disp1", 0, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000),
340 CORE_DVFS("disp1", 1, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000),
341 CORE_DVFS("disp1", 2, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000),
342 CORE_DVFS("disp1", 3, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000),
343
344 CORE_DVFS("disp2", 0, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000),
345 CORE_DVFS("disp2", 1, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000),
346 CORE_DVFS("disp2", 2, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000),
347 CORE_DVFS("disp2", 3, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000),
348
349 CORE_DVFS("pwm", -1, 1, KHZ, 1, 408000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
350 CORE_DVFS("spdif_out", -1, 1, KHZ, 1, 26000, 26000, 26000, 26000, 26000, 26000, 26000, 26000),
351};
352
353
354int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp)
355{
356 int ret;
357
358 ret = param_set_bool(arg, kp);
359 if (ret)
360 return ret;
361
362 if (tegra_dvfs_core_disabled)
363 tegra_dvfs_rail_disable(&tegra3_dvfs_rail_vdd_core);
364 else
365 tegra_dvfs_rail_enable(&tegra3_dvfs_rail_vdd_core);
366
367 return 0;
368}
369
370int tegra_dvfs_disable_cpu_set(const char *arg, const struct kernel_param *kp)
371{
372 int ret;
373
374 ret = param_set_bool(arg, kp);
375 if (ret)
376 return ret;
377
378 if (tegra_dvfs_cpu_disabled)
379 tegra_dvfs_rail_disable(&tegra3_dvfs_rail_vdd_cpu);
380 else
381 tegra_dvfs_rail_enable(&tegra3_dvfs_rail_vdd_cpu);
382
383 return 0;
384}
385
386int tegra_dvfs_disable_get(char *buffer, const struct kernel_param *kp)
387{
388 return param_get_bool(buffer, kp);
389}
390
391static struct kernel_param_ops tegra_dvfs_disable_core_ops = {
392 .set = tegra_dvfs_disable_core_set,
393 .get = tegra_dvfs_disable_get,
394};
395
396static struct kernel_param_ops tegra_dvfs_disable_cpu_ops = {
397 .set = tegra_dvfs_disable_cpu_set,
398 .get = tegra_dvfs_disable_get,
399};
400
401module_param_cb(disable_core, &tegra_dvfs_disable_core_ops,
402 &tegra_dvfs_core_disabled, 0644);
403module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops,
404 &tegra_dvfs_cpu_disabled, 0644);
405
406static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d)
407{
408#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
409 /* Do not apply common PLLM dvfs table on T30, T33, T37 rev A02+ and
410 do not apply restricted PLLM dvfs table for other SKUs/revs */
411 int cpu = tegra_cpu_speedo_id();
412 if (((cpu == 2) || (cpu == 5) || (cpu == 13)) ==
413 (d->speedo_id == -1))
414 return false;
415#endif
416 /* Check if PLLM boot frequency can be applied to clock tree at
417 minimum voltage. If yes, no need to enable dvfs on PLLM */
418 if (clk_get_rate_all_locked(c) <= d->freqs[0] * d->freqs_mult)
419 return false;
420
421 return true;
422}
423
424static void __init init_dvfs_one(struct dvfs *d, int nominal_mv_index)
425{
426 int ret;
427 struct clk *c = tegra_get_clock_by_name(d->clk_name);
428
429 if (!c) {
430 pr_debug("tegra3_dvfs: no clock found for %s\n",
431 d->clk_name);
432 return;
433 }
434
435 /*
436 * Update max rate for auto-dvfs clocks, except EMC.
437 * EMC is a special case, since EMC dvfs is board dependent: max rate
438 * and EMC scaling frequencies are determined by tegra BCT (flashed
439 * together with the image) and board specific EMC DFS table; we will
440 * check the scaling ladder against nominal core voltage when the table
441 * is loaded (and if on particular board the table is not loaded, EMC
442 * scaling is disabled).
443 */
444 if (!(c->flags & PERIPH_EMC_ENB) && d->auto_dvfs) {
445 BUG_ON(!d->freqs[nominal_mv_index]);
446 tegra_init_max_rate(
447 c, d->freqs[nominal_mv_index] * d->freqs_mult);
448 }
449 d->max_millivolts = d->dvfs_rail->nominal_millivolts;
450
451 /*
452 * Check if we may skip enabling dvfs on PLLM. PLLM is a special case,
453 * since its frequency never exceeds boot rate, and configuration with
454 * restricted PLLM usage is possible.
455 */
456 if (!(c->flags & PLLM) || is_pllm_dvfs(c, d)) {
457 ret = tegra_enable_dvfs_on_clk(c, d);
458 if (ret)
459 pr_err("tegra3_dvfs: failed to enable dvfs on %s\n",
460 c->name);
461 }
462}
463
464static void __init init_dvfs_cold(struct dvfs *d, int nominal_mv_index)
465{
466 int i;
467 unsigned long offs;
468
469 BUG_ON((nominal_mv_index == 0) || (nominal_mv_index > d->num_freqs));
470
471 for (i = 0; i < d->num_freqs; i++) {
472 offs = cpu_cold_offs_mhz[i] * MHZ;
473 if (i > nominal_mv_index)
474 d->alt_freqs[i] = d->alt_freqs[i - 1];
475 else if (d->freqs[i] > offs)
476 d->alt_freqs[i] = d->freqs[i] - offs;
477 else {
478 d->alt_freqs[i] = d->freqs[i];
479 pr_warn("tegra3_dvfs: cold offset %lu is too high for"
480 " regular dvfs limit %lu\n", offs, d->freqs[i]);
481 }
482
483 if (i)
484 BUG_ON(d->alt_freqs[i] < d->alt_freqs[i - 1]);
485 }
486 d->alt_freqs_state = ALT_FREQS_DISABLED;
487}
488
489static bool __init match_dvfs_one(struct dvfs *d, int speedo_id, int process_id)
490{
491 if ((d->process_id != -1 && d->process_id != process_id) ||
492 (d->speedo_id != -1 && d->speedo_id != speedo_id)) {
493 pr_debug("tegra3_dvfs: rejected %s speedo %d,"
494 " process %d\n", d->clk_name, d->speedo_id,
495 d->process_id);
496 return false;
497 }
498 return true;
499}
500
501static int __init get_cpu_nominal_mv_index(
502 int speedo_id, int process_id, struct dvfs **cpu_dvfs)
503{
504 int i, j, mv;
505 struct dvfs *d;
506 struct clk *c;
507
508 /*
509 * Find maximum cpu voltage that satisfies cpu_to_core dependency for
510 * nominal core voltage ("solve from cpu to core at nominal"). Clip
511 * result to the nominal cpu level for the chips with this speedo_id.
512 */
513 mv = tegra3_dvfs_rail_vdd_core.nominal_millivolts;
514 for (i = 0; i < MAX_DVFS_FREQS; i++) {
515 if ((cpu_millivolts[i] == 0) ||
516 tegra3_get_core_floor_mv(cpu_millivolts[i]) > mv)
517 break;
518 }
519 BUG_ON(i == 0);
520 mv = cpu_millivolts[i - 1];
521 BUG_ON(mv < tegra3_dvfs_rail_vdd_cpu.min_millivolts);
522 mv = min(mv, tegra_cpu_speedo_mv());
523
524 /*
525 * Find matching cpu dvfs entry, and use it to determine index to the
526 * final nominal voltage, that satisfies the following requirements:
527 * - allows CPU to run at minimum of the maximum rates specified in
528 * the dvfs entry and clock tree
529 * - does not violate cpu_to_core dependency as determined above
530 */
531 for (i = 0, j = 0; j < ARRAY_SIZE(cpu_dvfs_table); j++) {
532 d = &cpu_dvfs_table[j];
533 if (match_dvfs_one(d, speedo_id, process_id)) {
534 c = tegra_get_clock_by_name(d->clk_name);
535 BUG_ON(!c);
536
537 for (; i < MAX_DVFS_FREQS; i++) {
538 if ((d->freqs[i] == 0) ||
539 (cpu_millivolts[i] == 0) ||
540 (mv < cpu_millivolts[i]))
541 break;
542
543 if (c->max_rate <= d->freqs[i]*d->freqs_mult) {
544 i++;
545 break;
546 }
547 }
548 break;
549 }
550 }
551
552 BUG_ON(i == 0);
553 if (j == (ARRAY_SIZE(cpu_dvfs_table) - 1))
554 pr_err("tegra3_dvfs: WARNING!!!\n"
555 "tegra3_dvfs: no cpu dvfs table found for chip speedo_id"
556 " %d and process_id %d: set CPU rate limit at %lu\n"
557 "tegra3_dvfs: WARNING!!!\n",
558 speedo_id, process_id, d->freqs[i-1] * d->freqs_mult);
559
560 *cpu_dvfs = d;
561 return (i - 1);
562}
563
564static int __init get_core_nominal_mv_index(int speedo_id)
565{
566 int i;
567 int mv = tegra_core_speedo_mv();
568 int core_edp_limit = get_core_edp();
569
570 /*
571 * Start with nominal level for the chips with this speedo_id. Then,
572 * make sure core nominal voltage is below edp limit for the board
573 * (if edp limit is set).
574 */
575 if (core_edp_limit)
576 mv = min(mv, core_edp_limit);
577
578 /* Round nominal level down to the nearest core scaling step */
579 for (i = 0; i < MAX_DVFS_FREQS; i++) {
580 if ((core_millivolts[i] == 0) || (mv < core_millivolts[i]))
581 break;
582 }
583
584 if (i == 0) {
585 pr_err("tegra3_dvfs: unable to adjust core dvfs table to"
586 " nominal voltage %d\n", mv);
587 return -ENOSYS;
588 }
589 return (i - 1);
590}
591
592void __init tegra_soc_init_dvfs(void)
593{
594 int cpu_speedo_id = tegra_cpu_speedo_id();
595 int soc_speedo_id = tegra_soc_speedo_id();
596 int cpu_process_id = tegra_cpu_process_id();
597 int core_process_id = tegra_core_process_id();
598
599 int i;
600 int core_nominal_mv_index;
601 int cpu_nominal_mv_index;
602
603#ifndef CONFIG_TEGRA_CORE_DVFS
604 tegra_dvfs_core_disabled = true;
605#endif
606#ifndef CONFIG_TEGRA_CPU_DVFS
607 tegra_dvfs_cpu_disabled = true;
608#endif
609
610 /*
611 * Find nominal voltages for core (1st) and cpu rails before rail
612 * init. Nominal voltage index in the scaling ladder will also be
613 * used to determine max dvfs frequency for the respective domains.
614 */
615 core_nominal_mv_index = get_core_nominal_mv_index(soc_speedo_id);
616 if (core_nominal_mv_index < 0) {
617 tegra3_dvfs_rail_vdd_core.disabled = true;
618 tegra_dvfs_core_disabled = true;
619 core_nominal_mv_index = 0;
620 }
621 tegra3_dvfs_rail_vdd_core.nominal_millivolts =
622 core_millivolts[core_nominal_mv_index];
623
624 cpu_nominal_mv_index = get_cpu_nominal_mv_index(
625 cpu_speedo_id, cpu_process_id, &cpu_dvfs);
626 BUG_ON((cpu_nominal_mv_index < 0) || (!cpu_dvfs));
627 tegra3_dvfs_rail_vdd_cpu.nominal_millivolts =
628 cpu_millivolts[cpu_nominal_mv_index];
629
630 /* Init rail structures and dependencies */
631 tegra_dvfs_init_rails(tegra3_dvfs_rails, ARRAY_SIZE(tegra3_dvfs_rails));
632 tegra_dvfs_add_relationships(tegra3_dvfs_relationships,
633 ARRAY_SIZE(tegra3_dvfs_relationships));
634
635 /* Search core dvfs table for speedo/process matching entries and
636 initialize dvfs-ed clocks */
637 for (i = 0; i < ARRAY_SIZE(core_dvfs_table); i++) {
638 struct dvfs *d = &core_dvfs_table[i];
639 if (!match_dvfs_one(d, soc_speedo_id, core_process_id))
640 continue;
641 init_dvfs_one(d, core_nominal_mv_index);
642 }
643
644 /* Initialize matching cpu dvfs entry already found when nominal
645 voltage was determined */
646 init_dvfs_one(cpu_dvfs, cpu_nominal_mv_index);
647 init_dvfs_cold(cpu_dvfs, cpu_nominal_mv_index);
648
649 /* Finally disable dvfs on rails if necessary */
650 if (tegra_dvfs_core_disabled)
651 tegra_dvfs_rail_disable(&tegra3_dvfs_rail_vdd_core);
652 if (tegra_dvfs_cpu_disabled)
653 tegra_dvfs_rail_disable(&tegra3_dvfs_rail_vdd_cpu);
654
655 pr_info("tegra dvfs: VDD_CPU nominal %dmV, scaling %s\n",
656 tegra3_dvfs_rail_vdd_cpu.nominal_millivolts,
657 tegra_dvfs_cpu_disabled ? "disabled" : "enabled");
658 pr_info("tegra dvfs: VDD_CORE nominal %dmV, scaling %s\n",
659 tegra3_dvfs_rail_vdd_core.nominal_millivolts,
660 tegra_dvfs_core_disabled ? "disabled" : "enabled");
661}
662
663void tegra_cpu_dvfs_alter(int edp_thermal_index, bool before_clk_update)
664{
665 bool enable = !edp_thermal_index;
666
667 if (enable != before_clk_update) {
668 int ret = tegra_dvfs_alt_freqs_set(cpu_dvfs, enable);
669 WARN_ONCE(ret, "tegra dvfs: failed to set CPU alternative"
670 " frequency limits for cold temeperature\n");
671 }
672}
673
674int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail)
675{
676 int ret = 0;
677
678 if (tegra_emc_get_dram_type() != DRAM_TYPE_DDR3)
679 return ret;
680
681 if (((&tegra3_dvfs_rail_vdd_core == rail) &&
682 (rail->nominal_millivolts > TEGRA_EMC_BRIDGE_MVOLTS_MIN)) ||
683 ((&tegra3_dvfs_rail_vdd_cpu == rail) &&
684 (tegra3_get_core_floor_mv(rail->nominal_millivolts) >
685 TEGRA_EMC_BRIDGE_MVOLTS_MIN))) {
686 struct clk *bridge = tegra_get_clock_by_name("bridge.emc");
687 BUG_ON(!bridge);
688
689 ret = clk_enable(bridge);
690 pr_info("%s: %s: %s bridge.emc\n", __func__,
691 rail->reg_id, ret ? "failed to enable" : "enabled");
692 }
693 return ret;
694}
695
696int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
697{
698 if (tegra_emc_get_dram_type() != DRAM_TYPE_DDR3)
699 return 0;
700
701 if (((&tegra3_dvfs_rail_vdd_core == rail) &&
702 (rail->nominal_millivolts > TEGRA_EMC_BRIDGE_MVOLTS_MIN)) ||
703 ((&tegra3_dvfs_rail_vdd_cpu == rail) &&
704 (tegra3_get_core_floor_mv(rail->nominal_millivolts) >
705 TEGRA_EMC_BRIDGE_MVOLTS_MIN))) {
706 struct clk *bridge = tegra_get_clock_by_name("bridge.emc");
707 BUG_ON(!bridge);
708
709 clk_disable(bridge);
710 pr_info("%s: %s: disabled bridge.emc\n",
711 __func__, rail->reg_id);
712 }
713 return 0;
714}
715
716/*
717 * sysfs and dvfs interfaces to cap tegra core domains frequencies
718 */
719static DEFINE_MUTEX(core_cap_lock);
720
721struct core_cap {
722 int refcnt;
723 int level;
724};
725static struct core_cap tegra3_core_cap;
726static struct core_cap kdvfs_core_cap;
727static struct core_cap user_core_cap;
728
729static struct kobject *cap_kobj;
730
731/* Arranged in order required for enabling/lowering the cap */
732static struct {
733 const char *cap_name;
734 struct clk *cap_clk;
735 unsigned long freqs[MAX_DVFS_FREQS];
736} core_cap_table[] = {
737 { .cap_name = "cap.cbus" },
738 { .cap_name = "cap.sclk" },
739 { .cap_name = "cap.emc" },
740};
741
742
743static void core_cap_level_set(int level)
744{
745 int i, j;
746
747 for (j = 0; j < ARRAY_SIZE(core_millivolts); j++) {
748 int v = core_millivolts[j];
749 if ((v == 0) || (level < v))
750 break;
751 }
752 j = (j == 0) ? 0 : j - 1;
753 level = core_millivolts[j];
754
755 if (level < tegra3_core_cap.level) {
756 for (i = 0; i < ARRAY_SIZE(core_cap_table); i++)
757 if (core_cap_table[i].cap_clk)
758 clk_set_rate(core_cap_table[i].cap_clk,
759 core_cap_table[i].freqs[j]);
760 } else if (level > tegra3_core_cap.level) {
761 for (i = ARRAY_SIZE(core_cap_table) - 1; i >= 0; i--)
762 if (core_cap_table[i].cap_clk)
763 clk_set_rate(core_cap_table[i].cap_clk,
764 core_cap_table[i].freqs[j]);
765 }
766 tegra3_core_cap.level = level;
767}
768
769static void core_cap_update(void)
770{
771 int new_level = tegra3_dvfs_rail_vdd_core.max_millivolts;
772
773 if (kdvfs_core_cap.refcnt)
774 new_level = min(new_level, kdvfs_core_cap.level);
775 if (user_core_cap.refcnt)
776 new_level = min(new_level, user_core_cap.level);
777
778 if (tegra3_core_cap.level != new_level)
779 core_cap_level_set(new_level);
780}
781
782static void core_cap_enable(bool enable)
783{
784 int i;
785
786 if (enable) {
787 tegra3_core_cap.refcnt++;
788 if (tegra3_core_cap.refcnt == 1)
789 for (i = 0; i < ARRAY_SIZE(core_cap_table); i++)
790 if (core_cap_table[i].cap_clk)
791 clk_enable(core_cap_table[i].cap_clk);
792 } else if (tegra3_core_cap.refcnt) {
793 tegra3_core_cap.refcnt--;
794 if (tegra3_core_cap.refcnt == 0)
795 for (i = ARRAY_SIZE(core_cap_table) - 1; i >= 0; i--)
796 if (core_cap_table[i].cap_clk)
797 clk_disable(core_cap_table[i].cap_clk);
798 }
799 core_cap_update();
800}
801
802static ssize_t
803core_cap_state_show(struct kobject *kobj, struct kobj_attribute *attr,
804 char *buf)
805{
806 return sprintf(buf, "%d (%d)\n", tegra3_core_cap.refcnt ? 1 : 0,
807 user_core_cap.refcnt ? 1 : 0);
808}
809static ssize_t
810core_cap_state_store(struct kobject *kobj, struct kobj_attribute *attr,
811 const char *buf, size_t count)
812{
813 int state;
814
815 if (sscanf(buf, "%d", &state) != 1)
816 return -1;
817
818 mutex_lock(&core_cap_lock);
819
820 if (state) {
821 user_core_cap.refcnt++;
822 if (user_core_cap.refcnt == 1)
823 core_cap_enable(true);
824 } else if (user_core_cap.refcnt) {
825 user_core_cap.refcnt--;
826 if (user_core_cap.refcnt == 0)
827 core_cap_enable(false);
828 }
829
830 mutex_unlock(&core_cap_lock);
831 return count;
832}
833
834static ssize_t
835core_cap_level_show(struct kobject *kobj, struct kobj_attribute *attr,
836 char *buf)
837{
838 return sprintf(buf, "%d (%d)\n", tegra3_core_cap.level,
839 user_core_cap.level);
840}
841static ssize_t
842core_cap_level_store(struct kobject *kobj, struct kobj_attribute *attr,
843 const char *buf, size_t count)
844{
845 int level;
846
847 if (sscanf(buf, "%d", &level) != 1)
848 return -1;
849
850 mutex_lock(&core_cap_lock);
851 user_core_cap.level = level;
852 core_cap_update();
853 mutex_unlock(&core_cap_lock);
854 return count;
855}
856
857static struct kobj_attribute cap_state_attribute =
858 __ATTR(core_cap_state, 0644, core_cap_state_show, core_cap_state_store);
859static struct kobj_attribute cap_level_attribute =
860 __ATTR(core_cap_level, 0644, core_cap_level_show, core_cap_level_store);
861
862const struct attribute *cap_attributes[] = {
863 &cap_state_attribute.attr,
864 &cap_level_attribute.attr,
865 NULL,
866};
867
868void tegra_dvfs_core_cap_enable(bool enable)
869{
870 mutex_lock(&core_cap_lock);
871
872 if (enable) {
873 kdvfs_core_cap.refcnt++;
874 if (kdvfs_core_cap.refcnt == 1)
875 core_cap_enable(true);
876 } else if (kdvfs_core_cap.refcnt) {
877 kdvfs_core_cap.refcnt--;
878 if (kdvfs_core_cap.refcnt == 0)
879 core_cap_enable(false);
880 }
881 mutex_unlock(&core_cap_lock);
882}
883
884void tegra_dvfs_core_cap_level_set(int level)
885{
886 mutex_lock(&core_cap_lock);
887 kdvfs_core_cap.level = level;
888 core_cap_update();
889 mutex_unlock(&core_cap_lock);
890}
891
892static int __init init_core_cap_one(struct clk *c, unsigned long *freqs)
893{
894 int i, v, next_v;
895 unsigned long rate, next_rate = 0;
896
897 for (i = 0; i < ARRAY_SIZE(core_millivolts); i++) {
898 v = core_millivolts[i];
899 if (v == 0)
900 break;
901
902 for (;;) {
903 rate = next_rate;
904 next_rate = clk_round_rate(c, rate + 1000);
905 if (IS_ERR_VALUE(next_rate)) {
906 pr_debug("tegra3_dvfs: failed to round %s"
907 " rate %lu", c->name, rate);
908 return -EINVAL;
909 }
910 if (rate == next_rate)
911 break;
912
913 next_v = tegra_dvfs_predict_millivolts(
914 c->parent, next_rate);
915 if (IS_ERR_VALUE(next_rate)) {
916 pr_debug("tegra3_dvfs: failed to predict %s mV"
917 " for rate %lu", c->name, next_rate);
918 return -EINVAL;
919 }
920 if (next_v > v)
921 break;
922 }
923
924 if (rate == 0) {
925 rate = next_rate;
926 pr_warn("tegra3_dvfs: minimum %s rate %lu requires"
927 " %d mV", c->name, rate, next_v);
928 }
929 freqs[i] = rate;
930 next_rate = rate;
931 }
932 return 0;
933}
934
935static int __init tegra_dvfs_init_core_cap(void)
936{
937 int i;
938 struct clk *c = NULL;
939
940 tegra3_core_cap.level = kdvfs_core_cap.level = user_core_cap.level =
941 tegra3_dvfs_rail_vdd_core.max_millivolts;
942
943 for (i = 0; i < ARRAY_SIZE(core_cap_table); i++) {
944 c = tegra_get_clock_by_name(core_cap_table[i].cap_name);
945 if (!c || !c->parent ||
946 init_core_cap_one(c, core_cap_table[i].freqs)) {
947 pr_err("tegra3_dvfs: failed to initialize %s frequency"
948 " table", core_cap_table[i].cap_name);
949 continue;
950 }
951 core_cap_table[i].cap_clk = c;
952 }
953
954 cap_kobj = kobject_create_and_add("tegra_cap", kernel_kobj);
955 if (!cap_kobj) {
956 pr_err("tegra3_dvfs: failed to create sysfs cap object");
957 return 0;
958 }
959
960 if (sysfs_create_files(cap_kobj, cap_attributes)) {
961 pr_err("tegra3_dvfs: failed to create sysfs cap interface");
962 return 0;
963 }
964 pr_info("tegra dvfs: tegra sysfs cap interface is initialized\n");
965
966 return 0;
967}
968late_initcall(tegra_dvfs_init_core_cap);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 15:22:54 -0400