diff options
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 5212 |
1 files changed, 5212 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c new file mode 100644 index 00000000000..0b2d4f4fc6d --- /dev/null +++ b/arch/arm/mach-tegra/tegra3_clocks.c | |||
@@ -0,0 +1,5212 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/tegra3_clocks.c | ||
3 | * | ||
4 | * Copyright (C) 2010-2012 NVIDIA Corporation | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; version 2 of the License. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along | ||
16 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/module.h> | ||
23 | #include <linux/list.h> | ||
24 | #include <linux/spinlock.h> | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/err.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/clk.h> | ||
29 | #include <linux/cpufreq.h> | ||
30 | #include <linux/syscore_ops.h> | ||
31 | |||
32 | #include <asm/clkdev.h> | ||
33 | |||
34 | #include <mach/iomap.h> | ||
35 | #include <mach/edp.h> | ||
36 | |||
37 | #include "clock.h" | ||
38 | #include "fuse.h" | ||
39 | #include "dvfs.h" | ||
40 | #include "pm.h" | ||
41 | #include "sleep.h" | ||
42 | #include "tegra3_emc.h" | ||
43 | |||
44 | #define RST_DEVICES_L 0x004 | ||
45 | #define RST_DEVICES_H 0x008 | ||
46 | #define RST_DEVICES_U 0x00C | ||
47 | #define RST_DEVICES_V 0x358 | ||
48 | #define RST_DEVICES_W 0x35C | ||
49 | #define RST_DEVICES_SET_L 0x300 | ||
50 | #define RST_DEVICES_CLR_L 0x304 | ||
51 | #define RST_DEVICES_SET_V 0x430 | ||
52 | #define RST_DEVICES_CLR_V 0x434 | ||
53 | #define RST_DEVICES_NUM 5 | ||
54 | |||
55 | #define CLK_OUT_ENB_L 0x010 | ||
56 | #define CLK_OUT_ENB_H 0x014 | ||
57 | #define CLK_OUT_ENB_U 0x018 | ||
58 | #define CLK_OUT_ENB_V 0x360 | ||
59 | #define CLK_OUT_ENB_W 0x364 | ||
60 | #define CLK_OUT_ENB_SET_L 0x320 | ||
61 | #define CLK_OUT_ENB_CLR_L 0x324 | ||
62 | #define CLK_OUT_ENB_SET_V 0x440 | ||
63 | #define CLK_OUT_ENB_CLR_V 0x444 | ||
64 | #define CLK_OUT_ENB_NUM 5 | ||
65 | |||
66 | #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) | ||
67 | #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) | ||
68 | |||
69 | #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) | ||
70 | #define PERIPH_CLK_TO_RST_REG(c) \ | ||
71 | periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4) | ||
72 | #define PERIPH_CLK_TO_RST_SET_REG(c) \ | ||
73 | periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8) | ||
74 | #define PERIPH_CLK_TO_RST_CLR_REG(c) \ | ||
75 | periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8) | ||
76 | |||
77 | #define PERIPH_CLK_TO_ENB_REG(c) \ | ||
78 | periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4) | ||
79 | #define PERIPH_CLK_TO_ENB_SET_REG(c) \ | ||
80 | periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8) | ||
81 | #define PERIPH_CLK_TO_ENB_CLR_REG(c) \ | ||
82 | periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8) | ||
83 | |||
84 | #define CLK_MASK_ARM 0x44 | ||
85 | #define MISC_CLK_ENB 0x48 | ||
86 | |||
87 | #define OSC_CTRL 0x50 | ||
88 | #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) | ||
89 | #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) | ||
90 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) | ||
91 | #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) | ||
92 | #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) | ||
93 | #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) | ||
94 | #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) | ||
95 | #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) | ||
96 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) | ||
97 | |||
98 | #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) | ||
99 | #define OSC_CTRL_PLL_REF_DIV_1 (0<<26) | ||
100 | #define OSC_CTRL_PLL_REF_DIV_2 (1<<26) | ||
101 | #define OSC_CTRL_PLL_REF_DIV_4 (2<<26) | ||
102 | |||
103 | #define PERIPH_CLK_SOURCE_I2S1 0x100 | ||
104 | #define PERIPH_CLK_SOURCE_EMC 0x19c | ||
105 | #define PERIPH_CLK_SOURCE_OSC 0x1fc | ||
106 | #define PERIPH_CLK_SOURCE_NUM1 \ | ||
107 | ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) | ||
108 | |||
109 | #define PERIPH_CLK_SOURCE_G3D2 0x3b0 | ||
110 | #define PERIPH_CLK_SOURCE_SE 0x42c | ||
111 | #define PERIPH_CLK_SOURCE_NUM2 \ | ||
112 | ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) | ||
113 | |||
114 | #define AUDIO_DLY_CLK 0x49c | ||
115 | #define AUDIO_SYNC_CLK_SPDIF 0x4b4 | ||
116 | #define PERIPH_CLK_SOURCE_NUM3 \ | ||
117 | ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) | ||
118 | |||
119 | #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ | ||
120 | PERIPH_CLK_SOURCE_NUM2 + \ | ||
121 | PERIPH_CLK_SOURCE_NUM3) | ||
122 | |||
123 | #define CPU_SOFTRST_CTRL 0x380 | ||
124 | |||
125 | #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF | ||
126 | #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF | ||
127 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 | ||
128 | #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 | ||
129 | #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 | ||
130 | #define PERIPH_CLK_UART_DIV_ENB (1<<24) | ||
131 | #define PERIPH_CLK_VI_SEL_EX_SHIFT 24 | ||
132 | #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) | ||
133 | #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) | ||
134 | #define PERIPH_CLK_DTV_POLARITY_INV (1<<25) | ||
135 | |||
136 | #define AUDIO_SYNC_SOURCE_MASK 0x0F | ||
137 | #define AUDIO_SYNC_DISABLE_BIT 0x10 | ||
138 | #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) | ||
139 | |||
140 | #define PLL_BASE 0x0 | ||
141 | #define PLL_BASE_BYPASS (1<<31) | ||
142 | #define PLL_BASE_ENABLE (1<<30) | ||
143 | #define PLL_BASE_REF_ENABLE (1<<29) | ||
144 | #define PLL_BASE_OVERRIDE (1<<28) | ||
145 | #define PLL_BASE_LOCK (1<<27) | ||
146 | #define PLL_BASE_DIVP_MASK (0x7<<20) | ||
147 | #define PLL_BASE_DIVP_SHIFT 20 | ||
148 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) | ||
149 | #define PLL_BASE_DIVN_SHIFT 8 | ||
150 | #define PLL_BASE_DIVM_MASK (0x1F) | ||
151 | #define PLL_BASE_DIVM_SHIFT 0 | ||
152 | |||
153 | #define PLL_OUT_RATIO_MASK (0xFF<<8) | ||
154 | #define PLL_OUT_RATIO_SHIFT 8 | ||
155 | #define PLL_OUT_OVERRIDE (1<<2) | ||
156 | #define PLL_OUT_CLKEN (1<<1) | ||
157 | #define PLL_OUT_RESET_DISABLE (1<<0) | ||
158 | |||
159 | #define PLL_MISC(c) \ | ||
160 | (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) | ||
161 | #define PLL_MISC_LOCK_ENABLE(c) \ | ||
162 | (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) | ||
163 | |||
164 | #define PLL_MISC_DCCON_SHIFT 20 | ||
165 | #define PLL_MISC_CPCON_SHIFT 8 | ||
166 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) | ||
167 | #define PLL_MISC_LFCON_SHIFT 4 | ||
168 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) | ||
169 | #define PLL_MISC_VCOCON_SHIFT 0 | ||
170 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) | ||
171 | #define PLLD_MISC_CLKENABLE (1<<30) | ||
172 | |||
173 | #define PLLU_BASE_POST_DIV (1<<20) | ||
174 | |||
175 | #define PLLD_BASE_DSIB_MUX_SHIFT 25 | ||
176 | #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT) | ||
177 | #define PLLD_BASE_CSI_CLKENABLE (1<<26) | ||
178 | #define PLLD_MISC_DSI_CLKENABLE (1<<30) | ||
179 | #define PLLD_MISC_DIV_RST (1<<23) | ||
180 | #define PLLD_MISC_DCCON_SHIFT 12 | ||
181 | |||
182 | #define PLLDU_LFCON_SET_DIVN 600 | ||
183 | |||
184 | /* FIXME: OUT_OF_TABLE_CPCON per pll */ | ||
185 | #define OUT_OF_TABLE_CPCON 0x8 | ||
186 | |||
187 | #define SUPER_CLK_MUX 0x00 | ||
188 | #define SUPER_STATE_SHIFT 28 | ||
189 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) | ||
190 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) | ||
191 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) | ||
192 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) | ||
193 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) | ||
194 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) | ||
195 | #define SUPER_LP_DIV2_BYPASS (0x1 << 16) | ||
196 | #define SUPER_SOURCE_MASK 0xF | ||
197 | #define SUPER_FIQ_SOURCE_SHIFT 12 | ||
198 | #define SUPER_IRQ_SOURCE_SHIFT 8 | ||
199 | #define SUPER_RUN_SOURCE_SHIFT 4 | ||
200 | #define SUPER_IDLE_SOURCE_SHIFT 0 | ||
201 | |||
202 | #define SUPER_CLK_DIVIDER 0x04 | ||
203 | #define SUPER_CLOCK_SKIP_ENABLE (0x1 << 31) | ||
204 | #define SUPER_CLOCK_DIV_U71_SHIFT 16 | ||
205 | #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) | ||
206 | #define SUPER_CLOCK_SKIP_MUL_SHIFT 8 | ||
207 | #define SUPER_CLOCK_SKIP_MUL_MASK (0xff << SUPER_CLOCK_SKIP_MUL_SHIFT) | ||
208 | #define SUPER_CLOCK_SKIP_DIV_SHIFT 0 | ||
209 | #define SUPER_CLOCK_SKIP_DIV_MASK (0xff << SUPER_CLOCK_SKIP_DIV_SHIFT) | ||
210 | #define SUPER_CLOCK_SKIP_MASK \ | ||
211 | (SUPER_CLOCK_SKIP_MUL_MASK | SUPER_CLOCK_SKIP_DIV_MASK) | ||
212 | #define SUPER_CLOCK_SKIP_TERM_MAX 256 | ||
213 | |||
214 | #define BUS_CLK_DISABLE (1<<3) | ||
215 | #define BUS_CLK_DIV_MASK 0x3 | ||
216 | |||
217 | #define PMC_CTRL 0x0 | ||
218 | #define PMC_CTRL_BLINK_ENB (1 << 7) | ||
219 | |||
220 | #define PMC_DPD_PADS_ORIDE 0x1c | ||
221 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) | ||
222 | |||
223 | #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 | ||
224 | #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff | ||
225 | #define PMC_BLINK_TIMER_ENB (1 << 15) | ||
226 | #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 | ||
227 | #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff | ||
228 | |||
229 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | ||
230 | #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) | ||
231 | |||
232 | #define UTMIP_PLL_CFG2 0x488 | ||
233 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) | ||
234 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | ||
235 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) | ||
236 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) | ||
237 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) | ||
238 | |||
239 | #define UTMIP_PLL_CFG1 0x484 | ||
240 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | ||
241 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | ||
242 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) | ||
243 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) | ||
244 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) | ||
245 | |||
246 | #define PLLE_BASE_CML_ENABLE (1<<31) | ||
247 | #define PLLE_BASE_ENABLE (1<<30) | ||
248 | #define PLLE_BASE_DIVCML_SHIFT 24 | ||
249 | #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) | ||
250 | #define PLLE_BASE_DIVP_SHIFT 16 | ||
251 | #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT) | ||
252 | #define PLLE_BASE_DIVN_SHIFT 8 | ||
253 | #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT) | ||
254 | #define PLLE_BASE_DIVM_SHIFT 0 | ||
255 | #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT) | ||
256 | #define PLLE_BASE_DIV_MASK \ | ||
257 | (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \ | ||
258 | PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK) | ||
259 | #define PLLE_BASE_DIV(m, n, p, cml) \ | ||
260 | (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \ | ||
261 | ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT)) | ||
262 | |||
263 | #define PLLE_MISC_SETUP_BASE_SHIFT 16 | ||
264 | #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT) | ||
265 | #define PLLE_MISC_READY (1<<15) | ||
266 | #define PLLE_MISC_LOCK (1<<11) | ||
267 | #define PLLE_MISC_LOCK_ENABLE (1<<9) | ||
268 | #define PLLE_MISC_SETUP_EX_SHIFT 2 | ||
269 | #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT) | ||
270 | #define PLLE_MISC_SETUP_MASK \ | ||
271 | (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK) | ||
272 | #define PLLE_MISC_SETUP_VALUE \ | ||
273 | ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT)) | ||
274 | |||
275 | #define PLLE_SS_CTRL 0x68 | ||
276 | #define PLLE_SS_INCINTRV_SHIFT 24 | ||
277 | #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) | ||
278 | #define PLLE_SS_INC_SHIFT 16 | ||
279 | #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) | ||
280 | #define PLLE_SS_MAX_SHIFT 0 | ||
281 | #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) | ||
282 | #define PLLE_SS_COEFFICIENTS_MASK \ | ||
283 | (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) | ||
284 | #define PLLE_SS_COEFFICIENTS_12MHZ \ | ||
285 | ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ | ||
286 | (0x24<<PLLE_SS_MAX_SHIFT)) | ||
287 | #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) | ||
288 | |||
289 | #define PLLE_AUX 0x48c | ||
290 | #define PLLE_AUX_PLLP_SEL (1<<2) | ||
291 | #define PLLE_AUX_CML_SATA_ENABLE (1<<1) | ||
292 | #define PLLE_AUX_CML_PCIE_ENABLE (1<<0) | ||
293 | |||
294 | #define PMC_SATA_PWRGT 0x1ac | ||
295 | #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5) | ||
296 | #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4) | ||
297 | |||
298 | #define ROUND_DIVIDER_UP 0 | ||
299 | #define ROUND_DIVIDER_DOWN 1 | ||
300 | |||
301 | /* PLLP default fixed rate in h/w controlled mode */ | ||
302 | #define PLLP_DEFAULT_FIXED_RATE 216000000 | ||
303 | |||
304 | /* Threshold to engage CPU clock skipper during CPU rate change */ | ||
305 | #define SKIPPER_ENGAGE_RATE 800000000 | ||
306 | |||
307 | static void tegra3_pllp_init_dependencies(unsigned long pllp_rate); | ||
308 | static int tegra3_clk_shared_bus_update(struct clk *bus); | ||
309 | |||
310 | static unsigned long cpu_stay_on_backup_max; | ||
311 | static struct clk *emc_bridge; | ||
312 | |||
313 | static bool detach_shared_bus; | ||
314 | module_param(detach_shared_bus, bool, 0644); | ||
315 | |||
316 | static int skipper_delay = 10; | ||
317 | module_param(skipper_delay, int, 0644); | ||
318 | |||
319 | void tegra3_set_cpu_skipper_delay(int delay) | ||
320 | { | ||
321 | skipper_delay = delay; | ||
322 | } | ||
323 | |||
324 | /** | ||
325 | * Structure defining the fields for USB UTMI clocks Parameters. | ||
326 | */ | ||
327 | struct utmi_clk_param | ||
328 | { | ||
329 | /* Oscillator Frequency in KHz */ | ||
330 | u32 osc_frequency; | ||
331 | /* UTMIP PLL Enable Delay Count */ | ||
332 | u8 enable_delay_count; | ||
333 | /* UTMIP PLL Stable count */ | ||
334 | u8 stable_count; | ||
335 | /* UTMIP PLL Active delay count */ | ||
336 | u8 active_delay_count; | ||
337 | /* UTMIP PLL Xtal frequency count */ | ||
338 | u8 xtal_freq_count; | ||
339 | }; | ||
340 | |||
341 | static const struct utmi_clk_param utmi_parameters[] = | ||
342 | { | ||
343 | /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ | ||
344 | {13000000, 0x02, 0x33, 0x05, 0x7F}, | ||
345 | {19200000, 0x03, 0x4B, 0x06, 0xBB}, | ||
346 | {12000000, 0x02, 0x2F, 0x04, 0x76}, | ||
347 | {26000000, 0x04, 0x66, 0x09, 0xFE}, | ||
348 | {16800000, 0x03, 0x41, 0x0A, 0xA4}, | ||
349 | }; | ||
350 | |||
351 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); | ||
352 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); | ||
353 | static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); | ||
354 | |||
355 | #define MISC_GP_HIDREV 0x804 | ||
356 | |||
357 | /* | ||
358 | * Some peripheral clocks share an enable bit, so refcount the enable bits | ||
359 | * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates | ||
360 | * with lock | ||
361 | */ | ||
362 | static DEFINE_SPINLOCK(periph_refcount_lock); | ||
363 | static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; | ||
364 | |||
365 | #define clk_writel(value, reg) \ | ||
366 | __raw_writel(value, (u32)reg_clk_base + (reg)) | ||
367 | #define clk_readl(reg) \ | ||
368 | __raw_readl((u32)reg_clk_base + (reg)) | ||
369 | #define pmc_writel(value, reg) \ | ||
370 | __raw_writel(value, (u32)reg_pmc_base + (reg)) | ||
371 | #define pmc_readl(reg) \ | ||
372 | __raw_readl((u32)reg_pmc_base + (reg)) | ||
373 | #define chipid_readl() \ | ||
374 | __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) | ||
375 | |||
376 | #define clk_writel_delay(value, reg) \ | ||
377 | do { \ | ||
378 | __raw_writel((value), (u32)reg_clk_base + (reg)); \ | ||
379 | udelay(2); \ | ||
380 | } while (0) | ||
381 | |||
382 | |||
383 | static inline int clk_set_div(struct clk *c, u32 n) | ||
384 | { | ||
385 | return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); | ||
386 | } | ||
387 | |||
388 | static inline u32 periph_clk_to_reg( | ||
389 | struct clk *c, u32 reg_L, u32 reg_V, int offs) | ||
390 | { | ||
391 | u32 reg = c->u.periph.clk_num / 32; | ||
392 | BUG_ON(reg >= RST_DEVICES_NUM); | ||
393 | if (reg < 3) { | ||
394 | reg = reg_L + (reg * offs); | ||
395 | } else { | ||
396 | reg = reg_V + ((reg - 3) * offs); | ||
397 | } | ||
398 | return reg; | ||
399 | } | ||
400 | |||
401 | static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate, | ||
402 | u32 max_x, u32 flags, u32 round_mode) | ||
403 | { | ||
404 | s64 divider_ux1 = parent_rate; | ||
405 | if (!rate) | ||
406 | return -EINVAL; | ||
407 | |||
408 | if (!(flags & DIV_U71_INT)) | ||
409 | divider_ux1 *= 2; | ||
410 | |||
411 | if (round_mode == ROUND_DIVIDER_UP) | ||
412 | divider_ux1 += rate - 1; | ||
413 | do_div(divider_ux1, rate); | ||
414 | |||
415 | if (flags & DIV_U71_INT) | ||
416 | divider_ux1 *= 2; | ||
417 | |||
418 | if (divider_ux1 - 2 < 0) | ||
419 | return 0; | ||
420 | |||
421 | if (divider_ux1 - 2 > max_x) | ||
422 | return -EINVAL; | ||
423 | |||
424 | return divider_ux1 - 2; | ||
425 | } | ||
426 | |||
427 | static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, | ||
428 | u32 flags, u32 round_mode) | ||
429 | { | ||
430 | return clk_div_x1_get_divider(parent_rate, rate, 0xFF, | ||
431 | flags, round_mode); | ||
432 | } | ||
433 | |||
434 | static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate, | ||
435 | u32 flags, u32 round_mode) | ||
436 | { | ||
437 | return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF, | ||
438 | flags, round_mode); | ||
439 | } | ||
440 | |||
441 | static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) | ||
442 | { | ||
443 | s64 divider_u16; | ||
444 | |||
445 | divider_u16 = parent_rate; | ||
446 | if (!rate) | ||
447 | return -EINVAL; | ||
448 | divider_u16 += rate - 1; | ||
449 | do_div(divider_u16, rate); | ||
450 | |||
451 | if (divider_u16 - 1 < 0) | ||
452 | return 0; | ||
453 | |||
454 | if (divider_u16 - 1 > 0xFFFF) | ||
455 | return -EINVAL; | ||
456 | |||
457 | return divider_u16 - 1; | ||
458 | } | ||
459 | |||
460 | /* clk_m functions */ | ||
461 | static unsigned long tegra3_clk_m_autodetect_rate(struct clk *c) | ||
462 | { | ||
463 | u32 osc_ctrl = clk_readl(OSC_CTRL); | ||
464 | u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; | ||
465 | u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; | ||
466 | |||
467 | c->rate = tegra_clk_measure_input_freq(); | ||
468 | switch (c->rate) { | ||
469 | case 12000000: | ||
470 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; | ||
471 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | ||
472 | break; | ||
473 | case 13000000: | ||
474 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; | ||
475 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | ||
476 | break; | ||
477 | case 19200000: | ||
478 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; | ||
479 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | ||
480 | break; | ||
481 | case 26000000: | ||
482 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; | ||
483 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | ||
484 | break; | ||
485 | case 16800000: | ||
486 | auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; | ||
487 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | ||
488 | break; | ||
489 | case 38400000: | ||
490 | auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; | ||
491 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); | ||
492 | break; | ||
493 | case 48000000: | ||
494 | auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; | ||
495 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); | ||
496 | break; | ||
497 | default: | ||
498 | pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); | ||
499 | BUG(); | ||
500 | } | ||
501 | clk_writel(auto_clock_control, OSC_CTRL); | ||
502 | return c->rate; | ||
503 | } | ||
504 | |||
505 | static void tegra3_clk_m_init(struct clk *c) | ||
506 | { | ||
507 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
508 | tegra3_clk_m_autodetect_rate(c); | ||
509 | } | ||
510 | |||
511 | static int tegra3_clk_m_enable(struct clk *c) | ||
512 | { | ||
513 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
514 | return 0; | ||
515 | } | ||
516 | |||
517 | static void tegra3_clk_m_disable(struct clk *c) | ||
518 | { | ||
519 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
520 | WARN(1, "Attempting to disable main SoC clock\n"); | ||
521 | } | ||
522 | |||
523 | static struct clk_ops tegra_clk_m_ops = { | ||
524 | .init = tegra3_clk_m_init, | ||
525 | .enable = tegra3_clk_m_enable, | ||
526 | .disable = tegra3_clk_m_disable, | ||
527 | }; | ||
528 | |||
529 | static struct clk_ops tegra_clk_m_div_ops = { | ||
530 | .enable = tegra3_clk_m_enable, | ||
531 | }; | ||
532 | |||
533 | /* PLL reference divider functions */ | ||
534 | static void tegra3_pll_ref_init(struct clk *c) | ||
535 | { | ||
536 | u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; | ||
537 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
538 | |||
539 | switch (pll_ref_div) { | ||
540 | case OSC_CTRL_PLL_REF_DIV_1: | ||
541 | c->div = 1; | ||
542 | break; | ||
543 | case OSC_CTRL_PLL_REF_DIV_2: | ||
544 | c->div = 2; | ||
545 | break; | ||
546 | case OSC_CTRL_PLL_REF_DIV_4: | ||
547 | c->div = 4; | ||
548 | break; | ||
549 | default: | ||
550 | pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); | ||
551 | BUG(); | ||
552 | } | ||
553 | c->mul = 1; | ||
554 | c->state = ON; | ||
555 | } | ||
556 | |||
557 | static struct clk_ops tegra_pll_ref_ops = { | ||
558 | .init = tegra3_pll_ref_init, | ||
559 | .enable = tegra3_clk_m_enable, | ||
560 | .disable = tegra3_clk_m_disable, | ||
561 | }; | ||
562 | |||
563 | /* super clock functions */ | ||
564 | /* "super clocks" on tegra3 have two-stage muxes, fractional 7.1 divider and | ||
565 | * clock skipping super divider. We will ignore the clock skipping divider, | ||
566 | * since we can't lower the voltage when using the clock skip, but we can if | ||
567 | * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock | ||
568 | * only when its parent is a fixed rate PLL, since we can't change PLL rate | ||
569 | * in this case. | ||
570 | */ | ||
571 | static void tegra3_super_clk_init(struct clk *c) | ||
572 | { | ||
573 | u32 val; | ||
574 | int source; | ||
575 | int shift; | ||
576 | const struct clk_mux_sel *sel; | ||
577 | |||
578 | val = clk_readl(c->reg + SUPER_CLK_MUX); | ||
579 | c->state = ON; | ||
580 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | ||
581 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | ||
582 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | ||
583 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | ||
584 | source = (val >> shift) & SUPER_SOURCE_MASK; | ||
585 | if (c->flags & DIV_2) | ||
586 | source |= val & SUPER_LP_DIV2_BYPASS; | ||
587 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
588 | if (sel->value == source) | ||
589 | break; | ||
590 | } | ||
591 | BUG_ON(sel->input == NULL); | ||
592 | c->parent = sel->input; | ||
593 | |||
594 | if (c->flags & DIV_U71) { | ||
595 | /* Init safe 7.1 divider value (does not affect PLLX path). | ||
596 | Super skipper is enabled to be ready for emergency throttle, | ||
597 | but set 1:1 */ | ||
598 | c->mul = 2; | ||
599 | c->div = 2; | ||
600 | if (!(c->parent->flags & PLLX)) { | ||
601 | val = clk_readl(c->reg + SUPER_CLK_DIVIDER); | ||
602 | val &= SUPER_CLOCK_DIV_U71_MASK; | ||
603 | val >>= SUPER_CLOCK_DIV_U71_SHIFT; | ||
604 | val = max(val, c->u.cclk.div71); | ||
605 | c->u.cclk.div71 = val; | ||
606 | c->div += val; | ||
607 | } | ||
608 | val = SUPER_CLOCK_SKIP_ENABLE + | ||
609 | (c->u.cclk.div71 << SUPER_CLOCK_DIV_U71_SHIFT); | ||
610 | clk_writel(val, c->reg + SUPER_CLK_DIVIDER); | ||
611 | } | ||
612 | else | ||
613 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); | ||
614 | } | ||
615 | |||
616 | static int tegra3_super_clk_enable(struct clk *c) | ||
617 | { | ||
618 | return 0; | ||
619 | } | ||
620 | |||
621 | static void tegra3_super_clk_disable(struct clk *c) | ||
622 | { | ||
623 | /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and | ||
624 | geared up g-mode super clock - mode switch may request to disable | ||
625 | either of them; accept request with no affect on h/w */ | ||
626 | } | ||
627 | |||
628 | static int tegra3_super_clk_set_parent(struct clk *c, struct clk *p) | ||
629 | { | ||
630 | u32 val; | ||
631 | const struct clk_mux_sel *sel; | ||
632 | int shift; | ||
633 | |||
634 | val = clk_readl(c->reg + SUPER_CLK_MUX);; | ||
635 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | ||
636 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | ||
637 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | ||
638 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | ||
639 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
640 | if (sel->input == p) { | ||
641 | /* For LP mode super-clock switch between PLLX direct | ||
642 | and divided-by-2 outputs is allowed only when other | ||
643 | than PLLX clock source is current parent */ | ||
644 | if ((c->flags & DIV_2) && (p->flags & PLLX) && | ||
645 | ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) { | ||
646 | if (c->parent->flags & PLLX) | ||
647 | return -EINVAL; | ||
648 | val ^= SUPER_LP_DIV2_BYPASS; | ||
649 | clk_writel_delay(val, c->reg); | ||
650 | } | ||
651 | val &= ~(SUPER_SOURCE_MASK << shift); | ||
652 | val |= (sel->value & SUPER_SOURCE_MASK) << shift; | ||
653 | |||
654 | /* 7.1 divider for CPU super-clock does not affect | ||
655 | PLLX path */ | ||
656 | if (c->flags & DIV_U71) { | ||
657 | u32 div = 0; | ||
658 | if (!(p->flags & PLLX)) { | ||
659 | div = clk_readl(c->reg + | ||
660 | SUPER_CLK_DIVIDER); | ||
661 | div &= SUPER_CLOCK_DIV_U71_MASK; | ||
662 | div >>= SUPER_CLOCK_DIV_U71_SHIFT; | ||
663 | } | ||
664 | c->div = div + 2; | ||
665 | c->mul = 2; | ||
666 | } | ||
667 | |||
668 | if (c->refcnt) | ||
669 | clk_enable(p); | ||
670 | |||
671 | clk_writel_delay(val, c->reg); | ||
672 | |||
673 | if (c->refcnt && c->parent) | ||
674 | clk_disable(c->parent); | ||
675 | |||
676 | clk_reparent(c, p); | ||
677 | return 0; | ||
678 | } | ||
679 | } | ||
680 | return -EINVAL; | ||
681 | } | ||
682 | |||
683 | static DEFINE_SPINLOCK(super_divider_lock); | ||
684 | |||
685 | static void tegra3_super_clk_divider_update(struct clk *c, u8 div) | ||
686 | { | ||
687 | u32 val; | ||
688 | unsigned long flags; | ||
689 | |||
690 | spin_lock_irqsave(&super_divider_lock, flags); | ||
691 | val = clk_readl(c->reg + SUPER_CLK_DIVIDER); | ||
692 | val &= ~SUPER_CLOCK_DIV_U71_MASK; | ||
693 | val |= div << SUPER_CLOCK_DIV_U71_SHIFT; | ||
694 | clk_writel(val, c->reg + SUPER_CLK_DIVIDER); | ||
695 | spin_unlock_irqrestore(&super_divider_lock, flags); | ||
696 | udelay(2); | ||
697 | } | ||
698 | |||
699 | static void tegra3_super_clk_skipper_update(struct clk *c, u8 mul, u8 div) | ||
700 | { | ||
701 | u32 val; | ||
702 | unsigned long flags; | ||
703 | |||
704 | spin_lock_irqsave(&super_divider_lock, flags); | ||
705 | val = clk_readl(c->reg + SUPER_CLK_DIVIDER); | ||
706 | |||
707 | /* multiplier or divider value = the respective field + 1 */ | ||
708 | if (mul && div) { | ||
709 | u32 old_mul = ((val & SUPER_CLOCK_SKIP_MUL_MASK) >> | ||
710 | SUPER_CLOCK_SKIP_MUL_SHIFT) + 1; | ||
711 | u32 old_div = ((val & SUPER_CLOCK_SKIP_DIV_MASK) >> | ||
712 | SUPER_CLOCK_SKIP_DIV_SHIFT) + 1; | ||
713 | |||
714 | if (mul >= div) { | ||
715 | /* improper fraction is only used to reciprocate the | ||
716 | previous proper one - the division below is exact */ | ||
717 | old_mul /= div; | ||
718 | old_div /= mul; | ||
719 | } else { | ||
720 | old_mul *= mul; | ||
721 | old_div *= div; | ||
722 | } | ||
723 | mul = (old_mul <= SUPER_CLOCK_SKIP_TERM_MAX) ? | ||
724 | old_mul : SUPER_CLOCK_SKIP_TERM_MAX; | ||
725 | div = (old_div <= SUPER_CLOCK_SKIP_TERM_MAX) ? | ||
726 | old_div : SUPER_CLOCK_SKIP_TERM_MAX; | ||
727 | } | ||
728 | |||
729 | if (!mul || (mul >= div)) { | ||
730 | mul = 1; | ||
731 | div = 1; | ||
732 | } | ||
733 | val &= ~SUPER_CLOCK_SKIP_MASK; | ||
734 | val |= SUPER_CLOCK_SKIP_ENABLE | | ||
735 | ((mul - 1) << SUPER_CLOCK_SKIP_MUL_SHIFT) | | ||
736 | ((div - 1) << SUPER_CLOCK_SKIP_DIV_SHIFT); | ||
737 | |||
738 | clk_writel(val, c->reg + SUPER_CLK_DIVIDER); | ||
739 | spin_unlock_irqrestore(&super_divider_lock, flags); | ||
740 | } | ||
741 | |||
742 | /* | ||
743 | * Do not use super clocks "skippers", since dividing using a clock skipper | ||
744 | * does not allow the voltage to be scaled down. Instead adjust the rate of | ||
745 | * the parent clock. This requires that the parent of a super clock have no | ||
746 | * other children, otherwise the rate will change underneath the other | ||
747 | * children. Special case: if fixed rate PLL is CPU super clock parent the | ||
748 | * rate of this PLL can't be changed, and it has many other children. In | ||
749 | * this case use 7.1 fractional divider to adjust the super clock rate. | ||
750 | */ | ||
751 | static int tegra3_super_clk_set_rate(struct clk *c, unsigned long rate) | ||
752 | { | ||
753 | if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { | ||
754 | int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, | ||
755 | rate, c->flags, ROUND_DIVIDER_DOWN); | ||
756 | if (div < 0) | ||
757 | return div; | ||
758 | |||
759 | tegra3_super_clk_divider_update(c, div); | ||
760 | c->u.cclk.div71 = div; | ||
761 | c->div = div + 2; | ||
762 | c->mul = 2; | ||
763 | return 0; | ||
764 | } | ||
765 | return clk_set_rate(c->parent, rate); | ||
766 | } | ||
767 | |||
768 | static struct clk_ops tegra_super_ops = { | ||
769 | .init = tegra3_super_clk_init, | ||
770 | .enable = tegra3_super_clk_enable, | ||
771 | .disable = tegra3_super_clk_disable, | ||
772 | .set_parent = tegra3_super_clk_set_parent, | ||
773 | .set_rate = tegra3_super_clk_set_rate, | ||
774 | }; | ||
775 | |||
776 | static int tegra3_twd_clk_set_rate(struct clk *c, unsigned long rate) | ||
777 | { | ||
778 | /* The input value 'rate' is the clock rate of the CPU complex. */ | ||
779 | c->rate = (rate * c->mul) / c->div; | ||
780 | return 0; | ||
781 | } | ||
782 | |||
783 | static struct clk_ops tegra3_twd_ops = { | ||
784 | .set_rate = tegra3_twd_clk_set_rate, | ||
785 | }; | ||
786 | |||
787 | static struct clk tegra3_clk_twd = { | ||
788 | /* NOTE: The twd clock must have *NO* parent. It's rate is directly | ||
789 | updated by tegra3_cpu_cmplx_clk_set_rate() because the | ||
790 | frequency change notifer for the twd is called in an | ||
791 | atomic context which cannot take a mutex. */ | ||
792 | .name = "twd", | ||
793 | .ops = &tegra3_twd_ops, | ||
794 | .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */ | ||
795 | .mul = 1, | ||
796 | .div = 2, | ||
797 | }; | ||
798 | |||
799 | /* virtual cpu clock functions */ | ||
800 | /* some clocks can not be stopped (cpu, memory bus) while the SoC is running. | ||
801 | To change the frequency of these clocks, the parent pll may need to be | ||
802 | reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, | ||
803 | and then the clock moved back to the pll. Clock skipper maybe temporarily | ||
804 | engaged during the switch to limit frequency jumps. To hide this sequence, | ||
805 | a virtual clock handles it. | ||
806 | */ | ||
807 | static void tegra3_cpu_clk_init(struct clk *c) | ||
808 | { | ||
809 | c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF; | ||
810 | } | ||
811 | |||
812 | static int tegra3_cpu_clk_enable(struct clk *c) | ||
813 | { | ||
814 | return 0; | ||
815 | } | ||
816 | |||
817 | static void tegra3_cpu_clk_disable(struct clk *c) | ||
818 | { | ||
819 | /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock | ||
820 | and geared up g-mode clock - mode switch may request to disable | ||
821 | either of them; accept request with no affect on h/w */ | ||
822 | } | ||
823 | |||
824 | static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate) | ||
825 | { | ||
826 | int ret = 0; | ||
827 | bool skipped = false; | ||
828 | bool skip = (c->u.cpu.mode == MODE_G) && skipper_delay; | ||
829 | bool skip_from_backup = skip && (rate >= SKIPPER_ENGAGE_RATE); | ||
830 | bool skip_to_backup = | ||
831 | skip && (clk_get_rate_all_locked(c) >= SKIPPER_ENGAGE_RATE); | ||
832 | |||
833 | /* Hardware clock control is not possible on FPGA platforms. | ||
834 | Report success so that upper level layers don't complain | ||
835 | needlessly. */ | ||
836 | #ifndef CONFIG_TEGRA_FPGA_PLATFORM | ||
837 | if (c->dvfs) { | ||
838 | if (!c->dvfs->dvfs_rail) | ||
839 | return -ENOSYS; | ||
840 | else if ((!c->dvfs->dvfs_rail->reg) && | ||
841 | (clk_get_rate_locked(c) < rate)) { | ||
842 | WARN(1, "Increasing CPU rate while regulator is not" | ||
843 | " ready may overclock CPU\n"); | ||
844 | return -ENOSYS; | ||
845 | } | ||
846 | } | ||
847 | |||
848 | /* | ||
849 | * Take an extra reference to the main pll so it doesn't turn | ||
850 | * off when we move the cpu off of it | ||
851 | */ | ||
852 | clk_enable(c->u.cpu.main); | ||
853 | |||
854 | if (c->parent->parent != c->u.cpu.backup) { | ||
855 | if (skip_to_backup) { | ||
856 | /* on G CPU use 1/2 skipper step for main <=> backup */ | ||
857 | skipped = true; | ||
858 | tegra3_super_clk_skipper_update(c->parent, 1, 2); | ||
859 | udelay(skipper_delay); | ||
860 | } | ||
861 | |||
862 | ret = clk_set_parent(c->parent, c->u.cpu.backup); | ||
863 | if (ret) { | ||
864 | pr_err("Failed to switch cpu to clock %s\n", | ||
865 | c->u.cpu.backup->name); | ||
866 | goto out; | ||
867 | } | ||
868 | |||
869 | if (skipped && !skip_from_backup) { | ||
870 | skipped = false; | ||
871 | tegra3_super_clk_skipper_update(c->parent, 2, 1); | ||
872 | } | ||
873 | } | ||
874 | |||
875 | if (rate <= cpu_stay_on_backup_max) { | ||
876 | ret = clk_set_rate(c->parent, rate); | ||
877 | if (ret) | ||
878 | pr_err("Failed to set cpu rate %lu on backup source\n", | ||
879 | rate); | ||
880 | goto out; | ||
881 | } else { | ||
882 | ret = clk_set_rate(c->parent, c->u.cpu.backup_rate); | ||
883 | if (ret) { | ||
884 | pr_err("Failed to set cpu rate %lu on backup source\n", | ||
885 | c->u.cpu.backup_rate); | ||
886 | goto out; | ||
887 | } | ||
888 | } | ||
889 | |||
890 | if (rate != clk_get_rate(c->u.cpu.main)) { | ||
891 | ret = clk_set_rate(c->u.cpu.main, rate); | ||
892 | if (ret) { | ||
893 | pr_err("Failed to change cpu pll to %lu\n", rate); | ||
894 | goto out; | ||
895 | } | ||
896 | } | ||
897 | |||
898 | if (!skipped && skip_from_backup) { | ||
899 | skipped = true; | ||
900 | tegra3_super_clk_skipper_update(c->parent, 1, 2); | ||
901 | } | ||
902 | |||
903 | ret = clk_set_parent(c->parent, c->u.cpu.main); | ||
904 | if (ret) { | ||
905 | pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name); | ||
906 | goto out; | ||
907 | } | ||
908 | |||
909 | out: | ||
910 | if (skipped) { | ||
911 | udelay(skipper_delay); | ||
912 | tegra3_super_clk_skipper_update(c->parent, 2, 1); | ||
913 | } | ||
914 | clk_disable(c->u.cpu.main); | ||
915 | #endif | ||
916 | return ret; | ||
917 | } | ||
918 | |||
919 | static struct clk_ops tegra_cpu_ops = { | ||
920 | .init = tegra3_cpu_clk_init, | ||
921 | .enable = tegra3_cpu_clk_enable, | ||
922 | .disable = tegra3_cpu_clk_disable, | ||
923 | .set_rate = tegra3_cpu_clk_set_rate, | ||
924 | }; | ||
925 | |||
926 | |||
927 | static void tegra3_cpu_cmplx_clk_init(struct clk *c) | ||
928 | { | ||
929 | int i = !!is_lp_cluster(); | ||
930 | |||
931 | BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G); | ||
932 | BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP); | ||
933 | c->parent = c->inputs[i].input; | ||
934 | } | ||
935 | |||
936 | /* cpu complex clock provides second level vitualization (on top of | ||
937 | cpu virtual cpu rate control) in order to hide the CPU mode switch | ||
938 | sequence */ | ||
939 | #if PARAMETERIZE_CLUSTER_SWITCH | ||
940 | static unsigned int switch_delay; | ||
941 | static unsigned int switch_flags; | ||
942 | static DEFINE_SPINLOCK(parameters_lock); | ||
943 | |||
944 | void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags) | ||
945 | { | ||
946 | spin_lock(¶meters_lock); | ||
947 | switch_delay = us; | ||
948 | switch_flags = flags; | ||
949 | spin_unlock(¶meters_lock); | ||
950 | } | ||
951 | #endif | ||
952 | |||
953 | static int tegra3_cpu_cmplx_clk_enable(struct clk *c) | ||
954 | { | ||
955 | return 0; | ||
956 | } | ||
957 | |||
958 | static void tegra3_cpu_cmplx_clk_disable(struct clk *c) | ||
959 | { | ||
960 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
961 | |||
962 | /* oops - don't disable the CPU complex clock! */ | ||
963 | BUG(); | ||
964 | } | ||
965 | |||
966 | static int tegra3_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate) | ||
967 | { | ||
968 | unsigned long flags; | ||
969 | int ret; | ||
970 | struct clk *parent = c->parent; | ||
971 | |||
972 | if (!parent->ops || !parent->ops->set_rate) | ||
973 | return -ENOSYS; | ||
974 | |||
975 | clk_lock_save(parent, &flags); | ||
976 | |||
977 | ret = clk_set_rate_locked(parent, rate); | ||
978 | |||
979 | /* We can't parent the twd to directly to the CPU complex because | ||
980 | the TWD frequency update notifier is called in an atomic context | ||
981 | and the CPU frequency update requires a mutex. Update the twd | ||
982 | clock rate with the new CPU complex rate. */ | ||
983 | clk_set_rate(&tegra3_clk_twd, clk_get_rate_locked(parent)); | ||
984 | |||
985 | clk_unlock_restore(parent, &flags); | ||
986 | |||
987 | return ret; | ||
988 | } | ||
989 | |||
990 | static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) | ||
991 | { | ||
992 | int ret; | ||
993 | unsigned int flags, delay; | ||
994 | const struct clk_mux_sel *sel; | ||
995 | unsigned long rate = clk_get_rate(c->parent); | ||
996 | |||
997 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | ||
998 | BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G)); | ||
999 | |||
1000 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
1001 | if (sel->input == p) | ||
1002 | break; | ||
1003 | } | ||
1004 | if (!sel->input) | ||
1005 | return -EINVAL; | ||
1006 | |||
1007 | #if PARAMETERIZE_CLUSTER_SWITCH | ||
1008 | spin_lock(¶meters_lock); | ||
1009 | flags = switch_flags; | ||
1010 | delay = switch_delay; | ||
1011 | switch_flags = 0; | ||
1012 | spin_unlock(¶meters_lock); | ||
1013 | |||
1014 | if (flags) { | ||
1015 | /* over/under-clocking after switch - allow, but update rate */ | ||
1016 | if ((rate > p->max_rate) || (rate < p->min_rate)) { | ||
1017 | unsigned long fl; | ||
1018 | |||
1019 | rate = rate > p->max_rate ? p->max_rate : p->min_rate; | ||
1020 | ret = clk_set_rate(c->parent, rate); | ||
1021 | if (ret) { | ||
1022 | pr_err("%s: Failed to set rate %lu for %s\n", | ||
1023 | __func__, rate, p->name); | ||
1024 | return ret; | ||
1025 | } | ||
1026 | clk_lock_save(c->parent, &fl); | ||
1027 | clk_set_rate(&tegra3_clk_twd, | ||
1028 | clk_get_rate_locked(c->parent)); | ||
1029 | clk_unlock_restore(c->parent, &fl); | ||
1030 | } | ||
1031 | } else | ||
1032 | #endif | ||
1033 | { | ||
1034 | if (p == c->parent) /* already switched - exit*/ | ||
1035 | return 0; | ||
1036 | |||
1037 | if (rate > p->max_rate) { /* over-clocking - no switch */ | ||
1038 | pr_warn("%s: No %s mode switch to %s at rate %lu\n", | ||
1039 | __func__, c->name, p->name, rate); | ||
1040 | return -ECANCELED; | ||
1041 | } | ||
1042 | flags = TEGRA_POWER_CLUSTER_IMMEDIATE; | ||
1043 | delay = 0; | ||
1044 | } | ||
1045 | flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : | ||
1046 | TEGRA_POWER_CLUSTER_G; | ||
1047 | |||
1048 | /* Since in both LP and G mode CPU main and backup sources are the | ||
1049 | same, set rate on the new parent just synchronizes super-clock | ||
1050 | muxes before mode switch with no PLL re-locking */ | ||
1051 | ret = clk_set_rate(p, rate); | ||
1052 | if (ret) { | ||
1053 | pr_err("%s: Failed to set rate %lu for %s\n", | ||
1054 | __func__, rate, p->name); | ||
1055 | return ret; | ||
1056 | } | ||
1057 | |||
1058 | /* Enabling new parent scales new mode voltage rail in advanvce | ||
1059 | before the switch happens*/ | ||
1060 | if (c->refcnt) | ||
1061 | clk_enable(p); | ||
1062 | |||
1063 | /* switch CPU mode */ | ||
1064 | ret = tegra_cluster_control(delay, flags); | ||
1065 | if (ret) { | ||
1066 | if (c->refcnt) | ||
1067 | clk_disable(p); | ||
1068 | pr_err("%s: Failed to switch %s mode to %s\n", | ||
1069 | __func__, c->name, p->name); | ||
1070 | return ret; | ||
1071 | } | ||
1072 | |||
1073 | /* Disabling old parent scales old mode voltage rail */ | ||
1074 | if (c->refcnt && c->parent) | ||
1075 | clk_disable(c->parent); | ||
1076 | |||
1077 | clk_reparent(c, p); | ||
1078 | return 0; | ||
1079 | } | ||
1080 | |||
1081 | static long tegra3_cpu_cmplx_round_rate(struct clk *c, | ||
1082 | unsigned long rate) | ||
1083 | { | ||
1084 | if (rate > c->parent->max_rate) | ||
1085 | rate = c->parent->max_rate; | ||
1086 | else if (rate < c->parent->min_rate) | ||
1087 | rate = c->parent->min_rate; | ||
1088 | return rate; | ||
1089 | } | ||
1090 | |||
1091 | static struct clk_ops tegra_cpu_cmplx_ops = { | ||
1092 | .init = tegra3_cpu_cmplx_clk_init, | ||
1093 | .enable = tegra3_cpu_cmplx_clk_enable, | ||
1094 | .disable = tegra3_cpu_cmplx_clk_disable, | ||
1095 | .set_rate = tegra3_cpu_cmplx_clk_set_rate, | ||
1096 | .set_parent = tegra3_cpu_cmplx_clk_set_parent, | ||
1097 | .round_rate = tegra3_cpu_cmplx_round_rate, | ||
1098 | }; | ||
1099 | |||
1100 | /* virtual cop clock functions. Used to acquire the fake 'cop' clock to | ||
1101 | * reset the COP block (i.e. AVP) */ | ||
1102 | static void tegra3_cop_clk_reset(struct clk *c, bool assert) | ||
1103 | { | ||
1104 | unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L; | ||
1105 | |||
1106 | pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); | ||
1107 | clk_writel(1 << 1, reg); | ||
1108 | } | ||
1109 | |||
1110 | static struct clk_ops tegra_cop_ops = { | ||
1111 | .reset = tegra3_cop_clk_reset, | ||
1112 | }; | ||
1113 | |||
1114 | /* bus clock functions */ | ||
1115 | static void tegra3_bus_clk_init(struct clk *c) | ||
1116 | { | ||
1117 | u32 val = clk_readl(c->reg); | ||
1118 | c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; | ||
1119 | c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; | ||
1120 | c->mul = 1; | ||
1121 | } | ||
1122 | |||
1123 | static int tegra3_bus_clk_enable(struct clk *c) | ||
1124 | { | ||
1125 | u32 val = clk_readl(c->reg); | ||
1126 | val &= ~(BUS_CLK_DISABLE << c->reg_shift); | ||
1127 | clk_writel(val, c->reg); | ||
1128 | return 0; | ||
1129 | } | ||
1130 | |||
1131 | static void tegra3_bus_clk_disable(struct clk *c) | ||
1132 | { | ||
1133 | u32 val = clk_readl(c->reg); | ||
1134 | val |= BUS_CLK_DISABLE << c->reg_shift; | ||
1135 | clk_writel(val, c->reg); | ||
1136 | } | ||
1137 | |||
1138 | static int tegra3_bus_clk_set_rate(struct clk *c, unsigned long rate) | ||
1139 | { | ||
1140 | u32 val = clk_readl(c->reg); | ||
1141 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
1142 | int i; | ||
1143 | for (i = 1; i <= 4; i++) { | ||
1144 | if (rate >= parent_rate / i) { | ||
1145 | val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); | ||
1146 | val |= (i - 1) << c->reg_shift; | ||
1147 | clk_writel(val, c->reg); | ||
1148 | c->div = i; | ||
1149 | c->mul = 1; | ||
1150 | return 0; | ||
1151 | } | ||
1152 | } | ||
1153 | return -EINVAL; | ||
1154 | } | ||
1155 | |||
1156 | static struct clk_ops tegra_bus_ops = { | ||
1157 | .init = tegra3_bus_clk_init, | ||
1158 | .enable = tegra3_bus_clk_enable, | ||
1159 | .disable = tegra3_bus_clk_disable, | ||
1160 | .set_rate = tegra3_bus_clk_set_rate, | ||
1161 | }; | ||
1162 | |||
1163 | /* Virtual system bus complex clock is used to hide the sequence of | ||
1164 | changing sclk/hclk/pclk parents and dividers to configure requested | ||
1165 | sclk target rate. */ | ||
1166 | static void tegra3_sbus_cmplx_init(struct clk *c) | ||
1167 | { | ||
1168 | unsigned long rate; | ||
1169 | |||
1170 | c->max_rate = c->parent->max_rate; | ||
1171 | c->min_rate = c->parent->min_rate; | ||
1172 | |||
1173 | /* Threshold must be an exact proper factor of low range parent, | ||
1174 | and both low/high range parents have 7.1 fractional dividers */ | ||
1175 | rate = clk_get_rate(c->u.system.sclk_low->parent); | ||
1176 | if (c->u.system.threshold) { | ||
1177 | BUG_ON(c->u.system.threshold > rate) ; | ||
1178 | BUG_ON((rate % c->u.system.threshold) != 0); | ||
1179 | } | ||
1180 | BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71)); | ||
1181 | BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71)); | ||
1182 | } | ||
1183 | |||
1184 | /* This special sbus round function is implemented because: | ||
1185 | * | ||
1186 | * (a) fractional dividers can not be used to derive system bus clock with one | ||
1187 | * exception: 1 : 2.5 divider is allowed at 1.2V and above (and we do need this | ||
1188 | * divider to reach top sbus frequencies from high frequency source). | ||
1189 | * | ||
1190 | * (b) since sbus is a shared bus, and its frequency is set to the highest | ||
1191 | * enabled shared_bus_user clock, the target rate should be rounded up divider | ||
1192 | * ladder (if max limit allows it) - for pll_div and peripheral_div common is | ||
1193 | * rounding down - special case again. | ||
1194 | * | ||
1195 | * Note that final rate is trimmed (not rounded up) to avoid spiraling up in | ||
1196 | * recursive calls. Lost 1Hz is added in tegra3_sbus_cmplx_set_rate before | ||
1197 | * actually setting divider rate. | ||
1198 | */ | ||
1199 | static unsigned long sclk_high_2_5_rate; | ||
1200 | static bool sclk_high_2_5_valid; | ||
1201 | |||
1202 | static long tegra3_sbus_cmplx_round_rate(struct clk *c, unsigned long rate) | ||
1203 | { | ||
1204 | int i, divider; | ||
1205 | unsigned long source_rate, round_rate; | ||
1206 | struct clk *new_parent; | ||
1207 | |||
1208 | rate = max(rate, c->min_rate); | ||
1209 | |||
1210 | if (!sclk_high_2_5_rate) { | ||
1211 | source_rate = clk_get_rate(c->u.system.sclk_high->parent); | ||
1212 | sclk_high_2_5_rate = 2 * source_rate / 5; | ||
1213 | i = tegra_dvfs_predict_millivolts(c, sclk_high_2_5_rate); | ||
1214 | if (!IS_ERR_VALUE(i) && (i >= 1200) && | ||
1215 | (sclk_high_2_5_rate <= c->max_rate)) | ||
1216 | sclk_high_2_5_valid = true; | ||
1217 | } | ||
1218 | |||
1219 | new_parent = (rate <= c->u.system.threshold) ? | ||
1220 | c->u.system.sclk_low : c->u.system.sclk_high; | ||
1221 | source_rate = clk_get_rate(new_parent->parent); | ||
1222 | |||
1223 | divider = clk_div71_get_divider(source_rate, rate, | ||
1224 | new_parent->flags | DIV_U71_INT, ROUND_DIVIDER_DOWN); | ||
1225 | if (divider < 0) | ||
1226 | return divider; | ||
1227 | |||
1228 | round_rate = source_rate * 2 / (divider + 2); | ||
1229 | if (round_rate > c->max_rate) { | ||
1230 | divider += 2; | ||
1231 | round_rate = source_rate * 2 / (divider + 2); | ||
1232 | } | ||
1233 | |||
1234 | if (new_parent == c->u.system.sclk_high) { | ||
1235 | /* Check if 1 : 2.5 ratio provides better approximation */ | ||
1236 | if (sclk_high_2_5_valid) { | ||
1237 | if (((sclk_high_2_5_rate < round_rate) && | ||
1238 | (sclk_high_2_5_rate >= rate)) || | ||
1239 | ((round_rate < sclk_high_2_5_rate) && | ||
1240 | (round_rate < rate))) | ||
1241 | round_rate = sclk_high_2_5_rate; | ||
1242 | } | ||
1243 | |||
1244 | if (round_rate <= c->u.system.threshold) | ||
1245 | round_rate = c->u.system.threshold; | ||
1246 | } | ||
1247 | return round_rate; | ||
1248 | } | ||
1249 | |||
1250 | static int tegra3_sbus_cmplx_set_rate(struct clk *c, unsigned long rate) | ||
1251 | { | ||
1252 | int ret; | ||
1253 | struct clk *new_parent; | ||
1254 | |||
1255 | /* - select the appropriate sclk parent | ||
1256 | - keep hclk at the same rate as sclk | ||
1257 | - set pclk at 1:2 rate of hclk unless pclk minimum is violated, | ||
1258 | in the latter case switch to 1:1 ratio */ | ||
1259 | |||
1260 | if (rate >= c->u.system.pclk->min_rate * 2) { | ||
1261 | ret = clk_set_div(c->u.system.pclk, 2); | ||
1262 | if (ret) { | ||
1263 | pr_err("Failed to set 1 : 2 pclk divider\n"); | ||
1264 | return ret; | ||
1265 | } | ||
1266 | } | ||
1267 | |||
1268 | new_parent = (rate <= c->u.system.threshold) ? | ||
1269 | c->u.system.sclk_low : c->u.system.sclk_high; | ||
1270 | |||
1271 | ret = clk_set_rate(new_parent, rate + 1); | ||
1272 | if (ret) { | ||
1273 | pr_err("Failed to set sclk source %s to %lu\n", | ||
1274 | new_parent->name, rate); | ||
1275 | return ret; | ||
1276 | } | ||
1277 | |||
1278 | if (new_parent != clk_get_parent(c->parent)) { | ||
1279 | ret = clk_set_parent(c->parent, new_parent); | ||
1280 | if (ret) { | ||
1281 | pr_err("Failed to switch sclk source to %s\n", | ||
1282 | new_parent->name); | ||
1283 | return ret; | ||
1284 | } | ||
1285 | } | ||
1286 | |||
1287 | if (rate < c->u.system.pclk->min_rate * 2) { | ||
1288 | ret = clk_set_div(c->u.system.pclk, 1); | ||
1289 | if (ret) { | ||
1290 | pr_err("Failed to set 1 : 1 pclk divider\n"); | ||
1291 | return ret; | ||
1292 | } | ||
1293 | } | ||
1294 | |||
1295 | return 0; | ||
1296 | } | ||
1297 | |||
1298 | static struct clk_ops tegra_sbus_cmplx_ops = { | ||
1299 | .init = tegra3_sbus_cmplx_init, | ||
1300 | .set_rate = tegra3_sbus_cmplx_set_rate, | ||
1301 | .round_rate = tegra3_sbus_cmplx_round_rate, | ||
1302 | .shared_bus_update = tegra3_clk_shared_bus_update, | ||
1303 | }; | ||
1304 | |||
1305 | /* Blink output functions */ | ||
1306 | |||
1307 | static void tegra3_blink_clk_init(struct clk *c) | ||
1308 | { | ||
1309 | u32 val; | ||
1310 | |||
1311 | val = pmc_readl(PMC_CTRL); | ||
1312 | c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; | ||
1313 | c->mul = 1; | ||
1314 | val = pmc_readl(c->reg); | ||
1315 | |||
1316 | if (val & PMC_BLINK_TIMER_ENB) { | ||
1317 | unsigned int on_off; | ||
1318 | |||
1319 | on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & | ||
1320 | PMC_BLINK_TIMER_DATA_ON_MASK; | ||
1321 | val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | ||
1322 | val &= PMC_BLINK_TIMER_DATA_OFF_MASK; | ||
1323 | on_off += val; | ||
1324 | /* each tick in the blink timer is 4 32KHz clocks */ | ||
1325 | c->div = on_off * 4; | ||
1326 | } else { | ||
1327 | c->div = 1; | ||
1328 | } | ||
1329 | } | ||
1330 | |||
1331 | static int tegra3_blink_clk_enable(struct clk *c) | ||
1332 | { | ||
1333 | u32 val; | ||
1334 | |||
1335 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | ||
1336 | pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | ||
1337 | |||
1338 | val = pmc_readl(PMC_CTRL); | ||
1339 | pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); | ||
1340 | |||
1341 | return 0; | ||
1342 | } | ||
1343 | |||
1344 | static void tegra3_blink_clk_disable(struct clk *c) | ||
1345 | { | ||
1346 | u32 val; | ||
1347 | |||
1348 | val = pmc_readl(PMC_CTRL); | ||
1349 | pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); | ||
1350 | |||
1351 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | ||
1352 | pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | ||
1353 | } | ||
1354 | |||
1355 | static int tegra3_blink_clk_set_rate(struct clk *c, unsigned long rate) | ||
1356 | { | ||
1357 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
1358 | if (rate >= parent_rate) { | ||
1359 | c->div = 1; | ||
1360 | pmc_writel(0, c->reg); | ||
1361 | } else { | ||
1362 | unsigned int on_off; | ||
1363 | u32 val; | ||
1364 | |||
1365 | on_off = DIV_ROUND_UP(parent_rate / 8, rate); | ||
1366 | c->div = on_off * 8; | ||
1367 | |||
1368 | val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << | ||
1369 | PMC_BLINK_TIMER_DATA_ON_SHIFT; | ||
1370 | on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; | ||
1371 | on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | ||
1372 | val |= on_off; | ||
1373 | val |= PMC_BLINK_TIMER_ENB; | ||
1374 | pmc_writel(val, c->reg); | ||
1375 | } | ||
1376 | |||
1377 | return 0; | ||
1378 | } | ||
1379 | |||
1380 | static struct clk_ops tegra_blink_clk_ops = { | ||
1381 | .init = &tegra3_blink_clk_init, | ||
1382 | .enable = &tegra3_blink_clk_enable, | ||
1383 | .disable = &tegra3_blink_clk_disable, | ||
1384 | .set_rate = &tegra3_blink_clk_set_rate, | ||
1385 | }; | ||
1386 | |||
1387 | /* PLL Functions */ | ||
1388 | static int tegra3_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, u32 lock_bit) | ||
1389 | { | ||
1390 | #if USE_PLL_LOCK_BITS | ||
1391 | int i; | ||
1392 | for (i = 0; i < c->u.pll.lock_delay; i++) { | ||
1393 | if (clk_readl(lock_reg) & lock_bit) { | ||
1394 | udelay(PLL_POST_LOCK_DELAY); | ||
1395 | return 0; | ||
1396 | } | ||
1397 | udelay(2); /* timeout = 2 * lock time */ | ||
1398 | } | ||
1399 | pr_err("Timed out waiting for lock bit on pll %s", c->name); | ||
1400 | return -1; | ||
1401 | #endif | ||
1402 | udelay(c->u.pll.lock_delay); | ||
1403 | |||
1404 | return 0; | ||
1405 | } | ||
1406 | |||
1407 | |||
1408 | static void tegra3_utmi_param_configure(struct clk *c) | ||
1409 | { | ||
1410 | u32 reg; | ||
1411 | int i; | ||
1412 | unsigned long main_rate = | ||
1413 | clk_get_rate(c->parent->parent); | ||
1414 | |||
1415 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | ||
1416 | if (main_rate == utmi_parameters[i].osc_frequency) { | ||
1417 | break; | ||
1418 | } | ||
1419 | } | ||
1420 | |||
1421 | if (i >= ARRAY_SIZE(utmi_parameters)) { | ||
1422 | pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); | ||
1423 | return; | ||
1424 | } | ||
1425 | |||
1426 | reg = clk_readl(UTMIP_PLL_CFG2); | ||
1427 | |||
1428 | /* Program UTMIP PLL stable and active counts */ | ||
1429 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | ||
1430 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | ||
1431 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT( | ||
1432 | utmi_parameters[i].stable_count); | ||
1433 | |||
1434 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | ||
1435 | |||
1436 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( | ||
1437 | utmi_parameters[i].active_delay_count); | ||
1438 | |||
1439 | /* Remove power downs from UTMIP PLL control bits */ | ||
1440 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | ||
1441 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | ||
1442 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; | ||
1443 | |||
1444 | clk_writel(reg, UTMIP_PLL_CFG2); | ||
1445 | |||
1446 | /* Program UTMIP PLL delay and oscillator frequency counts */ | ||
1447 | reg = clk_readl(UTMIP_PLL_CFG1); | ||
1448 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | ||
1449 | |||
1450 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( | ||
1451 | utmi_parameters[i].enable_delay_count); | ||
1452 | |||
1453 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | ||
1454 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( | ||
1455 | utmi_parameters[i].xtal_freq_count); | ||
1456 | |||
1457 | /* Remove power downs from UTMIP PLL control bits */ | ||
1458 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | ||
1459 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; | ||
1460 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | ||
1461 | |||
1462 | clk_writel(reg, UTMIP_PLL_CFG1); | ||
1463 | } | ||
1464 | |||
1465 | static void tegra3_pll_clk_init(struct clk *c) | ||
1466 | { | ||
1467 | u32 val = clk_readl(c->reg + PLL_BASE); | ||
1468 | |||
1469 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; | ||
1470 | |||
1471 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { | ||
1472 | const struct clk_pll_freq_table *sel; | ||
1473 | unsigned long input_rate = clk_get_rate(c->parent); | ||
1474 | c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE; | ||
1475 | |||
1476 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | ||
1477 | if (sel->input_rate == input_rate && | ||
1478 | sel->output_rate == c->u.pll.fixed_rate) { | ||
1479 | c->mul = sel->n; | ||
1480 | c->div = sel->m * sel->p; | ||
1481 | return; | ||
1482 | } | ||
1483 | } | ||
1484 | pr_err("Clock %s has unknown fixed frequency\n", c->name); | ||
1485 | BUG(); | ||
1486 | } else if (val & PLL_BASE_BYPASS) { | ||
1487 | c->mul = 1; | ||
1488 | c->div = 1; | ||
1489 | } else { | ||
1490 | c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; | ||
1491 | c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; | ||
1492 | if (c->flags & PLLU) | ||
1493 | c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; | ||
1494 | else | ||
1495 | c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> | ||
1496 | PLL_BASE_DIVP_SHIFT)); | ||
1497 | } | ||
1498 | |||
1499 | if (c->flags & PLL_FIXED) { | ||
1500 | c->u.pll.fixed_rate = clk_get_rate_locked(c); | ||
1501 | } | ||
1502 | |||
1503 | if (c->flags & PLLU) { | ||
1504 | tegra3_utmi_param_configure(c); | ||
1505 | } | ||
1506 | } | ||
1507 | |||
1508 | static int tegra3_pll_clk_enable(struct clk *c) | ||
1509 | { | ||
1510 | u32 val; | ||
1511 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
1512 | |||
1513 | #if USE_PLL_LOCK_BITS | ||
1514 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1515 | val |= PLL_MISC_LOCK_ENABLE(c); | ||
1516 | clk_writel(val, c->reg + PLL_MISC(c)); | ||
1517 | #endif | ||
1518 | val = clk_readl(c->reg + PLL_BASE); | ||
1519 | val &= ~PLL_BASE_BYPASS; | ||
1520 | val |= PLL_BASE_ENABLE; | ||
1521 | clk_writel(val, c->reg + PLL_BASE); | ||
1522 | |||
1523 | if (c->flags & PLLM) { | ||
1524 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | ||
1525 | val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | ||
1526 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | ||
1527 | } | ||
1528 | |||
1529 | tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); | ||
1530 | |||
1531 | return 0; | ||
1532 | } | ||
1533 | |||
1534 | static void tegra3_pll_clk_disable(struct clk *c) | ||
1535 | { | ||
1536 | u32 val; | ||
1537 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
1538 | |||
1539 | val = clk_readl(c->reg); | ||
1540 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | ||
1541 | clk_writel(val, c->reg); | ||
1542 | |||
1543 | if (c->flags & PLLM) { | ||
1544 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | ||
1545 | val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | ||
1546 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | ||
1547 | } | ||
1548 | } | ||
1549 | |||
1550 | static int tegra3_pll_clk_set_rate(struct clk *c, unsigned long rate) | ||
1551 | { | ||
1552 | u32 val, p_div, old_base; | ||
1553 | unsigned long input_rate; | ||
1554 | const struct clk_pll_freq_table *sel; | ||
1555 | struct clk_pll_freq_table cfg; | ||
1556 | |||
1557 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | ||
1558 | |||
1559 | if (c->flags & PLL_FIXED) { | ||
1560 | int ret = 0; | ||
1561 | if (rate != c->u.pll.fixed_rate) { | ||
1562 | pr_err("%s: Can not change %s fixed rate %lu to %lu\n", | ||
1563 | __func__, c->name, c->u.pll.fixed_rate, rate); | ||
1564 | ret = -EINVAL; | ||
1565 | } | ||
1566 | return ret; | ||
1567 | } | ||
1568 | |||
1569 | if (c->flags & PLLM) { | ||
1570 | if (rate != clk_get_rate_locked(c)) { | ||
1571 | pr_err("%s: Can not change memory %s rate in flight\n", | ||
1572 | __func__, c->name); | ||
1573 | return -EINVAL; | ||
1574 | } | ||
1575 | return 0; | ||
1576 | } | ||
1577 | |||
1578 | p_div = 0; | ||
1579 | input_rate = clk_get_rate(c->parent); | ||
1580 | |||
1581 | /* Check if the target rate is tabulated */ | ||
1582 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | ||
1583 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | ||
1584 | if (c->flags & PLLU) { | ||
1585 | BUG_ON(sel->p < 1 || sel->p > 2); | ||
1586 | if (sel->p == 1) | ||
1587 | p_div = PLLU_BASE_POST_DIV; | ||
1588 | } else { | ||
1589 | BUG_ON(sel->p < 1); | ||
1590 | for (val = sel->p; val > 1; val >>= 1, p_div++); | ||
1591 | p_div <<= PLL_BASE_DIVP_SHIFT; | ||
1592 | } | ||
1593 | break; | ||
1594 | } | ||
1595 | } | ||
1596 | |||
1597 | /* Configure out-of-table rate */ | ||
1598 | if (sel->input_rate == 0) { | ||
1599 | unsigned long cfreq; | ||
1600 | BUG_ON(c->flags & PLLU); | ||
1601 | sel = &cfg; | ||
1602 | |||
1603 | switch (input_rate) { | ||
1604 | case 12000000: | ||
1605 | case 26000000: | ||
1606 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | ||
1607 | break; | ||
1608 | case 13000000: | ||
1609 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | ||
1610 | break; | ||
1611 | case 16800000: | ||
1612 | case 19200000: | ||
1613 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | ||
1614 | break; | ||
1615 | default: | ||
1616 | if (c->parent->flags & DIV_U71_FIXED) { | ||
1617 | /* PLLP_OUT1 rate is not in PLLA table */ | ||
1618 | pr_warn("%s: failed %s ref/out rates %lu/%lu\n", | ||
1619 | __func__, c->name, input_rate, rate); | ||
1620 | cfreq = input_rate/(input_rate/1000000); | ||
1621 | break; | ||
1622 | } | ||
1623 | pr_err("%s: Unexpected reference rate %lu\n", | ||
1624 | __func__, input_rate); | ||
1625 | BUG(); | ||
1626 | } | ||
1627 | |||
1628 | /* Raise VCO to guarantee 0.5% accuracy */ | ||
1629 | for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; | ||
1630 | cfg.output_rate <<= 1, p_div++); | ||
1631 | |||
1632 | cfg.p = 0x1 << p_div; | ||
1633 | cfg.m = input_rate / cfreq; | ||
1634 | cfg.n = cfg.output_rate / cfreq; | ||
1635 | cfg.cpcon = OUT_OF_TABLE_CPCON; | ||
1636 | |||
1637 | if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || | ||
1638 | (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || | ||
1639 | (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || | ||
1640 | (cfg.output_rate > c->u.pll.vco_max)) { | ||
1641 | pr_err("%s: Failed to set %s out-of-table rate %lu\n", | ||
1642 | __func__, c->name, rate); | ||
1643 | return -EINVAL; | ||
1644 | } | ||
1645 | p_div <<= PLL_BASE_DIVP_SHIFT; | ||
1646 | } | ||
1647 | |||
1648 | c->mul = sel->n; | ||
1649 | c->div = sel->m * sel->p; | ||
1650 | |||
1651 | old_base = val = clk_readl(c->reg + PLL_BASE); | ||
1652 | val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | | ||
1653 | ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); | ||
1654 | val |= (sel->m << PLL_BASE_DIVM_SHIFT) | | ||
1655 | (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; | ||
1656 | if (val == old_base) | ||
1657 | return 0; | ||
1658 | |||
1659 | if (c->state == ON) { | ||
1660 | tegra3_pll_clk_disable(c); | ||
1661 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | ||
1662 | } | ||
1663 | clk_writel(val, c->reg + PLL_BASE); | ||
1664 | |||
1665 | if (c->flags & PLL_HAS_CPCON) { | ||
1666 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1667 | val &= ~PLL_MISC_CPCON_MASK; | ||
1668 | val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; | ||
1669 | if (c->flags & (PLLU | PLLD)) { | ||
1670 | val &= ~PLL_MISC_LFCON_MASK; | ||
1671 | if (sel->n >= PLLDU_LFCON_SET_DIVN) | ||
1672 | val |= 0x1 << PLL_MISC_LFCON_SHIFT; | ||
1673 | } else if (c->flags & (PLLX | PLLM)) { | ||
1674 | val &= ~(0x1 << PLL_MISC_DCCON_SHIFT); | ||
1675 | if (rate >= (c->u.pll.vco_max >> 1)) | ||
1676 | val |= 0x1 << PLL_MISC_DCCON_SHIFT; | ||
1677 | } | ||
1678 | clk_writel(val, c->reg + PLL_MISC(c)); | ||
1679 | } | ||
1680 | |||
1681 | if (c->state == ON) | ||
1682 | tegra3_pll_clk_enable(c); | ||
1683 | |||
1684 | return 0; | ||
1685 | } | ||
1686 | |||
1687 | static struct clk_ops tegra_pll_ops = { | ||
1688 | .init = tegra3_pll_clk_init, | ||
1689 | .enable = tegra3_pll_clk_enable, | ||
1690 | .disable = tegra3_pll_clk_disable, | ||
1691 | .set_rate = tegra3_pll_clk_set_rate, | ||
1692 | }; | ||
1693 | |||
1694 | static void tegra3_pllp_clk_init(struct clk *c) | ||
1695 | { | ||
1696 | tegra3_pll_clk_init(c); | ||
1697 | tegra3_pllp_init_dependencies(c->u.pll.fixed_rate); | ||
1698 | } | ||
1699 | |||
1700 | static void tegra3_pllp_clk_resume(struct clk *c) | ||
1701 | { | ||
1702 | unsigned long rate = c->u.pll.fixed_rate; | ||
1703 | tegra3_pll_clk_init(c); | ||
1704 | BUG_ON(rate != c->u.pll.fixed_rate); | ||
1705 | } | ||
1706 | |||
1707 | static struct clk_ops tegra_pllp_ops = { | ||
1708 | .init = tegra3_pllp_clk_init, | ||
1709 | .enable = tegra3_pll_clk_enable, | ||
1710 | .disable = tegra3_pll_clk_disable, | ||
1711 | .set_rate = tegra3_pll_clk_set_rate, | ||
1712 | }; | ||
1713 | |||
1714 | static int | ||
1715 | tegra3_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) | ||
1716 | { | ||
1717 | u32 val, mask, reg; | ||
1718 | |||
1719 | switch (p) { | ||
1720 | case TEGRA_CLK_PLLD_CSI_OUT_ENB: | ||
1721 | mask = PLLD_BASE_CSI_CLKENABLE; | ||
1722 | reg = c->reg + PLL_BASE; | ||
1723 | break; | ||
1724 | case TEGRA_CLK_PLLD_DSI_OUT_ENB: | ||
1725 | mask = PLLD_MISC_DSI_CLKENABLE; | ||
1726 | reg = c->reg + PLL_MISC(c); | ||
1727 | break; | ||
1728 | case TEGRA_CLK_PLLD_MIPI_MUX_SEL: | ||
1729 | if (!(c->flags & PLL_ALT_MISC_REG)) { | ||
1730 | mask = PLLD_BASE_DSIB_MUX_MASK; | ||
1731 | reg = c->reg + PLL_BASE; | ||
1732 | break; | ||
1733 | } | ||
1734 | /* fall through - error since PLLD2 does not have MUX_SEL control */ | ||
1735 | default: | ||
1736 | return -EINVAL; | ||
1737 | } | ||
1738 | |||
1739 | val = clk_readl(reg); | ||
1740 | if (setting) | ||
1741 | val |= mask; | ||
1742 | else | ||
1743 | val &= ~mask; | ||
1744 | clk_writel(val, reg); | ||
1745 | return 0; | ||
1746 | } | ||
1747 | |||
1748 | static struct clk_ops tegra_plld_ops = { | ||
1749 | .init = tegra3_pll_clk_init, | ||
1750 | .enable = tegra3_pll_clk_enable, | ||
1751 | .disable = tegra3_pll_clk_disable, | ||
1752 | .set_rate = tegra3_pll_clk_set_rate, | ||
1753 | .clk_cfg_ex = tegra3_plld_clk_cfg_ex, | ||
1754 | }; | ||
1755 | |||
1756 | static void tegra3_plle_clk_init(struct clk *c) | ||
1757 | { | ||
1758 | u32 val; | ||
1759 | |||
1760 | val = clk_readl(PLLE_AUX); | ||
1761 | c->parent = (val & PLLE_AUX_PLLP_SEL) ? | ||
1762 | tegra_get_clock_by_name("pll_p") : | ||
1763 | tegra_get_clock_by_name("pll_ref"); | ||
1764 | |||
1765 | val = clk_readl(c->reg + PLL_BASE); | ||
1766 | c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; | ||
1767 | c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; | ||
1768 | c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT; | ||
1769 | c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT; | ||
1770 | } | ||
1771 | |||
1772 | static void tegra3_plle_clk_disable(struct clk *c) | ||
1773 | { | ||
1774 | u32 val; | ||
1775 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
1776 | |||
1777 | val = clk_readl(c->reg + PLL_BASE); | ||
1778 | val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | ||
1779 | clk_writel(val, c->reg + PLL_BASE); | ||
1780 | } | ||
1781 | |||
1782 | static void tegra3_plle_training(struct clk *c) | ||
1783 | { | ||
1784 | u32 val; | ||
1785 | |||
1786 | /* PLLE is already disabled, and setup cleared; | ||
1787 | * create falling edge on PLLE IDDQ input */ | ||
1788 | val = pmc_readl(PMC_SATA_PWRGT); | ||
1789 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | ||
1790 | pmc_writel(val, PMC_SATA_PWRGT); | ||
1791 | |||
1792 | val = pmc_readl(PMC_SATA_PWRGT); | ||
1793 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; | ||
1794 | pmc_writel(val, PMC_SATA_PWRGT); | ||
1795 | |||
1796 | val = pmc_readl(PMC_SATA_PWRGT); | ||
1797 | val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | ||
1798 | pmc_writel(val, PMC_SATA_PWRGT); | ||
1799 | |||
1800 | do { | ||
1801 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1802 | } while (!(val & PLLE_MISC_READY)); | ||
1803 | } | ||
1804 | |||
1805 | static int tegra3_plle_configure(struct clk *c, bool force_training) | ||
1806 | { | ||
1807 | u32 val; | ||
1808 | const struct clk_pll_freq_table *sel; | ||
1809 | unsigned long rate = c->u.pll.fixed_rate; | ||
1810 | unsigned long input_rate = clk_get_rate(c->parent); | ||
1811 | |||
1812 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | ||
1813 | if (sel->input_rate == input_rate && sel->output_rate == rate) | ||
1814 | break; | ||
1815 | } | ||
1816 | |||
1817 | if (sel->input_rate == 0) | ||
1818 | return -ENOSYS; | ||
1819 | |||
1820 | /* disable PLLE, clear setup fiels */ | ||
1821 | tegra3_plle_clk_disable(c); | ||
1822 | |||
1823 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1824 | val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); | ||
1825 | clk_writel(val, c->reg + PLL_MISC(c)); | ||
1826 | |||
1827 | /* training */ | ||
1828 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1829 | if (force_training || (!(val & PLLE_MISC_READY))) | ||
1830 | tegra3_plle_training(c); | ||
1831 | |||
1832 | /* configure dividers, setup, disable SS */ | ||
1833 | val = clk_readl(c->reg + PLL_BASE); | ||
1834 | val &= ~PLLE_BASE_DIV_MASK; | ||
1835 | val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon); | ||
1836 | clk_writel(val, c->reg + PLL_BASE); | ||
1837 | c->mul = sel->n; | ||
1838 | c->div = sel->m * sel->p; | ||
1839 | |||
1840 | val = clk_readl(c->reg + PLL_MISC(c)); | ||
1841 | val |= PLLE_MISC_SETUP_VALUE; | ||
1842 | val |= PLLE_MISC_LOCK_ENABLE; | ||
1843 | clk_writel(val, c->reg + PLL_MISC(c)); | ||
1844 | |||
1845 | val = clk_readl(PLLE_SS_CTRL); | ||
1846 | val |= PLLE_SS_DISABLE; | ||
1847 | clk_writel(val, PLLE_SS_CTRL); | ||
1848 | |||
1849 | /* enable and lock PLLE*/ | ||
1850 | val = clk_readl(c->reg + PLL_BASE); | ||
1851 | val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | ||
1852 | clk_writel(val, c->reg + PLL_BASE); | ||
1853 | |||
1854 | tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); | ||
1855 | |||
1856 | #if USE_PLLE_SS | ||
1857 | /* configure spread spectrum coefficients */ | ||
1858 | /* FIXME: coefficients for 216MHZ input? */ | ||
1859 | #ifdef CONFIG_TEGRA_SILICON_PLATFORM | ||
1860 | if (input_rate == 12000000) | ||
1861 | #endif | ||
1862 | { | ||
1863 | val = clk_readl(PLLE_SS_CTRL); | ||
1864 | val &= ~(PLLE_SS_COEFFICIENTS_MASK | PLLE_SS_DISABLE); | ||
1865 | val |= PLLE_SS_COEFFICIENTS_12MHZ; | ||
1866 | clk_writel(val, PLLE_SS_CTRL); | ||
1867 | } | ||
1868 | #endif | ||
1869 | return 0; | ||
1870 | } | ||
1871 | |||
1872 | static int tegra3_plle_clk_enable(struct clk *c) | ||
1873 | { | ||
1874 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
1875 | return tegra3_plle_configure(c, !c->set); | ||
1876 | } | ||
1877 | |||
1878 | static struct clk_ops tegra_plle_ops = { | ||
1879 | .init = tegra3_plle_clk_init, | ||
1880 | .enable = tegra3_plle_clk_enable, | ||
1881 | .disable = tegra3_plle_clk_disable, | ||
1882 | }; | ||
1883 | |||
1884 | /* Clock divider ops (non-atomic shared register access) */ | ||
1885 | static DEFINE_SPINLOCK(pll_div_lock); | ||
1886 | |||
1887 | static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate); | ||
1888 | static void tegra3_pll_div_clk_init(struct clk *c) | ||
1889 | { | ||
1890 | if (c->flags & DIV_U71) { | ||
1891 | u32 divu71; | ||
1892 | u32 val = clk_readl(c->reg); | ||
1893 | val >>= c->reg_shift; | ||
1894 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; | ||
1895 | if (!(val & PLL_OUT_RESET_DISABLE)) | ||
1896 | c->state = OFF; | ||
1897 | |||
1898 | if (c->u.pll_div.default_rate) { | ||
1899 | int ret = tegra3_pll_div_clk_set_rate( | ||
1900 | c, c->u.pll_div.default_rate); | ||
1901 | if (!ret) | ||
1902 | return; | ||
1903 | } | ||
1904 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; | ||
1905 | c->div = (divu71 + 2); | ||
1906 | c->mul = 2; | ||
1907 | } else if (c->flags & DIV_2) { | ||
1908 | c->state = ON; | ||
1909 | if (c->flags & (PLLD | PLLX)) { | ||
1910 | c->div = 2; | ||
1911 | c->mul = 1; | ||
1912 | } | ||
1913 | else | ||
1914 | BUG(); | ||
1915 | } else { | ||
1916 | c->state = ON; | ||
1917 | c->div = 1; | ||
1918 | c->mul = 1; | ||
1919 | } | ||
1920 | } | ||
1921 | |||
1922 | static int tegra3_pll_div_clk_enable(struct clk *c) | ||
1923 | { | ||
1924 | u32 val; | ||
1925 | u32 new_val; | ||
1926 | unsigned long flags; | ||
1927 | |||
1928 | pr_debug("%s: %s\n", __func__, c->name); | ||
1929 | if (c->flags & DIV_U71) { | ||
1930 | spin_lock_irqsave(&pll_div_lock, flags); | ||
1931 | val = clk_readl(c->reg); | ||
1932 | new_val = val >> c->reg_shift; | ||
1933 | new_val &= 0xFFFF; | ||
1934 | |||
1935 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | ||
1936 | |||
1937 | val &= ~(0xFFFF << c->reg_shift); | ||
1938 | val |= new_val << c->reg_shift; | ||
1939 | clk_writel_delay(val, c->reg); | ||
1940 | spin_unlock_irqrestore(&pll_div_lock, flags); | ||
1941 | return 0; | ||
1942 | } else if (c->flags & DIV_2) { | ||
1943 | return 0; | ||
1944 | } | ||
1945 | return -EINVAL; | ||
1946 | } | ||
1947 | |||
1948 | static void tegra3_pll_div_clk_disable(struct clk *c) | ||
1949 | { | ||
1950 | u32 val; | ||
1951 | u32 new_val; | ||
1952 | unsigned long flags; | ||
1953 | |||
1954 | pr_debug("%s: %s\n", __func__, c->name); | ||
1955 | if (c->flags & DIV_U71) { | ||
1956 | spin_lock_irqsave(&pll_div_lock, flags); | ||
1957 | val = clk_readl(c->reg); | ||
1958 | new_val = val >> c->reg_shift; | ||
1959 | new_val &= 0xFFFF; | ||
1960 | |||
1961 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); | ||
1962 | |||
1963 | val &= ~(0xFFFF << c->reg_shift); | ||
1964 | val |= new_val << c->reg_shift; | ||
1965 | clk_writel_delay(val, c->reg); | ||
1966 | spin_unlock_irqrestore(&pll_div_lock, flags); | ||
1967 | } | ||
1968 | } | ||
1969 | |||
1970 | static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate) | ||
1971 | { | ||
1972 | u32 val; | ||
1973 | u32 new_val; | ||
1974 | int divider_u71; | ||
1975 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
1976 | unsigned long flags; | ||
1977 | |||
1978 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | ||
1979 | if (c->flags & DIV_U71) { | ||
1980 | divider_u71 = clk_div71_get_divider( | ||
1981 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
1982 | if (divider_u71 >= 0) { | ||
1983 | spin_lock_irqsave(&pll_div_lock, flags); | ||
1984 | val = clk_readl(c->reg); | ||
1985 | new_val = val >> c->reg_shift; | ||
1986 | new_val &= 0xFFFF; | ||
1987 | if (c->flags & DIV_U71_FIXED) | ||
1988 | new_val |= PLL_OUT_OVERRIDE; | ||
1989 | new_val &= ~PLL_OUT_RATIO_MASK; | ||
1990 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; | ||
1991 | |||
1992 | val &= ~(0xFFFF << c->reg_shift); | ||
1993 | val |= new_val << c->reg_shift; | ||
1994 | clk_writel_delay(val, c->reg); | ||
1995 | c->div = divider_u71 + 2; | ||
1996 | c->mul = 2; | ||
1997 | spin_unlock_irqrestore(&pll_div_lock, flags); | ||
1998 | return 0; | ||
1999 | } | ||
2000 | } else if (c->flags & DIV_2) | ||
2001 | return clk_set_rate(c->parent, rate * 2); | ||
2002 | |||
2003 | return -EINVAL; | ||
2004 | } | ||
2005 | |||
2006 | static long tegra3_pll_div_clk_round_rate(struct clk *c, unsigned long rate) | ||
2007 | { | ||
2008 | int divider; | ||
2009 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
2010 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | ||
2011 | |||
2012 | if (c->flags & DIV_U71) { | ||
2013 | divider = clk_div71_get_divider( | ||
2014 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
2015 | if (divider < 0) | ||
2016 | return divider; | ||
2017 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | ||
2018 | } else if (c->flags & DIV_2) | ||
2019 | /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ | ||
2020 | return rate; | ||
2021 | |||
2022 | return -EINVAL; | ||
2023 | } | ||
2024 | |||
2025 | static struct clk_ops tegra_pll_div_ops = { | ||
2026 | .init = tegra3_pll_div_clk_init, | ||
2027 | .enable = tegra3_pll_div_clk_enable, | ||
2028 | .disable = tegra3_pll_div_clk_disable, | ||
2029 | .set_rate = tegra3_pll_div_clk_set_rate, | ||
2030 | .round_rate = tegra3_pll_div_clk_round_rate, | ||
2031 | }; | ||
2032 | |||
2033 | /* Periph clk ops */ | ||
2034 | static inline u32 periph_clk_source_mask(struct clk *c) | ||
2035 | { | ||
2036 | if (c->flags & MUX8) | ||
2037 | return 7 << 29; | ||
2038 | else if (c->flags & MUX_PWM) | ||
2039 | return 3 << 28; | ||
2040 | else if (c->flags & MUX_CLK_OUT) | ||
2041 | return 3 << (c->u.periph.clk_num + 4); | ||
2042 | else if (c->flags & PLLD) | ||
2043 | return PLLD_BASE_DSIB_MUX_MASK; | ||
2044 | else | ||
2045 | return 3 << 30; | ||
2046 | } | ||
2047 | |||
2048 | static inline u32 periph_clk_source_shift(struct clk *c) | ||
2049 | { | ||
2050 | if (c->flags & MUX8) | ||
2051 | return 29; | ||
2052 | else if (c->flags & MUX_PWM) | ||
2053 | return 28; | ||
2054 | else if (c->flags & MUX_CLK_OUT) | ||
2055 | return c->u.periph.clk_num + 4; | ||
2056 | else if (c->flags & PLLD) | ||
2057 | return PLLD_BASE_DSIB_MUX_SHIFT; | ||
2058 | else | ||
2059 | return 30; | ||
2060 | } | ||
2061 | |||
2062 | static void tegra3_periph_clk_init(struct clk *c) | ||
2063 | { | ||
2064 | u32 val = clk_readl(c->reg); | ||
2065 | const struct clk_mux_sel *mux = 0; | ||
2066 | const struct clk_mux_sel *sel; | ||
2067 | if (c->flags & MUX) { | ||
2068 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2069 | if (((val & periph_clk_source_mask(c)) >> | ||
2070 | periph_clk_source_shift(c)) == sel->value) | ||
2071 | mux = sel; | ||
2072 | } | ||
2073 | BUG_ON(!mux); | ||
2074 | |||
2075 | c->parent = mux->input; | ||
2076 | } else { | ||
2077 | c->parent = c->inputs[0].input; | ||
2078 | } | ||
2079 | |||
2080 | if (c->flags & DIV_U71) { | ||
2081 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; | ||
2082 | if (c->flags & DIV_U71_IDLE) { | ||
2083 | val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << | ||
2084 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | ||
2085 | val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << | ||
2086 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | ||
2087 | clk_writel(val, c->reg); | ||
2088 | } | ||
2089 | c->div = divu71 + 2; | ||
2090 | c->mul = 2; | ||
2091 | } else if (c->flags & DIV_U151) { | ||
2092 | u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; | ||
2093 | if ((c->flags & DIV_U151_UART) && | ||
2094 | (!(val & PERIPH_CLK_UART_DIV_ENB))) { | ||
2095 | divu151 = 0; | ||
2096 | } | ||
2097 | c->div = divu151 + 2; | ||
2098 | c->mul = 2; | ||
2099 | } else if (c->flags & DIV_U16) { | ||
2100 | u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; | ||
2101 | c->div = divu16 + 1; | ||
2102 | c->mul = 1; | ||
2103 | } else { | ||
2104 | c->div = 1; | ||
2105 | c->mul = 1; | ||
2106 | } | ||
2107 | |||
2108 | c->state = ON; | ||
2109 | |||
2110 | if (c->flags & PERIPH_NO_ENB) | ||
2111 | return; | ||
2112 | |||
2113 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | ||
2114 | c->state = OFF; | ||
2115 | if (!(c->flags & PERIPH_NO_RESET)) | ||
2116 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) | ||
2117 | c->state = OFF; | ||
2118 | } | ||
2119 | |||
2120 | static int tegra3_periph_clk_enable(struct clk *c) | ||
2121 | { | ||
2122 | unsigned long flags; | ||
2123 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
2124 | |||
2125 | if (c->flags & PERIPH_NO_ENB) | ||
2126 | return 0; | ||
2127 | |||
2128 | spin_lock_irqsave(&periph_refcount_lock, flags); | ||
2129 | |||
2130 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; | ||
2131 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) { | ||
2132 | spin_unlock_irqrestore(&periph_refcount_lock, flags); | ||
2133 | return 0; | ||
2134 | } | ||
2135 | |||
2136 | clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); | ||
2137 | if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) { | ||
2138 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) { | ||
2139 | udelay(5); /* reset propagation delay */ | ||
2140 | clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c)); | ||
2141 | } | ||
2142 | } | ||
2143 | spin_unlock_irqrestore(&periph_refcount_lock, flags); | ||
2144 | return 0; | ||
2145 | } | ||
2146 | |||
2147 | static void tegra3_periph_clk_disable(struct clk *c) | ||
2148 | { | ||
2149 | unsigned long val, flags; | ||
2150 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
2151 | |||
2152 | if (c->flags & PERIPH_NO_ENB) | ||
2153 | return; | ||
2154 | |||
2155 | spin_lock_irqsave(&periph_refcount_lock, flags); | ||
2156 | |||
2157 | if (c->refcnt) | ||
2158 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; | ||
2159 | |||
2160 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { | ||
2161 | /* If peripheral is in the APB bus then read the APB bus to | ||
2162 | * flush the write operation in apb bus. This will avoid the | ||
2163 | * peripheral access after disabling clock*/ | ||
2164 | if (c->flags & PERIPH_ON_APB) | ||
2165 | val = chipid_readl(); | ||
2166 | |||
2167 | clk_writel_delay( | ||
2168 | PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); | ||
2169 | } | ||
2170 | spin_unlock_irqrestore(&periph_refcount_lock, flags); | ||
2171 | } | ||
2172 | |||
2173 | static void tegra3_periph_clk_reset(struct clk *c, bool assert) | ||
2174 | { | ||
2175 | unsigned long val; | ||
2176 | pr_debug("%s %s on clock %s\n", __func__, | ||
2177 | assert ? "assert" : "deassert", c->name); | ||
2178 | |||
2179 | if (c->flags & PERIPH_NO_ENB) | ||
2180 | return; | ||
2181 | |||
2182 | if (!(c->flags & PERIPH_NO_RESET)) { | ||
2183 | if (assert) { | ||
2184 | /* If peripheral is in the APB bus then read the APB | ||
2185 | * bus to flush the write operation in apb bus. This | ||
2186 | * will avoid the peripheral access after disabling | ||
2187 | * clock */ | ||
2188 | if (c->flags & PERIPH_ON_APB) | ||
2189 | val = chipid_readl(); | ||
2190 | |||
2191 | clk_writel(PERIPH_CLK_TO_BIT(c), | ||
2192 | PERIPH_CLK_TO_RST_SET_REG(c)); | ||
2193 | } else | ||
2194 | clk_writel(PERIPH_CLK_TO_BIT(c), | ||
2195 | PERIPH_CLK_TO_RST_CLR_REG(c)); | ||
2196 | } | ||
2197 | } | ||
2198 | |||
2199 | static int tegra3_periph_clk_set_parent(struct clk *c, struct clk *p) | ||
2200 | { | ||
2201 | u32 val; | ||
2202 | const struct clk_mux_sel *sel; | ||
2203 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | ||
2204 | |||
2205 | if (!(c->flags & MUX)) | ||
2206 | return (p == c->parent) ? 0 : (-EINVAL); | ||
2207 | |||
2208 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2209 | if (sel->input == p) { | ||
2210 | val = clk_readl(c->reg); | ||
2211 | val &= ~periph_clk_source_mask(c); | ||
2212 | val |= (sel->value << periph_clk_source_shift(c)); | ||
2213 | |||
2214 | if (c->refcnt) | ||
2215 | clk_enable(p); | ||
2216 | |||
2217 | clk_writel_delay(val, c->reg); | ||
2218 | |||
2219 | if (c->refcnt && c->parent) | ||
2220 | clk_disable(c->parent); | ||
2221 | |||
2222 | clk_reparent(c, p); | ||
2223 | return 0; | ||
2224 | } | ||
2225 | } | ||
2226 | |||
2227 | return -EINVAL; | ||
2228 | } | ||
2229 | |||
2230 | static int tegra3_periph_clk_set_rate(struct clk *c, unsigned long rate) | ||
2231 | { | ||
2232 | u32 val; | ||
2233 | int divider; | ||
2234 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
2235 | |||
2236 | if (c->flags & DIV_U71) { | ||
2237 | divider = clk_div71_get_divider( | ||
2238 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
2239 | if (divider >= 0) { | ||
2240 | val = clk_readl(c->reg); | ||
2241 | val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; | ||
2242 | val |= divider; | ||
2243 | clk_writel_delay(val, c->reg); | ||
2244 | c->div = divider + 2; | ||
2245 | c->mul = 2; | ||
2246 | return 0; | ||
2247 | } | ||
2248 | } else if (c->flags & DIV_U151) { | ||
2249 | divider = clk_div151_get_divider( | ||
2250 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
2251 | if (divider >= 0) { | ||
2252 | val = clk_readl(c->reg); | ||
2253 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; | ||
2254 | val |= divider; | ||
2255 | if (c->flags & DIV_U151_UART) { | ||
2256 | if (divider) | ||
2257 | val |= PERIPH_CLK_UART_DIV_ENB; | ||
2258 | else | ||
2259 | val &= ~PERIPH_CLK_UART_DIV_ENB; | ||
2260 | } | ||
2261 | clk_writel_delay(val, c->reg); | ||
2262 | c->div = divider + 2; | ||
2263 | c->mul = 2; | ||
2264 | return 0; | ||
2265 | } | ||
2266 | } else if (c->flags & DIV_U16) { | ||
2267 | divider = clk_div16_get_divider(parent_rate, rate); | ||
2268 | if (divider >= 0) { | ||
2269 | val = clk_readl(c->reg); | ||
2270 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; | ||
2271 | val |= divider; | ||
2272 | clk_writel_delay(val, c->reg); | ||
2273 | c->div = divider + 1; | ||
2274 | c->mul = 1; | ||
2275 | return 0; | ||
2276 | } | ||
2277 | } else if (parent_rate <= rate) { | ||
2278 | c->div = 1; | ||
2279 | c->mul = 1; | ||
2280 | return 0; | ||
2281 | } | ||
2282 | return -EINVAL; | ||
2283 | } | ||
2284 | |||
2285 | static long tegra3_periph_clk_round_rate(struct clk *c, | ||
2286 | unsigned long rate) | ||
2287 | { | ||
2288 | int divider; | ||
2289 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
2290 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | ||
2291 | |||
2292 | if (c->flags & DIV_U71) { | ||
2293 | divider = clk_div71_get_divider( | ||
2294 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
2295 | if (divider < 0) | ||
2296 | return divider; | ||
2297 | |||
2298 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | ||
2299 | } else if (c->flags & DIV_U151) { | ||
2300 | divider = clk_div151_get_divider( | ||
2301 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | ||
2302 | if (divider < 0) | ||
2303 | return divider; | ||
2304 | |||
2305 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | ||
2306 | } else if (c->flags & DIV_U16) { | ||
2307 | divider = clk_div16_get_divider(parent_rate, rate); | ||
2308 | if (divider < 0) | ||
2309 | return divider; | ||
2310 | return DIV_ROUND_UP(parent_rate, divider + 1); | ||
2311 | } | ||
2312 | return -EINVAL; | ||
2313 | } | ||
2314 | |||
2315 | static struct clk_ops tegra_periph_clk_ops = { | ||
2316 | .init = &tegra3_periph_clk_init, | ||
2317 | .enable = &tegra3_periph_clk_enable, | ||
2318 | .disable = &tegra3_periph_clk_disable, | ||
2319 | .set_parent = &tegra3_periph_clk_set_parent, | ||
2320 | .set_rate = &tegra3_periph_clk_set_rate, | ||
2321 | .round_rate = &tegra3_periph_clk_round_rate, | ||
2322 | .reset = &tegra3_periph_clk_reset, | ||
2323 | }; | ||
2324 | |||
2325 | |||
2326 | /* Periph extended clock configuration ops */ | ||
2327 | static int | ||
2328 | tegra3_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) | ||
2329 | { | ||
2330 | if (p == TEGRA_CLK_VI_INP_SEL) { | ||
2331 | u32 val = clk_readl(c->reg); | ||
2332 | val &= ~PERIPH_CLK_VI_SEL_EX_MASK; | ||
2333 | val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & | ||
2334 | PERIPH_CLK_VI_SEL_EX_MASK; | ||
2335 | clk_writel(val, c->reg); | ||
2336 | return 0; | ||
2337 | } | ||
2338 | return -EINVAL; | ||
2339 | } | ||
2340 | |||
2341 | static struct clk_ops tegra_vi_clk_ops = { | ||
2342 | .init = &tegra3_periph_clk_init, | ||
2343 | .enable = &tegra3_periph_clk_enable, | ||
2344 | .disable = &tegra3_periph_clk_disable, | ||
2345 | .set_parent = &tegra3_periph_clk_set_parent, | ||
2346 | .set_rate = &tegra3_periph_clk_set_rate, | ||
2347 | .round_rate = &tegra3_periph_clk_round_rate, | ||
2348 | .clk_cfg_ex = &tegra3_vi_clk_cfg_ex, | ||
2349 | .reset = &tegra3_periph_clk_reset, | ||
2350 | }; | ||
2351 | |||
2352 | static int | ||
2353 | tegra3_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) | ||
2354 | { | ||
2355 | if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { | ||
2356 | u32 val = clk_readl(c->reg); | ||
2357 | if (setting) | ||
2358 | val |= PERIPH_CLK_NAND_DIV_EX_ENB; | ||
2359 | else | ||
2360 | val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; | ||
2361 | clk_writel(val, c->reg); | ||
2362 | return 0; | ||
2363 | } | ||
2364 | return -EINVAL; | ||
2365 | } | ||
2366 | |||
2367 | static struct clk_ops tegra_nand_clk_ops = { | ||
2368 | .init = &tegra3_periph_clk_init, | ||
2369 | .enable = &tegra3_periph_clk_enable, | ||
2370 | .disable = &tegra3_periph_clk_disable, | ||
2371 | .set_parent = &tegra3_periph_clk_set_parent, | ||
2372 | .set_rate = &tegra3_periph_clk_set_rate, | ||
2373 | .round_rate = &tegra3_periph_clk_round_rate, | ||
2374 | .clk_cfg_ex = &tegra3_nand_clk_cfg_ex, | ||
2375 | .reset = &tegra3_periph_clk_reset, | ||
2376 | }; | ||
2377 | |||
2378 | |||
2379 | static int | ||
2380 | tegra3_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) | ||
2381 | { | ||
2382 | if (p == TEGRA_CLK_DTV_INVERT) { | ||
2383 | u32 val = clk_readl(c->reg); | ||
2384 | if (setting) | ||
2385 | val |= PERIPH_CLK_DTV_POLARITY_INV; | ||
2386 | else | ||
2387 | val &= ~PERIPH_CLK_DTV_POLARITY_INV; | ||
2388 | clk_writel(val, c->reg); | ||
2389 | return 0; | ||
2390 | } | ||
2391 | return -EINVAL; | ||
2392 | } | ||
2393 | |||
2394 | static struct clk_ops tegra_dtv_clk_ops = { | ||
2395 | .init = &tegra3_periph_clk_init, | ||
2396 | .enable = &tegra3_periph_clk_enable, | ||
2397 | .disable = &tegra3_periph_clk_disable, | ||
2398 | .set_parent = &tegra3_periph_clk_set_parent, | ||
2399 | .set_rate = &tegra3_periph_clk_set_rate, | ||
2400 | .round_rate = &tegra3_periph_clk_round_rate, | ||
2401 | .clk_cfg_ex = &tegra3_dtv_clk_cfg_ex, | ||
2402 | .reset = &tegra3_periph_clk_reset, | ||
2403 | }; | ||
2404 | |||
2405 | static int tegra3_dsib_clk_set_parent(struct clk *c, struct clk *p) | ||
2406 | { | ||
2407 | const struct clk_mux_sel *sel; | ||
2408 | struct clk *d = tegra_get_clock_by_name("pll_d"); | ||
2409 | |||
2410 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | ||
2411 | |||
2412 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2413 | if (sel->input == p) { | ||
2414 | if (c->refcnt) | ||
2415 | clk_enable(p); | ||
2416 | |||
2417 | /* The DSIB parent selection bit is in PLLD base | ||
2418 | register - can not do direct r-m-w, must be | ||
2419 | protected by PLLD lock */ | ||
2420 | tegra_clk_cfg_ex( | ||
2421 | d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value); | ||
2422 | |||
2423 | if (c->refcnt && c->parent) | ||
2424 | clk_disable(c->parent); | ||
2425 | |||
2426 | clk_reparent(c, p); | ||
2427 | return 0; | ||
2428 | } | ||
2429 | } | ||
2430 | |||
2431 | return -EINVAL; | ||
2432 | } | ||
2433 | |||
2434 | static struct clk_ops tegra_dsib_clk_ops = { | ||
2435 | .init = &tegra3_periph_clk_init, | ||
2436 | .enable = &tegra3_periph_clk_enable, | ||
2437 | .disable = &tegra3_periph_clk_disable, | ||
2438 | .set_parent = &tegra3_dsib_clk_set_parent, | ||
2439 | .set_rate = &tegra3_periph_clk_set_rate, | ||
2440 | .round_rate = &tegra3_periph_clk_round_rate, | ||
2441 | .reset = &tegra3_periph_clk_reset, | ||
2442 | }; | ||
2443 | |||
2444 | /* pciex clock support only reset function */ | ||
2445 | static struct clk_ops tegra_pciex_clk_ops = { | ||
2446 | .reset = tegra3_periph_clk_reset, | ||
2447 | }; | ||
2448 | |||
2449 | /* Output clock ops (non-atomic shared register access) */ | ||
2450 | |||
2451 | static DEFINE_SPINLOCK(clk_out_lock); | ||
2452 | |||
2453 | static void tegra3_clk_out_init(struct clk *c) | ||
2454 | { | ||
2455 | const struct clk_mux_sel *mux = 0; | ||
2456 | const struct clk_mux_sel *sel; | ||
2457 | u32 val = pmc_readl(c->reg); | ||
2458 | |||
2459 | c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; | ||
2460 | c->mul = 1; | ||
2461 | c->div = 1; | ||
2462 | |||
2463 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2464 | if (((val & periph_clk_source_mask(c)) >> | ||
2465 | periph_clk_source_shift(c)) == sel->value) | ||
2466 | mux = sel; | ||
2467 | } | ||
2468 | BUG_ON(!mux); | ||
2469 | c->parent = mux->input; | ||
2470 | } | ||
2471 | |||
2472 | static int tegra3_clk_out_enable(struct clk *c) | ||
2473 | { | ||
2474 | u32 val; | ||
2475 | unsigned long flags; | ||
2476 | |||
2477 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
2478 | |||
2479 | spin_lock_irqsave(&clk_out_lock, flags); | ||
2480 | val = pmc_readl(c->reg); | ||
2481 | val |= (0x1 << c->u.periph.clk_num); | ||
2482 | pmc_writel(val, c->reg); | ||
2483 | spin_unlock_irqrestore(&clk_out_lock, flags); | ||
2484 | |||
2485 | return 0; | ||
2486 | } | ||
2487 | |||
2488 | static void tegra3_clk_out_disable(struct clk *c) | ||
2489 | { | ||
2490 | u32 val; | ||
2491 | unsigned long flags; | ||
2492 | |||
2493 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
2494 | |||
2495 | spin_lock_irqsave(&clk_out_lock, flags); | ||
2496 | val = pmc_readl(c->reg); | ||
2497 | val &= ~(0x1 << c->u.periph.clk_num); | ||
2498 | pmc_writel(val, c->reg); | ||
2499 | spin_unlock_irqrestore(&clk_out_lock, flags); | ||
2500 | } | ||
2501 | |||
2502 | static int tegra3_clk_out_set_parent(struct clk *c, struct clk *p) | ||
2503 | { | ||
2504 | u32 val; | ||
2505 | unsigned long flags; | ||
2506 | const struct clk_mux_sel *sel; | ||
2507 | |||
2508 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | ||
2509 | |||
2510 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2511 | if (sel->input == p) { | ||
2512 | if (c->refcnt) | ||
2513 | clk_enable(p); | ||
2514 | |||
2515 | spin_lock_irqsave(&clk_out_lock, flags); | ||
2516 | val = pmc_readl(c->reg); | ||
2517 | val &= ~periph_clk_source_mask(c); | ||
2518 | val |= (sel->value << periph_clk_source_shift(c)); | ||
2519 | pmc_writel(val, c->reg); | ||
2520 | spin_unlock_irqrestore(&clk_out_lock, flags); | ||
2521 | |||
2522 | if (c->refcnt && c->parent) | ||
2523 | clk_disable(c->parent); | ||
2524 | |||
2525 | clk_reparent(c, p); | ||
2526 | return 0; | ||
2527 | } | ||
2528 | } | ||
2529 | return -EINVAL; | ||
2530 | } | ||
2531 | |||
2532 | static struct clk_ops tegra_clk_out_ops = { | ||
2533 | .init = &tegra3_clk_out_init, | ||
2534 | .enable = &tegra3_clk_out_enable, | ||
2535 | .disable = &tegra3_clk_out_disable, | ||
2536 | .set_parent = &tegra3_clk_out_set_parent, | ||
2537 | }; | ||
2538 | |||
2539 | |||
2540 | /* External memory controller clock ops */ | ||
2541 | static void tegra3_emc_clk_init(struct clk *c) | ||
2542 | { | ||
2543 | tegra3_periph_clk_init(c); | ||
2544 | tegra_emc_dram_type_init(c); | ||
2545 | |||
2546 | /* On A01 limit EMC maximum rate to boot frequency; | ||
2547 | starting with A02 full PLLM range should be supported */ | ||
2548 | if (tegra_get_revision() == TEGRA_REVISION_A01) | ||
2549 | c->max_rate = clk_get_rate_locked(c); | ||
2550 | else | ||
2551 | c->max_rate = clk_get_rate(c->parent); | ||
2552 | } | ||
2553 | |||
2554 | static long tegra3_emc_clk_round_rate(struct clk *c, unsigned long rate) | ||
2555 | { | ||
2556 | long new_rate = max(rate, c->min_rate); | ||
2557 | |||
2558 | new_rate = tegra_emc_round_rate(new_rate); | ||
2559 | if (new_rate < 0) | ||
2560 | new_rate = c->max_rate; | ||
2561 | |||
2562 | return new_rate; | ||
2563 | } | ||
2564 | |||
2565 | static int tegra3_emc_clk_set_rate(struct clk *c, unsigned long rate) | ||
2566 | { | ||
2567 | int ret; | ||
2568 | u32 div_value; | ||
2569 | struct clk *p; | ||
2570 | |||
2571 | /* The tegra3 memory controller has an interlock with the clock | ||
2572 | * block that allows memory shadowed registers to be updated, | ||
2573 | * and then transfer them to the main registers at the same | ||
2574 | * time as the clock update without glitches. During clock change | ||
2575 | * operation both clock parent and divider may change simultaneously | ||
2576 | * to achieve requested rate. */ | ||
2577 | p = tegra_emc_predict_parent(rate, &div_value); | ||
2578 | div_value += 2; /* emc has fractional DIV_U71 divider */ | ||
2579 | if (!p) | ||
2580 | return -EINVAL; | ||
2581 | |||
2582 | if (p == c->parent) { | ||
2583 | if (div_value == c->div) | ||
2584 | return 0; | ||
2585 | } else if (c->refcnt) | ||
2586 | clk_enable(p); | ||
2587 | |||
2588 | ret = tegra_emc_set_rate(rate); | ||
2589 | if (ret < 0) | ||
2590 | return ret; | ||
2591 | |||
2592 | if (p != c->parent) { | ||
2593 | if(c->refcnt && c->parent) | ||
2594 | clk_disable(c->parent); | ||
2595 | clk_reparent(c, p); | ||
2596 | } | ||
2597 | c->div = div_value; | ||
2598 | c->mul = 2; | ||
2599 | return 0; | ||
2600 | } | ||
2601 | |||
2602 | static struct clk_ops tegra_emc_clk_ops = { | ||
2603 | .init = &tegra3_emc_clk_init, | ||
2604 | .enable = &tegra3_periph_clk_enable, | ||
2605 | .disable = &tegra3_periph_clk_disable, | ||
2606 | .set_rate = &tegra3_emc_clk_set_rate, | ||
2607 | .round_rate = &tegra3_emc_clk_round_rate, | ||
2608 | .reset = &tegra3_periph_clk_reset, | ||
2609 | .shared_bus_update = &tegra3_clk_shared_bus_update, | ||
2610 | }; | ||
2611 | |||
2612 | /* Clock doubler ops (non-atomic shared register access) */ | ||
2613 | static DEFINE_SPINLOCK(doubler_lock); | ||
2614 | |||
2615 | static void tegra3_clk_double_init(struct clk *c) | ||
2616 | { | ||
2617 | u32 val = clk_readl(c->reg); | ||
2618 | c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; | ||
2619 | c->div = 1; | ||
2620 | c->state = ON; | ||
2621 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | ||
2622 | c->state = OFF; | ||
2623 | }; | ||
2624 | |||
2625 | static int tegra3_clk_double_set_rate(struct clk *c, unsigned long rate) | ||
2626 | { | ||
2627 | u32 val; | ||
2628 | unsigned long parent_rate = clk_get_rate(c->parent); | ||
2629 | unsigned long flags; | ||
2630 | |||
2631 | if (rate == parent_rate) { | ||
2632 | spin_lock_irqsave(&doubler_lock, flags); | ||
2633 | val = clk_readl(c->reg) | (0x1 << c->reg_shift); | ||
2634 | clk_writel(val, c->reg); | ||
2635 | c->mul = 1; | ||
2636 | c->div = 1; | ||
2637 | spin_unlock_irqrestore(&doubler_lock, flags); | ||
2638 | return 0; | ||
2639 | } else if (rate == 2 * parent_rate) { | ||
2640 | spin_lock_irqsave(&doubler_lock, flags); | ||
2641 | val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); | ||
2642 | clk_writel(val, c->reg); | ||
2643 | c->mul = 2; | ||
2644 | c->div = 1; | ||
2645 | spin_unlock_irqrestore(&doubler_lock, flags); | ||
2646 | return 0; | ||
2647 | } | ||
2648 | return -EINVAL; | ||
2649 | } | ||
2650 | |||
2651 | static struct clk_ops tegra_clk_double_ops = { | ||
2652 | .init = &tegra3_clk_double_init, | ||
2653 | .enable = &tegra3_periph_clk_enable, | ||
2654 | .disable = &tegra3_periph_clk_disable, | ||
2655 | .set_rate = &tegra3_clk_double_set_rate, | ||
2656 | }; | ||
2657 | |||
2658 | /* Audio sync clock ops */ | ||
2659 | static int tegra3_sync_source_set_rate(struct clk *c, unsigned long rate) | ||
2660 | { | ||
2661 | c->rate = rate; | ||
2662 | return 0; | ||
2663 | } | ||
2664 | |||
2665 | static struct clk_ops tegra_sync_source_ops = { | ||
2666 | .set_rate = &tegra3_sync_source_set_rate, | ||
2667 | }; | ||
2668 | |||
2669 | static void tegra3_audio_sync_clk_init(struct clk *c) | ||
2670 | { | ||
2671 | int source; | ||
2672 | const struct clk_mux_sel *sel; | ||
2673 | u32 val = clk_readl(c->reg); | ||
2674 | c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; | ||
2675 | source = val & AUDIO_SYNC_SOURCE_MASK; | ||
2676 | for (sel = c->inputs; sel->input != NULL; sel++) | ||
2677 | if (sel->value == source) | ||
2678 | break; | ||
2679 | BUG_ON(sel->input == NULL); | ||
2680 | c->parent = sel->input; | ||
2681 | } | ||
2682 | |||
2683 | static int tegra3_audio_sync_clk_enable(struct clk *c) | ||
2684 | { | ||
2685 | u32 val = clk_readl(c->reg); | ||
2686 | clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); | ||
2687 | return 0; | ||
2688 | } | ||
2689 | |||
2690 | static void tegra3_audio_sync_clk_disable(struct clk *c) | ||
2691 | { | ||
2692 | u32 val = clk_readl(c->reg); | ||
2693 | clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); | ||
2694 | } | ||
2695 | |||
2696 | static int tegra3_audio_sync_clk_set_parent(struct clk *c, struct clk *p) | ||
2697 | { | ||
2698 | u32 val; | ||
2699 | const struct clk_mux_sel *sel; | ||
2700 | for (sel = c->inputs; sel->input != NULL; sel++) { | ||
2701 | if (sel->input == p) { | ||
2702 | val = clk_readl(c->reg); | ||
2703 | val &= ~AUDIO_SYNC_SOURCE_MASK; | ||
2704 | val |= sel->value; | ||
2705 | |||
2706 | if (c->refcnt) | ||
2707 | clk_enable(p); | ||
2708 | |||
2709 | clk_writel(val, c->reg); | ||
2710 | |||
2711 | if (c->refcnt && c->parent) | ||
2712 | clk_disable(c->parent); | ||
2713 | |||
2714 | clk_reparent(c, p); | ||
2715 | return 0; | ||
2716 | } | ||
2717 | } | ||
2718 | |||
2719 | return -EINVAL; | ||
2720 | } | ||
2721 | |||
2722 | static struct clk_ops tegra_audio_sync_clk_ops = { | ||
2723 | .init = tegra3_audio_sync_clk_init, | ||
2724 | .enable = tegra3_audio_sync_clk_enable, | ||
2725 | .disable = tegra3_audio_sync_clk_disable, | ||
2726 | .set_parent = tegra3_audio_sync_clk_set_parent, | ||
2727 | }; | ||
2728 | |||
2729 | /* cml0 (pcie), and cml1 (sata) clock ops (non-atomic shared register access) */ | ||
2730 | static DEFINE_SPINLOCK(cml_lock); | ||
2731 | |||
2732 | static void tegra3_cml_clk_init(struct clk *c) | ||
2733 | { | ||
2734 | u32 val = clk_readl(c->reg); | ||
2735 | c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; | ||
2736 | } | ||
2737 | |||
2738 | static int tegra3_cml_clk_enable(struct clk *c) | ||
2739 | { | ||
2740 | u32 val; | ||
2741 | unsigned long flags; | ||
2742 | |||
2743 | spin_lock_irqsave(&cml_lock, flags); | ||
2744 | val = clk_readl(c->reg); | ||
2745 | val |= (0x1 << c->u.periph.clk_num); | ||
2746 | clk_writel(val, c->reg); | ||
2747 | spin_unlock_irqrestore(&cml_lock, flags); | ||
2748 | return 0; | ||
2749 | } | ||
2750 | |||
2751 | static void tegra3_cml_clk_disable(struct clk *c) | ||
2752 | { | ||
2753 | u32 val; | ||
2754 | unsigned long flags; | ||
2755 | |||
2756 | spin_lock_irqsave(&cml_lock, flags); | ||
2757 | val = clk_readl(c->reg); | ||
2758 | val &= ~(0x1 << c->u.periph.clk_num); | ||
2759 | clk_writel(val, c->reg); | ||
2760 | spin_unlock_irqrestore(&cml_lock, flags); | ||
2761 | } | ||
2762 | |||
2763 | static struct clk_ops tegra_cml_clk_ops = { | ||
2764 | .init = &tegra3_cml_clk_init, | ||
2765 | .enable = &tegra3_cml_clk_enable, | ||
2766 | .disable = &tegra3_cml_clk_disable, | ||
2767 | }; | ||
2768 | |||
2769 | |||
2770 | /* cbus ops */ | ||
2771 | /* | ||
2772 | * Some clocks require dynamic re-locking of source PLL in order to | ||
2773 | * achieve frequency scaling granularity that matches characterized | ||
2774 | * core voltage steps. The cbus clock creates a shared bus that | ||
2775 | * provides a virtual root for such clocks to hide and synchronize | ||
2776 | * parent PLL re-locking as well as backup operations. | ||
2777 | */ | ||
2778 | |||
2779 | static void tegra3_clk_cbus_init(struct clk *c) | ||
2780 | { | ||
2781 | c->state = OFF; | ||
2782 | c->set = true; | ||
2783 | } | ||
2784 | |||
2785 | static int tegra3_clk_cbus_enable(struct clk *c) | ||
2786 | { | ||
2787 | return 0; | ||
2788 | } | ||
2789 | |||
2790 | static long tegra3_clk_cbus_round_rate(struct clk *c, unsigned long rate) | ||
2791 | { | ||
2792 | int i; | ||
2793 | |||
2794 | if (!c->dvfs) | ||
2795 | return rate; | ||
2796 | |||
2797 | /* update min now, since no dvfs table was available during init | ||
2798 | (skip placeholder entries set to 1 kHz) */ | ||
2799 | if (!c->min_rate) { | ||
2800 | for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { | ||
2801 | if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) { | ||
2802 | c->min_rate = c->dvfs->freqs[i]; | ||
2803 | break; | ||
2804 | } | ||
2805 | } | ||
2806 | BUG_ON(!c->min_rate); | ||
2807 | } | ||
2808 | rate = max(rate, c->min_rate); | ||
2809 | |||
2810 | for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { | ||
2811 | unsigned long f = c->dvfs->freqs[i]; | ||
2812 | if (f >= rate) | ||
2813 | break; | ||
2814 | } | ||
2815 | return c->dvfs->freqs[i]; | ||
2816 | } | ||
2817 | |||
2818 | static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort) | ||
2819 | { | ||
2820 | int ret = 0; | ||
2821 | |||
2822 | /* set new divider if it is bigger than the current one */ | ||
2823 | if (c->div < c->mul * div) { | ||
2824 | ret = clk_set_div(c, div); | ||
2825 | if (ret) { | ||
2826 | pr_err("%s: failed to set %s clock divider %u: %d\n", | ||
2827 | __func__, c->name, div, ret); | ||
2828 | if (abort) | ||
2829 | return ret; | ||
2830 | } | ||
2831 | } | ||
2832 | |||
2833 | ret = clk_set_parent(c, p); | ||
2834 | if (ret) { | ||
2835 | pr_err("%s: failed to set %s clock parent %s: %d\n", | ||
2836 | __func__, c->name, p->name, ret); | ||
2837 | if (abort) | ||
2838 | return ret; | ||
2839 | } | ||
2840 | |||
2841 | /* set new divider if it is smaller than the current one */ | ||
2842 | if (c->div > c->mul * div) { | ||
2843 | ret = clk_set_div(c, div); | ||
2844 | if (ret) | ||
2845 | pr_err("%s: failed to set %s clock divider %u: %d\n", | ||
2846 | __func__, c->name, div, ret); | ||
2847 | } | ||
2848 | |||
2849 | return ret; | ||
2850 | } | ||
2851 | |||
2852 | static int cbus_backup(struct clk *c) | ||
2853 | { | ||
2854 | int ret; | ||
2855 | struct clk *user; | ||
2856 | |||
2857 | list_for_each_entry(user, &c->shared_bus_list, | ||
2858 | u.shared_bus_user.node) { | ||
2859 | bool enabled = user->u.shared_bus_user.client && | ||
2860 | (user->u.shared_bus_user.enabled || | ||
2861 | user->u.shared_bus_user.client->refcnt); | ||
2862 | if (enabled) { | ||
2863 | ret = cbus_switch_one(user->u.shared_bus_user.client, | ||
2864 | c->shared_bus_backup.input, | ||
2865 | c->shared_bus_backup.value * | ||
2866 | user->div, true); | ||
2867 | if (ret) | ||
2868 | return ret; | ||
2869 | } | ||
2870 | } | ||
2871 | return 0; | ||
2872 | } | ||
2873 | |||
2874 | static void cbus_restore(struct clk *c) | ||
2875 | { | ||
2876 | struct clk *user; | ||
2877 | |||
2878 | list_for_each_entry(user, &c->shared_bus_list, | ||
2879 | u.shared_bus_user.node) { | ||
2880 | bool back = user->u.shared_bus_user.client && (c->parent != | ||
2881 | user->u.shared_bus_user.client->parent); | ||
2882 | if (back) | ||
2883 | cbus_switch_one(user->u.shared_bus_user.client, | ||
2884 | c->parent, c->div * user->div, false); | ||
2885 | } | ||
2886 | } | ||
2887 | |||
2888 | static int tegra3_clk_cbus_set_rate(struct clk *c, unsigned long rate) | ||
2889 | { | ||
2890 | int ret; | ||
2891 | |||
2892 | if (rate == 0) | ||
2893 | return 0; | ||
2894 | |||
2895 | ret = clk_enable(c->parent); | ||
2896 | if (ret) { | ||
2897 | pr_err("%s: failed to enable %s clock: %d\n", | ||
2898 | __func__, c->name, ret); | ||
2899 | return ret; | ||
2900 | } | ||
2901 | |||
2902 | ret = cbus_backup(c); | ||
2903 | if (ret) | ||
2904 | goto out; | ||
2905 | |||
2906 | ret = clk_set_rate(c->parent, rate * c->div); | ||
2907 | if (ret) { | ||
2908 | pr_err("%s: failed to set %s clock rate %lu: %d\n", | ||
2909 | __func__, c->name, rate, ret); | ||
2910 | goto out; | ||
2911 | } | ||
2912 | |||
2913 | cbus_restore(c); | ||
2914 | |||
2915 | out: | ||
2916 | clk_disable(c->parent); | ||
2917 | return ret; | ||
2918 | } | ||
2919 | |||
2920 | static struct clk_ops tegra_clk_cbus_ops = { | ||
2921 | .init = tegra3_clk_cbus_init, | ||
2922 | .enable = tegra3_clk_cbus_enable, | ||
2923 | .set_rate = tegra3_clk_cbus_set_rate, | ||
2924 | .round_rate = tegra3_clk_cbus_round_rate, | ||
2925 | .shared_bus_update = tegra3_clk_shared_bus_update, | ||
2926 | }; | ||
2927 | |||
2928 | /* shared bus ops */ | ||
2929 | /* | ||
2930 | * Some clocks may have multiple downstream users that need to request a | ||
2931 | * higher clock rate. Shared bus clocks provide a unique shared_bus_user | ||
2932 | * clock to each user. The frequency of the bus is set to the highest | ||
2933 | * enabled shared_bus_user clock, with a minimum value set by the | ||
2934 | * shared bus. | ||
2935 | */ | ||
2936 | |||
2937 | static noinline int shared_bus_set_rate(struct clk *bus, unsigned long rate, | ||
2938 | unsigned long old_rate) | ||
2939 | { | ||
2940 | int ret, mv, old_mv; | ||
2941 | unsigned long bridge_rate = emc_bridge->u.shared_bus_user.rate; | ||
2942 | |||
2943 | /* If bridge is not needed (LPDDR2) just set bus rate */ | ||
2944 | if (tegra_emc_get_dram_type() == DRAM_TYPE_LPDDR2) | ||
2945 | return clk_set_rate_locked(bus, rate); | ||
2946 | |||
2947 | mv = tegra_dvfs_predict_millivolts(bus, rate); | ||
2948 | old_mv = tegra_dvfs_predict_millivolts(bus, old_rate); | ||
2949 | if (IS_ERR_VALUE(mv) || IS_ERR_VALUE(old_mv)) { | ||
2950 | pr_err("%s: Failed to predict %s voltage for %lu => %lu\n", | ||
2951 | __func__, bus->name, old_rate, rate); | ||
2952 | return -EINVAL; | ||
2953 | } | ||
2954 | |||
2955 | /* emc bus: set bridge rate as intermediate step when crossing | ||
2956 | * bridge threshold in any direction | ||
2957 | */ | ||
2958 | if (bus->flags & PERIPH_EMC_ENB) { | ||
2959 | if (((mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && | ||
2960 | (old_rate < bridge_rate)) || | ||
2961 | ((old_mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && | ||
2962 | (rate < bridge_rate))) { | ||
2963 | ret = clk_set_rate_locked(bus, bridge_rate); | ||
2964 | if (ret) { | ||
2965 | pr_err("%s: Failed to set emc bridge rate %lu\n", | ||
2966 | __func__, bridge_rate); | ||
2967 | return ret; | ||
2968 | } | ||
2969 | } | ||
2970 | return clk_set_rate_locked(bus, rate); | ||
2971 | } | ||
2972 | |||
2973 | /* sbus and cbus: enable/disable emc bridge user when crossing voltage | ||
2974 | * threshold up/down respectively; hence, emc rate is kept above the | ||
2975 | * bridge rate as long as any sbus or cbus user requires high voltage | ||
2976 | */ | ||
2977 | if ((mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && | ||
2978 | (old_mv <= TEGRA_EMC_BRIDGE_MVOLTS_MIN)) { | ||
2979 | ret = clk_enable(emc_bridge); | ||
2980 | if (ret) { | ||
2981 | pr_err("%s: Failed to enable emc bridge\n", __func__); | ||
2982 | return ret; | ||
2983 | } | ||
2984 | } | ||
2985 | |||
2986 | ret = clk_set_rate_locked(bus, rate); | ||
2987 | if (ret) | ||
2988 | return ret; | ||
2989 | |||
2990 | if ((mv <= TEGRA_EMC_BRIDGE_MVOLTS_MIN) && | ||
2991 | (old_mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN)) | ||
2992 | clk_disable(emc_bridge); | ||
2993 | |||
2994 | return 0; | ||
2995 | } | ||
2996 | |||
2997 | static int tegra3_clk_shared_bus_update(struct clk *bus) | ||
2998 | { | ||
2999 | struct clk *c; | ||
3000 | unsigned long old_rate; | ||
3001 | unsigned long rate = bus->min_rate; | ||
3002 | unsigned long bw = 0; | ||
3003 | unsigned long ceiling = bus->max_rate; | ||
3004 | |||
3005 | if (detach_shared_bus) | ||
3006 | return 0; | ||
3007 | |||
3008 | list_for_each_entry(c, &bus->shared_bus_list, | ||
3009 | u.shared_bus_user.node) { | ||
3010 | /* Ignore requests from disabled users and from users with | ||
3011 | fixed bus-to-client ratio */ | ||
3012 | if (c->u.shared_bus_user.enabled) { | ||
3013 | switch (c->u.shared_bus_user.mode) { | ||
3014 | case SHARED_BW: | ||
3015 | bw += c->u.shared_bus_user.rate; | ||
3016 | break; | ||
3017 | case SHARED_CEILING: | ||
3018 | ceiling = min(c->u.shared_bus_user.rate, | ||
3019 | ceiling); | ||
3020 | break; | ||
3021 | case SHARED_AUTO: | ||
3022 | case SHARED_FLOOR: | ||
3023 | default: | ||
3024 | rate = max(c->u.shared_bus_user.rate, rate); | ||
3025 | } | ||
3026 | } | ||
3027 | } | ||
3028 | rate = min(max(rate, bw), ceiling); | ||
3029 | |||
3030 | old_rate = clk_get_rate_locked(bus); | ||
3031 | if (rate == old_rate) | ||
3032 | return 0; | ||
3033 | |||
3034 | return shared_bus_set_rate(bus, rate, old_rate); | ||
3035 | }; | ||
3036 | |||
3037 | static void tegra_clk_shared_bus_init(struct clk *c) | ||
3038 | { | ||
3039 | c->max_rate = c->parent->max_rate; | ||
3040 | c->u.shared_bus_user.rate = c->parent->max_rate; | ||
3041 | c->state = OFF; | ||
3042 | c->set = true; | ||
3043 | |||
3044 | if (c->u.shared_bus_user.client_id) { | ||
3045 | c->u.shared_bus_user.client = | ||
3046 | tegra_get_clock_by_name(c->u.shared_bus_user.client_id); | ||
3047 | if (!c->u.shared_bus_user.client) { | ||
3048 | pr_err("%s: could not find clk %s\n", __func__, | ||
3049 | c->u.shared_bus_user.client_id); | ||
3050 | return; | ||
3051 | } | ||
3052 | c->u.shared_bus_user.client->flags |= | ||
3053 | c->parent->flags & PERIPH_ON_CBUS; | ||
3054 | c->flags |= c->parent->flags & PERIPH_ON_CBUS; | ||
3055 | c->div = c->u.shared_bus_user.client_div ? : 1; | ||
3056 | c->mul = 1; | ||
3057 | } | ||
3058 | |||
3059 | list_add_tail(&c->u.shared_bus_user.node, | ||
3060 | &c->parent->shared_bus_list); | ||
3061 | } | ||
3062 | |||
3063 | static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) | ||
3064 | { | ||
3065 | c->u.shared_bus_user.rate = rate; | ||
3066 | tegra_clk_shared_bus_update(c->parent); | ||
3067 | return 0; | ||
3068 | } | ||
3069 | |||
3070 | static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate) | ||
3071 | { | ||
3072 | /* auto user follow others, by itself it run at minimum bus rate */ | ||
3073 | if (c->u.shared_bus_user.mode == SHARED_AUTO) | ||
3074 | rate = 0; | ||
3075 | |||
3076 | return clk_round_rate(c->parent, rate); | ||
3077 | } | ||
3078 | |||
3079 | static int tegra_clk_shared_bus_enable(struct clk *c) | ||
3080 | { | ||
3081 | c->u.shared_bus_user.enabled = true; | ||
3082 | tegra_clk_shared_bus_update(c->parent); | ||
3083 | if (c->u.shared_bus_user.client) { | ||
3084 | return clk_enable(c->u.shared_bus_user.client); | ||
3085 | } | ||
3086 | return 0; | ||
3087 | } | ||
3088 | |||
3089 | static void tegra_clk_shared_bus_disable(struct clk *c) | ||
3090 | { | ||
3091 | if (c->u.shared_bus_user.client) | ||
3092 | clk_disable(c->u.shared_bus_user.client); | ||
3093 | c->u.shared_bus_user.enabled = false; | ||
3094 | tegra_clk_shared_bus_update(c->parent); | ||
3095 | } | ||
3096 | |||
3097 | static void tegra_clk_shared_bus_reset(struct clk *c, bool assert) | ||
3098 | { | ||
3099 | if (c->u.shared_bus_user.client) { | ||
3100 | if (c->u.shared_bus_user.client->ops && | ||
3101 | c->u.shared_bus_user.client->ops->reset) | ||
3102 | c->u.shared_bus_user.client->ops->reset( | ||
3103 | c->u.shared_bus_user.client, assert); | ||
3104 | } | ||
3105 | } | ||
3106 | |||
3107 | static struct clk_ops tegra_clk_shared_bus_ops = { | ||
3108 | .init = tegra_clk_shared_bus_init, | ||
3109 | .enable = tegra_clk_shared_bus_enable, | ||
3110 | .disable = tegra_clk_shared_bus_disable, | ||
3111 | .set_rate = tegra_clk_shared_bus_set_rate, | ||
3112 | .round_rate = tegra_clk_shared_bus_round_rate, | ||
3113 | .reset = tegra_clk_shared_bus_reset, | ||
3114 | }; | ||
3115 | |||
3116 | /* emc bridge ops */ | ||
3117 | /* On Tegra3 platforms emc configurations for DDR3 low rates can not work | ||
3118 | * at high core voltage; the intermediate step (bridge) is mandatory whenever | ||
3119 | * core voltage is crossing the threshold: TEGRA_EMC_BRIDGE_MVOLTS_MIN (fixed | ||
3120 | * for the entire Tegra3 arch); also emc must run above the bridge rate if any | ||
3121 | * other than emc clock requires high voltage. LP CPU, memory, sbus and cbus | ||
3122 | * together include all clocks that may require core voltage above threshold | ||
3123 | * (other peripherals can reach their maximum rates below threshold). LP CPU | ||
3124 | * dependency is taken care of via tegra_emc_to_cpu_ratio() api. Memory clock | ||
3125 | * transitions are forced to step through bridge rate; sbus and cbus control | ||
3126 | * emc bridge to set emc clock floor as necessary. | ||
3127 | * | ||
3128 | * EMC bridge is implemented as a special emc shared bus user: initialized at | ||
3129 | * minimum rate until updated once by emc dvfs setup; then it is only enabled | ||
3130 | * or disabled when sbus and/or cbus voltage is crossing the threshold. | ||
3131 | */ | ||
3132 | static void tegra3_clk_emc_bridge_init(struct clk *c) | ||
3133 | { | ||
3134 | tegra_clk_shared_bus_init(c); | ||
3135 | c->u.shared_bus_user.rate = 0; | ||
3136 | } | ||
3137 | |||
3138 | static int tegra3_clk_emc_bridge_set_rate(struct clk *c, unsigned long rate) | ||
3139 | { | ||
3140 | if (c->u.shared_bus_user.rate == 0) | ||
3141 | c->u.shared_bus_user.rate = rate; | ||
3142 | return 0; | ||
3143 | } | ||
3144 | |||
3145 | static struct clk_ops tegra_clk_emc_bridge_ops = { | ||
3146 | .init = tegra3_clk_emc_bridge_init, | ||
3147 | .enable = tegra_clk_shared_bus_enable, | ||
3148 | .disable = tegra_clk_shared_bus_disable, | ||
3149 | .set_rate = tegra3_clk_emc_bridge_set_rate, | ||
3150 | .round_rate = tegra_clk_shared_bus_round_rate, | ||
3151 | }; | ||
3152 | |||
3153 | /* Clock definitions */ | ||
3154 | static struct clk tegra_clk_32k = { | ||
3155 | .name = "clk_32k", | ||
3156 | .rate = 32768, | ||
3157 | .ops = NULL, | ||
3158 | .max_rate = 32768, | ||
3159 | }; | ||
3160 | |||
3161 | static struct clk tegra_clk_m = { | ||
3162 | .name = "clk_m", | ||
3163 | .flags = ENABLE_ON_INIT, | ||
3164 | .ops = &tegra_clk_m_ops, | ||
3165 | .reg = 0x1fc, | ||
3166 | .reg_shift = 28, | ||
3167 | .max_rate = 48000000, | ||
3168 | }; | ||
3169 | |||
3170 | static struct clk tegra_clk_m_div2 = { | ||
3171 | .name = "clk_m_div2", | ||
3172 | .ops = &tegra_clk_m_div_ops, | ||
3173 | .parent = &tegra_clk_m, | ||
3174 | .mul = 1, | ||
3175 | .div = 2, | ||
3176 | .state = ON, | ||
3177 | .max_rate = 24000000, | ||
3178 | }; | ||
3179 | |||
3180 | static struct clk tegra_clk_m_div4 = { | ||
3181 | .name = "clk_m_div4", | ||
3182 | .ops = &tegra_clk_m_div_ops, | ||
3183 | .parent = &tegra_clk_m, | ||
3184 | .mul = 1, | ||
3185 | .div = 4, | ||
3186 | .state = ON, | ||
3187 | .max_rate = 12000000, | ||
3188 | }; | ||
3189 | |||
3190 | static struct clk tegra_pll_ref = { | ||
3191 | .name = "pll_ref", | ||
3192 | .flags = ENABLE_ON_INIT, | ||
3193 | .ops = &tegra_pll_ref_ops, | ||
3194 | .parent = &tegra_clk_m, | ||
3195 | .max_rate = 26000000, | ||
3196 | }; | ||
3197 | |||
3198 | static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { | ||
3199 | { 12000000, 1200000000, 600, 6, 1, 8}, | ||
3200 | { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ | ||
3201 | { 16800000, 1200000000, 500, 7, 1, 8}, | ||
3202 | { 19200000, 1200000000, 500, 8, 1, 8}, | ||
3203 | { 26000000, 1200000000, 600, 13, 1, 8}, | ||
3204 | |||
3205 | { 12000000, 1040000000, 520, 6, 1, 8}, | ||
3206 | { 13000000, 1040000000, 480, 6, 1, 8}, | ||
3207 | { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ | ||
3208 | { 19200000, 1040000000, 325, 6, 1, 6}, | ||
3209 | { 26000000, 1040000000, 520, 13, 1, 8}, | ||
3210 | |||
3211 | { 12000000, 832000000, 416, 6, 1, 8}, | ||
3212 | { 13000000, 832000000, 832, 13, 1, 8}, | ||
3213 | { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ | ||
3214 | { 19200000, 832000000, 260, 6, 1, 8}, | ||
3215 | { 26000000, 832000000, 416, 13, 1, 8}, | ||
3216 | |||
3217 | { 12000000, 624000000, 624, 12, 1, 8}, | ||
3218 | { 13000000, 624000000, 624, 13, 1, 8}, | ||
3219 | { 16800000, 624000000, 520, 14, 1, 8}, | ||
3220 | { 19200000, 624000000, 520, 16, 1, 8}, | ||
3221 | { 26000000, 624000000, 624, 26, 1, 8}, | ||
3222 | |||
3223 | { 12000000, 600000000, 600, 12, 1, 8}, | ||
3224 | { 13000000, 600000000, 600, 13, 1, 8}, | ||
3225 | { 16800000, 600000000, 500, 14, 1, 8}, | ||
3226 | { 19200000, 600000000, 375, 12, 1, 6}, | ||
3227 | { 26000000, 600000000, 600, 26, 1, 8}, | ||
3228 | |||
3229 | { 12000000, 520000000, 520, 12, 1, 8}, | ||
3230 | { 13000000, 520000000, 520, 13, 1, 8}, | ||
3231 | { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ | ||
3232 | { 19200000, 520000000, 325, 12, 1, 6}, | ||
3233 | { 26000000, 520000000, 520, 26, 1, 8}, | ||
3234 | |||
3235 | { 12000000, 416000000, 416, 12, 1, 8}, | ||
3236 | { 13000000, 416000000, 416, 13, 1, 8}, | ||
3237 | { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ | ||
3238 | { 19200000, 416000000, 260, 12, 1, 6}, | ||
3239 | { 26000000, 416000000, 416, 26, 1, 8}, | ||
3240 | { 0, 0, 0, 0, 0, 0 }, | ||
3241 | }; | ||
3242 | |||
3243 | static struct clk tegra_pll_c = { | ||
3244 | .name = "pll_c", | ||
3245 | .flags = PLL_HAS_CPCON, | ||
3246 | .ops = &tegra_pll_ops, | ||
3247 | .reg = 0x80, | ||
3248 | .parent = &tegra_pll_ref, | ||
3249 | .max_rate = 1400000000, | ||
3250 | .u.pll = { | ||
3251 | .input_min = 2000000, | ||
3252 | .input_max = 31000000, | ||
3253 | .cf_min = 1000000, | ||
3254 | .cf_max = 6000000, | ||
3255 | .vco_min = 20000000, | ||
3256 | .vco_max = 1400000000, | ||
3257 | .freq_table = tegra_pll_c_freq_table, | ||
3258 | .lock_delay = 300, | ||
3259 | }, | ||
3260 | }; | ||
3261 | |||
3262 | static struct clk tegra_pll_c_out1 = { | ||
3263 | .name = "pll_c_out1", | ||
3264 | .ops = &tegra_pll_div_ops, | ||
3265 | .flags = DIV_U71 | PERIPH_ON_CBUS, | ||
3266 | .parent = &tegra_pll_c, | ||
3267 | .reg = 0x84, | ||
3268 | .reg_shift = 0, | ||
3269 | .max_rate = 700000000, | ||
3270 | }; | ||
3271 | |||
3272 | static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { | ||
3273 | { 12000000, 666000000, 666, 12, 1, 8}, | ||
3274 | { 13000000, 666000000, 666, 13, 1, 8}, | ||
3275 | { 16800000, 666000000, 555, 14, 1, 8}, | ||
3276 | { 19200000, 666000000, 555, 16, 1, 8}, | ||
3277 | { 26000000, 666000000, 666, 26, 1, 8}, | ||
3278 | { 12000000, 600000000, 600, 12, 1, 8}, | ||
3279 | { 13000000, 600000000, 600, 13, 1, 8}, | ||
3280 | { 16800000, 600000000, 500, 14, 1, 8}, | ||
3281 | { 19200000, 600000000, 375, 12, 1, 6}, | ||
3282 | { 26000000, 600000000, 600, 26, 1, 8}, | ||
3283 | { 0, 0, 0, 0, 0, 0 }, | ||
3284 | }; | ||
3285 | |||
3286 | static struct clk tegra_pll_m = { | ||
3287 | .name = "pll_m", | ||
3288 | .flags = PLL_HAS_CPCON | PLLM, | ||
3289 | .ops = &tegra_pll_ops, | ||
3290 | .reg = 0x90, | ||
3291 | .parent = &tegra_pll_ref, | ||
3292 | .max_rate = 900000000, | ||
3293 | .u.pll = { | ||
3294 | .input_min = 2000000, | ||
3295 | .input_max = 31000000, | ||
3296 | .cf_min = 1000000, | ||
3297 | .cf_max = 6000000, | ||
3298 | .vco_min = 20000000, | ||
3299 | .vco_max = 1200000000, | ||
3300 | .freq_table = tegra_pll_m_freq_table, | ||
3301 | .lock_delay = 300, | ||
3302 | }, | ||
3303 | }; | ||
3304 | |||
3305 | static struct clk tegra_pll_m_out1 = { | ||
3306 | .name = "pll_m_out1", | ||
3307 | .ops = &tegra_pll_div_ops, | ||
3308 | .flags = DIV_U71, | ||
3309 | .parent = &tegra_pll_m, | ||
3310 | .reg = 0x94, | ||
3311 | .reg_shift = 0, | ||
3312 | .max_rate = 600000000, | ||
3313 | }; | ||
3314 | |||
3315 | static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { | ||
3316 | { 12000000, 216000000, 432, 12, 2, 8}, | ||
3317 | { 13000000, 216000000, 432, 13, 2, 8}, | ||
3318 | { 16800000, 216000000, 360, 14, 2, 8}, | ||
3319 | { 19200000, 216000000, 360, 16, 2, 8}, | ||
3320 | { 26000000, 216000000, 432, 26, 2, 8}, | ||
3321 | { 0, 0, 0, 0, 0, 0 }, | ||
3322 | }; | ||
3323 | |||
3324 | static struct clk tegra_pll_p = { | ||
3325 | .name = "pll_p", | ||
3326 | .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, | ||
3327 | .ops = &tegra_pllp_ops, | ||
3328 | .reg = 0xa0, | ||
3329 | .parent = &tegra_pll_ref, | ||
3330 | .max_rate = 432000000, | ||
3331 | .u.pll = { | ||
3332 | .input_min = 2000000, | ||
3333 | .input_max = 31000000, | ||
3334 | .cf_min = 1000000, | ||
3335 | .cf_max = 6000000, | ||
3336 | .vco_min = 20000000, | ||
3337 | .vco_max = 1400000000, | ||
3338 | .freq_table = tegra_pll_p_freq_table, | ||
3339 | .lock_delay = 300, | ||
3340 | }, | ||
3341 | }; | ||
3342 | |||
3343 | static struct clk tegra_pll_p_out1 = { | ||
3344 | .name = "pll_p_out1", | ||
3345 | .ops = &tegra_pll_div_ops, | ||
3346 | .flags = DIV_U71 | DIV_U71_FIXED, | ||
3347 | .parent = &tegra_pll_p, | ||
3348 | .reg = 0xa4, | ||
3349 | .reg_shift = 0, | ||
3350 | .max_rate = 432000000, | ||
3351 | }; | ||
3352 | |||
3353 | static struct clk tegra_pll_p_out2 = { | ||
3354 | .name = "pll_p_out2", | ||
3355 | .ops = &tegra_pll_div_ops, | ||
3356 | .flags = DIV_U71 | DIV_U71_FIXED, | ||
3357 | .parent = &tegra_pll_p, | ||
3358 | .reg = 0xa4, | ||
3359 | .reg_shift = 16, | ||
3360 | .max_rate = 432000000, | ||
3361 | }; | ||
3362 | |||
3363 | static struct clk tegra_pll_p_out3 = { | ||
3364 | .name = "pll_p_out3", | ||
3365 | .ops = &tegra_pll_div_ops, | ||
3366 | .flags = DIV_U71 | DIV_U71_FIXED, | ||
3367 | .parent = &tegra_pll_p, | ||
3368 | .reg = 0xa8, | ||
3369 | .reg_shift = 0, | ||
3370 | .max_rate = 432000000, | ||
3371 | }; | ||
3372 | |||
3373 | static struct clk tegra_pll_p_out4 = { | ||
3374 | .name = "pll_p_out4", | ||
3375 | .ops = &tegra_pll_div_ops, | ||
3376 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | ||
3377 | .parent = &tegra_pll_p, | ||
3378 | .reg = 0xa8, | ||
3379 | .reg_shift = 16, | ||
3380 | .max_rate = 432000000, | ||
3381 | }; | ||
3382 | |||
3383 | static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { | ||
3384 | { 9600000, 564480000, 294, 5, 1, 4}, | ||
3385 | { 9600000, 552960000, 288, 5, 1, 4}, | ||
3386 | { 9600000, 24000000, 5, 2, 1, 1}, | ||
3387 | |||
3388 | { 28800000, 56448000, 49, 25, 1, 1}, | ||
3389 | { 28800000, 73728000, 64, 25, 1, 1}, | ||
3390 | { 28800000, 24000000, 5, 6, 1, 1}, | ||
3391 | { 0, 0, 0, 0, 0, 0 }, | ||
3392 | }; | ||
3393 | |||
3394 | static struct clk tegra_pll_a = { | ||
3395 | .name = "pll_a", | ||
3396 | .flags = PLL_HAS_CPCON, | ||
3397 | .ops = &tegra_pll_ops, | ||
3398 | .reg = 0xb0, | ||
3399 | .parent = &tegra_pll_p_out1, | ||
3400 | .max_rate = 700000000, | ||
3401 | .u.pll = { | ||
3402 | .input_min = 2000000, | ||
3403 | .input_max = 31000000, | ||
3404 | .cf_min = 1000000, | ||
3405 | .cf_max = 6000000, | ||
3406 | .vco_min = 20000000, | ||
3407 | .vco_max = 1400000000, | ||
3408 | .freq_table = tegra_pll_a_freq_table, | ||
3409 | .lock_delay = 300, | ||
3410 | }, | ||
3411 | }; | ||
3412 | |||
3413 | static struct clk tegra_pll_a_out0 = { | ||
3414 | .name = "pll_a_out0", | ||
3415 | .ops = &tegra_pll_div_ops, | ||
3416 | .flags = DIV_U71, | ||
3417 | .parent = &tegra_pll_a, | ||
3418 | .reg = 0xb4, | ||
3419 | .reg_shift = 0, | ||
3420 | .max_rate = 100000000, | ||
3421 | }; | ||
3422 | |||
3423 | static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { | ||
3424 | { 12000000, 216000000, 216, 12, 1, 4}, | ||
3425 | { 13000000, 216000000, 216, 13, 1, 4}, | ||
3426 | { 16800000, 216000000, 180, 14, 1, 4}, | ||
3427 | { 19200000, 216000000, 180, 16, 1, 4}, | ||
3428 | { 26000000, 216000000, 216, 26, 1, 4}, | ||
3429 | |||
3430 | { 12000000, 594000000, 594, 12, 1, 8}, | ||
3431 | { 13000000, 594000000, 594, 13, 1, 8}, | ||
3432 | { 16800000, 594000000, 495, 14, 1, 8}, | ||
3433 | { 19200000, 594000000, 495, 16, 1, 8}, | ||
3434 | { 26000000, 594000000, 594, 26, 1, 8}, | ||
3435 | |||
3436 | { 12000000, 1000000000, 1000, 12, 1, 12}, | ||
3437 | { 13000000, 1000000000, 1000, 13, 1, 12}, | ||
3438 | { 19200000, 1000000000, 625, 12, 1, 8}, | ||
3439 | { 26000000, 1000000000, 1000, 26, 1, 12}, | ||
3440 | |||
3441 | { 0, 0, 0, 0, 0, 0 }, | ||
3442 | }; | ||
3443 | |||
3444 | static struct clk tegra_pll_d = { | ||
3445 | .name = "pll_d", | ||
3446 | .flags = PLL_HAS_CPCON | PLLD, | ||
3447 | .ops = &tegra_plld_ops, | ||
3448 | .reg = 0xd0, | ||
3449 | .parent = &tegra_pll_ref, | ||
3450 | .max_rate = 1000000000, | ||
3451 | .u.pll = { | ||
3452 | .input_min = 2000000, | ||
3453 | .input_max = 40000000, | ||
3454 | .cf_min = 1000000, | ||
3455 | .cf_max = 6000000, | ||
3456 | .vco_min = 40000000, | ||
3457 | .vco_max = 1000000000, | ||
3458 | .freq_table = tegra_pll_d_freq_table, | ||
3459 | .lock_delay = 1000, | ||
3460 | }, | ||
3461 | }; | ||
3462 | |||
3463 | static struct clk tegra_pll_d_out0 = { | ||
3464 | .name = "pll_d_out0", | ||
3465 | .ops = &tegra_pll_div_ops, | ||
3466 | .flags = DIV_2 | PLLD, | ||
3467 | .parent = &tegra_pll_d, | ||
3468 | .max_rate = 500000000, | ||
3469 | }; | ||
3470 | |||
3471 | static struct clk tegra_pll_d2 = { | ||
3472 | .name = "pll_d2", | ||
3473 | .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, | ||
3474 | .ops = &tegra_plld_ops, | ||
3475 | .reg = 0x4b8, | ||
3476 | .parent = &tegra_pll_ref, | ||
3477 | .max_rate = 1000000000, | ||
3478 | .u.pll = { | ||
3479 | .input_min = 2000000, | ||
3480 | .input_max = 40000000, | ||
3481 | .cf_min = 1000000, | ||
3482 | .cf_max = 6000000, | ||
3483 | .vco_min = 40000000, | ||
3484 | .vco_max = 1000000000, | ||
3485 | .freq_table = tegra_pll_d_freq_table, | ||
3486 | .lock_delay = 1000, | ||
3487 | }, | ||
3488 | }; | ||
3489 | |||
3490 | static struct clk tegra_pll_d2_out0 = { | ||
3491 | .name = "pll_d2_out0", | ||
3492 | .ops = &tegra_pll_div_ops, | ||
3493 | .flags = DIV_2 | PLLD, | ||
3494 | .parent = &tegra_pll_d2, | ||
3495 | .max_rate = 500000000, | ||
3496 | }; | ||
3497 | |||
3498 | static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { | ||
3499 | { 12000000, 480000000, 960, 12, 2, 12}, | ||
3500 | { 13000000, 480000000, 960, 13, 2, 12}, | ||
3501 | { 16800000, 480000000, 400, 7, 2, 5}, | ||
3502 | { 19200000, 480000000, 200, 4, 2, 3}, | ||
3503 | { 26000000, 480000000, 960, 26, 2, 12}, | ||
3504 | { 0, 0, 0, 0, 0, 0 }, | ||
3505 | }; | ||
3506 | |||
3507 | static struct clk tegra_pll_u = { | ||
3508 | .name = "pll_u", | ||
3509 | .flags = PLL_HAS_CPCON | PLLU, | ||
3510 | .ops = &tegra_pll_ops, | ||
3511 | .reg = 0xc0, | ||
3512 | .parent = &tegra_pll_ref, | ||
3513 | .max_rate = 480000000, | ||
3514 | .u.pll = { | ||
3515 | .input_min = 2000000, | ||
3516 | .input_max = 40000000, | ||
3517 | .cf_min = 1000000, | ||
3518 | .cf_max = 6000000, | ||
3519 | .vco_min = 480000000, | ||
3520 | .vco_max = 960000000, | ||
3521 | .freq_table = tegra_pll_u_freq_table, | ||
3522 | .lock_delay = 1000, | ||
3523 | }, | ||
3524 | }; | ||
3525 | |||
3526 | static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { | ||
3527 | /* 1.7 GHz */ | ||
3528 | { 12000000, 1700000000, 850, 6, 1, 8}, | ||
3529 | { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ | ||
3530 | { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ | ||
3531 | { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ | ||
3532 | { 26000000, 1700000000, 850, 13, 1, 8}, | ||
3533 | |||
3534 | /* 1.6 GHz */ | ||
3535 | { 12000000, 1600000000, 800, 6, 1, 8}, | ||
3536 | { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ | ||
3537 | { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ | ||
3538 | { 19200000, 1600000000, 500, 6, 1, 8}, | ||
3539 | { 26000000, 1600000000, 800, 13, 1, 8}, | ||
3540 | |||
3541 | /* 1.5 GHz */ | ||
3542 | { 12000000, 1500000000, 750, 6, 1, 8}, | ||
3543 | { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ | ||
3544 | { 16800000, 1500000000, 625, 7, 1, 8}, | ||
3545 | { 19200000, 1500000000, 625, 8, 1, 8}, | ||
3546 | { 26000000, 1500000000, 750, 13, 1, 8}, | ||
3547 | |||
3548 | /* 1.4 GHz */ | ||
3549 | { 12000000, 1400000000, 700, 6, 1, 8}, | ||
3550 | { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ | ||
3551 | { 16800000, 1400000000, 1000, 12, 1, 8}, | ||
3552 | { 19200000, 1400000000, 875, 12, 1, 8}, | ||
3553 | { 26000000, 1400000000, 700, 13, 1, 8}, | ||
3554 | |||
3555 | /* 1.3 GHz */ | ||
3556 | { 12000000, 1300000000, 975, 9, 1, 8}, | ||
3557 | { 13000000, 1300000000, 1000, 10, 1, 8}, | ||
3558 | { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ | ||
3559 | { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ | ||
3560 | { 26000000, 1300000000, 650, 13, 1, 8}, | ||
3561 | |||
3562 | /* 1.2 GHz */ | ||
3563 | { 12000000, 1200000000, 1000, 10, 1, 8}, | ||
3564 | { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ | ||
3565 | { 16800000, 1200000000, 1000, 14, 1, 8}, | ||
3566 | { 19200000, 1200000000, 1000, 16, 1, 8}, | ||
3567 | { 26000000, 1200000000, 600, 13, 1, 8}, | ||
3568 | |||
3569 | /* 1.1 GHz */ | ||
3570 | { 12000000, 1100000000, 825, 9, 1, 8}, | ||
3571 | { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ | ||
3572 | { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ | ||
3573 | { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ | ||
3574 | { 26000000, 1100000000, 550, 13, 1, 8}, | ||
3575 | |||
3576 | /* 1 GHz */ | ||
3577 | { 12000000, 1000000000, 1000, 12, 1, 8}, | ||
3578 | { 13000000, 1000000000, 1000, 13, 1, 8}, | ||
3579 | { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ | ||
3580 | { 19200000, 1000000000, 625, 12, 1, 8}, | ||
3581 | { 26000000, 1000000000, 1000, 26, 1, 8}, | ||
3582 | |||
3583 | { 0, 0, 0, 0, 0, 0 }, | ||
3584 | }; | ||
3585 | |||
3586 | static struct clk tegra_pll_x = { | ||
3587 | .name = "pll_x", | ||
3588 | .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, | ||
3589 | .ops = &tegra_pll_ops, | ||
3590 | .reg = 0xe0, | ||
3591 | .parent = &tegra_pll_ref, | ||
3592 | .max_rate = 1700000000, | ||
3593 | .u.pll = { | ||
3594 | .input_min = 2000000, | ||
3595 | .input_max = 31000000, | ||
3596 | .cf_min = 1000000, | ||
3597 | .cf_max = 6000000, | ||
3598 | .vco_min = 20000000, | ||
3599 | .vco_max = 1700000000, | ||
3600 | .freq_table = tegra_pll_x_freq_table, | ||
3601 | .lock_delay = 300, | ||
3602 | }, | ||
3603 | }; | ||
3604 | |||
3605 | static struct clk tegra_pll_x_out0 = { | ||
3606 | .name = "pll_x_out0", | ||
3607 | .ops = &tegra_pll_div_ops, | ||
3608 | .flags = DIV_2 | PLLX, | ||
3609 | .parent = &tegra_pll_x, | ||
3610 | .max_rate = 850000000, | ||
3611 | }; | ||
3612 | |||
3613 | |||
3614 | static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { | ||
3615 | /* PLLE special case: use cpcon field to store cml divider value */ | ||
3616 | { 12000000, 100000000, 150, 1, 18, 11}, | ||
3617 | { 216000000, 100000000, 200, 18, 24, 13}, | ||
3618 | #ifndef CONFIG_TEGRA_SILICON_PLATFORM | ||
3619 | { 13000000, 100000000, 200, 1, 26, 13}, | ||
3620 | #endif | ||
3621 | { 0, 0, 0, 0, 0, 0 }, | ||
3622 | }; | ||
3623 | |||
3624 | static struct clk tegra_pll_e = { | ||
3625 | .name = "pll_e", | ||
3626 | .flags = PLL_ALT_MISC_REG, | ||
3627 | .ops = &tegra_plle_ops, | ||
3628 | .reg = 0xe8, | ||
3629 | .max_rate = 100000000, | ||
3630 | .u.pll = { | ||
3631 | .input_min = 12000000, | ||
3632 | .input_max = 216000000, | ||
3633 | .cf_min = 12000000, | ||
3634 | .cf_max = 12000000, | ||
3635 | .vco_min = 1200000000, | ||
3636 | .vco_max = 2400000000U, | ||
3637 | .freq_table = tegra_pll_e_freq_table, | ||
3638 | .lock_delay = 300, | ||
3639 | .fixed_rate = 100000000, | ||
3640 | }, | ||
3641 | }; | ||
3642 | |||
3643 | static struct clk tegra_cml0_clk = { | ||
3644 | .name = "cml0", | ||
3645 | .parent = &tegra_pll_e, | ||
3646 | .ops = &tegra_cml_clk_ops, | ||
3647 | .reg = PLLE_AUX, | ||
3648 | .max_rate = 100000000, | ||
3649 | .u.periph = { | ||
3650 | .clk_num = 0, | ||
3651 | }, | ||
3652 | }; | ||
3653 | |||
3654 | static struct clk tegra_cml1_clk = { | ||
3655 | .name = "cml1", | ||
3656 | .parent = &tegra_pll_e, | ||
3657 | .ops = &tegra_cml_clk_ops, | ||
3658 | .reg = PLLE_AUX, | ||
3659 | .max_rate = 100000000, | ||
3660 | .u.periph = { | ||
3661 | .clk_num = 1, | ||
3662 | }, | ||
3663 | }; | ||
3664 | |||
3665 | static struct clk tegra_pciex_clk = { | ||
3666 | .name = "pciex", | ||
3667 | .parent = &tegra_pll_e, | ||
3668 | .ops = &tegra_pciex_clk_ops, | ||
3669 | .max_rate = 100000000, | ||
3670 | .u.periph = { | ||
3671 | .clk_num = 74, | ||
3672 | }, | ||
3673 | }; | ||
3674 | |||
3675 | /* Audio sync clocks */ | ||
3676 | #define SYNC_SOURCE(_id, _dev) \ | ||
3677 | { \ | ||
3678 | .name = #_id "_sync", \ | ||
3679 | .lookup = { \ | ||
3680 | .dev_id = #_dev , \ | ||
3681 | .con_id = "ext_audio_sync", \ | ||
3682 | }, \ | ||
3683 | .rate = 24000000, \ | ||
3684 | .max_rate = 24000000, \ | ||
3685 | .ops = &tegra_sync_source_ops \ | ||
3686 | } | ||
3687 | static struct clk tegra_sync_source_list[] = { | ||
3688 | SYNC_SOURCE(spdif_in, tegra30-spdif), | ||
3689 | SYNC_SOURCE(i2s0, tegra30-i2s.0), | ||
3690 | SYNC_SOURCE(i2s1, tegra30-i2s.1), | ||
3691 | SYNC_SOURCE(i2s2, tegra30-i2s.2), | ||
3692 | SYNC_SOURCE(i2s3, tegra30-i2s.3), | ||
3693 | SYNC_SOURCE(i2s4, tegra30-i2s.4), | ||
3694 | SYNC_SOURCE(vimclk, vimclk), | ||
3695 | }; | ||
3696 | |||
3697 | static struct clk_mux_sel mux_audio_sync_clk[] = | ||
3698 | { | ||
3699 | { .input = &tegra_sync_source_list[0], .value = 0}, | ||
3700 | { .input = &tegra_sync_source_list[1], .value = 1}, | ||
3701 | { .input = &tegra_sync_source_list[2], .value = 2}, | ||
3702 | { .input = &tegra_sync_source_list[3], .value = 3}, | ||
3703 | { .input = &tegra_sync_source_list[4], .value = 4}, | ||
3704 | { .input = &tegra_sync_source_list[5], .value = 5}, | ||
3705 | { .input = &tegra_pll_a_out0, .value = 6}, | ||
3706 | { .input = &tegra_sync_source_list[6], .value = 7}, | ||
3707 | { 0, 0 } | ||
3708 | }; | ||
3709 | |||
3710 | #define AUDIO_SYNC_CLK(_id, _dev, _index) \ | ||
3711 | { \ | ||
3712 | .name = #_id, \ | ||
3713 | .lookup = { \ | ||
3714 | .dev_id = #_dev, \ | ||
3715 | .con_id = "audio_sync", \ | ||
3716 | }, \ | ||
3717 | .inputs = mux_audio_sync_clk, \ | ||
3718 | .reg = 0x4A0 + (_index) * 4, \ | ||
3719 | .max_rate = 24000000, \ | ||
3720 | .ops = &tegra_audio_sync_clk_ops \ | ||
3721 | } | ||
3722 | static struct clk tegra_clk_audio_list[] = { | ||
3723 | AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0), | ||
3724 | AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1), | ||
3725 | AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2), | ||
3726 | AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3), | ||
3727 | AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4), | ||
3728 | AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), | ||
3729 | }; | ||
3730 | |||
3731 | #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \ | ||
3732 | { \ | ||
3733 | .name = #_id "_2x", \ | ||
3734 | .lookup = { \ | ||
3735 | .dev_id = #_dev, \ | ||
3736 | .con_id = "audio_sync_2x" \ | ||
3737 | }, \ | ||
3738 | .flags = PERIPH_NO_RESET, \ | ||
3739 | .max_rate = 48000000, \ | ||
3740 | .ops = &tegra_clk_double_ops, \ | ||
3741 | .reg = 0x49C, \ | ||
3742 | .reg_shift = 24 + (_index), \ | ||
3743 | .parent = &tegra_clk_audio_list[(_index)], \ | ||
3744 | .u.periph = { \ | ||
3745 | .clk_num = 113 + (_index), \ | ||
3746 | }, \ | ||
3747 | } | ||
3748 | static struct clk tegra_clk_audio_2x_list[] = { | ||
3749 | AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0), | ||
3750 | AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1), | ||
3751 | AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2), | ||
3752 | AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3), | ||
3753 | AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4), | ||
3754 | AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), | ||
3755 | }; | ||
3756 | |||
3757 | #define MUX_I2S_SPDIF(_id, _index) \ | ||
3758 | static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ | ||
3759 | {.input = &tegra_pll_a_out0, .value = 0}, \ | ||
3760 | {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ | ||
3761 | {.input = &tegra_pll_p, .value = 2}, \ | ||
3762 | {.input = &tegra_clk_m, .value = 3}, \ | ||
3763 | { 0, 0}, \ | ||
3764 | } | ||
3765 | MUX_I2S_SPDIF(audio0, 0); | ||
3766 | MUX_I2S_SPDIF(audio1, 1); | ||
3767 | MUX_I2S_SPDIF(audio2, 2); | ||
3768 | MUX_I2S_SPDIF(audio3, 3); | ||
3769 | MUX_I2S_SPDIF(audio4, 4); | ||
3770 | MUX_I2S_SPDIF(audio, 5); /* SPDIF */ | ||
3771 | |||
3772 | /* External clock outputs (through PMC) */ | ||
3773 | #define MUX_EXTERN_OUT(_id) \ | ||
3774 | static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \ | ||
3775 | {.input = &tegra_clk_m, .value = 0}, \ | ||
3776 | {.input = &tegra_clk_m_div2, .value = 1}, \ | ||
3777 | {.input = &tegra_clk_m_div4, .value = 2}, \ | ||
3778 | {.input = NULL, .value = 3}, /* placeholder */ \ | ||
3779 | { 0, 0}, \ | ||
3780 | } | ||
3781 | MUX_EXTERN_OUT(1); | ||
3782 | MUX_EXTERN_OUT(2); | ||
3783 | MUX_EXTERN_OUT(3); | ||
3784 | |||
3785 | static struct clk_mux_sel *mux_extern_out_list[] = { | ||
3786 | mux_clkm_clkm2_clkm4_extern1, | ||
3787 | mux_clkm_clkm2_clkm4_extern2, | ||
3788 | mux_clkm_clkm2_clkm4_extern3, | ||
3789 | }; | ||
3790 | |||
3791 | #define CLK_OUT_CLK(_id) \ | ||
3792 | { \ | ||
3793 | .name = "clk_out_" #_id, \ | ||
3794 | .lookup = { \ | ||
3795 | .dev_id = "clk_out_" #_id, \ | ||
3796 | .con_id = "extern" #_id, \ | ||
3797 | }, \ | ||
3798 | .ops = &tegra_clk_out_ops, \ | ||
3799 | .reg = 0x1a8, \ | ||
3800 | .inputs = mux_clkm_clkm2_clkm4_extern##_id, \ | ||
3801 | .flags = MUX_CLK_OUT, \ | ||
3802 | .max_rate = 216000000, \ | ||
3803 | .u.periph = { \ | ||
3804 | .clk_num = (_id - 1) * 8 + 2, \ | ||
3805 | }, \ | ||
3806 | } | ||
3807 | static struct clk tegra_clk_out_list[] = { | ||
3808 | CLK_OUT_CLK(1), | ||
3809 | CLK_OUT_CLK(2), | ||
3810 | CLK_OUT_CLK(3), | ||
3811 | }; | ||
3812 | |||
3813 | /* called after peripheral external clocks are initialized */ | ||
3814 | static void init_clk_out_mux(void) | ||
3815 | { | ||
3816 | int i; | ||
3817 | struct clk *c; | ||
3818 | |||
3819 | /* output clock con_id is the name of peripheral | ||
3820 | external clock connected to input 3 of the output mux */ | ||
3821 | for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) { | ||
3822 | c = tegra_get_clock_by_name( | ||
3823 | tegra_clk_out_list[i].lookup.con_id); | ||
3824 | if (!c) | ||
3825 | pr_err("%s: could not find clk %s\n", __func__, | ||
3826 | tegra_clk_out_list[i].lookup.con_id); | ||
3827 | mux_extern_out_list[i][3].input = c; | ||
3828 | } | ||
3829 | } | ||
3830 | |||
3831 | /* Peripheral muxes */ | ||
3832 | static struct clk_mux_sel mux_cclk_g[] = { | ||
3833 | { .input = &tegra_clk_m, .value = 0}, | ||
3834 | { .input = &tegra_pll_c, .value = 1}, | ||
3835 | { .input = &tegra_clk_32k, .value = 2}, | ||
3836 | { .input = &tegra_pll_m, .value = 3}, | ||
3837 | { .input = &tegra_pll_p, .value = 4}, | ||
3838 | { .input = &tegra_pll_p_out4, .value = 5}, | ||
3839 | { .input = &tegra_pll_p_out3, .value = 6}, | ||
3840 | /* { .input = &tegra_clk_d, .value = 7}, - no use on tegra3 */ | ||
3841 | { .input = &tegra_pll_x, .value = 8}, | ||
3842 | { 0, 0}, | ||
3843 | }; | ||
3844 | |||
3845 | static struct clk_mux_sel mux_cclk_lp[] = { | ||
3846 | { .input = &tegra_clk_m, .value = 0}, | ||
3847 | { .input = &tegra_pll_c, .value = 1}, | ||
3848 | { .input = &tegra_clk_32k, .value = 2}, | ||
3849 | { .input = &tegra_pll_m, .value = 3}, | ||
3850 | { .input = &tegra_pll_p, .value = 4}, | ||
3851 | { .input = &tegra_pll_p_out4, .value = 5}, | ||
3852 | { .input = &tegra_pll_p_out3, .value = 6}, | ||
3853 | /* { .input = &tegra_clk_d, .value = 7}, - no use on tegra3 */ | ||
3854 | { .input = &tegra_pll_x_out0, .value = 8}, | ||
3855 | { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS}, | ||
3856 | { 0, 0}, | ||
3857 | }; | ||
3858 | |||
3859 | static struct clk_mux_sel mux_sclk[] = { | ||
3860 | { .input = &tegra_clk_m, .value = 0}, | ||
3861 | { .input = &tegra_pll_c_out1, .value = 1}, | ||
3862 | { .input = &tegra_pll_p_out4, .value = 2}, | ||
3863 | { .input = &tegra_pll_p_out3, .value = 3}, | ||
3864 | { .input = &tegra_pll_p_out2, .value = 4}, | ||
3865 | /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra3 */ | ||
3866 | { .input = &tegra_clk_32k, .value = 6}, | ||
3867 | { .input = &tegra_pll_m_out1, .value = 7}, | ||
3868 | { 0, 0}, | ||
3869 | }; | ||
3870 | |||
3871 | static struct clk tegra_clk_cclk_g = { | ||
3872 | .name = "cclk_g", | ||
3873 | .flags = DIV_U71 | DIV_U71_INT, | ||
3874 | .inputs = mux_cclk_g, | ||
3875 | .reg = 0x368, | ||
3876 | .ops = &tegra_super_ops, | ||
3877 | .max_rate = 1700000000, | ||
3878 | }; | ||
3879 | |||
3880 | static struct clk tegra_clk_cclk_lp = { | ||
3881 | .name = "cclk_lp", | ||
3882 | .flags = DIV_2 | DIV_U71 | DIV_U71_INT, | ||
3883 | .inputs = mux_cclk_lp, | ||
3884 | .reg = 0x370, | ||
3885 | .ops = &tegra_super_ops, | ||
3886 | .max_rate = 620000000, | ||
3887 | }; | ||
3888 | |||
3889 | static struct clk tegra_clk_sclk = { | ||
3890 | .name = "sclk", | ||
3891 | .inputs = mux_sclk, | ||
3892 | .reg = 0x28, | ||
3893 | .ops = &tegra_super_ops, | ||
3894 | .max_rate = 378000000, | ||
3895 | .min_rate = 40000000, | ||
3896 | }; | ||
3897 | |||
3898 | static struct clk tegra_clk_virtual_cpu_g = { | ||
3899 | .name = "cpu_g", | ||
3900 | .parent = &tegra_clk_cclk_g, | ||
3901 | .ops = &tegra_cpu_ops, | ||
3902 | .max_rate = 1700000000, | ||
3903 | .u.cpu = { | ||
3904 | .main = &tegra_pll_x, | ||
3905 | .backup = &tegra_pll_p, | ||
3906 | .mode = MODE_G, | ||
3907 | }, | ||
3908 | }; | ||
3909 | |||
3910 | static struct clk tegra_clk_virtual_cpu_lp = { | ||
3911 | .name = "cpu_lp", | ||
3912 | .parent = &tegra_clk_cclk_lp, | ||
3913 | .ops = &tegra_cpu_ops, | ||
3914 | .max_rate = 620000000, | ||
3915 | .u.cpu = { | ||
3916 | .main = &tegra_pll_x, | ||
3917 | .backup = &tegra_pll_p, | ||
3918 | .mode = MODE_LP, | ||
3919 | }, | ||
3920 | }; | ||
3921 | |||
3922 | static struct clk_mux_sel mux_cpu_cmplx[] = { | ||
3923 | { .input = &tegra_clk_virtual_cpu_g, .value = 0}, | ||
3924 | { .input = &tegra_clk_virtual_cpu_lp, .value = 1}, | ||
3925 | { 0, 0}, | ||
3926 | }; | ||
3927 | |||
3928 | static struct clk tegra_clk_cpu_cmplx = { | ||
3929 | .name = "cpu", | ||
3930 | .inputs = mux_cpu_cmplx, | ||
3931 | .ops = &tegra_cpu_cmplx_ops, | ||
3932 | .max_rate = 1700000000, | ||
3933 | }; | ||
3934 | |||
3935 | static struct clk tegra_clk_cop = { | ||
3936 | .name = "cop", | ||
3937 | .parent = &tegra_clk_sclk, | ||
3938 | .ops = &tegra_cop_ops, | ||
3939 | .max_rate = 378000000, | ||
3940 | }; | ||
3941 | |||
3942 | static struct clk tegra_clk_hclk = { | ||
3943 | .name = "hclk", | ||
3944 | .flags = DIV_BUS, | ||
3945 | .parent = &tegra_clk_sclk, | ||
3946 | .reg = 0x30, | ||
3947 | .reg_shift = 4, | ||
3948 | .ops = &tegra_bus_ops, | ||
3949 | .max_rate = 378000000, | ||
3950 | .min_rate = 40000000, | ||
3951 | }; | ||
3952 | |||
3953 | static struct clk tegra_clk_pclk = { | ||
3954 | .name = "pclk", | ||
3955 | .flags = DIV_BUS, | ||
3956 | .parent = &tegra_clk_hclk, | ||
3957 | .reg = 0x30, | ||
3958 | .reg_shift = 0, | ||
3959 | .ops = &tegra_bus_ops, | ||
3960 | .max_rate = 167000000, | ||
3961 | .min_rate = 40000000, | ||
3962 | }; | ||
3963 | |||
3964 | static struct raw_notifier_head sbus_rate_change_nh; | ||
3965 | |||
3966 | static struct clk tegra_clk_sbus_cmplx = { | ||
3967 | .name = "sbus", | ||
3968 | .parent = &tegra_clk_sclk, | ||
3969 | .ops = &tegra_sbus_cmplx_ops, | ||
3970 | .u.system = { | ||
3971 | .pclk = &tegra_clk_pclk, | ||
3972 | .hclk = &tegra_clk_hclk, | ||
3973 | .sclk_low = &tegra_pll_p_out4, | ||
3974 | .sclk_high = &tegra_pll_m_out1, | ||
3975 | }, | ||
3976 | .rate_change_nh = &sbus_rate_change_nh, | ||
3977 | }; | ||
3978 | |||
3979 | static struct clk tegra_clk_blink = { | ||
3980 | .name = "blink", | ||
3981 | .parent = &tegra_clk_32k, | ||
3982 | .reg = 0x40, | ||
3983 | .ops = &tegra_blink_clk_ops, | ||
3984 | .max_rate = 32768, | ||
3985 | }; | ||
3986 | |||
3987 | static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { | ||
3988 | { .input = &tegra_pll_m, .value = 0}, | ||
3989 | { .input = &tegra_pll_c, .value = 1}, | ||
3990 | { .input = &tegra_pll_p, .value = 2}, | ||
3991 | { .input = &tegra_pll_a_out0, .value = 3}, | ||
3992 | { 0, 0}, | ||
3993 | }; | ||
3994 | |||
3995 | static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { | ||
3996 | { .input = &tegra_pll_m, .value = 0}, | ||
3997 | /* { .input = &tegra_pll_c, .value = 1}, not used on tegra3 */ | ||
3998 | { .input = &tegra_pll_p, .value = 2}, | ||
3999 | { .input = &tegra_clk_m, .value = 3}, | ||
4000 | { 0, 0}, | ||
4001 | }; | ||
4002 | |||
4003 | static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { | ||
4004 | { .input = &tegra_pll_p, .value = 0}, | ||
4005 | { .input = &tegra_pll_c, .value = 1}, | ||
4006 | #ifndef CONFIG_TEGRA_PLLM_RESTRICTED | ||
4007 | { .input = &tegra_pll_m, .value = 2}, | ||
4008 | #endif | ||
4009 | { .input = &tegra_clk_m, .value = 3}, | ||
4010 | { 0, 0}, | ||
4011 | }; | ||
4012 | |||
4013 | static struct clk_mux_sel mux_pllp_clkm[] = { | ||
4014 | { .input = &tegra_pll_p, .value = 0}, | ||
4015 | { .input = &tegra_clk_m, .value = 3}, | ||
4016 | { 0, 0}, | ||
4017 | }; | ||
4018 | |||
4019 | static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { | ||
4020 | {.input = &tegra_pll_p, .value = 0}, | ||
4021 | {.input = &tegra_pll_d_out0, .value = 1}, | ||
4022 | {.input = &tegra_pll_c, .value = 2}, | ||
4023 | {.input = &tegra_clk_m, .value = 3}, | ||
4024 | { 0, 0}, | ||
4025 | }; | ||
4026 | |||
4027 | static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { | ||
4028 | {.input = &tegra_pll_p, .value = 0}, | ||
4029 | #ifndef CONFIG_TEGRA_PLLM_RESTRICTED | ||
4030 | {.input = &tegra_pll_m, .value = 1}, | ||
4031 | #endif | ||
4032 | {.input = &tegra_pll_d_out0, .value = 2}, | ||
4033 | {.input = &tegra_pll_a_out0, .value = 3}, | ||
4034 | {.input = &tegra_pll_c, .value = 4}, | ||
4035 | {.input = &tegra_pll_d2_out0, .value = 5}, | ||
4036 | {.input = &tegra_clk_m, .value = 6}, | ||
4037 | { 0, 0}, | ||
4038 | }; | ||
4039 | |||
4040 | static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = { | ||
4041 | { .input = &tegra_pll_a_out0, .value = 0}, | ||
4042 | /* { .input = &tegra_pll_c, .value = 1}, no use on tegra3 */ | ||
4043 | { .input = &tegra_pll_p, .value = 2}, | ||
4044 | { .input = &tegra_clk_m, .value = 3}, | ||
4045 | { 0, 0}, | ||
4046 | }; | ||
4047 | |||
4048 | static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = { | ||
4049 | {.input = &tegra_pll_p, .value = 0}, | ||
4050 | {.input = &tegra_pll_c, .value = 1}, | ||
4051 | {.input = &tegra_clk_32k, .value = 2}, | ||
4052 | {.input = &tegra_clk_m, .value = 3}, | ||
4053 | { 0, 0}, | ||
4054 | }; | ||
4055 | |||
4056 | static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = { | ||
4057 | {.input = &tegra_pll_p, .value = 0}, | ||
4058 | {.input = &tegra_pll_c, .value = 1}, | ||
4059 | {.input = &tegra_clk_m, .value = 2}, | ||
4060 | {.input = &tegra_clk_32k, .value = 3}, | ||
4061 | { 0, 0}, | ||
4062 | }; | ||
4063 | |||
4064 | static struct clk_mux_sel mux_pllp_pllc_pllm[] = { | ||
4065 | {.input = &tegra_pll_p, .value = 0}, | ||
4066 | {.input = &tegra_pll_c, .value = 1}, | ||
4067 | #ifndef CONFIG_TEGRA_PLLM_RESTRICTED | ||
4068 | {.input = &tegra_pll_m, .value = 2}, | ||
4069 | #endif | ||
4070 | { 0, 0}, | ||
4071 | }; | ||
4072 | |||
4073 | static struct clk_mux_sel mux_clk_m[] = { | ||
4074 | { .input = &tegra_clk_m, .value = 0}, | ||
4075 | { 0, 0}, | ||
4076 | }; | ||
4077 | |||
4078 | static struct clk_mux_sel mux_pllp_out3[] = { | ||
4079 | { .input = &tegra_pll_p_out3, .value = 0}, | ||
4080 | { 0, 0}, | ||
4081 | }; | ||
4082 | |||
4083 | static struct clk_mux_sel mux_plld_out0[] = { | ||
4084 | { .input = &tegra_pll_d_out0, .value = 0}, | ||
4085 | { 0, 0}, | ||
4086 | }; | ||
4087 | |||
4088 | static struct clk_mux_sel mux_plld_out0_plld2_out0[] = { | ||
4089 | { .input = &tegra_pll_d_out0, .value = 0}, | ||
4090 | { .input = &tegra_pll_d2_out0, .value = 1}, | ||
4091 | { 0, 0}, | ||
4092 | }; | ||
4093 | |||
4094 | static struct clk_mux_sel mux_clk_32k[] = { | ||
4095 | { .input = &tegra_clk_32k, .value = 0}, | ||
4096 | { 0, 0}, | ||
4097 | }; | ||
4098 | |||
4099 | static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = { | ||
4100 | { .input = &tegra_pll_a_out0, .value = 0}, | ||
4101 | { .input = &tegra_clk_32k, .value = 1}, | ||
4102 | { .input = &tegra_pll_p, .value = 2}, | ||
4103 | { .input = &tegra_clk_m, .value = 3}, | ||
4104 | { .input = &tegra_pll_e, .value = 4}, | ||
4105 | { 0, 0}, | ||
4106 | }; | ||
4107 | |||
4108 | static struct raw_notifier_head emc_rate_change_nh; | ||
4109 | |||
4110 | static struct clk tegra_clk_emc = { | ||
4111 | .name = "emc", | ||
4112 | .ops = &tegra_emc_clk_ops, | ||
4113 | .reg = 0x19c, | ||
4114 | .max_rate = 900000000, | ||
4115 | .min_rate = 12000000, | ||
4116 | .inputs = mux_pllm_pllc_pllp_clkm, | ||
4117 | .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, | ||
4118 | .u.periph = { | ||
4119 | .clk_num = 57, | ||
4120 | }, | ||
4121 | .rate_change_nh = &emc_rate_change_nh, | ||
4122 | }; | ||
4123 | |||
4124 | static struct clk tegra_clk_emc_bridge = { | ||
4125 | .name = "bridge.emc", | ||
4126 | .ops = &tegra_clk_emc_bridge_ops, | ||
4127 | .parent = &tegra_clk_emc, | ||
4128 | }; | ||
4129 | |||
4130 | static struct clk tegra_clk_cbus = { | ||
4131 | .name = "cbus", | ||
4132 | .parent = &tegra_pll_c, | ||
4133 | .ops = &tegra_clk_cbus_ops, | ||
4134 | .max_rate = 700000000, | ||
4135 | .mul = 1, | ||
4136 | .div = 2, | ||
4137 | .flags = PERIPH_ON_CBUS, | ||
4138 | .shared_bus_backup = { | ||
4139 | .input = &tegra_pll_p, | ||
4140 | .value = 2, | ||
4141 | } | ||
4142 | }; | ||
4143 | |||
4144 | #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ | ||
4145 | { \ | ||
4146 | .name = _name, \ | ||
4147 | .lookup = { \ | ||
4148 | .dev_id = _dev, \ | ||
4149 | .con_id = _con, \ | ||
4150 | }, \ | ||
4151 | .ops = &tegra_periph_clk_ops, \ | ||
4152 | .reg = _reg, \ | ||
4153 | .inputs = _inputs, \ | ||
4154 | .flags = _flags, \ | ||
4155 | .max_rate = _max, \ | ||
4156 | .u.periph = { \ | ||
4157 | .clk_num = _clk_num, \ | ||
4158 | }, \ | ||
4159 | } | ||
4160 | |||
4161 | #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \ | ||
4162 | _flags, _ops) \ | ||
4163 | { \ | ||
4164 | .name = _name, \ | ||
4165 | .lookup = { \ | ||
4166 | .dev_id = _dev, \ | ||
4167 | .con_id = _con, \ | ||
4168 | }, \ | ||
4169 | .ops = _ops, \ | ||
4170 | .reg = _reg, \ | ||
4171 | .inputs = _inputs, \ | ||
4172 | .flags = _flags, \ | ||
4173 | .max_rate = _max, \ | ||
4174 | .u.periph = { \ | ||
4175 | .clk_num = _clk_num, \ | ||
4176 | }, \ | ||
4177 | } | ||
4178 | |||
4179 | #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ | ||
4180 | { \ | ||
4181 | .name = _name, \ | ||
4182 | .lookup = { \ | ||
4183 | .dev_id = _dev, \ | ||
4184 | .con_id = _con, \ | ||
4185 | }, \ | ||
4186 | .ops = &tegra_clk_shared_bus_ops, \ | ||
4187 | .parent = _parent, \ | ||
4188 | .u.shared_bus_user = { \ | ||
4189 | .client_id = _id, \ | ||
4190 | .client_div = _div, \ | ||
4191 | .mode = _mode, \ | ||
4192 | }, \ | ||
4193 | } | ||
4194 | struct clk tegra_list_clks[] = { | ||
4195 | PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0), | ||
4196 | PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), | ||
4197 | PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), | ||
4198 | PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), | ||
4199 | PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0), | ||
4200 | PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), | ||
4201 | PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), | ||
4202 | PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB), | ||
4203 | PERIPH_CLK("i2s0", "tegra30-i2s.0", "i2s", 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4204 | PERIPH_CLK("i2s1", "tegra30-i2s.1", "i2s", 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4205 | PERIPH_CLK("i2s2", "tegra30-i2s.2", "i2s", 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4206 | PERIPH_CLK("i2s3", "tegra30-i2s.3", "i2s", 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4207 | PERIPH_CLK("i2s4", "tegra30-i2s.4", "i2s", 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4208 | PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 26000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4209 | PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4210 | PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 408000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), | ||
4211 | PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4212 | PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), | ||
4213 | PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), | ||
4214 | PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), | ||
4215 | PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4216 | PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4217 | PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB), | ||
4218 | PERIPH_CLK("sbc1", "spi_tegra.0", "spi", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4219 | PERIPH_CLK("sbc2", "spi_tegra.1", "spi", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4220 | PERIPH_CLK("sbc3", "spi_tegra.2", "spi", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4221 | PERIPH_CLK("sbc4", "spi_tegra.3", "spi", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4222 | PERIPH_CLK("sbc5", "spi_tegra.4", "spi", 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4223 | PERIPH_CLK("sbc6", "spi_tegra.5", "spi", 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4224 | PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | ||
4225 | PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | ||
4226 | PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0), | ||
4227 | PERIPH_CLK_EX("ndflash","tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops), | ||
4228 | PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | ||
4229 | PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4230 | PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | ||
4231 | PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | ||
4232 | PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | ||
4233 | PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | ||
4234 | PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), | ||
4235 | PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), | ||
4236 | PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), | ||
4237 | PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), | ||
4238 | PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ | ||
4239 | PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | ||
4240 | PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4241 | PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ | ||
4242 | PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */ | ||
4243 | PERIPH_CLK("i2c1", "tegra-i2c.0", "i2c-div", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), | ||
4244 | PERIPH_CLK("i2c2", "tegra-i2c.1", "i2c-div", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), | ||
4245 | PERIPH_CLK("i2c3", "tegra-i2c.2", "i2c-div", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), | ||
4246 | PERIPH_CLK("i2c4", "tegra-i2c.3", "i2c-div", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), | ||
4247 | PERIPH_CLK("i2c5", "tegra-i2c.4", "i2c-div", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), | ||
4248 | PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), | ||
4249 | PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), | ||
4250 | PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), | ||
4251 | PERIPH_CLK("i2c4-fast", "tegra-i2c.3", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), | ||
4252 | PERIPH_CLK("i2c5-fast", "tegra-i2c.4", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), | ||
4253 | PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4254 | PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4255 | PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4256 | PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4257 | PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4258 | PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4259 | PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4260 | PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4261 | PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4262 | PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), | ||
4263 | PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 470000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), | ||
4264 | PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), | ||
4265 | PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), | ||
4266 | PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), | ||
4267 | PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE), | ||
4268 | PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), | ||
4269 | PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), | ||
4270 | PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), | ||
4271 | PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | ||
4272 | PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | ||
4273 | PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops), | ||
4274 | PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71), | ||
4275 | PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | ||
4276 | PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), | ||
4277 | PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), | ||
4278 | PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | ||
4279 | PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | ||
4280 | PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | ||
4281 | PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0), | ||
4282 | PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops), | ||
4283 | PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0), | ||
4284 | PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ | ||
4285 | PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), | ||
4286 | |||
4287 | PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71), | ||
4288 | PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71), | ||
4289 | PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), | ||
4290 | PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), | ||
4291 | PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), | ||
4292 | PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), | ||
4293 | PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0), | ||
4294 | PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0), | ||
4295 | PERIPH_CLK("se", "se", NULL, 127, 0x42c, 625000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), | ||
4296 | PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71), | ||
4297 | |||
4298 | SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4299 | SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4300 | SHARED_CLK("usbd.sclk", "fsl-tegra-udc", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4301 | SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4302 | SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4303 | SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4304 | SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4305 | SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), | ||
4306 | SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4307 | SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4308 | SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4309 | SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4310 | SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4311 | SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4312 | SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), | ||
4313 | |||
4314 | SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4315 | SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4316 | SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), | ||
4317 | SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), | ||
4318 | SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4319 | SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4320 | SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4321 | SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4322 | SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4323 | SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4324 | SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING), | ||
4325 | SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4326 | SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4327 | SHARED_CLK("mpe.emc", "tegra_mpe", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4328 | SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, 0), | ||
4329 | SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0), | ||
4330 | |||
4331 | SHARED_CLK("host1x.cbus", "tegra_host1x", "host1x", &tegra_clk_cbus, "host1x", 2, SHARED_AUTO), | ||
4332 | SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0), | ||
4333 | SHARED_CLK("3d2.cbus", "tegra_gr3d", "gr3d2", &tegra_clk_cbus, "3d2", 0, 0), | ||
4334 | SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0), | ||
4335 | SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0), | ||
4336 | SHARED_CLK("mpe.cbus", "tegra_mpe", "mpe", &tegra_clk_cbus, "mpe", 0, 0), | ||
4337 | SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0), | ||
4338 | SHARED_CLK("se.cbus", "tegra-se", NULL, &tegra_clk_cbus, "se", 0, 0), | ||
4339 | SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), | ||
4340 | SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), | ||
4341 | }; | ||
4342 | |||
4343 | #define CLK_DUPLICATE(_name, _dev, _con) \ | ||
4344 | { \ | ||
4345 | .name = _name, \ | ||
4346 | .lookup = { \ | ||
4347 | .dev_id = _dev, \ | ||
4348 | .con_id = _con, \ | ||
4349 | }, \ | ||
4350 | } | ||
4351 | |||
4352 | /* Some clocks may be used by different drivers depending on the board | ||
4353 | * configuration. List those here to register them twice in the clock lookup | ||
4354 | * table under two names. | ||
4355 | */ | ||
4356 | struct clk_duplicate tegra_clk_duplicates[] = { | ||
4357 | CLK_DUPLICATE("usbd", "utmip-pad", NULL), | ||
4358 | CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), | ||
4359 | CLK_DUPLICATE("usbd", "tegra-otg", NULL), | ||
4360 | CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), | ||
4361 | CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), | ||
4362 | CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), | ||
4363 | CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), | ||
4364 | CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), | ||
4365 | CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), | ||
4366 | CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), | ||
4367 | CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL), | ||
4368 | CLK_DUPLICATE("cop", "tegra-avp", "cop"), | ||
4369 | CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), | ||
4370 | CLK_DUPLICATE("cop", "nvavp", "cop"), | ||
4371 | CLK_DUPLICATE("bsev", "nvavp", "bsev"), | ||
4372 | CLK_DUPLICATE("vde", "tegra-aes", "vde"), | ||
4373 | CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), | ||
4374 | CLK_DUPLICATE("bsea", "nvavp", "bsea"), | ||
4375 | CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL), | ||
4376 | CLK_DUPLICATE("cml0", "tegra_pcie", "cml"), | ||
4377 | CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"), | ||
4378 | CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), | ||
4379 | CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), | ||
4380 | CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), | ||
4381 | CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), | ||
4382 | CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), | ||
4383 | CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL), | ||
4384 | CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL), | ||
4385 | CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL), | ||
4386 | CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL), | ||
4387 | CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL), | ||
4388 | CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), | ||
4389 | CLK_DUPLICATE("twd", "smp_twd", NULL), | ||
4390 | CLK_DUPLICATE("vcp", "nvavp", "vcp"), | ||
4391 | CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"), | ||
4392 | CLK_DUPLICATE("avp.emc", "nvavp", "emc"), | ||
4393 | CLK_DUPLICATE("vde.cbus", "nvavp", "vde"), | ||
4394 | }; | ||
4395 | |||
4396 | struct clk *tegra_ptr_clks[] = { | ||
4397 | &tegra_clk_32k, | ||
4398 | &tegra_clk_m, | ||
4399 | &tegra_clk_m_div2, | ||
4400 | &tegra_clk_m_div4, | ||
4401 | &tegra_pll_ref, | ||
4402 | &tegra_pll_m, | ||
4403 | &tegra_pll_m_out1, | ||
4404 | &tegra_pll_c, | ||
4405 | &tegra_pll_c_out1, | ||
4406 | &tegra_pll_p, | ||
4407 | &tegra_pll_p_out1, | ||
4408 | &tegra_pll_p_out2, | ||
4409 | &tegra_pll_p_out3, | ||
4410 | &tegra_pll_p_out4, | ||
4411 | &tegra_pll_a, | ||
4412 | &tegra_pll_a_out0, | ||
4413 | &tegra_pll_d, | ||
4414 | &tegra_pll_d_out0, | ||
4415 | &tegra_pll_d2, | ||
4416 | &tegra_pll_d2_out0, | ||
4417 | &tegra_pll_u, | ||
4418 | &tegra_pll_x, | ||
4419 | &tegra_pll_x_out0, | ||
4420 | &tegra_pll_e, | ||
4421 | &tegra_cml0_clk, | ||
4422 | &tegra_cml1_clk, | ||
4423 | &tegra_pciex_clk, | ||
4424 | &tegra_clk_cclk_g, | ||
4425 | &tegra_clk_cclk_lp, | ||
4426 | &tegra_clk_sclk, | ||
4427 | &tegra_clk_hclk, | ||
4428 | &tegra_clk_pclk, | ||
4429 | &tegra_clk_virtual_cpu_g, | ||
4430 | &tegra_clk_virtual_cpu_lp, | ||
4431 | &tegra_clk_cpu_cmplx, | ||
4432 | &tegra_clk_blink, | ||
4433 | &tegra_clk_cop, | ||
4434 | &tegra_clk_sbus_cmplx, | ||
4435 | &tegra_clk_emc, | ||
4436 | &tegra3_clk_twd, | ||
4437 | &tegra_clk_emc_bridge, | ||
4438 | &tegra_clk_cbus, | ||
4439 | }; | ||
4440 | |||
4441 | /* | ||
4442 | * Backup rate targets for each CPU mode is selected below Fmax(Vmin), and | ||
4443 | * high enough to avoid voltage droop when CPU clock is switched between | ||
4444 | * backup and main clock sources. Actual backup rates will be rounded based | ||
4445 | * on backup source fixed frequency. Maximum stay-on-backup rate will be set | ||
4446 | * as a minimum of G and LP backup rates to be supported in both modes. | ||
4447 | * | ||
4448 | * Sbus threshold must be exact factor of pll_p rate. | ||
4449 | */ | ||
4450 | #define CPU_G_BACKUP_RATE_TARGET 440000000 | ||
4451 | #define CPU_LP_BACKUP_RATE_TARGET 220000000 | ||
4452 | |||
4453 | static void tegra3_pllp_init_dependencies(unsigned long pllp_rate) | ||
4454 | { | ||
4455 | u32 div; | ||
4456 | unsigned long backup_rate; | ||
4457 | |||
4458 | switch (pllp_rate) { | ||
4459 | case 216000000: | ||
4460 | tegra_pll_p_out1.u.pll_div.default_rate = 28800000; | ||
4461 | tegra_pll_p_out3.u.pll_div.default_rate = 72000000; | ||
4462 | tegra_clk_sbus_cmplx.u.system.threshold = 108000000; | ||
4463 | break; | ||
4464 | case 408000000: | ||
4465 | tegra_pll_p_out1.u.pll_div.default_rate = 9600000; | ||
4466 | tegra_pll_p_out3.u.pll_div.default_rate = 102000000; | ||
4467 | tegra_clk_sbus_cmplx.u.system.threshold = 204000000; | ||
4468 | break; | ||
4469 | case 204000000: | ||
4470 | tegra_pll_p_out1.u.pll_div.default_rate = 4800000; | ||
4471 | tegra_pll_p_out3.u.pll_div.default_rate = 102000000; | ||
4472 | tegra_clk_sbus_cmplx.u.system.threshold = 204000000; | ||
4473 | break; | ||
4474 | default: | ||
4475 | pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate); | ||
4476 | BUG(); | ||
4477 | } | ||
4478 | pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate); | ||
4479 | |||
4480 | div = DIV_ROUND_UP(pllp_rate, CPU_G_BACKUP_RATE_TARGET); | ||
4481 | backup_rate = pllp_rate / div; | ||
4482 | tegra_clk_cclk_g.u.cclk.div71 = 2 * div - 2; | ||
4483 | tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate; | ||
4484 | cpu_stay_on_backup_max = backup_rate; | ||
4485 | |||
4486 | div = DIV_ROUND_UP(pllp_rate, CPU_LP_BACKUP_RATE_TARGET); | ||
4487 | backup_rate = pllp_rate / div; | ||
4488 | tegra_clk_cclk_lp.u.cclk.div71 = 2 * div - 2; | ||
4489 | tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate; | ||
4490 | cpu_stay_on_backup_max = min(cpu_stay_on_backup_max, backup_rate); | ||
4491 | } | ||
4492 | |||
4493 | bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) | ||
4494 | { | ||
4495 | if (c->flags & PERIPH_ON_CBUS) | ||
4496 | return p != &tegra_pll_m; | ||
4497 | else | ||
4498 | return p != &tegra_pll_c; | ||
4499 | |||
4500 | return true; | ||
4501 | } | ||
4502 | |||
4503 | static void tegra3_init_one_clock(struct clk *c) | ||
4504 | { | ||
4505 | clk_init(c); | ||
4506 | INIT_LIST_HEAD(&c->shared_bus_list); | ||
4507 | if (!c->lookup.dev_id && !c->lookup.con_id) | ||
4508 | c->lookup.con_id = c->name; | ||
4509 | c->lookup.clk = c; | ||
4510 | clkdev_add(&c->lookup); | ||
4511 | } | ||
4512 | |||
4513 | /* | ||
4514 | * Emergency throttle of G-CPU by setting G-super clock skipper underneath | ||
4515 | * clock framework, dvfs, and cpufreq driver s/w layers. Can be called in | ||
4516 | * ISR context for EDP events. When releasing throttle, LP-divider is cleared | ||
4517 | * just in case it was set as a result of save/restore operations across | ||
4518 | * cluster switch (should not happen) | ||
4519 | */ | ||
4520 | void tegra_edp_throttle_cpu_now(u8 factor) | ||
4521 | { | ||
4522 | if (factor > 1) { | ||
4523 | if (!is_lp_cluster()) | ||
4524 | tegra3_super_clk_skipper_update( | ||
4525 | &tegra_clk_cclk_g, 1, factor); | ||
4526 | } else if (factor == 0) { | ||
4527 | tegra3_super_clk_skipper_update(&tegra_clk_cclk_g, 0, 0); | ||
4528 | tegra3_super_clk_skipper_update(&tegra_clk_cclk_lp, 0, 0); | ||
4529 | } | ||
4530 | } | ||
4531 | |||
4532 | #ifdef CONFIG_CPU_FREQ | ||
4533 | |||
4534 | /* | ||
4535 | * Frequency table index must be sequential starting at 0 and frequencies | ||
4536 | * must be ascending. Re-configurable PLLX is used as a source for rates | ||
4537 | * above 204MHz. Rates 204MHz and below are divided down from fixed frequency | ||
4538 | * PLLP that may run either at 408MHz or at 204MHz on Tegra3 silicon platforms | ||
4539 | * (on FPGA platform PLLP output is reported as 216MHz, but no respective | ||
4540 | * tables are provided, since there is no clock scaling on FPGA at all). | ||
4541 | */ | ||
4542 | |||
4543 | static struct cpufreq_frequency_table freq_table_300MHz[] = { | ||
4544 | { 0, 204000 }, | ||
4545 | { 1, 300000 }, | ||
4546 | { 2, CPUFREQ_TABLE_END }, | ||
4547 | }; | ||
4548 | |||
4549 | static struct cpufreq_frequency_table freq_table_1p0GHz[] = { | ||
4550 | { 0, 51000 }, | ||
4551 | { 1, 102000 }, | ||
4552 | { 2, 204000 }, | ||
4553 | { 3, 312000 }, | ||
4554 | { 4, 456000 }, | ||
4555 | { 5, 608000 }, | ||
4556 | { 6, 760000 }, | ||
4557 | { 7, 816000 }, | ||
4558 | { 8, 912000 }, | ||
4559 | { 9, 1000000 }, | ||
4560 | {10, CPUFREQ_TABLE_END }, | ||
4561 | }; | ||
4562 | |||
4563 | static struct cpufreq_frequency_table freq_table_1p3GHz[] = { | ||
4564 | { 0, 51000 }, | ||
4565 | { 1, 102000 }, | ||
4566 | { 2, 204000 }, | ||
4567 | { 3, 340000 }, | ||
4568 | { 4, 475000 }, | ||
4569 | { 5, 640000 }, | ||
4570 | { 6, 760000 }, | ||
4571 | { 7, 860000 }, | ||
4572 | { 8, 1000000 }, | ||
4573 | { 9, 1100000 }, | ||
4574 | {10, 1200000 }, | ||
4575 | {11, 1300000 }, | ||
4576 | {12, CPUFREQ_TABLE_END }, | ||
4577 | }; | ||
4578 | |||
4579 | static struct cpufreq_frequency_table freq_table_1p4GHz[] = { | ||
4580 | { 0, 51000 }, | ||
4581 | { 1, 102000 }, | ||
4582 | { 2, 204000 }, | ||
4583 | { 3, 370000 }, | ||
4584 | { 4, 475000 }, | ||
4585 | { 5, 620000 }, | ||
4586 | { 6, 760000 }, | ||
4587 | { 7, 860000 }, | ||
4588 | { 8, 1000000 }, | ||
4589 | { 9, 1100000 }, | ||
4590 | {10, 1200000 }, | ||
4591 | {11, 1300000 }, | ||
4592 | {12, 1400000 }, | ||
4593 | {13, CPUFREQ_TABLE_END }, | ||
4594 | }; | ||
4595 | |||
4596 | static struct cpufreq_frequency_table freq_table_1p5GHz[] = { | ||
4597 | { 0, 51000 }, | ||
4598 | { 1, 102000 }, | ||
4599 | { 2, 204000 }, | ||
4600 | { 3, 340000 }, | ||
4601 | { 4, 475000 }, | ||
4602 | { 5, 640000 }, | ||
4603 | { 6, 760000 }, | ||
4604 | { 7, 860000 }, | ||
4605 | { 8, 1000000 }, | ||
4606 | { 9, 1100000 }, | ||
4607 | {10, 1200000 }, | ||
4608 | {11, 1300000 }, | ||
4609 | {12, 1400000 }, | ||
4610 | {13, 1500000 }, | ||
4611 | {14, CPUFREQ_TABLE_END }, | ||
4612 | }; | ||
4613 | |||
4614 | static struct cpufreq_frequency_table freq_table_1p7GHz[] = { | ||
4615 | { 0, 51000 }, | ||
4616 | { 1, 102000 }, | ||
4617 | { 2, 204000 }, | ||
4618 | { 3, 370000 }, | ||
4619 | { 4, 475000 }, | ||
4620 | { 5, 620000 }, | ||
4621 | { 6, 760000 }, | ||
4622 | { 7, 910000 }, | ||
4623 | { 8, 1150000 }, | ||
4624 | { 9, 1300000 }, | ||
4625 | {10, 1400000 }, | ||
4626 | {11, 1500000 }, | ||
4627 | {12, 1600000 }, | ||
4628 | {13, 1700000 }, | ||
4629 | {14, CPUFREQ_TABLE_END }, | ||
4630 | }; | ||
4631 | |||
4632 | static struct tegra_cpufreq_table_data cpufreq_tables[] = { | ||
4633 | { freq_table_300MHz, 0, 1 }, | ||
4634 | { freq_table_1p0GHz, 2, 8 }, | ||
4635 | { freq_table_1p3GHz, 2, 10 }, | ||
4636 | { freq_table_1p4GHz, 2, 11 }, | ||
4637 | { freq_table_1p5GHz, 2, 12 }, | ||
4638 | { freq_table_1p7GHz, 2, 12 }, | ||
4639 | }; | ||
4640 | |||
4641 | static int clip_cpu_rate_limits( | ||
4642 | struct tegra_cpufreq_table_data *data, | ||
4643 | struct cpufreq_policy *policy, | ||
4644 | struct clk *cpu_clk_g, | ||
4645 | struct clk *cpu_clk_lp) | ||
4646 | { | ||
4647 | int idx, ret; | ||
4648 | struct cpufreq_frequency_table *freq_table = data->freq_table; | ||
4649 | |||
4650 | /* clip CPU G mode maximum frequency to table entry */ | ||
4651 | ret = cpufreq_frequency_table_target(policy, freq_table, | ||
4652 | cpu_clk_g->max_rate / 1000, CPUFREQ_RELATION_H, &idx); | ||
4653 | if (ret) { | ||
4654 | pr_err("%s: G CPU max rate %lu outside of cpufreq table", | ||
4655 | __func__, cpu_clk_g->max_rate); | ||
4656 | return ret; | ||
4657 | } | ||
4658 | cpu_clk_g->max_rate = freq_table[idx].frequency * 1000; | ||
4659 | if (cpu_clk_g->max_rate < cpu_clk_lp->max_rate) { | ||
4660 | pr_err("%s: G CPU max rate %lu is below LP CPU max rate %lu", | ||
4661 | __func__, cpu_clk_g->max_rate, cpu_clk_lp->max_rate); | ||
4662 | return -EINVAL; | ||
4663 | } | ||
4664 | |||
4665 | /* clip CPU LP mode maximum frequency to table entry, and | ||
4666 | set CPU G mode minimum frequency one table step below */ | ||
4667 | ret = cpufreq_frequency_table_target(policy, freq_table, | ||
4668 | cpu_clk_lp->max_rate / 1000, CPUFREQ_RELATION_H, &idx); | ||
4669 | if (ret || !idx) { | ||
4670 | pr_err("%s: LP CPU max rate %lu %s of cpufreq table", __func__, | ||
4671 | cpu_clk_lp->max_rate, ret ? "outside" : "at the bottom"); | ||
4672 | return ret; | ||
4673 | } | ||
4674 | cpu_clk_lp->max_rate = freq_table[idx].frequency * 1000; | ||
4675 | cpu_clk_g->min_rate = freq_table[idx-1].frequency * 1000; | ||
4676 | data->suspend_index = idx; | ||
4677 | return 0; | ||
4678 | } | ||
4679 | |||
4680 | struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) | ||
4681 | { | ||
4682 | int i, ret; | ||
4683 | unsigned long selection_rate; | ||
4684 | struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); | ||
4685 | struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); | ||
4686 | |||
4687 | /* For table selection use top cpu_g rate in dvfs ladder; selection | ||
4688 | rate may exceed cpu max_rate (e.g., because of edp limitations on | ||
4689 | cpu voltage) - in any case max_rate will be clipped to the table */ | ||
4690 | if (cpu_clk_g->dvfs && cpu_clk_g->dvfs->num_freqs) | ||
4691 | selection_rate = | ||
4692 | cpu_clk_g->dvfs->freqs[cpu_clk_g->dvfs->num_freqs - 1]; | ||
4693 | else | ||
4694 | selection_rate = cpu_clk_g->max_rate; | ||
4695 | |||
4696 | for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) { | ||
4697 | struct cpufreq_policy policy; | ||
4698 | policy.cpu = 0; /* any on-line cpu */ | ||
4699 | ret = cpufreq_frequency_table_cpuinfo( | ||
4700 | &policy, cpufreq_tables[i].freq_table); | ||
4701 | if (!ret) { | ||
4702 | if ((policy.max * 1000) == selection_rate) { | ||
4703 | ret = clip_cpu_rate_limits( | ||
4704 | &cpufreq_tables[i], | ||
4705 | &policy, cpu_clk_g, cpu_clk_lp); | ||
4706 | if (!ret) | ||
4707 | return &cpufreq_tables[i]; | ||
4708 | } | ||
4709 | } | ||
4710 | } | ||
4711 | WARN(1, "%s: No cpufreq table matching G & LP cpu ranges", __func__); | ||
4712 | return NULL; | ||
4713 | } | ||
4714 | |||
4715 | /* On DDR3 platforms there is an implicit dependency in this mapping: when cpu | ||
4716 | * exceeds max dvfs level for LP CPU clock at TEGRA_EMC_BRIDGE_MVOLTS_MIN, the | ||
4717 | * respective emc rate should be above TEGRA_EMC_BRIDGE_RATE_MIN | ||
4718 | */ | ||
4719 | /* FIXME: explicitly check this dependency */ | ||
4720 | unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) | ||
4721 | { | ||
4722 | static unsigned long emc_max_rate = 0; | ||
4723 | |||
4724 | if (emc_max_rate == 0) | ||
4725 | emc_max_rate = clk_round_rate( | ||
4726 | tegra_get_clock_by_name("emc"), ULONG_MAX); | ||
4727 | |||
4728 | /* Vote on memory bus frequency based on cpu frequency; | ||
4729 | cpu rate is in kHz, emc rate is in Hz */ | ||
4730 | if (cpu_rate >= 750000) | ||
4731 | return emc_max_rate; /* cpu >= 750 MHz, emc max */ | ||
4732 | else if (cpu_rate >= 450000) | ||
4733 | return emc_max_rate/2; /* cpu >= 500 MHz, emc max/2 */ | ||
4734 | else if (cpu_rate >= 250000) | ||
4735 | return 100000000; /* cpu >= 250 MHz, emc 100 MHz */ | ||
4736 | else | ||
4737 | return 0; /* emc min */ | ||
4738 | } | ||
4739 | |||
4740 | int tegra_update_mselect_rate(unsigned long cpu_rate) | ||
4741 | { | ||
4742 | static struct clk *mselect = NULL; | ||
4743 | |||
4744 | unsigned long mselect_rate; | ||
4745 | |||
4746 | if (!mselect) { | ||
4747 | mselect = tegra_get_clock_by_name("mselect"); | ||
4748 | if (!mselect) | ||
4749 | return -ENODEV; | ||
4750 | } | ||
4751 | |||
4752 | /* Vote on mselect frequency based on cpu frequency: | ||
4753 | keep mselect at half of cpu rate up to 102 MHz; | ||
4754 | cpu rate is in kHz, mselect rate is in Hz */ | ||
4755 | mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000; | ||
4756 | mselect_rate = min(mselect_rate, 102000000UL); | ||
4757 | |||
4758 | if (mselect_rate != clk_get_rate(mselect)) | ||
4759 | return clk_set_rate(mselect, mselect_rate); | ||
4760 | |||
4761 | return 0; | ||
4762 | } | ||
4763 | #endif | ||
4764 | |||
4765 | #ifdef CONFIG_PM_SLEEP | ||
4766 | static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + | ||
4767 | PERIPH_CLK_SOURCE_NUM + 24]; | ||
4768 | |||
4769 | static int tegra_clk_suspend(void) | ||
4770 | { | ||
4771 | unsigned long off; | ||
4772 | u32 *ctx = clk_rst_suspend; | ||
4773 | |||
4774 | *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; | ||
4775 | *ctx++ = clk_readl(CPU_SOFTRST_CTRL); | ||
4776 | |||
4777 | *ctx++ = clk_readl(tegra_pll_p_out1.reg); | ||
4778 | *ctx++ = clk_readl(tegra_pll_p_out3.reg); | ||
4779 | |||
4780 | *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); | ||
4781 | *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); | ||
4782 | *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); | ||
4783 | *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); | ||
4784 | *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); | ||
4785 | *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); | ||
4786 | *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE); | ||
4787 | *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); | ||
4788 | |||
4789 | *ctx++ = clk_readl(tegra_pll_m_out1.reg); | ||
4790 | *ctx++ = clk_readl(tegra_pll_a_out0.reg); | ||
4791 | *ctx++ = clk_readl(tegra_pll_c_out1.reg); | ||
4792 | |||
4793 | *ctx++ = clk_readl(tegra_clk_cclk_g.reg); | ||
4794 | *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); | ||
4795 | *ctx++ = clk_readl(tegra_clk_cclk_lp.reg); | ||
4796 | *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); | ||
4797 | |||
4798 | *ctx++ = clk_readl(tegra_clk_sclk.reg); | ||
4799 | *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); | ||
4800 | *ctx++ = clk_readl(tegra_clk_pclk.reg); | ||
4801 | |||
4802 | for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; | ||
4803 | off += 4) { | ||
4804 | if (off == PERIPH_CLK_SOURCE_EMC) | ||
4805 | continue; | ||
4806 | *ctx++ = clk_readl(off); | ||
4807 | } | ||
4808 | for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; | ||
4809 | off+=4) { | ||
4810 | *ctx++ = clk_readl(off); | ||
4811 | } | ||
4812 | for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { | ||
4813 | *ctx++ = clk_readl(off); | ||
4814 | } | ||
4815 | |||
4816 | *ctx++ = clk_readl(RST_DEVICES_L); | ||
4817 | *ctx++ = clk_readl(RST_DEVICES_H); | ||
4818 | *ctx++ = clk_readl(RST_DEVICES_U); | ||
4819 | *ctx++ = clk_readl(RST_DEVICES_V); | ||
4820 | *ctx++ = clk_readl(RST_DEVICES_W); | ||
4821 | |||
4822 | *ctx++ = clk_readl(CLK_OUT_ENB_L); | ||
4823 | *ctx++ = clk_readl(CLK_OUT_ENB_H); | ||
4824 | *ctx++ = clk_readl(CLK_OUT_ENB_U); | ||
4825 | *ctx++ = clk_readl(CLK_OUT_ENB_V); | ||
4826 | *ctx++ = clk_readl(CLK_OUT_ENB_W); | ||
4827 | |||
4828 | *ctx++ = clk_readl(MISC_CLK_ENB); | ||
4829 | *ctx++ = clk_readl(CLK_MASK_ARM); | ||
4830 | |||
4831 | return 0; | ||
4832 | } | ||
4833 | |||
4834 | static void tegra_clk_resume(void) | ||
4835 | { | ||
4836 | unsigned long off; | ||
4837 | const u32 *ctx = clk_rst_suspend; | ||
4838 | u32 val; | ||
4839 | u32 pllc_base; | ||
4840 | u32 plla_base; | ||
4841 | u32 plld_base; | ||
4842 | u32 plld2_base; | ||
4843 | u32 pll_p_out12, pll_p_out34; | ||
4844 | u32 pll_a_out0, pll_m_out1, pll_c_out1; | ||
4845 | struct clk *p; | ||
4846 | |||
4847 | val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; | ||
4848 | val |= *ctx++; | ||
4849 | clk_writel(val, OSC_CTRL); | ||
4850 | clk_writel(*ctx++, CPU_SOFTRST_CTRL); | ||
4851 | |||
4852 | /* Since we are going to reset devices and switch clock sources in this | ||
4853 | * function, plls and secondary dividers is required to be enabled. The | ||
4854 | * actual value will be restored back later. Note that boot plls: pllm, | ||
4855 | * pllp, and pllu are already configured and enabled. | ||
4856 | */ | ||
4857 | val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | ||
4858 | val |= val << 16; | ||
4859 | pll_p_out12 = *ctx++; | ||
4860 | clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg); | ||
4861 | pll_p_out34 = *ctx++; | ||
4862 | clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg); | ||
4863 | |||
4864 | pllc_base = *ctx++; | ||
4865 | clk_writel(pllc_base | PLL_BASE_ENABLE, tegra_pll_c.reg + PLL_BASE); | ||
4866 | clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); | ||
4867 | |||
4868 | plla_base = *ctx++; | ||
4869 | clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE); | ||
4870 | clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); | ||
4871 | |||
4872 | plld_base = *ctx++; | ||
4873 | clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE); | ||
4874 | clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); | ||
4875 | |||
4876 | plld2_base = *ctx++; | ||
4877 | clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE); | ||
4878 | clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); | ||
4879 | |||
4880 | udelay(1000); | ||
4881 | |||
4882 | val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | ||
4883 | pll_m_out1 = *ctx++; | ||
4884 | clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg); | ||
4885 | pll_a_out0 = *ctx++; | ||
4886 | clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg); | ||
4887 | pll_c_out1 = *ctx++; | ||
4888 | clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg); | ||
4889 | |||
4890 | clk_writel(*ctx++, tegra_clk_cclk_g.reg); | ||
4891 | clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); | ||
4892 | clk_writel(*ctx++, tegra_clk_cclk_lp.reg); | ||
4893 | clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); | ||
4894 | |||
4895 | clk_writel(*ctx++, tegra_clk_sclk.reg); | ||
4896 | clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); | ||
4897 | clk_writel(*ctx++, tegra_clk_pclk.reg); | ||
4898 | |||
4899 | /* enable all clocks before configuring clock sources */ | ||
4900 | clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L); | ||
4901 | clk_writel(0xfefff7f7ul, CLK_OUT_ENB_H); | ||
4902 | clk_writel(0x75f79bfful, CLK_OUT_ENB_U); | ||
4903 | clk_writel(0xfffffffful, CLK_OUT_ENB_V); | ||
4904 | clk_writel(0x00003ffful, CLK_OUT_ENB_W); | ||
4905 | wmb(); | ||
4906 | |||
4907 | for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; | ||
4908 | off += 4) { | ||
4909 | if (off == PERIPH_CLK_SOURCE_EMC) | ||
4910 | continue; | ||
4911 | clk_writel(*ctx++, off); | ||
4912 | } | ||
4913 | for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; | ||
4914 | off += 4) { | ||
4915 | clk_writel(*ctx++, off); | ||
4916 | } | ||
4917 | for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { | ||
4918 | clk_writel(*ctx++, off); | ||
4919 | } | ||
4920 | wmb(); | ||
4921 | |||
4922 | clk_writel(*ctx++, RST_DEVICES_L); | ||
4923 | clk_writel(*ctx++, RST_DEVICES_H); | ||
4924 | clk_writel(*ctx++, RST_DEVICES_U); | ||
4925 | |||
4926 | /* For LP0 resume, don't reset lpcpu, since we are running from it */ | ||
4927 | val = *ctx++; | ||
4928 | val &= ~RST_DEVICES_V_SWR_CPULP_RST_DIS; | ||
4929 | clk_writel(val, RST_DEVICES_V); | ||
4930 | |||
4931 | clk_writel(*ctx++, RST_DEVICES_W); | ||
4932 | wmb(); | ||
4933 | |||
4934 | clk_writel(*ctx++, CLK_OUT_ENB_L); | ||
4935 | clk_writel(*ctx++, CLK_OUT_ENB_H); | ||
4936 | clk_writel(*ctx++, CLK_OUT_ENB_U); | ||
4937 | |||
4938 | /* For LP0 resume, clk to lpcpu is required to be on */ | ||
4939 | val = *ctx++; | ||
4940 | val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN; | ||
4941 | clk_writel(val, CLK_OUT_ENB_V); | ||
4942 | |||
4943 | clk_writel(*ctx++, CLK_OUT_ENB_W); | ||
4944 | wmb(); | ||
4945 | |||
4946 | clk_writel(*ctx++, MISC_CLK_ENB); | ||
4947 | clk_writel(*ctx++, CLK_MASK_ARM); | ||
4948 | |||
4949 | /* Restore back the actual pll and secondary divider values */ | ||
4950 | /* FIXME: need to root cause why pllc is required to be on | ||
4951 | * clk_writel(pllc_base, tegra_pll_c.reg + PLL_BASE); | ||
4952 | */ | ||
4953 | clk_writel(pll_p_out12, tegra_pll_p_out1.reg); | ||
4954 | clk_writel(pll_p_out34, tegra_pll_p_out3.reg); | ||
4955 | |||
4956 | clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE); | ||
4957 | clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE); | ||
4958 | clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE); | ||
4959 | |||
4960 | clk_writel(pll_m_out1, tegra_pll_m_out1.reg); | ||
4961 | clk_writel(pll_a_out0, tegra_pll_a_out0.reg); | ||
4962 | clk_writel(pll_c_out1, tegra_pll_c_out1.reg); | ||
4963 | |||
4964 | /* Since EMC clock is not restored, and may not preserve parent across | ||
4965 | suspend, update current state, and mark EMC DFS as out of sync */ | ||
4966 | p = tegra_clk_emc.parent; | ||
4967 | tegra3_periph_clk_init(&tegra_clk_emc); | ||
4968 | |||
4969 | if (p != tegra_clk_emc.parent) { | ||
4970 | /* FIXME: old parent is left enabled here even if EMC was its | ||
4971 | only child before suspend (never happens on Tegra3) */ | ||
4972 | pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)", | ||
4973 | p->name, p->refcnt, tegra_clk_emc.parent->name, | ||
4974 | tegra_clk_emc.parent->refcnt); | ||
4975 | |||
4976 | BUG_ON(!p->refcnt); | ||
4977 | p->refcnt--; | ||
4978 | |||
4979 | /* the new parent is enabled by low level code, but ref count | ||
4980 | need to be updated up to the root */ | ||
4981 | p = tegra_clk_emc.parent; | ||
4982 | while (p && ((p->refcnt++) == 0)) | ||
4983 | p = p->parent; | ||
4984 | } | ||
4985 | tegra_emc_timing_invalidate(); | ||
4986 | |||
4987 | tegra3_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */ | ||
4988 | tegra3_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */ | ||
4989 | } | ||
4990 | #else | ||
4991 | #define tegra_clk_suspend NULL | ||
4992 | #define tegra_clk_resume NULL | ||
4993 | #endif | ||
4994 | |||
4995 | static struct syscore_ops tegra_clk_syscore_ops = { | ||
4996 | .suspend = tegra_clk_suspend, | ||
4997 | .resume = tegra_clk_resume, | ||
4998 | }; | ||
4999 | |||
5000 | #ifdef CONFIG_TEGRA_PREINIT_CLOCKS | ||
5001 | |||
5002 | #define CLK_RSTENB_DEV_V_0_DAM2_BIT (1 << 14) | ||
5003 | #define CLK_RSTENB_DEV_V_0_DAM1_BIT (1 << 13) | ||
5004 | #define CLK_RSTENB_DEV_V_0_DAM0_BIT (1 << 12) | ||
5005 | #define CLK_RSTENB_DEV_V_0_AUDIO_BIT (1 << 10) | ||
5006 | |||
5007 | #define CLK_RSTENB_DEV_L_0_HOST1X_BIT (1 << 28) | ||
5008 | #define CLK_RSTENB_DEV_L_0_DISP1_BIT (1 << 27) | ||
5009 | |||
5010 | #define DISP1_CLK_REG_OFFSET 0x138 | ||
5011 | #define DISP1_CLK_SRC_SHIFT 29 | ||
5012 | #define DISP1_CLK_SRC_MASK (0x7 << DISP1_CLK_SRC_SHIFT) | ||
5013 | #define DISP1_CLK_SRC_PLLP_OUT0 0 | ||
5014 | #define DISP1_CLK_SRC_PLLM_OUT0 1 | ||
5015 | #define DISP1_CLK_SRC_PLLD_OUT0 2 | ||
5016 | #define DISP1_CLK_SRC_PLLA_OUT0 3 | ||
5017 | #define DISP1_CLK_SRC_PLLC_OUT0 4 | ||
5018 | #define DISP1_CLK_SRC_PLLD2_OUT0 5 | ||
5019 | #define DISP1_CLK_SRC_CLKM 6 | ||
5020 | #define DISP1_CLK_SRC_DEFAULT (DISP1_CLK_SRC_PLLP_OUT0 << DISP1_CLK_SRC_SHIFT) | ||
5021 | |||
5022 | #define HOST1X_CLK_REG_OFFSET 0x180 | ||
5023 | #define HOST1X_CLK_SRC_SHIFT 30 | ||
5024 | #define HOST1X_CLK_SRC_MASK (0x3 << HOST1X_CLK_SRC_SHIFT) | ||
5025 | #define HOST1X_CLK_SRC_PLLM_OUT0 0 | ||
5026 | #define HOST1X_CLK_SRC_PLLC_OUT0 1 | ||
5027 | #define HOST1X_CLK_SRC_PLLP_OUT0 2 | ||
5028 | #define HOST1X_CLK_SRC_PLLA_OUT0 3 | ||
5029 | #define HOST1X_CLK_SRC_DEFAULT (\ | ||
5030 | HOST1X_CLK_SRC_PLLP_OUT0 << HOST1X_CLK_SRC_SHIFT) | ||
5031 | #define HOST1X_CLK_IDLE_DIV_SHIFT 8 | ||
5032 | #define HOST1X_CLK_IDLE_DIV_MASK (0xff << HOST1X_CLK_IDLE_DIV_SHIFT) | ||
5033 | #define HOST1X_CLK_IDLE_DIV_DEFAULT (0 << HOST1X_CLK_IDLE_DIV_SHIFT) | ||
5034 | #define HOST1X_CLK_DIV_SHIFT 0 | ||
5035 | #define HOST1X_CLK_DIV_MASK (0xff << HOST1X_CLK_DIV_SHIFT) | ||
5036 | #define HOST1X_CLK_DIV_DEFAULT (3 << HOST1X_CLK_DIV_SHIFT) | ||
5037 | |||
5038 | #define AUDIO_CLK_REG_OFFSET 0x3d0 | ||
5039 | #define DAM0_CLK_REG_OFFSET 0x3d8 | ||
5040 | #define DAM1_CLK_REG_OFFSET 0x3dc | ||
5041 | #define DAM2_CLK_REG_OFFSET 0x3e0 | ||
5042 | #define AUDIO_CLK_SRC_SHIFT 28 | ||
5043 | #define AUDIO_CLK_SRC_MASK (0x0f << AUDIO_CLK_SRC_SHIFT) | ||
5044 | #define AUDIO_CLK_SRC_PLLA_OUT0 0x01 | ||
5045 | #define AUDIO_CLK_SRC_PLLC_OUT0 0x05 | ||
5046 | #define AUDIO_CLK_SRC_PLLP_OUT0 0x09 | ||
5047 | #define AUDIO_CLK_SRC_CLKM 0x0d | ||
5048 | #define AUDIO_CLK_SRC_DEFAULT (\ | ||
5049 | AUDIO_CLK_SRC_CLKM << AUDIO_CLK_SRC_SHIFT) | ||
5050 | #define AUDIO_CLK_DIV_SHIFT 0 | ||
5051 | #define AUDIO_CLK_DIV_MASK (0xff << AUDIO_CLK_DIV_SHIFT) | ||
5052 | #define AUDIO_CLK_DIV_DEFAULT (\ | ||
5053 | (0 << AUDIO_CLK_DIV_SHIFT)) | ||
5054 | |||
5055 | static void __init clk_setbit(u32 reg, u32 bit) | ||
5056 | { | ||
5057 | u32 val = clk_readl(reg); | ||
5058 | |||
5059 | if ((val & bit) == bit) | ||
5060 | return; | ||
5061 | val |= bit; | ||
5062 | clk_writel(val, reg); | ||
5063 | udelay(2); | ||
5064 | } | ||
5065 | |||
5066 | static void __init clk_clrbit(u32 reg, u32 bit) | ||
5067 | { | ||
5068 | u32 val = clk_readl(reg); | ||
5069 | |||
5070 | if ((val & bit) == 0) | ||
5071 | return; | ||
5072 | val &= ~bit; | ||
5073 | clk_writel(val, reg); | ||
5074 | udelay(2); | ||
5075 | } | ||
5076 | |||
5077 | static void __init clk_setbits(u32 reg, u32 bits, u32 mask) | ||
5078 | { | ||
5079 | u32 val = clk_readl(reg); | ||
5080 | |||
5081 | if ((val & mask) == bits) | ||
5082 | return; | ||
5083 | val &= ~mask; | ||
5084 | val |= bits; | ||
5085 | clk_writel(val, reg); | ||
5086 | udelay(2); | ||
5087 | } | ||
5088 | |||
5089 | static int __init tegra_soc_preinit_clocks(void) | ||
5090 | { | ||
5091 | /* | ||
5092 | * Make sure host1x clock configuration has: | ||
5093 | * HOST1X_CLK_SRC : PLLP_OUT0. | ||
5094 | * HOST1X_CLK_DIVISOR: >2 to start from safe enough frequency. | ||
5095 | */ | ||
5096 | clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); | ||
5097 | clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); | ||
5098 | clk_setbits(HOST1X_CLK_REG_OFFSET, | ||
5099 | HOST1X_CLK_DIV_DEFAULT, HOST1X_CLK_DIV_MASK); | ||
5100 | clk_setbits(HOST1X_CLK_REG_OFFSET, | ||
5101 | HOST1X_CLK_IDLE_DIV_DEFAULT, HOST1X_CLK_IDLE_DIV_MASK); | ||
5102 | clk_setbits(HOST1X_CLK_REG_OFFSET, | ||
5103 | HOST1X_CLK_SRC_DEFAULT, HOST1X_CLK_SRC_MASK); | ||
5104 | clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); | ||
5105 | |||
5106 | /* | ||
5107 | * Make sure disp1 clock configuration ha: | ||
5108 | * DISP1_CLK_SRC: DISP1_CLK_SRC_PLLP_OUT0 | ||
5109 | */ | ||
5110 | clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); | ||
5111 | clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); | ||
5112 | clk_setbits(DISP1_CLK_REG_OFFSET, | ||
5113 | DISP1_CLK_SRC_DEFAULT, DISP1_CLK_SRC_MASK); | ||
5114 | clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); | ||
5115 | |||
5116 | /* | ||
5117 | * Make sure dam2 clock configuration has: | ||
5118 | * DAM2_CLK_SRC: AUDIO_CLK_SRC_CLKM | ||
5119 | */ | ||
5120 | clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); | ||
5121 | clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); | ||
5122 | clk_setbits(DAM2_CLK_REG_OFFSET, | ||
5123 | AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); | ||
5124 | clk_setbits(DAM2_CLK_REG_OFFSET, | ||
5125 | AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); | ||
5126 | clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); | ||
5127 | |||
5128 | /* | ||
5129 | * Make sure dam1 clock configuration has: | ||
5130 | * DAM1_CLK_SRC: AUDIO_CLK_SRC_CLKM | ||
5131 | */ | ||
5132 | clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); | ||
5133 | clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); | ||
5134 | clk_setbits(DAM1_CLK_REG_OFFSET, | ||
5135 | AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); | ||
5136 | clk_setbits(DAM1_CLK_REG_OFFSET, | ||
5137 | AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); | ||
5138 | clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); | ||
5139 | |||
5140 | /* | ||
5141 | * Make sure dam0 clock configuration has: | ||
5142 | * DAM0_CLK_SRC: AUDIO_CLK_SRC_CLKM | ||
5143 | */ | ||
5144 | clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); | ||
5145 | clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); | ||
5146 | clk_setbits(DAM0_CLK_REG_OFFSET, | ||
5147 | AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); | ||
5148 | clk_setbits(DAM0_CLK_REG_OFFSET, | ||
5149 | AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); | ||
5150 | clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); | ||
5151 | |||
5152 | /* | ||
5153 | * Make sure d_audio clock configuration has: | ||
5154 | * AUDIO_CLK_SRC: AUDIO_CLK_SRC_CLKM | ||
5155 | */ | ||
5156 | clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); | ||
5157 | clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); | ||
5158 | clk_setbits(AUDIO_CLK_REG_OFFSET, | ||
5159 | AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); | ||
5160 | clk_setbits(AUDIO_CLK_REG_OFFSET, | ||
5161 | AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); | ||
5162 | clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); | ||
5163 | |||
5164 | return 0; | ||
5165 | } | ||
5166 | #endif /* CONFIG_TEGRA_PREINIT_CLOCKS */ | ||
5167 | |||
5168 | void __init tegra_soc_init_clocks(void) | ||
5169 | { | ||
5170 | int i; | ||
5171 | struct clk *c; | ||
5172 | |||
5173 | #ifdef CONFIG_TEGRA_PREINIT_CLOCKS | ||
5174 | tegra_soc_preinit_clocks(); | ||
5175 | #endif /* CONFIG_TEGRA_PREINIT_CLOCKS */ | ||
5176 | |||
5177 | for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) | ||
5178 | tegra3_init_one_clock(tegra_ptr_clks[i]); | ||
5179 | |||
5180 | for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) | ||
5181 | tegra3_init_one_clock(&tegra_list_clks[i]); | ||
5182 | |||
5183 | for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { | ||
5184 | c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); | ||
5185 | if (!c) { | ||
5186 | pr_err("%s: Unknown duplicate clock %s\n", __func__, | ||
5187 | tegra_clk_duplicates[i].name); | ||
5188 | continue; | ||
5189 | } | ||
5190 | |||
5191 | tegra_clk_duplicates[i].lookup.clk = c; | ||
5192 | clkdev_add(&tegra_clk_duplicates[i].lookup); | ||
5193 | } | ||
5194 | |||
5195 | for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) | ||
5196 | tegra3_init_one_clock(&tegra_sync_source_list[i]); | ||
5197 | for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) | ||
5198 | tegra3_init_one_clock(&tegra_clk_audio_list[i]); | ||
5199 | for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) | ||
5200 | tegra3_init_one_clock(&tegra_clk_audio_2x_list[i]); | ||
5201 | |||
5202 | init_clk_out_mux(); | ||
5203 | for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) | ||
5204 | tegra3_init_one_clock(&tegra_clk_out_list[i]); | ||
5205 | |||
5206 | emc_bridge = &tegra_clk_emc_bridge; | ||
5207 | |||
5208 | /* Initialize to default */ | ||
5209 | tegra_init_cpu_edp_limits(0); | ||
5210 | |||
5211 | register_syscore_ops(&tegra_clk_syscore_ops); | ||
5212 | } | ||