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-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2930
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diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
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1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * Copyright (C) 2010-2012 NVIDIA Corporation
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clkdev.h>
29#include <linux/clk.h>
30#include <linux/syscore_ops.h>
31#include <linux/cpufreq.h>
32
33#include <mach/iomap.h>
34#include <mach/pinmux.h>
35
36#include "clock.h"
37#include "fuse.h"
38#include "tegra2_emc.h"
39#include "tegra2_statmon.h"
40
41#define RST_DEVICES 0x004
42#define RST_DEVICES_SET 0x300
43#define RST_DEVICES_CLR 0x304
44#define RST_DEVICES_NUM 3
45
46#define CLK_OUT_ENB 0x010
47#define CLK_OUT_ENB_SET 0x320
48#define CLK_OUT_ENB_CLR 0x324
49#define CLK_OUT_ENB_NUM 3
50
51#define CLK_MASK_ARM 0x44
52#define MISC_CLK_ENB 0x48
53
54#define OSC_CTRL 0x50
55#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
56#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
57#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
58#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
59#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
60#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
61
62#define PERIPH_CLK_SOURCE_I2S1 0x100
63#define PERIPH_CLK_SOURCE_EMC 0x19c
64#define PERIPH_CLK_SOURCE_OSC 0x1fc
65#define PERIPH_CLK_SOURCE_NUM \
66 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
67
68#define PERIPH_CLK_SOURCE_MASK (3<<30)
69#define PERIPH_CLK_SOURCE_SHIFT 30
70#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
71#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
72#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
73#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
74
75#define SDMMC_CLK_INT_FB_SEL (1 << 23)
76#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
77#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
78
79#define PLL_BASE 0x0
80#define PLL_BASE_BYPASS (1<<31)
81#define PLL_BASE_ENABLE (1<<30)
82#define PLL_BASE_REF_ENABLE (1<<29)
83#define PLL_BASE_OVERRIDE (1<<28)
84#define PLL_BASE_DIVP_MASK (0x7<<20)
85#define PLL_BASE_DIVP_SHIFT 20
86#define PLL_BASE_DIVN_MASK (0x3FF<<8)
87#define PLL_BASE_DIVN_SHIFT 8
88#define PLL_BASE_DIVM_MASK (0x1F)
89#define PLL_BASE_DIVM_SHIFT 0
90
91#define PLL_OUT_RATIO_MASK (0xFF<<8)
92#define PLL_OUT_RATIO_SHIFT 8
93#define PLL_OUT_OVERRIDE (1<<2)
94#define PLL_OUT_CLKEN (1<<1)
95#define PLL_OUT_RESET_DISABLE (1<<0)
96
97#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
98
99#define PLL_MISC_DCCON_SHIFT 20
100#define PLL_MISC_CPCON_SHIFT 8
101#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
102#define PLL_MISC_LFCON_SHIFT 4
103#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
104#define PLL_MISC_VCOCON_SHIFT 0
105#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
106
107#define PLLU_BASE_POST_DIV (1<<20)
108
109#define PLLD_MISC_CLKENABLE (1<<30)
110#define PLLD_MISC_DIV_RST (1<<23)
111#define PLLD_MISC_DCCON_SHIFT 12
112
113#define PLLE_MISC_READY (1 << 15)
114
115#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
116#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
117#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
118
119#define SUPER_CLK_MUX 0x00
120#define SUPER_STATE_SHIFT 28
121#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
122#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
123#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
124#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
125#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
126#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
127#define SUPER_SOURCE_MASK 0xF
128#define SUPER_FIQ_SOURCE_SHIFT 12
129#define SUPER_IRQ_SOURCE_SHIFT 8
130#define SUPER_RUN_SOURCE_SHIFT 4
131#define SUPER_IDLE_SOURCE_SHIFT 0
132
133#define SUPER_CLK_DIVIDER 0x04
134
135#define BUS_CLK_DISABLE (1<<3)
136#define BUS_CLK_DIV_MASK 0x3
137
138#define PMC_CTRL 0x0
139 #define PMC_CTRL_BLINK_ENB (1 << 7)
140
141#define PMC_DPD_PADS_ORIDE 0x1c
142 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
143
144#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
145#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
146#define PMC_BLINK_TIMER_ENB (1 << 15)
147#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
148#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
149
150#define AP25_EMC_BRIDGE_RATE 380000000
151#define AP25_EMC_INTERMEDIATE_RATE 760000000
152#define AP25_EMC_SCALING_STEP 600000000
153
154static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
155static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
157
158#define MISC_GP_HIDREV 0x804
159#define PLLDU_LFCON_SET_DIVN 600
160
161static int tegra2_clk_shared_bus_update(struct clk *bus);
162
163/*
164 * Some clocks share a register with other clocks. Any clock op that
165 * non-atomically modifies a register used by another clock must lock
166 * clock_register_lock first.
167 */
168static DEFINE_SPINLOCK(clock_register_lock);
169
170/*
171 * Some peripheral clocks share an enable bit, so refcount the enable bits
172 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
173 */
174static int tegra_periph_clk_enable_refcount[3 * 32];
175
176#define clk_writel(value, reg) \
177 __raw_writel(value, (u32)reg_clk_base + (reg))
178#define clk_readl(reg) \
179 __raw_readl((u32)reg_clk_base + (reg))
180#define pmc_writel(value, reg) \
181 __raw_writel(value, (u32)reg_pmc_base + (reg))
182#define pmc_readl(reg) \
183 __raw_readl((u32)reg_pmc_base + (reg))
184#define chipid_readl() \
185 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
186
187static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
188{
189 s64 divider_u71 = parent_rate * 2;
190 divider_u71 += rate - 1;
191 do_div(divider_u71, rate);
192
193 if (divider_u71 - 2 < 0)
194 return 0;
195
196 if (divider_u71 - 2 > 255)
197 return -EINVAL;
198
199 return divider_u71 - 2;
200}
201
202static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
203{
204 s64 divider_u16;
205
206 divider_u16 = parent_rate;
207 divider_u16 += rate - 1;
208 do_div(divider_u16, rate);
209
210 if (divider_u16 - 1 < 0)
211 return 0;
212
213 if (divider_u16 - 1 > 0xFFFF)
214 return -EINVAL;
215
216 return divider_u16 - 1;
217}
218
219static inline int clk_set_div(struct clk *c, int n)
220{
221 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
222}
223
224/* clk_m functions */
225static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
226{
227 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
228
229 c->rate = tegra_clk_measure_input_freq();
230 switch (c->rate) {
231 case 12000000:
232 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
233 break;
234 case 13000000:
235 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
236 break;
237 case 19200000:
238 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
239 break;
240 case 26000000:
241 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
242 break;
243 default:
244 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
245 BUG();
246 }
247 clk_writel(auto_clock_control, OSC_CTRL);
248 return c->rate;
249}
250
251static void tegra2_clk_m_init(struct clk *c)
252{
253 pr_debug("%s on clock %s\n", __func__, c->name);
254 tegra2_clk_m_autodetect_rate(c);
255}
256
257static int tegra2_clk_m_enable(struct clk *c)
258{
259 pr_debug("%s on clock %s\n", __func__, c->name);
260 return 0;
261}
262
263static void tegra2_clk_m_disable(struct clk *c)
264{
265 pr_debug("%s on clock %s\n", __func__, c->name);
266 BUG();
267}
268
269static struct clk_ops tegra_clk_m_ops = {
270 .init = tegra2_clk_m_init,
271 .enable = tegra2_clk_m_enable,
272 .disable = tegra2_clk_m_disable,
273};
274
275/* super clock functions */
276/* "super clocks" on tegra have two-stage muxes and a clock skipping
277 * super divider. We will ignore the clock skipping divider, since we
278 * can't lower the voltage when using the clock skip, but we can if we
279 * lower the PLL frequency.
280 */
281static void tegra2_super_clk_init(struct clk *c)
282{
283 u32 val;
284 int source;
285 int shift;
286 const struct clk_mux_sel *sel;
287 val = clk_readl(c->reg + SUPER_CLK_MUX);
288 c->state = ON;
289 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
290 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
291 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
292 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
293 source = (val >> shift) & SUPER_SOURCE_MASK;
294 for (sel = c->inputs; sel->input != NULL; sel++) {
295 if (sel->value == source)
296 break;
297 }
298 BUG_ON(sel->input == NULL);
299 c->parent = sel->input;
300}
301
302static int tegra2_super_clk_enable(struct clk *c)
303{
304 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
305 return 0;
306}
307
308static void tegra2_super_clk_disable(struct clk *c)
309{
310 pr_debug("%s on clock %s\n", __func__, c->name);
311
312 /* oops - don't disable the CPU clock! */
313 BUG();
314}
315
316static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
317{
318 u32 val;
319 const struct clk_mux_sel *sel;
320 int shift;
321
322 val = clk_readl(c->reg + SUPER_CLK_MUX);
323 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
324 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
325 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
326 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
327 for (sel = c->inputs; sel->input != NULL; sel++) {
328 if (sel->input == p) {
329 val &= ~(SUPER_SOURCE_MASK << shift);
330 val |= sel->value << shift;
331
332 if (c->refcnt)
333 clk_enable(p);
334
335 clk_writel(val, c->reg);
336
337 if (c->refcnt && c->parent)
338 clk_disable(c->parent);
339
340 clk_reparent(c, p);
341 return 0;
342 }
343 }
344 return -EINVAL;
345}
346
347/*
348 * Super clocks have "clock skippers" instead of dividers. Dividing using
349 * a clock skipper does not allow the voltage to be scaled down, so instead
350 * adjust the rate of the parent clock. This requires that the parent of a
351 * super clock have no other children, otherwise the rate will change
352 * underneath the other children.
353 */
354static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
355{
356 return clk_set_rate(c->parent, rate);
357}
358
359static struct clk_ops tegra_super_ops = {
360 .init = tegra2_super_clk_init,
361 .enable = tegra2_super_clk_enable,
362 .disable = tegra2_super_clk_disable,
363 .set_parent = tegra2_super_clk_set_parent,
364 .set_rate = tegra2_super_clk_set_rate,
365};
366
367static int tegra2_twd_clk_set_rate(struct clk *c, unsigned long rate)
368{
369 /* The input value 'rate' is the clock rate of the CPU complex. */
370 c->rate = (rate * c->mul) / c->div;
371 return 0;
372}
373
374static struct clk_ops tegra2_twd_ops = {
375 .set_rate = tegra2_twd_clk_set_rate,
376};
377
378static struct clk tegra2_clk_twd = {
379 /* NOTE: The twd clock must have *NO* parent. It's rate is directly
380 updated by tegra3_cpu_cmplx_clk_set_rate() because the
381 frequency change notifer for the twd is called in an
382 atomic context which cannot take a mutex. */
383 .name = "twd",
384 .ops = &tegra2_twd_ops,
385 .max_rate = 1000000000, /* Same as tegra_clk_virtual_cpu.max_rate */
386 .mul = 1,
387 .div = 4,
388};
389
390/* virtual cpu clock functions */
391/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
392 To change the frequency of these clocks, the parent pll may need to be
393 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
394 and then the clock moved back to the pll. To hide this sequence, a virtual
395 clock handles it.
396 */
397static void tegra2_cpu_clk_init(struct clk *c)
398{
399}
400
401static int tegra2_cpu_clk_enable(struct clk *c)
402{
403 return 0;
404}
405
406static void tegra2_cpu_clk_disable(struct clk *c)
407{
408 pr_debug("%s on clock %s\n", __func__, c->name);
409
410 /* oops - don't disable the CPU clock! */
411 BUG();
412}
413
414static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
415{
416 int ret;
417 /*
418 * Take an extra reference to the main pll so it doesn't turn
419 * off when we move the cpu off of it
420 */
421 clk_enable(c->u.cpu.main);
422
423 ret = clk_set_parent(c->parent, c->u.cpu.backup);
424 if (ret) {
425 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
426 goto out;
427 }
428
429 if (rate == clk_get_rate(c->u.cpu.backup))
430 goto out;
431
432 ret = clk_set_rate(c->u.cpu.main, rate);
433 if (ret) {
434 pr_err("Failed to change cpu pll to %lu\n", rate);
435 goto out;
436 }
437
438 ret = clk_set_parent(c->parent, c->u.cpu.main);
439 if (ret) {
440 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
441 goto out;
442 }
443
444out:
445 /* We can't parent the twd to directly to the CPU complex because
446 the TWD frequency update notifier is called in an atomic context
447 and the CPU frequency update requires a mutex. Update the twd
448 clock rate with the new CPU complex rate. */
449 clk_set_rate(&tegra2_clk_twd, clk_get_rate_locked(c));
450
451 clk_disable(c->u.cpu.main);
452 return ret;
453}
454
455static struct clk_ops tegra_cpu_ops = {
456 .init = tegra2_cpu_clk_init,
457 .enable = tegra2_cpu_clk_enable,
458 .disable = tegra2_cpu_clk_disable,
459 .set_rate = tegra2_cpu_clk_set_rate,
460};
461
462static void tegra2_virtual_sclk_init(struct clk *c)
463{
464 c->max_rate = c->parent->max_rate;
465 c->min_rate = c->parent->min_rate;
466}
467
468static long tegra2_virtual_sclk_round_rate(struct clk *c, unsigned long rate)
469{
470 long new_rate = rate;
471 return new_rate;
472}
473
474static int tegra2_virtual_sclk_set_rate(struct clk *c, unsigned long rate)
475{
476 int ret;
477
478 if (rate >= c->u.system.pclk->min_rate * 2) {
479 ret = clk_set_div(c->u.system.pclk, 2);
480 if (ret) {
481 pr_err("Failed to set 1 : 2 pclk divider\n");
482 return ret;
483 }
484 }
485
486 ret = clk_set_rate(c->parent, rate);
487 if (ret) {
488 pr_err("Failed to set sclk source %s to %lu\n",
489 c->parent->name, rate);
490 return ret;
491 }
492
493 if (rate < c->u.system.pclk->min_rate * 2) {
494 ret = clk_set_div(c->u.system.pclk, 1);
495 if (ret) {
496 pr_err("Failed to set 1 : 1 pclk divider\n");
497 return ret;
498 }
499 }
500
501 return 0;
502}
503
504static struct clk_ops tegra_virtual_sclk_ops = {
505 .init = tegra2_virtual_sclk_init,
506 .set_rate = tegra2_virtual_sclk_set_rate,
507 .round_rate = tegra2_virtual_sclk_round_rate,
508 .shared_bus_update = tegra2_clk_shared_bus_update,
509};
510
511/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
512 * reset the COP block (i.e. AVP) */
513static void tegra2_cop_clk_reset(struct clk *c, bool assert)
514{
515 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
516
517 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
518 clk_writel(1 << 1, reg);
519}
520
521static struct clk_ops tegra_cop_ops = {
522 .reset = tegra2_cop_clk_reset,
523};
524
525/* bus clock functions */
526static void tegra2_bus_clk_init(struct clk *c)
527{
528 u32 val = clk_readl(c->reg);
529 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
530 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
531 c->mul = 1;
532}
533
534static int tegra2_bus_clk_enable(struct clk *c)
535{
536 u32 val;
537 unsigned long flags;
538
539 spin_lock_irqsave(&clock_register_lock, flags);
540
541 val = clk_readl(c->reg);
542 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
543 clk_writel(val, c->reg);
544
545 spin_unlock_irqrestore(&clock_register_lock, flags);
546
547 return 0;
548}
549
550static void tegra2_bus_clk_disable(struct clk *c)
551{
552 u32 val;
553 unsigned long flags;
554
555 spin_lock_irqsave(&clock_register_lock, flags);
556
557 val = clk_readl(c->reg);
558 val |= BUS_CLK_DISABLE << c->reg_shift;
559 clk_writel(val, c->reg);
560
561 spin_unlock_irqrestore(&clock_register_lock, flags);
562}
563
564static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
565{
566 u32 val;
567 unsigned long parent_rate = clk_get_rate(c->parent);
568 unsigned long flags;
569 int ret = -EINVAL;
570 int i;
571
572 spin_lock_irqsave(&clock_register_lock, flags);
573
574 val = clk_readl(c->reg);
575 for (i = 1; i <= 4; i++) {
576 if (rate >= parent_rate / i) {
577 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
578 val |= (i - 1) << c->reg_shift;
579 clk_writel(val, c->reg);
580 c->div = i;
581 c->mul = 1;
582 ret = 0;
583 break;
584 }
585 }
586
587 spin_unlock_irqrestore(&clock_register_lock, flags);
588
589 return ret;
590}
591
592static struct clk_ops tegra_bus_ops = {
593 .init = tegra2_bus_clk_init,
594 .enable = tegra2_bus_clk_enable,
595 .disable = tegra2_bus_clk_disable,
596 .set_rate = tegra2_bus_clk_set_rate,
597};
598
599/* Blink output functions */
600
601static void tegra2_blink_clk_init(struct clk *c)
602{
603 u32 val;
604
605 val = pmc_readl(PMC_CTRL);
606 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
607 c->mul = 1;
608 val = pmc_readl(c->reg);
609
610 if (val & PMC_BLINK_TIMER_ENB) {
611 unsigned int on_off;
612
613 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
614 PMC_BLINK_TIMER_DATA_ON_MASK;
615 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
616 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
617 on_off += val;
618 /* each tick in the blink timer is 4 32KHz clocks */
619 c->div = on_off * 4;
620 } else {
621 c->div = 1;
622 }
623}
624
625static int tegra2_blink_clk_enable(struct clk *c)
626{
627 u32 val;
628
629 val = pmc_readl(PMC_DPD_PADS_ORIDE);
630 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
631
632 val = pmc_readl(PMC_CTRL);
633 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
634
635 return 0;
636}
637
638static void tegra2_blink_clk_disable(struct clk *c)
639{
640 u32 val;
641
642 val = pmc_readl(PMC_CTRL);
643 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
644
645 val = pmc_readl(PMC_DPD_PADS_ORIDE);
646 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
647}
648
649static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
650{
651 unsigned long parent_rate = clk_get_rate(c->parent);
652 if (rate >= parent_rate) {
653 c->div = 1;
654 pmc_writel(0, c->reg);
655 } else {
656 unsigned int on_off;
657 u32 val;
658
659 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
660 c->div = on_off * 8;
661
662 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
663 PMC_BLINK_TIMER_DATA_ON_SHIFT;
664 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
665 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
666 val |= on_off;
667 val |= PMC_BLINK_TIMER_ENB;
668 pmc_writel(val, c->reg);
669 }
670
671 return 0;
672}
673
674static struct clk_ops tegra_blink_clk_ops = {
675 .init = &tegra2_blink_clk_init,
676 .enable = &tegra2_blink_clk_enable,
677 .disable = &tegra2_blink_clk_disable,
678 .set_rate = &tegra2_blink_clk_set_rate,
679};
680
681/* PLL Functions */
682static int tegra2_pll_clk_wait_for_lock(struct clk *c)
683{
684 udelay(c->u.pll.lock_delay);
685
686 return 0;
687}
688
689static void tegra2_pll_clk_init(struct clk *c)
690{
691 u32 val = clk_readl(c->reg + PLL_BASE);
692
693 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
694
695 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
696 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
697 c->mul = 1;
698 c->div = 1;
699 } else if (val & PLL_BASE_BYPASS) {
700 c->mul = 1;
701 c->div = 1;
702 } else {
703 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
704 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
705 if (c->flags & PLLU)
706 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
707 else
708 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
709 }
710}
711
712static int tegra2_pll_clk_enable(struct clk *c)
713{
714 u32 val;
715 pr_debug("%s on clock %s\n", __func__, c->name);
716
717 val = clk_readl(c->reg + PLL_BASE);
718 val &= ~PLL_BASE_BYPASS;
719 val |= PLL_BASE_ENABLE;
720 clk_writel(val, c->reg + PLL_BASE);
721
722 if (c->flags & PLLD) {
723 val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE);
724 val |= PLLD_MISC_CLKENABLE;
725 clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE);
726 }
727
728 tegra2_pll_clk_wait_for_lock(c);
729
730 return 0;
731}
732
733static void tegra2_pll_clk_disable(struct clk *c)
734{
735 u32 val;
736 pr_debug("%s on clock %s\n", __func__, c->name);
737
738 val = clk_readl(c->reg);
739 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
740 clk_writel(val, c->reg);
741
742 if (c->flags & PLLD) {
743 val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE);
744 val &= ~PLLD_MISC_CLKENABLE;
745 clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE);
746 }
747}
748
749static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
750{
751 u32 val;
752 u32 p_div = 0;
753 u32 old_base = 0;
754 unsigned long input_rate;
755 const struct clk_pll_freq_table *sel;
756
757 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
758
759 input_rate = clk_get_rate(c->parent);
760 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
761 if (sel->input_rate == input_rate && sel->output_rate == rate) {
762 if (c->flags & PLLU) {
763 BUG_ON(sel->p < 1 || sel->p > 2);
764 if (sel->p == 1)
765 p_div = PLLU_BASE_POST_DIV;
766 } else {
767 BUG_ON(sel->p < 1);
768 for (val = sel->p;
769 val > 1; val >>= 1, p_div++)
770 ;
771 p_div <<= PLL_BASE_DIVP_SHIFT;
772 }
773 break;
774 }
775 }
776
777 /*If required rate is not available in pll's frequency table, prepare
778 parameters manually */
779
780 if (sel->input_rate == 0) {
781 unsigned long cfreq;
782 BUG_ON(c->flags & PLLU);
783 struct clk_pll_freq_table cfg;
784 sel = &cfg;
785
786 switch (input_rate) {
787 case 12000000:
788 case 26000000:
789 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
790 break;
791 case 13000000:
792 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
793 break;
794 case 16800000:
795 case 19200000:
796 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
797 break;
798 default:
799 if (c->parent->flags & DIV_U71_FIXED) {
800 /* PLLP_OUT1 rate is not in PLLA table */
801 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
802 __func__, c->name, input_rate, rate);
803 cfreq = input_rate/(input_rate/1000000);
804 break;
805 }
806 pr_err("%s: Unexpected reference rate %lu\n",
807 __func__, input_rate);
808 BUG();
809 }
810
811 /* Raise VCO to guarantee 0.5% accuracy */
812 for (cfg.output_rate = rate;
813 cfg.output_rate < 200 * cfreq;
814 cfg.output_rate <<= 1, p_div++)
815 ;
816
817 cfg.p = 0x1 << p_div;
818 cfg.m = input_rate / cfreq;
819 cfg.n = cfg.output_rate / cfreq;
820 cfg.cpcon = 0x08; /* OUT_OF_TABLE_CPCON */
821
822 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
823 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
824 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
825 (cfg.output_rate > c->u.pll.vco_max)) {
826 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
827 __func__, c->name, rate);
828 return -EINVAL;
829 }
830 p_div <<= PLL_BASE_DIVP_SHIFT;
831 }
832
833 /*Setup multipliers and divisors, then setup rate*/
834
835 c->mul = sel->n;
836 c->div = sel->m * sel->p;
837
838 old_base = val = clk_readl(c->reg + PLL_BASE);
839 if (c->flags & PLL_FIXED)
840 val |= PLL_BASE_OVERRIDE;
841 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
842 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
843 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
844 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
845 if (val == old_base)
846 return 0;
847
848 if (c->state == ON) {
849 tegra2_pll_clk_disable(c);
850 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
851 }
852 clk_writel(val, c->reg + PLL_BASE);
853
854 if (c->flags & PLL_HAS_CPCON) {
855 val = clk_readl(c->reg + PLL_MISC(c));
856 val &= ~PLL_MISC_CPCON_MASK;
857 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
858 if (c->flags & (PLLU | PLLD)) {
859 val &= ~PLL_MISC_LFCON_MASK;
860 if (sel->n >= PLLDU_LFCON_SET_DIVN)
861 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
862 } else if (c->flags & (PLLX | PLLM)) {
863 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
864 if (rate >= (c->u.pll.vco_max >> 1))
865 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
866 }
867 clk_writel(val, c->reg + PLL_MISC(c));
868 }
869
870 if (c->state == ON)
871 tegra2_pll_clk_enable(c);
872
873 return 0;
874
875}
876
877static struct clk_ops tegra_pll_ops = {
878 .init = tegra2_pll_clk_init,
879 .enable = tegra2_pll_clk_enable,
880 .disable = tegra2_pll_clk_disable,
881 .set_rate = tegra2_pll_clk_set_rate,
882};
883
884static int tegra2_plle_clk_enable(struct clk *c)
885{
886 u32 val;
887
888 pr_debug("%s on clock %s\n", __func__, c->name);
889
890 mdelay(1);
891
892 val = clk_readl(c->reg + PLL_BASE);
893 if (!(val & PLLE_MISC_READY))
894 return -EBUSY;
895
896 val = clk_readl(c->reg + PLL_BASE);
897 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
898 clk_writel(val, c->reg + PLL_BASE);
899
900 return 0;
901}
902
903static struct clk_ops tegra_plle_ops = {
904 .init = tegra2_pll_clk_init,
905 .enable = tegra2_plle_clk_enable,
906 .set_rate = tegra2_pll_clk_set_rate,
907};
908
909/* Clock divider ops */
910static void tegra2_pll_div_clk_init(struct clk *c)
911{
912 u32 val = clk_readl(c->reg);
913 u32 divu71;
914 val >>= c->reg_shift;
915 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
916 if (!(val & PLL_OUT_RESET_DISABLE))
917 c->state = OFF;
918
919 if (c->flags & DIV_U71) {
920 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
921 c->div = (divu71 + 2);
922 c->mul = 2;
923 } else if (c->flags & DIV_2) {
924 c->div = 2;
925 c->mul = 1;
926 } else {
927 c->div = 1;
928 c->mul = 1;
929 }
930}
931
932static int tegra2_pll_div_clk_enable(struct clk *c)
933{
934 u32 val;
935 u32 new_val;
936 unsigned long flags;
937
938 pr_debug("%s: %s\n", __func__, c->name);
939 if (c->flags & DIV_U71) {
940 spin_lock_irqsave(&clock_register_lock, flags);
941 val = clk_readl(c->reg);
942 new_val = val >> c->reg_shift;
943 new_val &= 0xFFFF;
944
945 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
946
947 val &= ~(0xFFFF << c->reg_shift);
948 val |= new_val << c->reg_shift;
949 clk_writel(val, c->reg);
950 spin_unlock_irqrestore(&clock_register_lock, flags);
951 return 0;
952 } else if (c->flags & DIV_2) {
953 BUG_ON(!(c->flags & PLLD));
954 spin_lock_irqsave(&clock_register_lock, flags);
955 val = clk_readl(c->reg);
956 val &= ~PLLD_MISC_DIV_RST;
957 clk_writel(val, c->reg);
958 spin_unlock_irqrestore(&clock_register_lock, flags);
959 return 0;
960 }
961 return -EINVAL;
962}
963
964static void tegra2_pll_div_clk_disable(struct clk *c)
965{
966 u32 val;
967 u32 new_val;
968 unsigned long flags;
969
970 pr_debug("%s: %s\n", __func__, c->name);
971 if (c->flags & DIV_U71) {
972 spin_lock_irqsave(&clock_register_lock, flags);
973 val = clk_readl(c->reg);
974 new_val = val >> c->reg_shift;
975 new_val &= 0xFFFF;
976
977 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
978
979 val &= ~(0xFFFF << c->reg_shift);
980 val |= new_val << c->reg_shift;
981 clk_writel(val, c->reg);
982 spin_unlock_irqrestore(&clock_register_lock, flags);
983 } else if (c->flags & DIV_2) {
984 BUG_ON(!(c->flags & PLLD));
985 spin_lock_irqsave(&clock_register_lock, flags);
986 val = clk_readl(c->reg);
987 val |= PLLD_MISC_DIV_RST;
988 clk_writel(val, c->reg);
989 spin_unlock_irqrestore(&clock_register_lock, flags);
990 }
991}
992
993static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
994{
995 u32 val;
996 u32 new_val;
997 int divider_u71;
998 unsigned long parent_rate = clk_get_rate(c->parent);
999 unsigned long flags;
1000
1001 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1002 if (c->flags & DIV_U71) {
1003 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1004 if (divider_u71 >= 0) {
1005 spin_lock_irqsave(&clock_register_lock, flags);
1006 val = clk_readl(c->reg);
1007 new_val = val >> c->reg_shift;
1008 new_val &= 0xFFFF;
1009 if (c->flags & DIV_U71_FIXED)
1010 new_val |= PLL_OUT_OVERRIDE;
1011 new_val &= ~PLL_OUT_RATIO_MASK;
1012 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1013
1014 val &= ~(0xFFFF << c->reg_shift);
1015 val |= new_val << c->reg_shift;
1016 clk_writel(val, c->reg);
1017 c->div = divider_u71 + 2;
1018 c->mul = 2;
1019 spin_unlock_irqrestore(&clock_register_lock, flags);
1020 return 0;
1021 }
1022 } else if (c->flags & DIV_2) {
1023 if (parent_rate == rate * 2)
1024 return 0;
1025 }
1026 return -EINVAL;
1027}
1028
1029static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1030{
1031 int divider;
1032 unsigned long parent_rate = clk_get_rate(c->parent);
1033 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1034
1035 if (c->flags & DIV_U71) {
1036 divider = clk_div71_get_divider(parent_rate, rate);
1037 if (divider < 0)
1038 return divider;
1039 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1040 } else if (c->flags & DIV_2) {
1041 return DIV_ROUND_UP(parent_rate, 2);
1042 }
1043 return -EINVAL;
1044}
1045
1046static struct clk_ops tegra_pll_div_ops = {
1047 .init = tegra2_pll_div_clk_init,
1048 .enable = tegra2_pll_div_clk_enable,
1049 .disable = tegra2_pll_div_clk_disable,
1050 .set_rate = tegra2_pll_div_clk_set_rate,
1051 .round_rate = tegra2_pll_div_clk_round_rate,
1052};
1053
1054/* Periph clk ops */
1055
1056static void tegra2_periph_clk_init(struct clk *c)
1057{
1058 u32 val = clk_readl(c->reg);
1059 const struct clk_mux_sel *mux = 0;
1060 const struct clk_mux_sel *sel;
1061 if (c->flags & MUX) {
1062 for (sel = c->inputs; sel->input != NULL; sel++) {
1063 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
1064 mux = sel;
1065 }
1066 BUG_ON(!mux);
1067
1068 c->parent = mux->input;
1069 } else {
1070 c->parent = c->inputs[0].input;
1071 }
1072
1073 if (c->flags & DIV_U71) {
1074 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1075 c->div = divu71 + 2;
1076 c->mul = 2;
1077 } else if (c->flags & DIV_U16) {
1078 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1079 c->div = divu16 + 1;
1080 c->mul = 1;
1081 } else {
1082 c->div = 1;
1083 c->mul = 1;
1084 }
1085
1086 c->state = ON;
1087 if (c->flags & PERIPH_NO_ENB)
1088 return;
1089
1090 if (!c->u.periph.clk_num)
1091 return;
1092
1093 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1094 PERIPH_CLK_TO_ENB_BIT(c)))
1095 c->state = OFF;
1096
1097 if (!(c->flags & PERIPH_NO_RESET))
1098 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1099 PERIPH_CLK_TO_ENB_BIT(c))
1100 c->state = OFF;
1101}
1102
1103static int tegra2_periph_clk_enable(struct clk *c)
1104{
1105 u32 val;
1106 unsigned long flags;
1107 int refcount;
1108 pr_debug("%s on clock %s\n", __func__, c->name);
1109
1110 if (c->flags & PERIPH_NO_ENB)
1111 return 0;
1112
1113 if (!c->u.periph.clk_num)
1114 return 0;
1115
1116 spin_lock_irqsave(&clock_register_lock, flags);
1117
1118 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1119
1120 if (refcount > 1)
1121 goto out;
1122
1123 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1124 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1125 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1126 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1127 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1128 if (c->flags & PERIPH_EMC_ENB) {
1129 /* The EMC peripheral clock has 2 extra enable bits */
1130 /* FIXME: Do they need to be disabled? */
1131 val = clk_readl(c->reg);
1132 val |= 0x3 << 24;
1133 clk_writel(val, c->reg);
1134 }
1135
1136out:
1137 spin_unlock_irqrestore(&clock_register_lock, flags);
1138
1139 return 0;
1140}
1141
1142static void tegra2_periph_clk_disable(struct clk *c)
1143{
1144 unsigned long flags;
1145 unsigned long val;
1146
1147 pr_debug("%s on clock %s\n", __func__, c->name);
1148
1149 if (c->flags & PERIPH_NO_ENB)
1150 return;
1151
1152 if (!c->u.periph.clk_num)
1153 return;
1154
1155 spin_lock_irqsave(&clock_register_lock, flags);
1156
1157 if (c->refcnt)
1158 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1159
1160 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
1161 /* If peripheral is in the APB bus then read the APB bus to
1162 * flush the write operation in apb bus. This will avoid the
1163 * peripheral access after disabling clock*/
1164 if (c->flags & PERIPH_ON_APB)
1165 val = chipid_readl();
1166
1167 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1168 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1169 }
1170
1171 spin_unlock_irqrestore(&clock_register_lock, flags);
1172}
1173
1174static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1175{
1176 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1177 unsigned long val;
1178
1179 pr_debug("%s %s on clock %s\n", __func__,
1180 assert ? "assert" : "deassert", c->name);
1181
1182 if (c->flags & PERIPH_NO_ENB)
1183 return;
1184
1185 BUG_ON(!c->u.periph.clk_num);
1186
1187 if (!(c->flags & PERIPH_NO_RESET)) {
1188 /* If peripheral is in the APB bus then read the APB bus to
1189 * flush the write operation in apb bus. This will avoid the
1190 * peripheral access after disabling clock*/
1191 if (c->flags & PERIPH_ON_APB)
1192 val = chipid_readl();
1193
1194 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1195 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1196 }
1197}
1198
1199static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1200{
1201 u32 val;
1202 const struct clk_mux_sel *sel;
1203 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1204 for (sel = c->inputs; sel->input != NULL; sel++) {
1205 if (sel->input == p) {
1206 val = clk_readl(c->reg);
1207 val &= ~((c->reg_shift >> 8) << (c->reg_shift & 0xFF));
1208 val |= (sel->value) << (c->reg_shift & 0xFF);
1209
1210 if (c->refcnt)
1211 clk_enable(p);
1212
1213 clk_writel(val, c->reg);
1214
1215 if (c->refcnt && c->parent)
1216 clk_disable(c->parent);
1217
1218 clk_reparent(c, p);
1219 return 0;
1220 }
1221 }
1222
1223 return -EINVAL;
1224}
1225
1226static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1227{
1228 u32 val;
1229 int divider;
1230 unsigned long parent_rate = clk_get_rate(c->parent);
1231
1232 if (c->flags & DIV_U71) {
1233 divider = clk_div71_get_divider(parent_rate, rate);
1234 if (divider >= 0) {
1235 val = clk_readl(c->reg);
1236 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1237 val |= divider;
1238 clk_writel(val, c->reg);
1239 c->div = divider + 2;
1240 c->mul = 2;
1241 return 0;
1242 }
1243 } else if (c->flags & DIV_U16) {
1244 divider = clk_div16_get_divider(parent_rate, rate);
1245 if (divider >= 0) {
1246 val = clk_readl(c->reg);
1247 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1248 val |= divider;
1249 clk_writel(val, c->reg);
1250 c->div = divider + 1;
1251 c->mul = 1;
1252 return 0;
1253 }
1254 } else if (parent_rate <= rate) {
1255 c->div = 1;
1256 c->mul = 1;
1257 return 0;
1258 }
1259 return -EINVAL;
1260}
1261
1262static long tegra2_periph_clk_round_rate(struct clk *c,
1263 unsigned long rate)
1264{
1265 int divider;
1266 unsigned long parent_rate = clk_get_rate(c->parent);
1267 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1268
1269 if (c->flags & DIV_U71) {
1270 divider = clk_div71_get_divider(parent_rate, rate);
1271 if (divider < 0)
1272 return divider;
1273
1274 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1275 } else if (c->flags & DIV_U16) {
1276 divider = clk_div16_get_divider(parent_rate, rate);
1277 if (divider < 0)
1278 return divider;
1279 return DIV_ROUND_UP(parent_rate, divider + 1);
1280 }
1281 return -EINVAL;
1282}
1283
1284static struct clk_ops tegra_periph_clk_ops = {
1285 .init = &tegra2_periph_clk_init,
1286 .enable = &tegra2_periph_clk_enable,
1287 .disable = &tegra2_periph_clk_disable,
1288 .set_parent = &tegra2_periph_clk_set_parent,
1289 .set_rate = &tegra2_periph_clk_set_rate,
1290 .round_rate = &tegra2_periph_clk_round_rate,
1291 .reset = &tegra2_periph_clk_reset,
1292};
1293
1294/* The SDMMC controllers have extra bits in the clock source register that
1295 * adjust the delay between the clock and data to compenstate for delays
1296 * on the PCB. */
1297void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1298{
1299 u32 reg;
1300
1301 delay = clamp(delay, 0, 15);
1302 reg = clk_readl(c->reg);
1303 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1304 reg |= SDMMC_CLK_INT_FB_SEL;
1305 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1306 clk_writel(reg, c->reg);
1307}
1308
1309/* External memory controller clock ops */
1310static void tegra2_emc_clk_init(struct clk *c)
1311{
1312 tegra2_periph_clk_init(c);
1313 c->max_rate = clk_get_rate_locked(c);
1314}
1315
1316static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1317{
1318 long new_rate = rate;
1319
1320 new_rate = tegra_emc_round_rate(new_rate);
1321 if (new_rate < 0)
1322 return c->max_rate;
1323
1324 return new_rate;
1325}
1326
1327static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1328{
1329 int ret;
1330 int divider;
1331 struct clk *p = NULL;
1332 unsigned long inp_rate;
1333 unsigned long new_rate;
1334 const struct clk_mux_sel *sel;
1335
1336 for (sel = c->inputs; sel->input != NULL; sel++) {
1337 inp_rate = clk_get_rate(sel->input);
1338
1339 divider = clk_div71_get_divider(inp_rate, rate);
1340 if (divider < 0)
1341 return divider;
1342
1343 new_rate = DIV_ROUND_UP(inp_rate * 2, divider + 2);
1344 if ((abs(rate - new_rate)) < 2000) {
1345 p = sel->input;
1346 break;
1347 }
1348 }
1349
1350 BUG_ON(!p);
1351 BUG_ON(divider & 0x1);
1352
1353 /*
1354 * The Tegra2 memory controller has an interlock with the clock
1355 * block that allows memory shadowed registers to be updated,
1356 * and then transfer them to the main registers at the same
1357 * time as the clock update without glitches.
1358 */
1359 ret = tegra_emc_set_rate(rate);
1360 if (ret < 0)
1361 return ret;
1362
1363 if (c->parent != p) {
1364 BUG_ON(divider != 0);
1365 ret = clk_set_parent_locked(c, p);
1366 udelay(1);
1367 return ret;
1368 }
1369
1370 ret = tegra2_periph_clk_set_rate(c, rate);
1371 udelay(1);
1372
1373 return ret;
1374}
1375
1376static struct clk_ops tegra_emc_clk_ops = {
1377 .init = &tegra2_emc_clk_init,
1378 .enable = &tegra2_periph_clk_enable,
1379 .disable = &tegra2_periph_clk_disable,
1380 .set_parent = &tegra2_periph_clk_set_parent,
1381 .set_rate = &tegra2_emc_clk_set_rate,
1382 .round_rate = &tegra2_emc_clk_round_rate,
1383 .reset = &tegra2_periph_clk_reset,
1384 .shared_bus_update = &tegra2_clk_shared_bus_update,
1385};
1386
1387/* Clock doubler ops */
1388static void tegra2_clk_double_init(struct clk *c)
1389{
1390 c->mul = 2;
1391 c->div = 1;
1392 c->state = ON;
1393
1394 if (!c->u.periph.clk_num)
1395 return;
1396
1397 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1398 PERIPH_CLK_TO_ENB_BIT(c)))
1399 c->state = OFF;
1400};
1401
1402static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1403{
1404 if (rate != 2 * clk_get_rate(c->parent))
1405 return -EINVAL;
1406 c->mul = 2;
1407 c->div = 1;
1408 return 0;
1409}
1410
1411static struct clk_ops tegra_clk_double_ops = {
1412 .init = &tegra2_clk_double_init,
1413 .enable = &tegra2_periph_clk_enable,
1414 .disable = &tegra2_periph_clk_disable,
1415 .set_rate = &tegra2_clk_double_set_rate,
1416};
1417
1418/* Audio sync clock ops */
1419static void tegra2_audio_sync_clk_init(struct clk *c)
1420{
1421 int source;
1422 const struct clk_mux_sel *sel;
1423 u32 val = clk_readl(c->reg);
1424 c->state = (val & (1<<4)) ? OFF : ON;
1425 source = val & 0xf;
1426 for (sel = c->inputs; sel->input != NULL; sel++)
1427 if (sel->value == source)
1428 break;
1429 BUG_ON(sel->input == NULL);
1430 c->parent = sel->input;
1431}
1432
1433static int tegra2_audio_sync_clk_enable(struct clk *c)
1434{
1435 clk_writel(0, c->reg);
1436 return 0;
1437}
1438
1439static void tegra2_audio_sync_clk_disable(struct clk *c)
1440{
1441 clk_writel(1, c->reg);
1442}
1443
1444static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1445{
1446 u32 val;
1447 const struct clk_mux_sel *sel;
1448 for (sel = c->inputs; sel->input != NULL; sel++) {
1449 if (sel->input == p) {
1450 val = clk_readl(c->reg);
1451 val &= ~0xf;
1452 val |= sel->value;
1453
1454 if (c->refcnt)
1455 clk_enable(p);
1456
1457 clk_writel(val, c->reg);
1458
1459 if (c->refcnt && c->parent)
1460 clk_disable(c->parent);
1461
1462 clk_reparent(c, p);
1463 return 0;
1464 }
1465 }
1466
1467 return -EINVAL;
1468}
1469
1470static struct clk_ops tegra_audio_sync_clk_ops = {
1471 .init = tegra2_audio_sync_clk_init,
1472 .enable = tegra2_audio_sync_clk_enable,
1473 .disable = tegra2_audio_sync_clk_disable,
1474 .set_parent = tegra2_audio_sync_clk_set_parent,
1475};
1476
1477/* call this function after pinmux configuration */
1478static void tegra2_cdev_clk_set_parent(struct clk *c)
1479{
1480 const struct clk_mux_sel *mux = 0;
1481 const struct clk_mux_sel *sel;
1482 enum tegra_pingroup pg = TEGRA_PINGROUP_CDEV1;
1483 int val;
1484
1485 /* Get pinmux setting for cdev1 and cdev2 from APB_MISC register */
1486 if (!strcmp(c->name, "cdev2"))
1487 pg = TEGRA_PINGROUP_CDEV2;
1488
1489 val = tegra_pinmux_get_func(pg);
1490 for (sel = c->inputs; sel->input != NULL; sel++) {
1491 if (val == sel->value)
1492 mux = sel;
1493 }
1494 BUG_ON(!mux);
1495
1496 c->parent = mux->input;
1497}
1498
1499/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1500static void tegra2_cdev_clk_init(struct clk *c)
1501{
1502 const struct clk_mux_sel *sel;
1503
1504 /* Find max rate from inputs */
1505 for (sel = c->inputs; sel->input != NULL; sel++) {
1506 c->max_rate = max(sel->input->max_rate, c->max_rate);
1507 }
1508
1509 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1510 * currently done in the pinmux code. */
1511 c->state = ON;
1512
1513 BUG_ON(!c->u.periph.clk_num);
1514
1515 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1516 PERIPH_CLK_TO_ENB_BIT(c)))
1517 c->state = OFF;
1518}
1519
1520static int tegra2_cdev_clk_enable(struct clk *c)
1521{
1522 BUG_ON(!c->u.periph.clk_num);
1523
1524 if (!c->parent) {
1525 /* Set parent from inputs */
1526 tegra2_cdev_clk_set_parent(c);
1527 clk_enable(c->parent);
1528 }
1529
1530 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1531 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1532 return 0;
1533}
1534
1535static void tegra2_cdev_clk_disable(struct clk *c)
1536{
1537 BUG_ON(!c->u.periph.clk_num);
1538
1539 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1540 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1541}
1542
1543static struct clk_ops tegra_cdev_clk_ops = {
1544 .init = &tegra2_cdev_clk_init,
1545 .enable = &tegra2_cdev_clk_enable,
1546 .disable = &tegra2_cdev_clk_disable,
1547};
1548
1549/* shared bus ops */
1550/*
1551 * Some clocks may have multiple downstream users that need to request a
1552 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1553 * clock to each user. The frequency of the bus is set to the highest
1554 * enabled shared_bus_user clock, with a minimum value set by the
1555 * shared bus.
1556 */
1557static int tegra2_clk_shared_bus_update(struct clk *bus)
1558{
1559 struct clk *c;
1560 unsigned long old_rate;
1561 unsigned long rate = bus->min_rate;
1562 int sku_id = tegra_sku_id();
1563
1564 list_for_each_entry(c, &bus->shared_bus_list,
1565 u.shared_bus_user.node) {
1566 if (c->u.shared_bus_user.enabled)
1567 rate = max(c->u.shared_bus_user.rate, rate);
1568 }
1569
1570 old_rate = clk_get_rate_locked(bus);
1571
1572 if (rate == old_rate)
1573 return 0;
1574
1575 /* WAR: For AP25 EMC scaling */
1576 if ((sku_id == 0x17) && (bus->flags & PERIPH_EMC_ENB)) {
1577 if (old_rate == AP25_EMC_SCALING_STEP &&
1578 rate != AP25_EMC_INTERMEDIATE_RATE)
1579 clk_set_rate_locked(bus, AP25_EMC_INTERMEDIATE_RATE);
1580
1581 if (((old_rate > AP25_EMC_BRIDGE_RATE) &&
1582 (rate < AP25_EMC_BRIDGE_RATE)) ||
1583 ((old_rate < AP25_EMC_BRIDGE_RATE) &&
1584 (rate > AP25_EMC_BRIDGE_RATE)))
1585 clk_set_rate_locked(bus, AP25_EMC_BRIDGE_RATE);
1586
1587 if (rate == AP25_EMC_SCALING_STEP &&
1588 old_rate != AP25_EMC_INTERMEDIATE_RATE)
1589 clk_set_rate_locked(bus, AP25_EMC_INTERMEDIATE_RATE);
1590 }
1591
1592 return clk_set_rate_locked(bus, rate);
1593};
1594
1595static void tegra_clk_shared_bus_init(struct clk *c)
1596{
1597 unsigned long flags;
1598
1599 c->max_rate = c->parent->max_rate;
1600 c->u.shared_bus_user.rate = c->parent->max_rate;
1601 c->state = OFF;
1602 c->set = true;
1603
1604 clk_lock_save(c->parent, &flags);
1605
1606 list_add_tail(&c->u.shared_bus_user.node,
1607 &c->parent->shared_bus_list);
1608
1609 clk_unlock_restore(c->parent, &flags);
1610}
1611
1612static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1613{
1614 int ret;
1615 long new_rate = rate;
1616
1617 new_rate = clk_round_rate(c->parent, new_rate);
1618 if (new_rate < 0)
1619 return new_rate;
1620
1621 c->u.shared_bus_user.rate = new_rate;
1622 ret = tegra_clk_shared_bus_update(c->parent);
1623
1624 return ret;
1625}
1626
1627static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1628{
1629 return clk_round_rate(c->parent, rate);
1630}
1631
1632static int tegra_clk_shared_bus_enable(struct clk *c)
1633{
1634 int ret;
1635
1636 c->u.shared_bus_user.enabled = true;
1637 ret = tegra_clk_shared_bus_update(c->parent);
1638 if (strcmp(c->name, "avp.sclk") == 0)
1639 tegra2_statmon_start();
1640
1641 return ret;
1642}
1643
1644static void tegra_clk_shared_bus_disable(struct clk *c)
1645{
1646 int ret;
1647
1648 if (strcmp(c->name, "avp.sclk") == 0)
1649 tegra2_statmon_stop();
1650 c->u.shared_bus_user.enabled = false;
1651 ret = tegra_clk_shared_bus_update(c->parent);
1652 WARN_ON_ONCE(ret);
1653}
1654
1655static struct clk_ops tegra_clk_shared_bus_ops = {
1656 .init = tegra_clk_shared_bus_init,
1657 .enable = tegra_clk_shared_bus_enable,
1658 .disable = tegra_clk_shared_bus_disable,
1659 .set_rate = tegra_clk_shared_bus_set_rate,
1660 .round_rate = tegra_clk_shared_bus_round_rate,
1661};
1662
1663
1664/* Clock definitions */
1665static struct clk tegra_clk_32k = {
1666 .name = "clk_32k",
1667 .rate = 32768,
1668 .ops = NULL,
1669 .max_rate = 32768,
1670};
1671
1672static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1673 {32768, 12000000, 366, 1, 1, 0},
1674 {32768, 13000000, 397, 1, 1, 0},
1675 {32768, 19200000, 586, 1, 1, 0},
1676 {32768, 26000000, 793, 1, 1, 0},
1677 {0, 0, 0, 0, 0, 0},
1678};
1679
1680static struct clk tegra_pll_s = {
1681 .name = "pll_s",
1682 .flags = PLL_ALT_MISC_REG,
1683 .ops = &tegra_pll_ops,
1684 .parent = &tegra_clk_32k,
1685 .max_rate = 26000000,
1686 .reg = 0xf0,
1687 .u.pll = {
1688 .input_min = 32768,
1689 .input_max = 32768,
1690 .cf_min = 0, /* FIXME */
1691 .cf_max = 0, /* FIXME */
1692 .vco_min = 12000000,
1693 .vco_max = 26000000,
1694 .freq_table = tegra_pll_s_freq_table,
1695 .lock_delay = 300,
1696 },
1697};
1698
1699static struct clk_mux_sel tegra_clk_m_sel[] = {
1700 { .input = &tegra_clk_32k, .value = 0},
1701 { .input = &tegra_pll_s, .value = 1},
1702 { 0, 0},
1703};
1704
1705static struct clk tegra_clk_m = {
1706 .name = "clk_m",
1707 .flags = ENABLE_ON_INIT,
1708 .ops = &tegra_clk_m_ops,
1709 .inputs = tegra_clk_m_sel,
1710 .reg = 0x1fc,
1711 .reg_shift = 28,
1712 .max_rate = 26000000,
1713};
1714
1715static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1716 { 12000000, 522000000, 348, 8, 1, 8},
1717 { 13000000, 522000000, 522, 13, 1, 8},
1718 { 19200000, 522000000, 435, 16, 1, 8},
1719 { 26000000, 522000000, 522, 26, 1, 8},
1720 { 12000000, 598000000, 598, 12, 1, 8},
1721 { 13000000, 598000000, 598, 13, 1, 8},
1722 { 19200000, 598000000, 375, 12, 1, 6},
1723 { 26000000, 598000000, 598, 26, 1, 8},
1724 { 0, 0, 0, 0, 0, 0 },
1725};
1726
1727static struct clk tegra_pll_c = {
1728 .name = "pll_c",
1729 .flags = PLL_HAS_CPCON,
1730 .ops = &tegra_pll_ops,
1731 .reg = 0x80,
1732 .parent = &tegra_clk_m,
1733 .max_rate = 600000000,
1734 .u.pll = {
1735 .input_min = 2000000,
1736 .input_max = 31000000,
1737 .cf_min = 1000000,
1738 .cf_max = 6000000,
1739 .vco_min = 20000000,
1740 .vco_max = 1400000000,
1741 .freq_table = tegra_pll_c_freq_table,
1742 .lock_delay = 300,
1743 },
1744};
1745
1746static struct clk tegra_pll_c_out1 = {
1747 .name = "pll_c_out1",
1748 .ops = &tegra_pll_div_ops,
1749 .flags = DIV_U71,
1750 .parent = &tegra_pll_c,
1751 .reg = 0x84,
1752 .reg_shift = 0,
1753 .max_rate = 600000000,
1754};
1755
1756static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1757 { 12000000, 666000000, 666, 12, 1, 8},
1758 { 13000000, 666000000, 666, 13, 1, 8},
1759 { 19200000, 666000000, 555, 16, 1, 8},
1760 { 26000000, 666000000, 666, 26, 1, 8},
1761 { 12000000, 600000000, 600, 12, 1, 8},
1762 { 13000000, 600000000, 600, 13, 1, 8},
1763 { 19200000, 600000000, 375, 12, 1, 6},
1764 { 26000000, 600000000, 600, 26, 1, 8},
1765 { 0, 0, 0, 0, 0, 0 },
1766};
1767
1768static struct clk tegra_pll_m = {
1769 .name = "pll_m",
1770 .flags = PLL_HAS_CPCON,
1771 .ops = &tegra_pll_ops,
1772 .reg = 0x90,
1773 .parent = &tegra_clk_m,
1774 .max_rate = 800000000,
1775 .u.pll = {
1776 .input_min = 2000000,
1777 .input_max = 31000000,
1778 .cf_min = 1000000,
1779 .cf_max = 6000000,
1780 .vco_min = 20000000,
1781 .vco_max = 1200000000,
1782 .freq_table = tegra_pll_m_freq_table,
1783 .lock_delay = 300,
1784 },
1785};
1786
1787static struct clk tegra_pll_m_out1 = {
1788 .name = "pll_m_out1",
1789 .ops = &tegra_pll_div_ops,
1790 .flags = DIV_U71,
1791 .parent = &tegra_pll_m,
1792 .reg = 0x94,
1793 .reg_shift = 0,
1794 .max_rate = 600000000,
1795};
1796
1797static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1798 { 12000000, 216000000, 432, 12, 2, 8},
1799 { 13000000, 216000000, 432, 13, 2, 8},
1800 { 19200000, 216000000, 90, 4, 2, 1},
1801 { 26000000, 216000000, 432, 26, 2, 8},
1802 { 12000000, 432000000, 432, 12, 1, 8},
1803 { 13000000, 432000000, 432, 13, 1, 8},
1804 { 19200000, 432000000, 90, 4, 1, 1},
1805 { 26000000, 432000000, 432, 26, 1, 8},
1806 { 0, 0, 0, 0, 0, 0 },
1807};
1808
1809static struct clk tegra_pll_p = {
1810 .name = "pll_p",
1811 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1812 .ops = &tegra_pll_ops,
1813 .reg = 0xa0,
1814 .parent = &tegra_clk_m,
1815 .max_rate = 432000000,
1816 .u.pll = {
1817 .input_min = 2000000,
1818 .input_max = 31000000,
1819 .cf_min = 1000000,
1820 .cf_max = 6000000,
1821 .vco_min = 20000000,
1822 .vco_max = 1400000000,
1823 .freq_table = tegra_pll_p_freq_table,
1824 .lock_delay = 300,
1825 },
1826};
1827
1828static struct clk tegra_pll_p_out1 = {
1829 .name = "pll_p_out1",
1830 .ops = &tegra_pll_div_ops,
1831 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1832 .parent = &tegra_pll_p,
1833 .reg = 0xa4,
1834 .reg_shift = 0,
1835 .max_rate = 432000000,
1836};
1837
1838static struct clk tegra_pll_p_out2 = {
1839 .name = "pll_p_out2",
1840 .ops = &tegra_pll_div_ops,
1841 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1842 .parent = &tegra_pll_p,
1843 .reg = 0xa4,
1844 .reg_shift = 16,
1845 .max_rate = 432000000,
1846};
1847
1848static struct clk tegra_pll_p_out3 = {
1849 .name = "pll_p_out3",
1850 .ops = &tegra_pll_div_ops,
1851 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1852 .parent = &tegra_pll_p,
1853 .reg = 0xa8,
1854 .reg_shift = 0,
1855 .max_rate = 432000000,
1856};
1857
1858static struct clk tegra_pll_p_out4 = {
1859 .name = "pll_p_out4",
1860 .ops = &tegra_pll_div_ops,
1861 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1862 .parent = &tegra_pll_p,
1863 .reg = 0xa8,
1864 .reg_shift = 16,
1865 .max_rate = 432000000,
1866};
1867
1868static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1869 { 28800000, 56448000, 49, 25, 1, 1},
1870 { 28800000, 73728000, 64, 25, 1, 1},
1871 { 28800000, 24000000, 5, 6, 1, 1},
1872 { 0, 0, 0, 0, 0, 0 },
1873};
1874
1875static struct clk tegra_pll_a = {
1876 .name = "pll_a",
1877 .flags = PLL_HAS_CPCON,
1878 .ops = &tegra_pll_ops,
1879 .reg = 0xb0,
1880 .parent = &tegra_pll_p_out1,
1881 .max_rate = 73728000,
1882 .u.pll = {
1883 .input_min = 2000000,
1884 .input_max = 31000000,
1885 .cf_min = 1000000,
1886 .cf_max = 6000000,
1887 .vco_min = 20000000,
1888 .vco_max = 1400000000,
1889 .freq_table = tegra_pll_a_freq_table,
1890 .lock_delay = 300,
1891 },
1892};
1893
1894static struct clk tegra_pll_a_out0 = {
1895 .name = "pll_a_out0",
1896 .ops = &tegra_pll_div_ops,
1897 .flags = DIV_U71,
1898 .parent = &tegra_pll_a,
1899 .reg = 0xb4,
1900 .reg_shift = 0,
1901 .max_rate = 73728000,
1902};
1903
1904static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1905 { 12000000, 216000000, 216, 12, 1, 4},
1906 { 13000000, 216000000, 216, 13, 1, 4},
1907 { 19200000, 216000000, 135, 12, 1, 3},
1908 { 26000000, 216000000, 216, 26, 1, 4},
1909
1910 { 12000000, 5000000, 10, 24, 1, 4},
1911 { 12000000, 10000000, 10, 12, 1, 4},
1912 { 12000000, 161500000, 323, 24, 1, 4},
1913 { 12000000, 162000000, 162, 12, 1, 4},
1914
1915 { 12000000, 594000000, 594, 12, 1, 8},
1916 { 13000000, 594000000, 594, 13, 1, 8},
1917 { 19200000, 594000000, 495, 16, 1, 8},
1918 { 26000000, 594000000, 594, 26, 1, 8},
1919
1920 { 12000000, 1000000000, 1000, 12, 1, 12},
1921 { 13000000, 1000000000, 1000, 13, 1, 12},
1922 { 19200000, 1000000000, 625, 12, 1, 8},
1923 { 26000000, 1000000000, 1000, 26, 1, 12},
1924
1925 { 12000000, 504000000, 504, 12, 1, 8},
1926 { 13000000, 504000000, 504, 13, 1, 8},
1927 { 19200000, 504000000, 420, 16, 1, 8},
1928 { 26000000, 504000000, 504, 26, 1, 8},
1929
1930 { 0, 0, 0, 0, 0, 0 },
1931};
1932
1933static struct clk tegra_pll_d = {
1934 .name = "pll_d",
1935 .flags = PLL_HAS_CPCON | PLLD,
1936 .ops = &tegra_pll_ops,
1937 .reg = 0xd0,
1938 .parent = &tegra_clk_m,
1939 .max_rate = 1000000000,
1940 .u.pll = {
1941 .input_min = 2000000,
1942 .input_max = 40000000,
1943 .cf_min = 1000000,
1944 .cf_max = 6000000,
1945 .vco_min = 40000000,
1946 .vco_max = 1000000000,
1947 .freq_table = tegra_pll_d_freq_table,
1948 .lock_delay = 1000,
1949 },
1950};
1951
1952static struct clk tegra_pll_d_out0 = {
1953 .name = "pll_d_out0",
1954 .ops = &tegra_pll_div_ops,
1955 .flags = DIV_2 | PLLD,
1956 .parent = &tegra_pll_d,
1957 .max_rate = 500000000,
1958};
1959
1960static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1961 { 12000000, 480000000, 960, 12, 2, 0},
1962 { 13000000, 480000000, 960, 13, 2, 0},
1963 { 19200000, 480000000, 200, 4, 2, 0},
1964 { 26000000, 480000000, 960, 26, 2, 0},
1965 { 0, 0, 0, 0, 0, 0 },
1966};
1967
1968static struct clk tegra_pll_u = {
1969 .name = "pll_u",
1970 .flags = PLLU,
1971 .ops = &tegra_pll_ops,
1972 .reg = 0xc0,
1973 .parent = &tegra_clk_m,
1974 .max_rate = 480000000,
1975 .u.pll = {
1976 .input_min = 2000000,
1977 .input_max = 40000000,
1978 .cf_min = 1000000,
1979 .cf_max = 6000000,
1980 .vco_min = 480000000,
1981 .vco_max = 960000000,
1982 .freq_table = tegra_pll_u_freq_table,
1983 .lock_delay = 1000,
1984 },
1985};
1986
1987static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1988 /* 1.2 GHz */
1989 { 12000000, 1200000000, 600, 6, 1, 12},
1990 { 13000000, 1200000000, 923, 10, 1, 12},
1991 { 19200000, 1200000000, 750, 12, 1, 8},
1992 { 26000000, 1200000000, 600, 13, 1, 12},
1993
1994 /* 1 GHz */
1995 { 12000000, 1000000000, 1000, 12, 1, 12},
1996 { 13000000, 1000000000, 1000, 13, 1, 12},
1997 { 19200000, 1000000000, 625, 12, 1, 8},
1998 { 26000000, 1000000000, 1000, 26, 1, 12},
1999
2000 /* 912 MHz */
2001 { 12000000, 912000000, 912, 12, 1, 12},
2002 { 13000000, 912000000, 912, 13, 1, 12},
2003 { 19200000, 912000000, 760, 16, 1, 8},
2004 { 26000000, 912000000, 912, 26, 1, 12},
2005
2006 /* 816 MHz */
2007 { 12000000, 816000000, 816, 12, 1, 12},
2008 { 13000000, 816000000, 816, 13, 1, 12},
2009 { 19200000, 816000000, 680, 16, 1, 8},
2010 { 26000000, 816000000, 816, 26, 1, 12},
2011
2012 /* 760 MHz */
2013 { 12000000, 760000000, 760, 12, 1, 12},
2014 { 13000000, 760000000, 760, 13, 1, 12},
2015 { 19200000, 760000000, 950, 24, 1, 8},
2016 { 26000000, 760000000, 760, 26, 1, 12},
2017
2018 /* 750 MHz */
2019 { 12000000, 750000000, 750, 12, 1, 12},
2020 { 13000000, 750000000, 750, 13, 1, 12},
2021 { 19200000, 750000000, 625, 16, 1, 8},
2022 { 26000000, 750000000, 750, 26, 1, 12},
2023
2024 /* 608 MHz */
2025 { 12000000, 608000000, 608, 12, 1, 12},
2026 { 13000000, 608000000, 608, 13, 1, 12},
2027 { 19200000, 608000000, 380, 12, 1, 8},
2028 { 26000000, 608000000, 608, 26, 1, 12},
2029
2030 /* 456 MHz */
2031 { 12000000, 456000000, 456, 12, 1, 12},
2032 { 13000000, 456000000, 456, 13, 1, 12},
2033 { 19200000, 456000000, 380, 16, 1, 8},
2034 { 26000000, 456000000, 456, 26, 1, 12},
2035
2036 /* 312 MHz */
2037 { 12000000, 312000000, 312, 12, 1, 12},
2038 { 13000000, 312000000, 312, 13, 1, 12},
2039 { 19200000, 312000000, 260, 16, 1, 8},
2040 { 26000000, 312000000, 312, 26, 1, 12},
2041
2042 { 0, 0, 0, 0, 0, 0 },
2043};
2044
2045static struct clk tegra_pll_x = {
2046 .name = "pll_x",
2047 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
2048 .ops = &tegra_pll_ops,
2049 .reg = 0xe0,
2050 .parent = &tegra_clk_m,
2051 .max_rate = 1000000000,
2052 .u.pll = {
2053 .input_min = 2000000,
2054 .input_max = 31000000,
2055 .cf_min = 1000000,
2056 .cf_max = 6000000,
2057 .vco_min = 20000000,
2058 .vco_max = 1200000000,
2059 .freq_table = tegra_pll_x_freq_table,
2060 .lock_delay = 300,
2061 },
2062};
2063
2064static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2065 { 12000000, 100000000, 200, 24, 1, 0 },
2066 { 0, 0, 0, 0, 0, 0 },
2067};
2068
2069static struct clk tegra_pll_e = {
2070 .name = "pll_e",
2071 .flags = PLL_ALT_MISC_REG,
2072 .ops = &tegra_plle_ops,
2073 .parent = &tegra_clk_m,
2074 .reg = 0xe8,
2075 .max_rate = 100000000,
2076 .u.pll = {
2077 .input_min = 12000000,
2078 .input_max = 12000000,
2079 .freq_table = tegra_pll_e_freq_table,
2080 },
2081};
2082
2083static struct clk tegra_clk_d = {
2084 .name = "clk_d",
2085 .flags = PERIPH_NO_RESET,
2086 .ops = &tegra_clk_double_ops,
2087 .reg = 0x34,
2088 .reg_shift = 12,
2089 .parent = &tegra_clk_m,
2090 .max_rate = 52000000,
2091 .u.periph = {
2092 .clk_num = 90,
2093 },
2094};
2095
2096/* initialized before peripheral clocks */
2097static struct clk_mux_sel mux_audio_sync_clk[8+1];
2098static const struct audio_sources {
2099 const char *name;
2100 int value;
2101} mux_audio_sync_clk_sources[] = {
2102 { .name = "spdif_in", .value = 0 },
2103 { .name = "i2s1", .value = 1 },
2104 { .name = "i2s2", .value = 2 },
2105 { .name = "pll_a_out0", .value = 4 },
2106#if 0 /* FIXME: not implemented */
2107 { .name = "ac97", .value = 3 },
2108 { .name = "ext_audio_clk2", .value = 5 },
2109 { .name = "ext_audio_clk1", .value = 6 },
2110 { .name = "ext_vimclk", .value = 7 },
2111#endif
2112 { 0, 0 }
2113};
2114
2115static struct clk tegra_clk_audio = {
2116 .name = "audio",
2117 .inputs = mux_audio_sync_clk,
2118 .reg = 0x38,
2119 .max_rate = 73728000,
2120 .ops = &tegra_audio_sync_clk_ops
2121};
2122
2123static struct clk tegra_clk_audio_2x = {
2124 .name = "audio_2x",
2125 .flags = PERIPH_NO_RESET,
2126 .max_rate = 48000000,
2127 .ops = &tegra_clk_double_ops,
2128 .reg = 0x34,
2129 .reg_shift = 8,
2130 .parent = &tegra_clk_audio,
2131 .u.periph = {
2132 .clk_num = 89,
2133 },
2134};
2135
2136struct clk_lookup tegra_audio_clk_lookups[] = {
2137 { .con_id = "audio", .clk = &tegra_clk_audio },
2138 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
2139};
2140
2141/* This is called after peripheral clocks are initialized, as the
2142 * audio_sync clock depends on some of the peripheral clocks.
2143 */
2144
2145static void init_audio_sync_clock_mux(void)
2146{
2147 int i;
2148 struct clk_mux_sel *sel = mux_audio_sync_clk;
2149 const struct audio_sources *src = mux_audio_sync_clk_sources;
2150 struct clk_lookup *lookup;
2151
2152 for (i = 0; src->name; i++, sel++, src++) {
2153 sel->input = tegra_get_clock_by_name(src->name);
2154 if (!sel->input)
2155 pr_err("%s: could not find clk %s\n", __func__,
2156 src->name);
2157 sel->value = src->value;
2158 }
2159
2160 lookup = tegra_audio_clk_lookups;
2161 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
2162 clk_init(lookup->clk);
2163 clkdev_add(lookup);
2164 }
2165}
2166
2167static struct clk_mux_sel mux_cclk[] = {
2168 { .input = &tegra_clk_m, .value = 0},
2169 { .input = &tegra_pll_c, .value = 1},
2170 { .input = &tegra_clk_32k, .value = 2},
2171 { .input = &tegra_pll_m, .value = 3},
2172 { .input = &tegra_pll_p, .value = 4},
2173 { .input = &tegra_pll_p_out4, .value = 5},
2174 { .input = &tegra_pll_p_out3, .value = 6},
2175 { .input = &tegra_clk_d, .value = 7},
2176 { .input = &tegra_pll_x, .value = 8},
2177 { 0, 0},
2178};
2179
2180static struct clk_mux_sel mux_sclk[] = {
2181 { .input = &tegra_clk_m, .value = 0},
2182 { .input = &tegra_pll_c_out1, .value = 1},
2183 { .input = &tegra_pll_p_out4, .value = 2},
2184 { .input = &tegra_pll_p_out3, .value = 3},
2185 { .input = &tegra_pll_p_out2, .value = 4},
2186 { .input = &tegra_clk_d, .value = 5},
2187 { .input = &tegra_clk_32k, .value = 6},
2188 { .input = &tegra_pll_m_out1, .value = 7},
2189 { 0, 0},
2190};
2191
2192static struct clk tegra_clk_cclk = {
2193 .name = "cclk",
2194 .inputs = mux_cclk,
2195 .reg = 0x20,
2196 .ops = &tegra_super_ops,
2197 .max_rate = 1000000000,
2198};
2199
2200static struct clk tegra_clk_sclk = {
2201 .name = "sclk",
2202 .inputs = mux_sclk,
2203 .reg = 0x28,
2204 .ops = &tegra_super_ops,
2205 .max_rate = 240000000,
2206 .min_rate = 40000000,
2207};
2208
2209static struct clk tegra_clk_virtual_cpu = {
2210 .name = "cpu",
2211 .parent = &tegra_clk_cclk,
2212 .ops = &tegra_cpu_ops,
2213 .max_rate = 1000000000,
2214 .u.cpu = {
2215 .main = &tegra_pll_x,
2216 .backup = &tegra_pll_p,
2217 },
2218};
2219
2220static struct clk tegra_clk_cop = {
2221 .name = "cop",
2222 .parent = &tegra_clk_sclk,
2223 .ops = &tegra_cop_ops,
2224 .max_rate = 240000000,
2225};
2226
2227static struct clk tegra_clk_hclk = {
2228 .name = "hclk",
2229 .flags = DIV_BUS,
2230 .parent = &tegra_clk_sclk,
2231 .reg = 0x30,
2232 .reg_shift = 4,
2233 .ops = &tegra_bus_ops,
2234 .max_rate = 240000000,
2235 .min_rate = 36000000,
2236};
2237
2238static struct clk tegra_clk_pclk = {
2239 .name = "pclk",
2240 .flags = DIV_BUS,
2241 .parent = &tegra_clk_hclk,
2242 .reg = 0x30,
2243 .reg_shift = 0,
2244 .ops = &tegra_bus_ops,
2245 .max_rate = 120000000,
2246 .min_rate = 36000000,
2247};
2248
2249static struct clk tegra_clk_virtual_sclk = {
2250 .name = "virt_sclk",
2251 .parent = &tegra_clk_sclk,
2252 .ops = &tegra_virtual_sclk_ops,
2253 .u.system = {
2254 .pclk = &tegra_clk_pclk,
2255 },
2256};
2257
2258static struct clk tegra_clk_blink = {
2259 .name = "blink",
2260 .parent = &tegra_clk_32k,
2261 .reg = 0x40,
2262 .ops = &tegra_blink_clk_ops,
2263 .max_rate = 32768,
2264};
2265static struct clk_mux_sel mux_dev1_clk[] = {
2266 { .input = &tegra_clk_m, .value = 0 },
2267 { .input = &tegra_pll_a_out0, .value = 1 },
2268 { .input = &tegra_pll_m_out1, .value = 2 },
2269 { .input = &tegra_clk_audio, .value = 3 },
2270 { 0, 0 }
2271};
2272
2273static struct clk_mux_sel mux_dev2_clk[] = {
2274 { .input = &tegra_clk_m, .value = 0 },
2275 { .input = &tegra_clk_hclk, .value = 1 },
2276 { .input = &tegra_clk_pclk, .value = 2 },
2277 { .input = &tegra_pll_p_out4, .value = 3 },
2278 { 0, 0 }
2279};
2280
2281/* dap_mclk1, belongs to the cdev1 pingroup. */
2282static struct clk tegra_clk_cdev1 = {
2283 .name = "cdev1",
2284 .ops = &tegra_cdev_clk_ops,
2285 .inputs = mux_dev1_clk,
2286 .u.periph = {
2287 .clk_num = 94,
2288 },
2289 .flags = MUX,
2290};
2291
2292/* dap_mclk2, belongs to the cdev2 pingroup. */
2293static struct clk tegra_clk_cdev2 = {
2294 .name = "cdev2",
2295 .ops = &tegra_cdev_clk_ops,
2296 .inputs = mux_dev2_clk,
2297 .u.periph = {
2298 .clk_num = 93,
2299 },
2300 .flags = MUX,
2301};
2302
2303static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2304 { .input = &tegra_pll_m, .value = 0},
2305 { .input = &tegra_pll_c, .value = 1},
2306 { .input = &tegra_pll_p, .value = 2},
2307 { .input = &tegra_pll_a_out0, .value = 3},
2308 { 0, 0},
2309};
2310
2311static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2312 { .input = &tegra_pll_m, .value = 0},
2313 { .input = &tegra_pll_c, .value = 1},
2314 { .input = &tegra_pll_p, .value = 2},
2315 { .input = &tegra_clk_m, .value = 3},
2316 { 0, 0},
2317};
2318
2319static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2320 { .input = &tegra_pll_p, .value = 0},
2321 { .input = &tegra_pll_c, .value = 1},
2322 { .input = &tegra_pll_m, .value = 2},
2323 { .input = &tegra_clk_m, .value = 3},
2324 { 0, 0},
2325};
2326
2327static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2328 {.input = &tegra_pll_a_out0, .value = 0},
2329 {.input = &tegra_clk_audio_2x, .value = 1},
2330 {.input = &tegra_pll_p, .value = 2},
2331 {.input = &tegra_clk_m, .value = 3},
2332 { 0, 0},
2333};
2334
2335static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2336 {.input = &tegra_pll_p, .value = 0},
2337 {.input = &tegra_pll_d_out0, .value = 1},
2338 {.input = &tegra_pll_c, .value = 2},
2339 {.input = &tegra_clk_m, .value = 3},
2340 { 0, 0},
2341};
2342
2343static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2344 {.input = &tegra_pll_p, .value = 0},
2345 {.input = &tegra_pll_c, .value = 1},
2346 {.input = &tegra_clk_audio, .value = 2},
2347 {.input = &tegra_clk_m, .value = 3},
2348 {.input = &tegra_clk_32k, .value = 4},
2349 { 0, 0},
2350};
2351
2352static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2353 {.input = &tegra_pll_p, .value = 0},
2354 {.input = &tegra_pll_c, .value = 1},
2355 {.input = &tegra_pll_m, .value = 2},
2356 { 0, 0},
2357};
2358
2359static struct clk_mux_sel mux_clk_m[] = {
2360 { .input = &tegra_clk_m, .value = 0},
2361 { 0, 0},
2362};
2363
2364static struct clk_mux_sel mux_pllp_out3[] = {
2365 { .input = &tegra_pll_p_out3, .value = 0},
2366 { 0, 0},
2367};
2368
2369static struct clk_mux_sel mux_plld_out0[] = {
2370 { .input = &tegra_pll_d_out0, .value = 0},
2371 { 0, 0},
2372};
2373
2374static struct clk_mux_sel mux_clk_32k[] = {
2375 { .input = &tegra_clk_32k, .value = 0},
2376 { 0, 0},
2377};
2378
2379static struct clk_mux_sel mux_pclk[] = {
2380 { .input = &tegra_clk_pclk, .value = 0},
2381 { 0, 0},
2382};
2383
2384static struct clk tegra_clk_emc = {
2385 .name = "emc",
2386 .ops = &tegra_emc_clk_ops,
2387 .reg = 0x19c,
2388 .max_rate = 800000000,
2389 .inputs = mux_pllm_pllc_pllp_clkm,
2390 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2391 .u.periph = {
2392 .clk_num = 57,
2393 },
2394};
2395
2396#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _reg_shift, _max, _inputs, _flags) \
2397 { \
2398 .name = _name, \
2399 .lookup = { \
2400 .dev_id = _dev, \
2401 .con_id = _con, \
2402 }, \
2403 .ops = &tegra_periph_clk_ops, \
2404 .reg = _reg, \
2405 .reg_shift = _reg_shift, \
2406 .inputs = _inputs, \
2407 .flags = _flags, \
2408 .max_rate = _max, \
2409 .u.periph = { \
2410 .clk_num = _clk_num, \
2411 }, \
2412 }
2413
2414#define SHARED_CLK(_name, _dev, _con, _parent) \
2415 { \
2416 .name = _name, \
2417 .lookup = { \
2418 .dev_id = _dev, \
2419 .con_id = _con, \
2420 }, \
2421 .ops = &tegra_clk_shared_bus_ops, \
2422 .parent = _parent, \
2423 }
2424
2425struct clk tegra_list_periph_clks[] = {
2426 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 0x31E, 108000000, mux_pclk, 0),
2427 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2428 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2429 PERIPH_CLK("timer", "timer", NULL, 5, 0, 0x31E, 26000000, mux_clk_m, 0),
2430 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2431 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2432 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 0x31E, 26000000, mux_clk_m, PERIPH_ON_APB),
2433 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 0x31E, 26000000, mux_clk_m, PERIPH_ON_APB),
2434 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 0x31E, 26000000, mux_clk_m, 0),
2435 PERIPH_CLK("spdif_out", "tegra20-spdif", "spdif_out", 10, 0x108, 0x31E, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2436 PERIPH_CLK("spdif_in", "tegra20-spdif", "spdif_in", 10, 0x10c, 0x31E, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2437 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 0x71C, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
2438 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 0x31E, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2439 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 0x31E, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2440 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 0x31E, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2441 PERIPH_CLK("sbc1", "spi_tegra.0", "spi", 41, 0x134, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2442 PERIPH_CLK("sbc2", "spi_tegra.1", "spi", 44, 0x118, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2443 PERIPH_CLK("sbc3", "spi_tegra.2", "spi", 46, 0x11c, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2444 PERIPH_CLK("sbc4", "spi_tegra.3", "spi", 68, 0x1b4, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2445 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 0x31E, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2446 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 0x31E, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2447 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 0x31E, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2448 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 0x31E, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2449 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 0x31E, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2450 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 0x31E, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2451 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 0x31E, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2452 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 0x31E, 250000000, mux_clk_m, 0),
2453 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 0x31E, 250000000, mux_clk_m, 0),
2454 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 0x31E, 250000000, mux_clk_m, 0),
2455 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 0x31E, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2456 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 0x31E, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2457 /* FIXME: what is la? */
2458 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2459 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2460 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2461 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 0x31E, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2462 PERIPH_CLK("i2c1", "tegra-i2c.0", "i2c-div", 12, 0x124, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2463 PERIPH_CLK("i2c2", "tegra-i2c.1", "i2c-div", 54, 0x198, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2464 PERIPH_CLK("i2c3", "tegra-i2c.2", "i2c-div", 67, 0x1b8, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2465 PERIPH_CLK("dvc", "tegra-i2c.3", "i2c-div", 47, 0x128, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2466 PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
2467 PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
2468 PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
2469 PERIPH_CLK("dvc-fast", "tegra-i2c.3", "i2c-fast", 0, 0, 0x31E, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
2470 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB),
2471 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB),
2472 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB),
2473 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB),
2474 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 0x31E, 600000000, mux_pllp_pllc_pllm_clkm, MUX | PERIPH_ON_APB),
2475 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2476 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2477 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 0x31E, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2478 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 0x31E, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2479 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2480 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2481 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 0x31E, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2482 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 0x31E, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2483 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 0x31E, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2484 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 0x31E, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2485 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 0x31E, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2486 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 0x31E, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2487 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 0x31E, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2488 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */
2489 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */
2490 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */
2491 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 0x31E, 500000000, mux_plld_out0, 0), /* scales with voltage */
2492 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 0x31E, 72000000, mux_pllp_out3, 0),
2493 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 0x31E, 150000000, mux_clk_m, 0), /* same frequency as VI */
2494 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 0x31E, 150000000, mux_clk_m, PERIPH_NO_RESET),
2495 PERIPH_CLK("pex", NULL, "pex", 70, 0, 0x31E, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2496 PERIPH_CLK("afi", NULL, "afi", 72, 0, 0x31E, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2497 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 0x31E, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2498 PERIPH_CLK("stat_mon", "tegra-stat-mon", NULL, 37, 0, 0x31E, 26000000, mux_clk_m, 0),
2499};
2500
2501struct clk tegra_list_shared_clks[] = {
2502 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_virtual_sclk),
2503 SHARED_CLK("mon.sclk", "tegra-stat-mon", "sclk", &tegra_clk_virtual_sclk),
2504 SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_virtual_sclk),
2505 SHARED_CLK("usbd.sclk", "fsl-tegra-udc", "sclk", &tegra_clk_virtual_sclk),
2506 SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_virtual_sclk),
2507 SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_virtual_sclk),
2508 SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_virtual_sclk),
2509 SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_virtual_sclk),
2510 SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_virtual_sclk),
2511 SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_virtual_sclk),
2512 SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_virtual_sclk),
2513 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2514 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2515 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2516 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2517 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2518 SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc),
2519 SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc),
2520 SHARED_CLK("mpe.emc", "tegra_mpe", "emc", &tegra_clk_emc),
2521 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2522 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2523 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2524 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2525 SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc),
2526};
2527
2528#define CLK_DUPLICATE(_name, _dev, _con) \
2529 { \
2530 .name = _name, \
2531 .lookup = { \
2532 .dev_id = _dev, \
2533 .con_id = _con, \
2534 }, \
2535 }
2536
2537/* Some clocks may be used by different drivers depending on the board
2538 * configuration. List those here to register them twice in the clock lookup
2539 * table under two names.
2540 */
2541struct clk_duplicate tegra_clk_duplicates[] = {
2542 CLK_DUPLICATE("uarta", "serial8250.0", "uarta"),
2543 CLK_DUPLICATE("uartb", "serial8250.0", "uartb"),
2544 CLK_DUPLICATE("uartc", "serial8250.0", "uartc"),
2545 CLK_DUPLICATE("uartd", "serial8250.0", "uartd"),
2546 CLK_DUPLICATE("uarte", "serial8250.0", "uarte"),
2547 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2548 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2549 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2550 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2551 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2552 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2553 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2554 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2555 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2556 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2557 CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
2558 CLK_DUPLICATE("2d", "tegra_gr2d", "gr2d"),
2559 CLK_DUPLICATE("3d", "tegra_gr3d", "gr3d"),
2560 CLK_DUPLICATE("epp", "tegra_gr2d", "epp"),
2561 CLK_DUPLICATE("mpe", "tegra_mpe", "mpe"),
2562 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2563 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2564 CLK_DUPLICATE("twd", "smp_twd", NULL),
2565 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
2566};
2567
2568#define CLK(dev, con, ck) \
2569 { \
2570 .dev_id = dev, \
2571 .con_id = con, \
2572 .clk = ck, \
2573 }
2574
2575struct clk *tegra_ptr_clks[] = {
2576 &tegra_clk_32k,
2577 &tegra_pll_s,
2578 &tegra_clk_m,
2579 &tegra_pll_m,
2580 &tegra_pll_m_out1,
2581 &tegra_pll_c,
2582 &tegra_pll_c_out1,
2583 &tegra_pll_p,
2584 &tegra_pll_p_out1,
2585 &tegra_pll_p_out2,
2586 &tegra_pll_p_out3,
2587 &tegra_pll_p_out4,
2588 &tegra_pll_a,
2589 &tegra_pll_a_out0,
2590 &tegra_pll_d,
2591 &tegra_pll_d_out0,
2592 &tegra_pll_u,
2593 &tegra_pll_x,
2594 &tegra_pll_e,
2595 &tegra_clk_cclk,
2596 &tegra_clk_sclk,
2597 &tegra_clk_hclk,
2598 &tegra_clk_pclk,
2599 &tegra_clk_d,
2600 &tegra_clk_cdev1,
2601 &tegra_clk_cdev2,
2602 &tegra_clk_virtual_cpu,
2603 &tegra_clk_virtual_sclk,
2604 &tegra_clk_blink,
2605 &tegra_clk_cop,
2606 &tegra_clk_emc,
2607 &tegra2_clk_twd,
2608};
2609
2610/* For some clocks maximum rate limits depend on tegra2 SKU */
2611#define RATE_LIMIT(_name, _max_rate, _skus...) \
2612 { \
2613 .clk_name = _name, \
2614 .max_rate = _max_rate, \
2615 .sku_ids = {_skus} \
2616 }
2617
2618static struct tegra_sku_rate_limit sku_limits[] =
2619{
2620 RATE_LIMIT("cpu", 750000000, 0x07, 0x10),
2621 RATE_LIMIT("cclk", 750000000, 0x07, 0x10),
2622 RATE_LIMIT("pll_x", 750000000, 0x07, 0x10),
2623
2624 RATE_LIMIT("cpu", 1000000000, 0x04, 0x08, 0x0F),
2625 RATE_LIMIT("cclk", 1000000000, 0x04, 0x08, 0x0F),
2626 RATE_LIMIT("pll_x", 1000000000, 0x04, 0x08, 0x0F),
2627
2628 RATE_LIMIT("cpu", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2629 RATE_LIMIT("cclk", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2630 RATE_LIMIT("pll_x", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2631
2632 RATE_LIMIT("sclk", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
2633 RATE_LIMIT("hclk", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
2634 RATE_LIMIT("vde", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
2635 RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
2636
2637 RATE_LIMIT("host1x", 108000000, 0x0F),
2638
2639 RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2640 RATE_LIMIT("virt_sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2641 RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2642 RATE_LIMIT("pclk", 150000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2643 RATE_LIMIT("vde", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2644 RATE_LIMIT("3d", 400000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2645
2646 RATE_LIMIT("uarta", 800000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2647 RATE_LIMIT("uartb", 800000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2648 RATE_LIMIT("uartc", 800000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2649 RATE_LIMIT("uartd", 800000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2650 RATE_LIMIT("uarte", 800000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
2651};
2652
2653static void tegra2_init_sku_limits(void)
2654{
2655 int i, j;
2656 struct clk *c;
2657 int sku_id = tegra_sku_id();
2658
2659 for (i = 0; i < ARRAY_SIZE(sku_limits); i++) {
2660 struct tegra_sku_rate_limit *limit = &sku_limits[i];
2661
2662 for (j = 0; (j < MAX_SAME_LIMIT_SKU_IDS) &&
2663 (limit->sku_ids[j] != 0); j++) {
2664 if (limit->sku_ids[j] == sku_id) {
2665 c = tegra_get_clock_by_name(limit->clk_name);
2666 if (!c) {
2667 pr_err("%s: Unknown sku clock %s\n",
2668 __func__, limit->clk_name);
2669 continue;
2670 }
2671 c->max_rate = limit->max_rate;
2672 }
2673 }
2674 }
2675}
2676
2677static void tegra2_init_one_clock(struct clk *c)
2678{
2679 clk_init(c);
2680 INIT_LIST_HEAD(&c->shared_bus_list);
2681 if (!c->lookup.dev_id && !c->lookup.con_id)
2682 c->lookup.con_id = c->name;
2683 c->lookup.clk = c;
2684 clkdev_add(&c->lookup);
2685}
2686
2687#ifdef CONFIG_CPU_FREQ
2688
2689/*
2690 * Frequency table index must be sequential starting at 0 and frequencies
2691 * must be ascending.
2692 */
2693
2694static struct cpufreq_frequency_table freq_table_750MHz[] = {
2695 { 0, 216000 },
2696 { 1, 312000 },
2697 { 2, 456000 },
2698 { 3, 608000 },
2699 { 4, 750000 },
2700 { 5, CPUFREQ_TABLE_END },
2701};
2702
2703static struct cpufreq_frequency_table freq_table_1p0GHz[] = {
2704 { 0, 216000 },
2705 { 1, 312000 },
2706 { 2, 456000 },
2707 { 3, 608000 },
2708 { 4, 760000 },
2709 { 5, 816000 },
2710 { 6, 912000 },
2711 { 7, 1000000 },
2712 { 8, CPUFREQ_TABLE_END },
2713};
2714
2715static struct cpufreq_frequency_table freq_table_1p2GHz[] = {
2716 { 0, 216000 },
2717 { 1, 312000 },
2718 { 2, 456000 },
2719 { 3, 608000 },
2720 { 4, 760000 },
2721 { 5, 816000 },
2722 { 6, 912000 },
2723 { 7, 1000000 },
2724 { 8, 1200000 },
2725 { 9, CPUFREQ_TABLE_END },
2726};
2727
2728static struct tegra_cpufreq_table_data cpufreq_tables[] = {
2729 { freq_table_750MHz, 1, 4 },
2730 { freq_table_1p0GHz, 2, 6 },
2731 { freq_table_1p2GHz, 2, 7 },
2732};
2733
2734struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
2735{
2736 int i, ret;
2737 struct clk *cpu_clk = tegra_get_clock_by_name("cpu");
2738
2739 for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) {
2740 struct cpufreq_policy policy;
2741 ret = cpufreq_frequency_table_cpuinfo(
2742 &policy, cpufreq_tables[i].freq_table);
2743 BUG_ON(ret);
2744 if ((policy.max * 1000) == cpu_clk->max_rate)
2745 return &cpufreq_tables[i];
2746 }
2747 pr_err("%s: No cpufreq table matching cpu range", __func__);
2748 BUG();
2749 return &cpufreq_tables[0];
2750}
2751
2752unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
2753{
2754 /* Vote on memory bus frequency based on cpu frequency */
2755 if (cpu_rate > 1000000000)
2756 return 760000000;
2757 else if (cpu_rate >= 816000)
2758 return 600000000; /* cpu 816 MHz, emc max */
2759 else if (cpu_rate >= 608000)
2760 return 300000000; /* cpu 608 MHz, emc 150Mhz */
2761 else if (cpu_rate >= 456000)
2762 return 150000000; /* cpu 456 MHz, emc 75Mhz */
2763 else if (cpu_rate >= 312000)
2764 return 100000000; /* cpu 312 MHz, emc 50Mhz */
2765 else
2766 return 50000000; /* emc 25Mhz */
2767}
2768#endif
2769
2770#ifdef CONFIG_PM_SLEEP
2771static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2772 PERIPH_CLK_SOURCE_NUM + 22];
2773
2774static int tegra_clk_suspend(void)
2775{
2776 unsigned long off, i;
2777 u32 *ctx = clk_rst_suspend;
2778
2779 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2780 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2781 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2782 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2783 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2784 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2785 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2786 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2787 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2788 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2789 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2790
2791 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2792 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2793 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2794
2795 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2796 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2797
2798 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2799 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2800 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2801
2802 *ctx++ = clk_readl(tegra_clk_audio.reg);
2803
2804 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2805 off += 4) {
2806 if (off == PERIPH_CLK_SOURCE_EMC)
2807 continue;
2808 *ctx++ = clk_readl(off);
2809 }
2810
2811 off = RST_DEVICES;
2812 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2813 *ctx++ = clk_readl(off);
2814
2815 off = CLK_OUT_ENB;
2816 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2817 *ctx++ = clk_readl(off);
2818
2819 *ctx++ = clk_readl(MISC_CLK_ENB);
2820 *ctx++ = clk_readl(CLK_MASK_ARM);
2821
2822 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2823
2824 return 0;
2825}
2826
2827static void tegra_clk_resume(void)
2828{
2829 unsigned long off, i;
2830 const u32 *ctx = clk_rst_suspend;
2831 u32 val;
2832
2833 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2834 val |= *ctx++;
2835 clk_writel(val, OSC_CTRL);
2836
2837 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2838 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2839 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2840 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2841 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2842 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2843 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2844 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2845 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2846 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2847 udelay(1000);
2848
2849 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2850 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2851 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2852
2853 clk_writel(*ctx++, tegra_clk_cclk.reg);
2854 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2855
2856 clk_writel(*ctx++, tegra_clk_sclk.reg);
2857 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2858 clk_writel(*ctx++, tegra_clk_pclk.reg);
2859
2860 clk_writel(*ctx++, tegra_clk_audio.reg);
2861
2862 /* enable all clocks before configuring clock sources */
2863 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2864 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2865 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2866 wmb();
2867
2868 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2869 off += 4) {
2870 if (off == PERIPH_CLK_SOURCE_EMC)
2871 continue;
2872 clk_writel(*ctx++, off);
2873 }
2874 wmb();
2875
2876 off = RST_DEVICES;
2877 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2878 clk_writel(*ctx++, off);
2879 wmb();
2880
2881 off = CLK_OUT_ENB;
2882 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2883 clk_writel(*ctx++, off);
2884 wmb();
2885
2886 clk_writel(*ctx++, MISC_CLK_ENB);
2887 clk_writel(*ctx++, CLK_MASK_ARM);
2888}
2889
2890#else
2891#define tegra_clk_suspend NULL
2892#define tegra_clk_resume NULL
2893#endif
2894
2895static struct syscore_ops tegra_clk_syscore_ops = {
2896 .suspend = tegra_clk_suspend,
2897 .resume = tegra_clk_resume,
2898};
2899
2900void __init tegra_soc_init_clocks(void)
2901{
2902 int i;
2903 struct clk *c;
2904
2905 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2906 tegra2_init_one_clock(tegra_ptr_clks[i]);
2907
2908 for (i = 0; i < ARRAY_SIZE(tegra_list_periph_clks); i++)
2909 tegra2_init_one_clock(&tegra_list_periph_clks[i]);
2910
2911 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2912 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2913 if (!c) {
2914 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2915 tegra_clk_duplicates[i].name);
2916 continue;
2917 }
2918
2919 tegra_clk_duplicates[i].lookup.clk = c;
2920 clkdev_add(&tegra_clk_duplicates[i].lookup);
2921 }
2922
2923 init_audio_sync_clock_mux();
2924 tegra2_init_sku_limits();
2925
2926 for (i = 0; i < ARRAY_SIZE(tegra_list_shared_clks); i++)
2927 tegra2_init_one_clock(&tegra_list_shared_clks[i]);
2928
2929 register_syscore_ops(&tegra_clk_syscore_ops);
2930}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-16 05:11:07 -0400