diff options
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/irqs.h')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/irqs.h | 391 |
1 files changed, 391 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h new file mode 100644 index 00000000000..bf1b12559be --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/irqs.h | |||
| @@ -0,0 +1,391 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-tegra/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Google, Inc. | ||
| 5 | * Copyright (C) 2011 NVIDIA Corporation. | ||
| 6 | * | ||
| 7 | * Author: | ||
| 8 | * Colin Cross <ccross@google.com> | ||
| 9 | * Erik Gilling <konkers@google.com> | ||
| 10 | * | ||
| 11 | * This software is licensed under the terms of the GNU General Public | ||
| 12 | * License version 2, as published by the Free Software Foundation, and | ||
| 13 | * may be copied, distributed, and modified under those terms. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __MACH_TEGRA_IRQS_H | ||
| 23 | #define __MACH_TEGRA_IRQS_H | ||
| 24 | |||
| 25 | #define INT_GIC_BASE 0 | ||
| 26 | |||
| 27 | #define IRQ_LOCALTIMER 29 | ||
| 28 | |||
| 29 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
| 30 | /* Primary Interrupt Controller */ | ||
| 31 | #define INT_PRI_BASE (INT_GIC_BASE + 32) | ||
| 32 | #define INT_TMR1 (INT_PRI_BASE + 0) | ||
| 33 | #define INT_TMR2 (INT_PRI_BASE + 1) | ||
| 34 | #define INT_RTC (INT_PRI_BASE + 2) | ||
| 35 | #define INT_I2S2 (INT_PRI_BASE + 3) | ||
| 36 | #define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) | ||
| 37 | #define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) | ||
| 38 | #define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) | ||
| 39 | #define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) | ||
| 40 | #define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) | ||
| 41 | #define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) | ||
| 42 | #define INT_VDE_BSE_V (INT_PRI_BASE + 10) | ||
| 43 | #define INT_VDE_BSE_A (INT_PRI_BASE + 11) | ||
| 44 | #define INT_VDE_SXE (INT_PRI_BASE + 12) | ||
| 45 | #define INT_I2S1 (INT_PRI_BASE + 13) | ||
| 46 | #define INT_SDMMC1 (INT_PRI_BASE + 14) | ||
| 47 | #define INT_SDMMC2 (INT_PRI_BASE + 15) | ||
| 48 | #define INT_XIO (INT_PRI_BASE + 16) | ||
| 49 | #define INT_VDE (INT_PRI_BASE + 17) | ||
| 50 | #define INT_AVP_UCQ (INT_PRI_BASE + 18) | ||
| 51 | #define INT_SDMMC3 (INT_PRI_BASE + 19) | ||
| 52 | #define INT_USB (INT_PRI_BASE + 20) | ||
| 53 | #define INT_USB2 (INT_PRI_BASE + 21) | ||
| 54 | #define INT_PRI_RES_22 (INT_PRI_BASE + 22) | ||
| 55 | #define INT_EIDE (INT_PRI_BASE + 23) | ||
| 56 | #define INT_NANDFLASH (INT_PRI_BASE + 24) | ||
| 57 | #define INT_VCP (INT_PRI_BASE + 25) | ||
| 58 | #define INT_APB_DMA (INT_PRI_BASE + 26) | ||
| 59 | #define INT_AHB_DMA (INT_PRI_BASE + 27) | ||
| 60 | #define INT_GNT_0 (INT_PRI_BASE + 28) | ||
| 61 | #define INT_GNT_1 (INT_PRI_BASE + 29) | ||
| 62 | #define INT_OWR (INT_PRI_BASE + 30) | ||
| 63 | #define INT_SDMMC4 (INT_PRI_BASE + 31) | ||
| 64 | |||
| 65 | /* Secondary Interrupt Controller */ | ||
| 66 | #define INT_SEC_BASE (INT_PRI_BASE + 32) | ||
| 67 | #define INT_GPIO1 (INT_SEC_BASE + 0) | ||
| 68 | #define INT_GPIO2 (INT_SEC_BASE + 1) | ||
| 69 | #define INT_GPIO3 (INT_SEC_BASE + 2) | ||
| 70 | #define INT_GPIO4 (INT_SEC_BASE + 3) | ||
| 71 | #define INT_UARTA (INT_SEC_BASE + 4) | ||
| 72 | #define INT_UARTB (INT_SEC_BASE + 5) | ||
| 73 | #define INT_I2C (INT_SEC_BASE + 6) | ||
| 74 | #define INT_SPI (INT_SEC_BASE + 7) | ||
| 75 | #define INT_TWC (INT_SEC_BASE + 8) | ||
| 76 | #define INT_TMR3 (INT_SEC_BASE + 9) | ||
| 77 | #define INT_TMR4 (INT_SEC_BASE + 10) | ||
| 78 | #define INT_FLOW_RSM0 (INT_SEC_BASE + 11) | ||
| 79 | #define INT_FLOW_RSM1 (INT_SEC_BASE + 12) | ||
| 80 | #define INT_SPDIF (INT_SEC_BASE + 13) | ||
| 81 | #define INT_UARTC (INT_SEC_BASE + 14) | ||
| 82 | #define INT_MIPI (INT_SEC_BASE + 15) | ||
| 83 | #define INT_EVENTA (INT_SEC_BASE + 16) | ||
| 84 | #define INT_EVENTB (INT_SEC_BASE + 17) | ||
| 85 | #define INT_EVENTC (INT_SEC_BASE + 18) | ||
| 86 | #define INT_EVENTD (INT_SEC_BASE + 19) | ||
| 87 | #define INT_VFIR (INT_SEC_BASE + 20) | ||
| 88 | #define INT_DVC (INT_SEC_BASE + 21) | ||
| 89 | #define INT_SYS_STATS_MON (INT_SEC_BASE + 22) | ||
| 90 | #define INT_GPIO5 (INT_SEC_BASE + 23) | ||
| 91 | #define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) | ||
| 92 | #define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25) | ||
| 93 | #define INT_SEC_RES_26 (INT_SEC_BASE + 26) | ||
| 94 | #define INT_SPI_1 (INT_SEC_BASE + 27) | ||
| 95 | #define INT_APB_DMA_COP (INT_SEC_BASE + 28) | ||
| 96 | #define INT_AHB_DMA_COP (INT_SEC_BASE + 29) | ||
| 97 | #define INT_DMA_TX (INT_SEC_BASE + 30) | ||
| 98 | #define INT_DMA_RX (INT_SEC_BASE + 31) | ||
| 99 | |||
| 100 | /* Tertiary Interrupt Controller */ | ||
| 101 | #define INT_TRI_BASE (INT_SEC_BASE + 32) | ||
| 102 | #define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) | ||
| 103 | #define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) | ||
| 104 | #define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) | ||
| 105 | #define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) | ||
| 106 | #define INT_MPE_GENERAL (INT_TRI_BASE + 4) | ||
| 107 | #define INT_VI_GENERAL (INT_TRI_BASE + 5) | ||
| 108 | #define INT_EPP_GENERAL (INT_TRI_BASE + 6) | ||
| 109 | #define INT_ISP_GENERAL (INT_TRI_BASE + 7) | ||
| 110 | #define INT_2D_GENERAL (INT_TRI_BASE + 8) | ||
| 111 | #define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) | ||
| 112 | #define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) | ||
| 113 | #define INT_HDMI (INT_TRI_BASE + 11) | ||
| 114 | #define INT_TVO_GENERAL (INT_TRI_BASE + 12) | ||
| 115 | #define INT_MC_GENERAL (INT_TRI_BASE + 13) | ||
| 116 | #define INT_EMC_GENERAL (INT_TRI_BASE + 14) | ||
| 117 | #define INT_TRI_RES_15 (INT_TRI_BASE + 15) | ||
| 118 | #define INT_TRI_RES_16 (INT_TRI_BASE + 16) | ||
| 119 | #define INT_AC97 (INT_TRI_BASE + 17) | ||
| 120 | #define INT_SPI_2 (INT_TRI_BASE + 18) | ||
| 121 | #define INT_SPI_3 (INT_TRI_BASE + 19) | ||
| 122 | #define INT_I2C2 (INT_TRI_BASE + 20) | ||
| 123 | #define INT_KBC (INT_TRI_BASE + 21) | ||
| 124 | #define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) | ||
| 125 | #define INT_GPIO6 (INT_TRI_BASE + 23) | ||
| 126 | #define INT_TVDAC (INT_TRI_BASE + 24) | ||
| 127 | #define INT_GPIO7 (INT_TRI_BASE + 25) | ||
| 128 | #define INT_UARTD (INT_TRI_BASE + 26) | ||
| 129 | #define INT_UARTE (INT_TRI_BASE + 27) | ||
| 130 | #define INT_I2C3 (INT_TRI_BASE + 28) | ||
| 131 | #define INT_SPI_4 (INT_TRI_BASE + 29) | ||
| 132 | #define INT_TRI_RES_30 (INT_TRI_BASE + 30) | ||
| 133 | #define INT_SW_RESERVED (INT_TRI_BASE + 31) | ||
| 134 | |||
| 135 | /* Quaternary Interrupt Controller */ | ||
| 136 | #define INT_QUAD_BASE (INT_TRI_BASE + 32) | ||
| 137 | #define INT_SNOR (INT_QUAD_BASE + 0) | ||
| 138 | #define INT_USB3 (INT_QUAD_BASE + 1) | ||
| 139 | #define INT_PCIE_INTR (INT_QUAD_BASE + 2) | ||
| 140 | #define INT_PCIE_MSI (INT_QUAD_BASE + 3) | ||
| 141 | #define INT_QUAD_RES_4 (INT_QUAD_BASE + 4) | ||
| 142 | #define INT_QUAD_RES_5 (INT_QUAD_BASE + 5) | ||
| 143 | #define INT_QUAD_RES_6 (INT_QUAD_BASE + 6) | ||
| 144 | #define INT_QUAD_RES_7 (INT_QUAD_BASE + 7) | ||
| 145 | #define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) | ||
| 146 | #define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) | ||
| 147 | #define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) | ||
| 148 | #define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) | ||
| 149 | #define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) | ||
| 150 | #define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) | ||
| 151 | #define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) | ||
| 152 | #define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) | ||
| 153 | #define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) | ||
| 154 | #define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) | ||
| 155 | #define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) | ||
| 156 | #define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) | ||
| 157 | #define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) | ||
| 158 | #define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) | ||
| 159 | #define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) | ||
| 160 | #define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) | ||
| 161 | #define INT_QUAD_RES_24 (INT_QUAD_BASE + 24) | ||
| 162 | #define INT_QUAD_RES_25 (INT_QUAD_BASE + 25) | ||
| 163 | #define INT_QUAD_RES_26 (INT_QUAD_BASE + 26) | ||
| 164 | #define INT_QUAD_RES_27 (INT_QUAD_BASE + 27) | ||
| 165 | #define INT_QUAD_RES_28 (INT_QUAD_BASE + 28) | ||
| 166 | #define INT_QUAD_RES_29 (INT_QUAD_BASE + 29) | ||
| 167 | #define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) | ||
| 168 | #define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) | ||
| 169 | |||
| 170 | #define INT_GIC_NR (INT_QUAD_BASE + 32) | ||
| 171 | |||
| 172 | #define INT_MAIN_NR (INT_GIC_NR - INT_PRI_BASE) | ||
| 173 | |||
| 174 | #define INT_SYNCPT_THRESH_BASE (INT_QUAD_BASE + 32) | ||
| 175 | #define INT_SYNCPT_THRESH_NR 32 | ||
| 176 | |||
| 177 | #define INT_GPIO_BASE (INT_SYNCPT_THRESH_BASE + \ | ||
| 178 | INT_SYNCPT_THRESH_NR) | ||
| 179 | #define INT_GPIO_NR (28 * 8) | ||
| 180 | |||
| 181 | #define INT_PCI_MSI_BASE (INT_GPIO_BASE + \ | ||
| 182 | INT_GPIO_NR) | ||
| 183 | #define INT_PCI_MSI_NR (0) | ||
| 184 | |||
| 185 | #elif defined(CONFIG_ARCH_TEGRA_3x_SOC) | ||
| 186 | |||
| 187 | /* Primary Interrupt Controller */ | ||
| 188 | #define INT_PRI_BASE (INT_GIC_BASE + 32) | ||
| 189 | #define INT_TMR1 (INT_PRI_BASE + 0) | ||
| 190 | #define INT_TMR2 (INT_PRI_BASE + 1) | ||
| 191 | #define INT_RTC (INT_PRI_BASE + 2) | ||
| 192 | #define INT_CEC (INT_PRI_BASE + 3) | ||
| 193 | #define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) | ||
| 194 | #define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) | ||
| 195 | #define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) | ||
| 196 | #define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) | ||
| 197 | #define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) | ||
| 198 | #define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) | ||
| 199 | #define INT_VDE_BSE_V (INT_PRI_BASE + 10) | ||
| 200 | #define INT_VDE_BSE_A (INT_PRI_BASE + 11) | ||
| 201 | #define INT_VDE_SXE (INT_PRI_BASE + 12) | ||
| 202 | #define INT_SATA_RX_STAT (INT_PRI_BASE + 13) | ||
| 203 | #define INT_SDMMC1 (INT_PRI_BASE + 14) | ||
| 204 | #define INT_SDMMC2 (INT_PRI_BASE + 15) | ||
| 205 | #define INT_XIO (INT_PRI_BASE + 16) | ||
| 206 | #define INT_VDE (INT_PRI_BASE + 17) | ||
| 207 | #define INT_AVP_UCQ (INT_PRI_BASE + 18) | ||
| 208 | #define INT_SDMMC3 (INT_PRI_BASE + 19) | ||
| 209 | #define INT_USB (INT_PRI_BASE + 20) | ||
| 210 | #define INT_USB2 (INT_PRI_BASE + 21) | ||
| 211 | #define INT_HSMMC (INT_PRI_BASE + 22) | ||
| 212 | #define INT_SATA_CTL (INT_PRI_BASE + 23) | ||
| 213 | #define INT_NANDFLASH (INT_PRI_BASE + 24) | ||
| 214 | #define INT_VCP (INT_PRI_BASE + 25) | ||
| 215 | #define INT_APB_DMA (INT_PRI_BASE + 26) | ||
| 216 | #define INT_AHB_DMA (INT_PRI_BASE + 27) | ||
| 217 | #define INT_GNT_0 (INT_PRI_BASE + 28) | ||
| 218 | #define INT_GNT_1 (INT_PRI_BASE + 29) | ||
| 219 | #define INT_OWR (INT_PRI_BASE + 30) | ||
| 220 | #define INT_SDMMC4 (INT_PRI_BASE + 31) | ||
| 221 | |||
| 222 | /* Secondary Interrupt Controller */ | ||
| 223 | #define INT_SEC_BASE (INT_PRI_BASE + 32) | ||
| 224 | #define INT_GPIO1 (INT_SEC_BASE + 0) | ||
| 225 | #define INT_GPIO2 (INT_SEC_BASE + 1) | ||
| 226 | #define INT_GPIO3 (INT_SEC_BASE + 2) | ||
| 227 | #define INT_GPIO4 (INT_SEC_BASE + 3) | ||
| 228 | #define INT_UARTA (INT_SEC_BASE + 4) | ||
| 229 | #define INT_UARTB (INT_SEC_BASE + 5) | ||
| 230 | #define INT_I2C (INT_SEC_BASE + 6) | ||
| 231 | #define INT_SPI (INT_SEC_BASE + 7) | ||
| 232 | #define INT_DTV INT_SPI | ||
| 233 | #define INT_TWC (INT_SEC_BASE + 8) | ||
| 234 | #define INT_TMR3 (INT_SEC_BASE + 9) | ||
| 235 | #define INT_TMR4 (INT_SEC_BASE + 10) | ||
| 236 | #define INT_FLOW_RSM0 (INT_SEC_BASE + 11) | ||
| 237 | #define INT_FLOW_RSM1 (INT_SEC_BASE + 12) | ||
| 238 | #define INT_ACTMON (INT_SEC_BASE + 13) | ||
| 239 | #define INT_UARTC (INT_SEC_BASE + 14) | ||
| 240 | #define INT_MIPI (INT_SEC_BASE + 15) | ||
| 241 | #define INT_EVENTA (INT_SEC_BASE + 16) | ||
| 242 | #define INT_EVENTB (INT_SEC_BASE + 17) | ||
| 243 | #define INT_EVENTC (INT_SEC_BASE + 18) | ||
| 244 | #define INT_EVENTD (INT_SEC_BASE + 19) | ||
| 245 | #define INT_VFIR (INT_SEC_BASE + 20) | ||
| 246 | #define INT_I2C5 (INT_SEC_BASE + 21) | ||
| 247 | #define INT_SYS_STATS_MON (INT_SEC_BASE + 22) | ||
| 248 | #define INT_GPIO5 (INT_SEC_BASE + 23) | ||
| 249 | #define INT_SPEEDO_PMON_0 (INT_SEC_BASE + 24) | ||
| 250 | #define INT_SPEEDO_PMON_1 (INT_SEC_BASE + 25) | ||
| 251 | #define INT_SE (INT_SEC_BASE + 26) | ||
| 252 | #define INT_SPI_1 (INT_SEC_BASE + 27) | ||
| 253 | #define INT_APB_DMA_COP (INT_SEC_BASE + 28) | ||
| 254 | #define INT_AHB_DMA_COP (INT_SEC_BASE + 29) | ||
| 255 | #define INT_DMA_TX (INT_SEC_BASE + 30) | ||
| 256 | #define INT_DMA_RX (INT_SEC_BASE + 31) | ||
| 257 | |||
| 258 | /* Tertiary Interrupt Controller */ | ||
| 259 | #define INT_TRI_BASE (INT_SEC_BASE + 32) | ||
| 260 | #define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) | ||
| 261 | #define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) | ||
| 262 | #define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) | ||
| 263 | #define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) | ||
| 264 | #define INT_MPE_GENERAL (INT_TRI_BASE + 4) | ||
| 265 | #define INT_VI_GENERAL (INT_TRI_BASE + 5) | ||
| 266 | #define INT_EPP_GENERAL (INT_TRI_BASE + 6) | ||
| 267 | #define INT_ISP_GENERAL (INT_TRI_BASE + 7) | ||
| 268 | #define INT_2D_GENERAL (INT_TRI_BASE + 8) | ||
| 269 | #define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) | ||
| 270 | #define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) | ||
| 271 | #define INT_HDMI (INT_TRI_BASE + 11) | ||
| 272 | #define INT_TVO_GENERAL (INT_TRI_BASE + 12) | ||
| 273 | #define INT_MC_GENERAL (INT_TRI_BASE + 13) | ||
| 274 | #define INT_EMC_GENERAL (INT_TRI_BASE + 14) | ||
| 275 | #define INT_SPI_6 (INT_SEC_BASE + 15) | ||
| 276 | #define INT_NOR_FLASH (INT_TRI_BASE + 16) | ||
| 277 | #define INT_HDA (INT_TRI_BASE + 17) | ||
| 278 | #define INT_SPI_2 (INT_TRI_BASE + 18) | ||
| 279 | #define INT_SPI_3 (INT_TRI_BASE + 19) | ||
| 280 | #define INT_I2C2 (INT_TRI_BASE + 20) | ||
| 281 | #define INT_KBC (INT_TRI_BASE + 21) | ||
| 282 | #define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) | ||
| 283 | #define INT_GPIO6 (INT_TRI_BASE + 23) | ||
| 284 | #define INT_TVDAC (INT_TRI_BASE + 24) | ||
| 285 | #define INT_GPIO7 (INT_TRI_BASE + 25) | ||
| 286 | #define INT_UARTD (INT_TRI_BASE + 26) | ||
| 287 | #define INT_UARTE (INT_TRI_BASE + 27) | ||
| 288 | #define INT_I2C3 (INT_TRI_BASE + 28) | ||
| 289 | #define INT_SPI_4 (INT_TRI_BASE + 29) | ||
| 290 | #define INT_SPI_5 (INT_TRI_BASE + 30) | ||
| 291 | #define INT_SW_RESERVED (INT_TRI_BASE + 31) | ||
| 292 | |||
| 293 | /* Quaternary Interrupt Controller */ | ||
| 294 | #define INT_QUAD_BASE (INT_TRI_BASE + 32) | ||
| 295 | #define INT_SNOR (INT_QUAD_BASE + 0) | ||
| 296 | #define INT_USB3 (INT_QUAD_BASE + 1) | ||
| 297 | #define INT_PCIE_INTR (INT_QUAD_BASE + 2) | ||
| 298 | #define INT_PCIE_MSI (INT_QUAD_BASE + 3) | ||
| 299 | #define INT_PCIE (INT_QUAD_BASE + 4) | ||
| 300 | #define INT_AVP_CACHE (INT_QUAD_BASE + 5) | ||
| 301 | #define INT_TSENSOR (INT_QUAD_BASE + 6) | ||
| 302 | #define INT_AUDIO_CLUSTER (INT_QUAD_BASE + 7) | ||
| 303 | #define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) | ||
| 304 | #define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) | ||
| 305 | #define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) | ||
| 306 | #define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) | ||
| 307 | #define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) | ||
| 308 | #define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) | ||
| 309 | #define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) | ||
| 310 | #define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) | ||
| 311 | #define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) | ||
| 312 | #define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) | ||
| 313 | #define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) | ||
| 314 | #define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) | ||
| 315 | #define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) | ||
| 316 | #define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) | ||
| 317 | #define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) | ||
| 318 | #define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) | ||
| 319 | #define INT_I2C4 (INT_QUAD_BASE + 24) | ||
| 320 | #define INT_TMR5 (INT_QUAD_BASE + 25) | ||
| 321 | #define INT_TMR_SHARED (INT_QUAD_BASE + 26) /* Deprecated */ | ||
| 322 | #define INT_WDT_CPU (INT_QUAD_BASE + 27) | ||
| 323 | #define INT_WDT_AVP (INT_QUAD_BASE + 28) | ||
| 324 | #define INT_GPIO8 (INT_QUAD_BASE + 29) | ||
| 325 | #define INT_CAR (INT_QUAD_BASE + 30) | ||
| 326 | #define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) | ||
| 327 | |||
| 328 | /* Quintary Interrupt Controller */ | ||
| 329 | #define INT_QUINT_BASE (INT_QUAD_BASE + 32) | ||
| 330 | #define INT_APB_DMA_CH16 (INT_QUINT_BASE + 0) | ||
| 331 | #define INT_APB_DMA_CH17 (INT_QUINT_BASE + 1) | ||
| 332 | #define INT_APB_DMA_CH18 (INT_QUINT_BASE + 2) | ||
| 333 | #define INT_APB_DMA_CH19 (INT_QUINT_BASE + 3) | ||
| 334 | #define INT_APB_DMA_CH20 (INT_QUINT_BASE + 4) | ||
| 335 | #define INT_APB_DMA_CH21 (INT_QUINT_BASE + 5) | ||
| 336 | #define INT_APB_DMA_CH22 (INT_QUINT_BASE + 6) | ||
| 337 | #define INT_APB_DMA_CH23 (INT_QUINT_BASE + 7) | ||
| 338 | #define INT_APB_DMA_CH24 (INT_QUINT_BASE + 8) | ||
| 339 | #define INT_APB_DMA_CH25 (INT_QUINT_BASE + 9) | ||
| 340 | #define INT_APB_DMA_CH26 (INT_QUINT_BASE + 10) | ||
| 341 | #define INT_APB_DMA_CH27 (INT_QUINT_BASE + 11) | ||
| 342 | #define INT_APB_DMA_CH28 (INT_QUINT_BASE + 12) | ||
| 343 | #define INT_APB_DMA_CH29 (INT_QUINT_BASE + 13) | ||
| 344 | #define INT_APB_DMA_CH30 (INT_QUINT_BASE + 14) | ||
| 345 | #define INT_APB_DMA_CH31 (INT_QUINT_BASE + 15) | ||
| 346 | #define INT_CPU0_PMU_INTR (INT_QUINT_BASE + 16) | ||
| 347 | #define INT_CPU1_PMU_INTR (INT_QUINT_BASE + 17) | ||
| 348 | #define INT_CPU2_PMU_INTR (INT_QUINT_BASE + 18) | ||
| 349 | #define INT_CPU3_PMU_INTR (INT_QUINT_BASE + 19) | ||
| 350 | #define INT_CPU4_PMU_INTR (INT_QUINT_BASE + 20) | ||
| 351 | #define INT_CPU5_PMU_INTR (INT_QUINT_BASE + 21) | ||
| 352 | #define INT_CPU6_PMU_INTR (INT_QUINT_BASE + 22) | ||
| 353 | #define INT_CPU7_PMU_INTR (INT_QUINT_BASE + 23) | ||
| 354 | #define INT_TMR6 (INT_QUINT_BASE + 24) | ||
| 355 | #define INT_TMR7 (INT_QUINT_BASE + 25) | ||
| 356 | #define INT_TMR8 (INT_QUINT_BASE + 26) | ||
| 357 | #define INT_TMR9 (INT_QUINT_BASE + 27) | ||
| 358 | #define INT_TMR10 (INT_QUINT_BASE + 28) | ||
| 359 | #define INT_QUINT_RES_29 (INT_QUINT_BASE + 29) | ||
| 360 | #define INT_QUINT_RES_30 (INT_QUINT_BASE + 30) | ||
| 361 | #define INT_QUINT_RES_31 (INT_QUINT_BASE + 31) | ||
| 362 | |||
| 363 | #define INT_GIC_NR (INT_QUINT_BASE + 32) | ||
| 364 | |||
| 365 | #define INT_MAIN_NR (INT_GIC_NR - INT_PRI_BASE) | ||
| 366 | |||
| 367 | #define INT_SYNCPT_THRESH_BASE (INT_QUINT_BASE + 32) | ||
| 368 | #define INT_SYNCPT_THRESH_NR 32 | ||
| 369 | |||
| 370 | #define INT_GPIO_BASE (INT_SYNCPT_THRESH_BASE + \ | ||
| 371 | INT_SYNCPT_THRESH_NR) | ||
| 372 | #define INT_GPIO_NR (32 * 8) | ||
| 373 | |||
| 374 | #define INT_PCI_MSI_BASE (INT_GPIO_BASE + \ | ||
| 375 | INT_GPIO_NR) | ||
| 376 | #define INT_PCI_MSI_NR (32 * 8) | ||
| 377 | |||
| 378 | #endif | ||
| 379 | |||
| 380 | #define FIQ_START INT_GIC_BASE | ||
| 381 | |||
| 382 | #define TEGRA_NR_IRQS (INT_PCI_MSI_BASE + \ | ||
| 383 | INT_PCI_MSI_NR) | ||
| 384 | |||
| 385 | #define INT_BOARD_BASE TEGRA_NR_IRQS | ||
| 386 | |||
| 387 | #define NR_BOARD_IRQS 64 | ||
| 388 | |||
| 389 | #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) | ||
| 390 | |||
| 391 | #endif | ||