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-rw-r--r--arch/arm/mach-tegra/fiq.c99
1 files changed, 99 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/fiq.c b/arch/arm/mach-tegra/fiq.c
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1/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Brian Swetland <swetland@google.com>
6 * Iliyan Malchev <malchev@google.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25
26#include <asm/hardware/gic.h>
27
28#include <mach/iomap.h>
29#include <mach/fiq.h>
30
31#include "board.h"
32
33#define ICTLR_CPU_IER 0x20
34#define ICTLR_CPU_IER_SET 0x24
35#define ICTLR_CPU_IER_CLR 0x28
36#define ICTLR_CPU_IEP_CLASS 0x2C
37
38#define FIRST_LEGACY_IRQ 32
39
40static void __iomem *ictlr_reg_base[] = {
41 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
42 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
43 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
44 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
45};
46
47static void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
48{
49 void __iomem *base;
50 pr_debug("%s: %d\n", __func__, irq);
51
52 irq -= FIRST_LEGACY_IRQ;
53 base = ictlr_reg_base[irq>>5];
54 writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
55}
56
57static void tegra_fiq_mask(struct irq_data *d)
58{
59 void __iomem *base;
60 int leg_irq;
61
62 if (d->irq < FIRST_LEGACY_IRQ)
63 return;
64
65 leg_irq = d->irq - FIRST_LEGACY_IRQ;
66 base = ictlr_reg_base[leg_irq >> 5];
67 writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_CLR);
68}
69
70static void tegra_fiq_unmask(struct irq_data *d)
71{
72 void __iomem *base;
73 int leg_irq;
74
75 if (d->irq < FIRST_LEGACY_IRQ)
76 return;
77
78 leg_irq = d->irq - FIRST_LEGACY_IRQ;
79 base = ictlr_reg_base[leg_irq >> 5];
80 writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_SET);
81}
82
83void tegra_fiq_enable(int irq)
84{
85 void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100);
86 /* enable FIQ */
87 u32 val = readl(base + GIC_CPU_CTRL);
88 val &= ~8; /* pass FIQs through */
89 val |= 2; /* enableNS */
90 writel(val, base + GIC_CPU_CTRL);
91 tegra_legacy_select_fiq(irq, true);
92 tegra_fiq_unmask(irq_get_irq_data(irq));
93}
94
95void tegra_fiq_disable(int irq)
96{
97 tegra_fiq_mask(irq_get_irq_data(irq));
98 tegra_legacy_select_fiq(irq, false);
99}