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Diffstat (limited to 'arch/arm/mach-tegra/board-whistler-memory.c')
-rw-r--r--arch/arm/mach-tegra/board-whistler-memory.c632
1 files changed, 632 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-whistler-memory.c b/arch/arm/mach-tegra/board-whistler-memory.c
new file mode 100644
index 00000000000..8dd4c8fe225
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-memory.c
@@ -0,0 +1,632 @@
1/*
2 * Copyright (C) 2011 NVIDIA, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16 * 02111-1307, USA
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21
22#include "board-whistler.h"
23#include "tegra2_emc.h"
24#include "board.h"
25#include "fuse.h"
26
27static const struct tegra_emc_table whistler_emc_tables_elpida_300Mhz[] = {
28 {
29 .rate = 25000, /* SDRAM frquency */
30 .regs = {
31 0x00000002, /* RC */
32 0x00000006, /* RFC */
33 0x00000003, /* RAS */
34 0x00000003, /* RP */
35 0x00000006, /* R2W */
36 0x00000004, /* W2R */
37 0x00000002, /* R2P */
38 0x00000009, /* W2P */
39 0x00000003, /* RD_RCD */
40 0x00000003, /* WR_RCD */
41 0x00000002, /* RRD */
42 0x00000002, /* REXT */
43 0x00000002, /* WDV */
44 0x00000004, /* QUSE */
45 0x00000003, /* QRST */
46 0x00000008, /* QSAFE */
47 0x0000000b, /* RDV */
48 0x0000004d, /* REFRESH */
49 0x00000000, /* BURST_REFRESH_NUM */
50 0x00000003, /* PDEX2WR */
51 0x00000003, /* PDEX2RD */
52 0x00000003, /* PCHG2PDEN */
53 0x00000008, /* ACT2PDEN */
54 0x00000001, /* AR2PDEN */
55 0x0000000a, /* RW2PDEN */
56 0x00000004, /* TXSR */
57 0x00000003, /* TCKE */
58 0x00000008, /* TFAW */
59 0x00000004, /* TRPAB */
60 0x00000006, /* TCLKSTABLE */
61 0x00000002, /* TCLKSTOP */
62 0x00000068, /* TREFBW */
63 0x00000000, /* QUSE_EXTRA */
64 0x00000003, /* FBIO_CFG6 */
65 0x00000000, /* ODT_WRITE */
66 0x00000000, /* ODT_READ */
67 0x00000282, /* FBIO_CFG5 */
68 0xa06a04ae, /* CFG_DIG_DLL */
69 0x0001f000, /* DLL_XFORM_DQS */
70 0x00000000, /* DLL_XFORM_QUSE */
71 0x00000000, /* ZCAL_REF_CNT */
72 0x00000003, /* ZCAL_WAIT_CNT */
73 0x00000000, /* AUTO_CAL_INTERVAL */
74 0x00000000, /* CFG_CLKTRIM_0 */
75 0x00000000, /* CFG_CLKTRIM_1 */
76 0x00000000, /* CFG_CLKTRIM_2 */
77 }
78 },
79 {
80 .rate = 50000, /* SDRAM frequency */
81 .regs = {
82 0x00000003, /* RC */
83 0x00000007, /* RFC */
84 0x00000003, /* RAS */
85 0x00000003, /* RP */
86 0x00000006, /* R2W */
87 0x00000004, /* W2R */
88 0x00000002, /* R2P */
89 0x00000009, /* W2P */
90 0x00000003, /* RD_RCD */
91 0x00000003, /* WR_RCD */
92 0x00000002, /* RRD */
93 0x00000002, /* REXT */
94 0x00000002, /* WDV */
95 0x00000005, /* QUSE */
96 0x00000003, /* QRST */
97 0x00000008, /* QSAFE */
98 0x0000000b, /* RDV */
99 0x0000009f, /* REFRESH */
100 0x00000000, /* BURST_REFRESH_NUM */
101 0x00000003, /* PDEX2WR */
102 0x00000003, /* PDEX2RD */
103 0x00000003, /* PCHG2PDEN */
104 0x00000008, /* ACT2PDEN */
105 0x00000001, /* AR2PDEN */
106 0x0000000a, /* RW2PDEN */
107 0x00000007, /* TXSR */
108 0x00000003, /* TCKE */
109 0x00000008, /* TFAW */
110 0x00000004, /* TRPAB */
111 0x00000006, /* TCLKSTABLE */
112 0x00000002, /* TCLKSTOP */
113 0x000000d0, /* TREFBW */
114 0x00000000, /* QUSE_EXTRA */
115 0x00000000, /* FBIO_CFG6 */
116 0x00000000, /* ODT_WRITE */
117 0x00000000, /* ODT_READ */
118 0x00000282, /* FBIO_CFG5 */
119 0xa06a04ae, /* CFG_DIG_DLL */
120 0x0001f000, /* DLL_XFORM_DQS */
121 0x00000000, /* DLL_XFORM_QUSE */
122 0x00000000, /* ZCAL_REF_CNT */
123 0x00000005, /* ZCAL_WAIT_CNT */
124 0x00000000, /* AUTO_CAL_INTERVAL */
125 0x00000000, /* CFG_CLKTRIM_0 */
126 0x00000000, /* CFG_CLKTRIM_1 */
127 0x00000000, /* CFG_CLKTRIM_2 */
128 }
129 },
130 {
131 .rate = 75000, /* SDRAM frequency */
132 .regs = {
133 0x00000005, /* RC */
134 0x0000000a, /* RFC */
135 0x00000004, /* RAS */
136 0x00000003, /* RP */
137 0x00000006, /* R2W */
138 0x00000004, /* W2R */
139 0x00000002, /* R2P */
140 0x00000009, /* W2P */
141 0x00000003, /* RD_RCD */
142 0x00000003, /* WR_RCD */
143 0x00000002, /* RRD */
144 0x00000002, /* REXT */
145 0x00000002, /* WDV */
146 0x00000005, /* QUSE */
147 0x00000003, /* QRST */
148 0x00000008, /* QSAFE */
149 0x0000000b, /* RDV */
150 0x000000ff, /* REFRESH */
151 0x00000000, /* BURST_REFRESH_NUM */
152 0x00000003, /* PDEX2WR */
153 0x00000003, /* PDEX2RD */
154 0x00000003, /* PCHG2PDEN */
155 0x00000008, /* ACT2PDEN */
156 0x00000001, /* AR2PDEN */
157 0x0000000a, /* RW2PDEN */
158 0x0000000b, /* TXSR */
159 0x00000003, /* TCKE */
160 0x00000008, /* TFAW */
161 0x00000004, /* TRPAB */
162 0x00000006, /* TCLKSTABLE */
163 0x00000002, /* TCLKSTOP */
164 0x00000138, /* TREFBW */
165 0x00000000, /* QUSE_EXTRA */
166 0x00000000, /* FBIO_CFG6 */
167 0x00000000, /* ODT_WRITE */
168 0x00000000, /* ODT_READ */
169 0x00000282, /* FBIO_CFG5 */
170 0xa06a04ae, /* CFG_DIG_DLL */
171 0x0001f000, /* DLL_XFORM_DQS */
172 0x00000000, /* DLL_XFORM_QUSE */
173 0x00000000, /* ZCAL_REF_CNT */
174 0x00000007, /* ZCAL_WAIT_CNT */
175 0x00000000, /* AUTO_CAL_INTERVAL */
176 0x00000000, /* CFG_CLKTRIM_0 */
177 0x00000000, /* CFG_CLKTRIM_1 */
178 0x00000000, /* CFG_CLKTRIM_2 */
179 }
180 },
181 {
182 .rate = 150000, /* SDRAM frequency */
183 .regs = {
184 0x00000009, /* RC */
185 0x00000014, /* RFC */
186 0x00000007, /* RAS */
187 0x00000004, /* RP */
188 0x00000006, /* R2W */
189 0x00000004, /* W2R */
190 0x00000002, /* R2P */
191 0x00000009, /* W2P */
192 0x00000003, /* RD_RCD */
193 0x00000003, /* WR_RCD */
194 0x00000002, /* RRD */
195 0x00000002, /* REXT */
196 0x00000002, /* WDV */
197 0x00000005, /* QUSE */
198 0x00000003, /* QRST */
199 0x00000008, /* QSAFE */
200 0x0000000b, /* RDV */
201 0x0000021f, /* REFRESH */
202 0x00000000, /* BURST_REFRESH_NUM */
203 0x00000003, /* PDEX2WR */
204 0x00000003, /* PDEX2RD */
205 0x00000004, /* PCHG2PDEN */
206 0x00000008, /* ACT2PDEN */
207 0x00000001, /* AR2PDEN */
208 0x0000000a, /* RW2PDEN */
209 0x00000015, /* TXSR */
210 0x00000003, /* TCKE */
211 0x00000008, /* TFAW */
212 0x00000004, /* TRPAB */
213 0x00000006, /* TCLKSTABLE */
214 0x00000002, /* TCLKSTOP */
215 0x00000270, /* TREFBW */
216 0x00000000, /* QUSE_EXTRA */
217 0x00000001, /* FBIO_CFG6 */
218 0x00000000, /* ODT_WRITE */
219 0x00000000, /* ODT_READ */
220 0x00000282, /* FBIO_CFG5 */
221 0xA04C04AE, /* CFG_DIG_DLL */
222 0x007FC010, /* DLL_XFORM_DQS */
223 0x00000000, /* DLL_XFORM_QUSE */
224 0x00000000, /* ZCAL_REF_CNT */
225 0x0000000e, /* ZCAL_WAIT_CNT */
226 0x00000000, /* AUTO_CAL_INTERVAL */
227 0x00000000, /* CFG_CLKTRIM_0 */
228 0x00000000, /* CFG_CLKTRIM_1 */
229 0x00000000, /* CFG_CLKTRIM_2 */
230 }
231 },
232 {
233 .rate = 300000, /* SDRAM frequency */
234 .regs = {
235 0x00000012, /* RC */
236 0x00000027, /* RFC */
237 0x0000000D, /* RAS */
238 0x00000007, /* RP */
239 0x00000007, /* R2W */
240 0x00000005, /* W2R */
241 0x00000003, /* R2P */
242 0x00000009, /* W2P */
243 0x00000006, /* RD_RCD */
244 0x00000006, /* WR_RCD */
245 0x00000003, /* RRD */
246 0x00000003, /* REXT */
247 0x00000002, /* WDV */
248 0x00000006, /* QUSE */
249 0x00000003, /* QRST */
250 0x00000009, /* QSAFE */
251 0x0000000c, /* RDV */
252 0x0000045f, /* REFRESH */
253 0x00000000, /* BURST_REFRESH_NUM */
254 0x00000004, /* PDEX2WR */
255 0x00000004, /* PDEX2RD */
256 0x00000007, /* PCHG2PDEN */
257 0x00000008, /* ACT2PDEN */
258 0x00000001, /* AR2PDEN */
259 0x0000000e, /* RW2PDEN */
260 0x0000002A, /* TXSR */
261 0x00000003, /* TCKE */
262 0x0000000F, /* TFAW */
263 0x00000008, /* TRPAB */
264 0x00000005, /* TCLKSTABLE */
265 0x00000002, /* TCLKSTOP */
266 0x000004E1, /* TREFBW */
267 0x00000005, /* QUSE_EXTRA */
268 0x00000002, /* FBIO_CFG6 */
269 0x00000000, /* ODT_WRITE */
270 0x00000000, /* ODT_READ */
271 0x00000282, /* FBIO_CFG5 */
272 0xE03C048B, /* CFG_DIG_DLL */
273 0x007FC010, /* DLL_XFORM_DQS */
274 0x00000000, /* DLL_XFORM_QUSE */
275 0x00000000, /* ZCAL_REF_CNT */
276 0x0000001B, /* ZCAL_WAIT_CNT */
277 0x00000000, /* AUTO_CAL_INTERVAL */
278 0x00000000, /* CFG_CLKTRIM_0 */
279 0x00000000, /* CFG_CLKTRIM_1 */
280 0x00000000, /* CFG_CLKTRIM_2 */
281 }
282 }
283};
284
285static const struct tegra_emc_table whistler_emc_tables_elpida_380Mhz[] = {
286 {
287 .rate = 23750, /* SDRAM frquency */
288 .regs = {
289 0x00000002, /* RC */
290 0x00000006, /* RFC */
291 0x00000003, /* RAS */
292 0x00000003, /* RP */
293 0x00000006, /* R2W */
294 0x00000004, /* W2R */
295 0x00000002, /* R2P */
296 0x0000000b, /* W2P */
297 0x00000003, /* RD_RCD */
298 0x00000003, /* WR_RCD */
299 0x00000002, /* RRD */
300 0x00000002, /* REXT */
301 0x00000003, /* WDV */
302 0x00000005, /* QUSE */
303 0x00000004, /* QRST */
304 0x00000008, /* QSAFE */
305 0x0000000c, /* RDV */
306 0x00000047, /* REFRESH */
307 0x00000000, /* BURST_REFRESH_NUM */
308 0x00000003, /* PDEX2WR */
309 0x00000003, /* PDEX2RD */
310 0x00000003, /* PCHG2PDEN */
311 0x00000008, /* ACT2PDEN */
312 0x00000001, /* AR2PDEN */
313 0x0000000b, /* RW2PDEN */
314 0x00000004, /* TXSR */
315 0x00000003, /* TCKE */
316 0x00000008, /* TFAW */
317 0x00000004, /* TRPAB */
318 0x00000008, /* TCLKSTABLE */
319 0x00000002, /* TCLKSTOP */
320 0x00000060, /* TREFBW */
321 0x00000000, /* QUSE_EXTRA */
322 0x00000003, /* FBIO_CFG6 */
323 0x00000000, /* ODT_WRITE */
324 0x00000000, /* ODT_READ */
325 0x00000282, /* FBIO_CFG5 */
326 0xa0ae04ae, /* CFG_DIG_DLL */
327 0x0001f800, /* DLL_XFORM_DQS */
328 0x00000000, /* DLL_XFORM_QUSE */
329 0x00000000, /* ZCAL_REF_CNT */
330 0x00000003, /* ZCAL_WAIT_CNT */
331 0x00000000, /* AUTO_CAL_INTERVAL */
332 0x00000000, /* CFG_CLKTRIM_0 */
333 0x00000000, /* CFG_CLKTRIM_1 */
334 0x00000000, /* CFG_CLKTRIM_2 */
335 }
336 },
337 {
338 .rate = 63334, /* SDRAM frquency */
339 .regs = {
340 0x00000004, /* RC */
341 0x00000009, /* RFC */
342 0x00000003, /* RAS */
343 0x00000003, /* RP */
344 0x00000006, /* R2W */
345 0x00000004, /* W2R */
346 0x00000002, /* R2P */
347 0x0000000b, /* W2P */
348 0x00000003, /* RD_RCD */
349 0x00000003, /* WR_RCD */
350 0x00000002, /* RRD */
351 0x00000002, /* REXT */
352 0x00000003, /* WDV */
353 0x00000006, /* QUSE */
354 0x00000004, /* QRST */
355 0x00000008, /* QSAFE */
356 0x0000000c, /* RDV */
357 0x000000c4, /* REFRESH */
358 0x00000000, /* BURST_REFRESH_NUM */
359 0x00000003, /* PDEX2WR */
360 0x00000003, /* PDEX2RD */
361 0x00000003, /* PCHG2PDEN */
362 0x00000008, /* ACT2PDEN */
363 0x00000001, /* AR2PDEN */
364 0x0000000b, /* RW2PDEN */
365 0x00000009, /* TXSR */
366 0x00000003, /* TCKE */
367 0x00000008, /* TFAW */
368 0x00000004, /* TRPAB */
369 0x00000008, /* TCLKSTABLE */
370 0x00000002, /* TCLKSTOP */
371 0x00000107, /* TREFBW */
372 0x00000000, /* QUSE_EXTRA */
373 0x00000000, /* FBIO_CFG6 */
374 0x00000000, /* ODT_WRITE */
375 0x00000000, /* ODT_READ */
376 0x00000282, /* FBIO_CFG5 */
377 0xa0ae04ae, /* CFG_DIG_DLL */
378 0x0001f800, /* DLL_XFORM_DQS */
379 0x00000000, /* DLL_XFORM_QUSE */
380 0x00000000, /* ZCAL_REF_CNT */
381 0x00000006, /* ZCAL_WAIT_CNT */
382 0x00000000, /* AUTO_CAL_INTERVAL */
383 0x00000000, /* CFG_CLKTRIM_0 */
384 0x00000000, /* CFG_CLKTRIM_1 */
385 0x00000000, /* CFG_CLKTRIM_2 */
386 }
387 },
388 {
389 .rate = 95000, /* SDRAM frquency */
390 .regs = {
391 0x00000006, /* RC */
392 0x0000000d, /* RFC */
393 0x00000004, /* RAS */
394 0x00000003, /* RP */
395 0x00000006, /* R2W */
396 0x00000004, /* W2R */
397 0x00000002, /* R2P */
398 0x0000000b, /* W2P */
399 0x00000003, /* RD_RCD */
400 0x00000003, /* WR_RCD */
401 0x00000002, /* RRD */
402 0x00000002, /* REXT */
403 0x00000003, /* WDV */
404 0x00000006, /* QUSE */
405 0x00000004, /* QRST */
406 0x00000008, /* QSAFE */
407 0x0000000c, /* RDV */
408 0x0000013f, /* REFRESH */
409 0x00000000, /* BURST_REFRESH_NUM */
410 0x00000003, /* PDEX2WR */
411 0x00000003, /* PDEX2RD */
412 0x00000003, /* PCHG2PDEN */
413 0x00000008, /* ACT2PDEN */
414 0x00000001, /* AR2PDEN */
415 0x0000000b, /* RW2PDEN */
416 0x0000000e, /* TXSR */
417 0x00000003, /* TCKE */
418 0x00000008, /* TFAW */
419 0x00000004, /* TRPAB */
420 0x00000008, /* TCLKSTABLE */
421 0x00000002, /* TCLKSTOP */
422 0x0000018c, /* TREFBW */
423 0x00000000, /* QUSE_EXTRA */
424 0x00000001, /* FBIO_CFG6 */
425 0x00000000, /* ODT_WRITE */
426 0x00000000, /* ODT_READ */
427 0x00000282, /* FBIO_CFG5 */
428 0xa0ae04ae, /* CFG_DIG_DLL */
429 0x0001f000, /* DLL_XFORM_DQS */
430 0x00000000, /* DLL_XFORM_QUSE */
431 0x00000000, /* ZCAL_REF_CNT */
432 0x00000009, /* ZCAL_WAIT_CNT */
433 0x00000000, /* AUTO_CAL_INTERVAL */
434 0x00000000, /* CFG_CLKTRIM_0 */
435 0x00000000, /* CFG_CLKTRIM_1 */
436 0x00000000, /* CFG_CLKTRIM_2 */
437 }
438 },
439 {
440 .rate = 190000, /* SDRAM frquency */
441 .regs = {
442 0x0000000c, /* RC */
443 0x00000019, /* RFC */
444 0x00000008, /* RAS */
445 0x00000004, /* RP */
446 0x00000007, /* R2W */
447 0x00000004, /* W2R */
448 0x00000002, /* R2P */
449 0x0000000b, /* W2P */
450 0x00000004, /* RD_RCD */
451 0x00000004, /* WR_RCD */
452 0x00000002, /* RRD */
453 0x00000003, /* REXT */
454 0x00000003, /* WDV */
455 0x00000006, /* QUSE */
456 0x00000004, /* QRST */
457 0x00000009, /* QSAFE */
458 0x0000000d, /* RDV */
459 0x000002bf, /* REFRESH */
460 0x00000000, /* BURST_REFRESH_NUM */
461 0x00000003, /* PDEX2WR */
462 0x00000003, /* PDEX2RD */
463 0x00000004, /* PCHG2PDEN */
464 0x00000008, /* ACT2PDEN */
465 0x00000001, /* AR2PDEN */
466 0x0000000c, /* RW2PDEN */
467 0x0000001b, /* TXSR */
468 0x00000003, /* TCKE */
469 0x0000000a, /* TFAW */
470 0x00000004, /* TRPAB */
471 0x00000008, /* TCLKSTABLE */
472 0x00000002, /* TCLKSTOP */
473 0x00000317, /* TREFBW */
474 0x00000000, /* QUSE_EXTRA */
475 0x00000002, /* FBIO_CFG6 */
476 0x00000000, /* ODT_WRITE */
477 0x00000000, /* ODT_READ */
478 0x00000282, /* FBIO_CFG5 */
479 0xa06204ae, /* CFG_DIG_DLL */
480 0x007f7010, /* DLL_XFORM_DQS */
481 0x00000000, /* DLL_XFORM_QUSE */
482 0x00000000, /* ZCAL_REF_CNT */
483 0x00000012, /* ZCAL_WAIT_CNT */
484 0x00000000, /* AUTO_CAL_INTERVAL */
485 0x00000000, /* CFG_CLKTRIM_0 */
486 0x00000000, /* CFG_CLKTRIM_1 */
487 0x00000000, /* CFG_CLKTRIM_2 */
488 }
489 },
490 {
491 .rate = 300000, /* SDRAM frquency */
492 .regs = {
493 0x00000012, /* RC */
494 0x00000027, /* RFC */
495 0x0000000d, /* RAS */
496 0x00000006, /* RP */
497 0x00000007, /* R2W */
498 0x00000005, /* W2R */
499 0x00000003, /* R2P */
500 0x0000000b, /* W2P */
501 0x00000006, /* RD_RCD */
502 0x00000006, /* WR_RCD */
503 0x00000003, /* RRD */
504 0x00000003, /* REXT */
505 0x00000003, /* WDV */
506 0x00000007, /* QUSE */
507 0x00000004, /* QRST */
508 0x00000009, /* QSAFE */
509 0x0000000d, /* RDV */
510 0x0000045f, /* REFRESH */
511 0x00000000, /* BURST_REFRESH_NUM */
512 0x00000004, /* PDEX2WR */
513 0x00000004, /* PDEX2RD */
514 0x00000006, /* PCHG2PDEN */
515 0x00000008, /* ACT2PDEN */
516 0x00000001, /* AR2PDEN */
517 0x0000000f, /* RW2PDEN */
518 0x0000002a, /* TXSR */
519 0x00000003, /* TCKE */
520 0x0000000f, /* TFAW */
521 0x00000007, /* TRPAB */
522 0x00000007, /* TCLKSTABLE */
523 0x00000002, /* TCLKSTOP */
524 0x000004e0, /* TREFBW */
525 0x00000006, /* QUSE_EXTRA */
526 0x00000002, /* FBIO_CFG6 */
527 0x00000000, /* ODT_WRITE */
528 0x00000000, /* ODT_READ */
529 0x00000282, /* FBIO_CFG5 */
530 0xe05e048b, /* CFG_DIG_DLL */
531 0x007f2010, /* DLL_XFORM_DQS */
532 0x00000000, /* DLL_XFORM_QUSE */
533 0x00000000, /* ZCAL_REF_CNT */
534 0x0000001b, /* ZCAL_WAIT_CNT */
535 0x00000000, /* AUTO_CAL_INTERVAL */
536 0x00000000, /* CFG_CLKTRIM_0 */
537 0x00000000, /* CFG_CLKTRIM_1 */
538 0x00000000, /* CFG_CLKTRIM_2 */
539 }
540 },
541 {
542 .rate = 380000, /* SDRAM frquency */
543 .regs = {
544 0x00000017, /* RC */
545 0x00000032, /* RFC */
546 0x00000010, /* RAS */
547 0x00000007, /* RP */
548 0x00000008, /* R2W */
549 0x00000005, /* W2R */
550 0x00000003, /* R2P */
551 0x0000000b, /* W2P */
552 0x00000007, /* RD_RCD */
553 0x00000007, /* WR_RCD */
554 0x00000004, /* RRD */
555 0x00000003, /* REXT */
556 0x00000003, /* WDV */
557 0x00000007, /* QUSE */
558 0x00000004, /* QRST */
559 0x0000000a, /* QSAFE */
560 0x0000000e, /* RDV */
561 0x0000059f, /* REFRESH */
562 0x00000000, /* BURST_REFRESH_NUM */
563 0x00000004, /* PDEX2WR */
564 0x00000004, /* PDEX2RD */
565 0x00000007, /* PCHG2PDEN */
566 0x00000008, /* ACT2PDEN */
567 0x00000001, /* AR2PDEN */
568 0x00000011, /* RW2PDEN */
569 0x00000036, /* TXSR */
570 0x00000003, /* TCKE */
571 0x00000013, /* TFAW */
572 0x00000008, /* TRPAB */
573 0x00000007, /* TCLKSTABLE */
574 0x00000002, /* TCLKSTOP */
575 0x0000062d, /* TREFBW */
576 0x00000006, /* QUSE_EXTRA */
577 0x00000003, /* FBIO_CFG6 */
578 0x00000000, /* ODT_WRITE */
579 0x00000000, /* ODT_READ */
580 0x00000282, /* FBIO_CFG5 */
581 0xe044048b, /* CFG_DIG_DLL */
582 0x007fb010, /* DLL_XFORM_DQS */
583 0x00000000, /* DLL_XFORM_QUSE */
584 0x00000000, /* ZCAL_REF_CNT */
585 0x00000023, /* ZCAL_WAIT_CNT */
586 0x00000000, /* AUTO_CAL_INTERVAL */
587 0x00000000, /* CFG_CLKTRIM_0 */
588 0x00000000, /* CFG_CLKTRIM_1 */
589 0x00000000, /* CFG_CLKTRIM_2 */
590 }
591 }
592};
593
594static const struct tegra_emc_chip whistler_emc_chips[] = {
595 {
596 .description = "Elpida 300MHz",
597 .mem_manufacturer_id = 0x0303,
598 .mem_revision_id1 = -1,
599 .mem_revision_id2 = -1,
600 .mem_pid = -1,
601 .table = whistler_emc_tables_elpida_300Mhz,
602 .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz)
603 },
604};
605
606static const struct tegra_emc_chip whistler_ap25_emc_chips[] = {
607 {
608 .description = "Elpida 380MHz",
609 .mem_manufacturer_id = 0x0303,
610 .mem_revision_id1 = -1,
611 .mem_revision_id2 = -1,
612 .mem_pid = -1,
613 .table = whistler_emc_tables_elpida_380Mhz,
614 .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_380Mhz)
615 },
616};
617
618#define TEGRA25_SKU 0x17
619
620int __init whistler_emc_init(void)
621{
622 int sku_id = tegra_sku_id();
623
624 if (sku_id == TEGRA25_SKU)
625 tegra_init_emc(whistler_ap25_emc_chips,
626 ARRAY_SIZE(whistler_ap25_emc_chips));
627 else
628 tegra_init_emc(whistler_emc_chips,
629 ARRAY_SIZE(whistler_emc_chips));
630
631 return 0;
632}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 03:57:57 -0400