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diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c
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+++ b/arch/arm/mach-tegra/board-p1852-pinmux.c
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1/*
2 * arch/arm/mach-tegra/board-p1852-pinmux.c
3 *
4 * Copyright (C) 2010-2012 NVIDIA Corporation
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <mach/pinmux.h>
20#include "board.h"
21#include "board-p1852.h"
22#include "gpio-names.h"
23
24#define DEFAULT_DRIVE(_name) \
25 { \
26 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
27 .hsm = TEGRA_HSM_DISABLE, \
28 .schmitt = TEGRA_SCHMITT_ENABLE, \
29 .drive = TEGRA_DRIVE_DIV_1, \
30 .pull_down = TEGRA_PULL_31, \
31 .pull_up = TEGRA_PULL_31, \
32 .slew_rising = TEGRA_SLEW_SLOWEST, \
33 .slew_falling = TEGRA_SLEW_SLOWEST, \
34 }
35/* Setting the drive strength of pins
36 * hsm: Enable High speed mode (ENABLE/DISABLE)
37 * Schimit: Enable/disable schimit (ENABLE/DISABLE)
38 * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
39 * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
40 * strength code. Value from 0 to 31.
41 * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
42 * strength code. Value from 0 to 31.
43 * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
44 * code 11 is least slewing of signal. code 00 is highest
45 * slewing of the signal.
46 * Value - FASTEST, FAST, SLOW, SLOWEST
47 * pullup_slew - Driver Output Pull-Down slew control code -
48 * code 11 is least slewing of signal. code 00 is highest
49 * slewing of the signal.
50 * Value - FASTEST, FAST, SLOW, SLOWEST
51 */
52#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
53 { \
54 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
55 .hsm = TEGRA_HSM_##_hsm, \
56 .schmitt = TEGRA_SCHMITT_##_schmitt, \
57 .drive = TEGRA_DRIVE_##_drive, \
58 .pull_down = TEGRA_PULL_##_pulldn_drive, \
59 .pull_up = TEGRA_PULL_##_pullup_drive, \
60 .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
61 .slew_falling = TEGRA_SLEW_##_pullup_slew, \
62 }
63
64/* !!!FIXME!!!! Update drive strength with characterized value */
65static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = {
66 SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
67
68 /* All I2C pins are driven to maximum drive strength */
69 /* GEN1 I2C */
70 SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
71
72 /* GEN2 I2C */
73 SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
74
75 /* DDC I2C */
76 SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
77
78 /* PWR_I2C */
79 SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
80
81 /* SDMMC4 */
82 SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 22, 18, SLOWEST, SLOWEST),
83 SET_DRIVE(GMF, DISABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST),
84 SET_DRIVE(GMG, DISABLE, ENABLE, DIV_1, 15, 6, SLOWEST, SLOWEST),
85 SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 12, 6, SLOWEST, SLOWEST),
86};
87
88#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \
89 { \
90 .pingroup = TEGRA_PINGROUP_##_pingroup, \
91 .func = TEGRA_MUX_##_mux, \
92 .pupd = TEGRA_PUPD_##_pupd, \
93 .tristate = TEGRA_TRI_##_tri, \
94 .io = TEGRA_PIN_##_io, \
95 .lock = TEGRA_PIN_LOCK_DEFAULT, \
96 .od = TEGRA_PIN_OD_DEFAULT, \
97 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
98 }
99
100#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
101 { \
102 .pingroup = TEGRA_PINGROUP_##_pingroup, \
103 .func = TEGRA_MUX_##_mux, \
104 .pupd = TEGRA_PUPD_##_pupd, \
105 .tristate = TEGRA_TRI_##_tri, \
106 .io = TEGRA_PIN_##_io, \
107 .lock = TEGRA_PIN_LOCK_##_lock, \
108 .od = TEGRA_PIN_OD_##_od, \
109 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
110 }
111
112#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
113 { \
114 .pingroup = TEGRA_PINGROUP_##_pingroup, \
115 .func = TEGRA_MUX_##_mux, \
116 .pupd = TEGRA_PUPD_##_pupd, \
117 .tristate = TEGRA_TRI_##_tri, \
118 .io = TEGRA_PIN_##_io, \
119 .lock = TEGRA_PIN_LOCK_##_lock, \
120 .od = TEGRA_PIN_OD_DEFAULT, \
121 .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \
122 }
123
124static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = {
125 /* SDMMC1 pinmux */
126 DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
127 DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT),
128 DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT),
129 DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT),
130 DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT),
131 DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT),
132
133 /* SDMMC2 pinmux */
134 DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT),
135 DEFAULT_PINMUX(KB_ROW11, SDMMC2, PULL_UP, NORMAL, INPUT),
136 DEFAULT_PINMUX(KB_ROW12, SDMMC2, PULL_UP, NORMAL, INPUT),
137 DEFAULT_PINMUX(KB_ROW13, SDMMC2, PULL_UP, NORMAL, INPUT),
138 DEFAULT_PINMUX(KB_ROW14, SDMMC2, PULL_UP, NORMAL, INPUT),
139 DEFAULT_PINMUX(KB_ROW15, SDMMC2, PULL_UP, NORMAL, INPUT),
140 DEFAULT_PINMUX(KB_ROW6, SDMMC2, PULL_UP, NORMAL, INPUT),
141 DEFAULT_PINMUX(KB_ROW7, SDMMC2, PULL_UP, NORMAL, INPUT),
142 DEFAULT_PINMUX(KB_ROW8, SDMMC2, PULL_UP, NORMAL, INPUT),
143 DEFAULT_PINMUX(KB_ROW9, SDMMC2, PULL_UP, NORMAL, INPUT),
144
145 /* SDMMC3 pinmux */
146 DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
147 DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT),
148 DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT),
149 DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT),
150 DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT),
151 DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT),
152
153 /* SDMMC4 pinmux */
154 DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT),
155 DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, NORMAL, INPUT),
156 DEFAULT_PINMUX(GPIO_PBB0, POPSDMMC4, PULL_UP, NORMAL, INPUT),
157 I2C_PINMUX(CAM_I2C_SCL, POPSDMMC4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE),
158 I2C_PINMUX(CAM_I2C_SDA, POPSDMMC4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE),
159 DEFAULT_PINMUX(GPIO_PBB3, POPSDMMC4, PULL_UP, NORMAL, INPUT),
160 DEFAULT_PINMUX(GPIO_PBB4, POPSDMMC4, PULL_UP, NORMAL, INPUT),
161 DEFAULT_PINMUX(GPIO_PBB5, POPSDMMC4, PULL_UP, NORMAL, INPUT),
162 DEFAULT_PINMUX(GPIO_PBB6, POPSDMMC4, PULL_UP, NORMAL, INPUT),
163 DEFAULT_PINMUX(GPIO_PBB7, POPSDMMC4, PULL_UP, NORMAL, INPUT),
164
165 /* UART1 pinmux */
166 DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
167 DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
168 DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
169 DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, OUTPUT),
170
171 /* UART2 pinmux */
172 DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
173 DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
174
175 /* UART4 pinmux */
176 DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
177 DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT),
178 DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT),
179 DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
180
181 /* UART5 pinmux */
182 DEFAULT_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, INPUT),
183 DEFAULT_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, OUTPUT),
184 DEFAULT_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT),
185 DEFAULT_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT),
186
187 /* I2C1 pinmux */
188 I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
189 I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
190
191 /* I2C2 pinmux */
192 I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
193 I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
194
195 /* I2C4 pinmux */
196 I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
197 I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
198
199 /* PowerI2C pinmux */
200 I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
201 I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
202
203 /* SPI1 pinmux */
204 DEFAULT_PINMUX(ULPI_CLK, SPI1, NORMAL, NORMAL, INPUT),
205 DEFAULT_PINMUX(ULPI_DIR, SPI1, NORMAL, NORMAL, INPUT),
206 DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
207 DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
208
209 /* SPI2 pinmux */
210 DEFAULT_PINMUX(ULPI_DATA4, SPI2, NORMAL, NORMAL, INPUT),
211 DEFAULT_PINMUX(ULPI_DATA5, SPI2, NORMAL, NORMAL, INPUT),
212 DEFAULT_PINMUX(ULPI_DATA6, SPI2, NORMAL, NORMAL, INPUT),
213 DEFAULT_PINMUX(ULPI_DATA7, SPI2, NORMAL, NORMAL, INPUT),
214
215 /* SPDIF pinmux */
216 DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
217
218 /* DAP1 */
219 DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
220 DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
221 DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
222 DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
223
224 /* DAP2 */
225 DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
226 DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
227 DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
228 DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
229
230 /* DAP3 */
231 DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT),
232 DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT),
233 DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT),
234 DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT),
235
236 /* NOR pinmux */
237 DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT),
238 DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, INPUT),
239 DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT),
240 DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT),
241 DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, NORMAL, INPUT),
242 DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, NORMAL, INPUT),
243 DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, NORMAL, INPUT),
244 DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, NORMAL, INPUT),
245 DEFAULT_PINMUX(GMI_AD8, GMI, NORMAL, NORMAL, INPUT),
246 DEFAULT_PINMUX(GMI_AD9, GMI, NORMAL, NORMAL, INPUT),
247 DEFAULT_PINMUX(GMI_AD10, GMI, NORMAL, NORMAL, INPUT),
248 DEFAULT_PINMUX(GMI_AD11, GMI, NORMAL, NORMAL, INPUT),
249 DEFAULT_PINMUX(GMI_AD12, GMI, NORMAL, NORMAL, INPUT),
250 DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT),
251 DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT),
252 DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT),
253 DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, OUTPUT),
254 DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, NORMAL, OUTPUT),
255 DEFAULT_PINMUX(GMI_CS0_N, GMI, NORMAL, NORMAL, OUTPUT),
256 DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, OUTPUT),
257 DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, OUTPUT),
258 DEFAULT_PINMUX(GMI_WAIT, GMI, NORMAL, NORMAL, INPUT),
259 DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, OUTPUT),
260 DEFAULT_PINMUX(GMI_WR_N, GMI, NORMAL, NORMAL, OUTPUT),
261 DEFAULT_PINMUX(DAP2_FS, GMI, NORMAL, NORMAL, OUTPUT),
262 DEFAULT_PINMUX(DAP2_DIN, GMI, NORMAL, NORMAL, OUTPUT),
263 DEFAULT_PINMUX(DAP2_DOUT, GMI, NORMAL, NORMAL, OUTPUT),
264 DEFAULT_PINMUX(DAP2_SCLK, GMI, NORMAL, NORMAL, OUTPUT),
265 DEFAULT_PINMUX(SPI1_MOSI, GMI, NORMAL, NORMAL, OUTPUT),
266 DEFAULT_PINMUX(SPI2_CS0_N, GMI, NORMAL, NORMAL, OUTPUT),
267 DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, OUTPUT),
268 DEFAULT_PINMUX(SPI2_MOSI, GMI, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(SPI2_MISO, GMI, NORMAL, NORMAL, OUTPUT),
270 DEFAULT_PINMUX(DAP4_FS, GMI, NORMAL, NORMAL, OUTPUT),
271 DEFAULT_PINMUX(DAP4_DIN, GMI, NORMAL, NORMAL, OUTPUT),
272 DEFAULT_PINMUX(DAP4_DOUT, GMI, NORMAL, NORMAL, OUTPUT),
273 DEFAULT_PINMUX(DAP4_SCLK, GMI, NORMAL, NORMAL, OUTPUT),
274 DEFAULT_PINMUX(GPIO_PU0, GMI, NORMAL, NORMAL, OUTPUT),
275 DEFAULT_PINMUX(GPIO_PU1, GMI, NORMAL, NORMAL, OUTPUT),
276 DEFAULT_PINMUX(GPIO_PU2, GMI, NORMAL, NORMAL, OUTPUT),
277 DEFAULT_PINMUX(GPIO_PU3, GMI, NORMAL, NORMAL, OUTPUT),
278 DEFAULT_PINMUX(GPIO_PU4, GMI, NORMAL, NORMAL, OUTPUT),
279 DEFAULT_PINMUX(GPIO_PU5, GMI, NORMAL, NORMAL, OUTPUT),
280 DEFAULT_PINMUX(GPIO_PU6, GMI, NORMAL, NORMAL, OUTPUT),
281 DEFAULT_PINMUX(UART2_RTS_N, GMI, NORMAL, NORMAL, OUTPUT),
282 DEFAULT_PINMUX(UART2_CTS_N, GMI, NORMAL, NORMAL, OUTPUT),
283 DEFAULT_PINMUX(UART3_TXD, GMI, NORMAL, NORMAL, OUTPUT),
284 DEFAULT_PINMUX(UART3_RXD, GMI, NORMAL, NORMAL, OUTPUT),
285 DEFAULT_PINMUX(UART3_CTS_N, GMI, NORMAL, NORMAL, OUTPUT),
286 DEFAULT_PINMUX(UART3_RTS_N, GMI, NORMAL, NORMAL, OUTPUT),
287
288
289 /* DISPLAY pinmux */
290 DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT),
291 DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT),
292 DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT),
293 DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT),
294 DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT),
295 DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT),
296 DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT),
297 DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT),
298 DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT),
299 DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT),
300 DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT),
301 DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT),
302 DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT),
303 DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT),
304 DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT),
305 DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT),
306 DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT),
307 DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT),
308 DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT),
309 DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT),
310 DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT),
311 DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT),
312 DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT),
313 DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT),
314 DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT),
315 DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT),
316 DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT),
317 DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
318 DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT),
319 DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
320 DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT),
321
322 DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
323 DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
324 DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
325 DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
326 DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
327 DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
328 DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
329
330 VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
331 VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
332 VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
333 VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
334 VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
335 VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
336 VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
337 VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
338 VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE),
339
340 /* pin config for gpios */
341 DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT),
342 DEFAULT_PINMUX(CLK1_OUT, RSVD1, NORMAL, NORMAL, INPUT),
343 DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT),
344 DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT),
345 DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT),
346 DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT),
347 DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT),
348 DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT),
349 DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT),
350 DEFAULT_PINMUX(SPI1_SCK, SPI2, NORMAL, NORMAL, INPUT),
351 DEFAULT_PINMUX(SPI1_CS0_N, SPI2, NORMAL, NORMAL, INPUT),
352 DEFAULT_PINMUX(SPI1_MISO, SAFE, NORMAL, NORMAL, INPUT),
353};
354
355int __init p1852_pinmux_init(void)
356{
357 tegra_pinmux_config_table(p1852_pinmux_common,
358 ARRAY_SIZE(p1852_pinmux_common));
359 tegra_drive_pinmux_config_table(p1852_drive_pinmux,
360 ARRAY_SIZE(p1852_drive_pinmux));
361 return 0;
362}
363
364static struct gpio p1852_sku8_gpios[] = {
365 {TEGRA_GPIO_PW4, GPIOF_OUT_INIT_HIGH, "w4"},
366 {TEGRA_GPIO_PEE2, GPIOF_OUT_INIT_HIGH, "ee2"},
367 {TEGRA_GPIO_PZ4, GPIOF_OUT_INIT_HIGH, "z4"},
368 {TEGRA_GPIO_PD2, GPIOF_OUT_INIT_HIGH, "d2"},
369 {TEGRA_GPIO_PD1, GPIOF_OUT_INIT_HIGH, "d1"},
370 {TEGRA_GPIO_PD0, GPIOF_OUT_INIT_HIGH, "d0"},
371 {TEGRA_GPIO_PW2, GPIOF_IN, "therm_alert"},
372 {TEGRA_GPIO_PK5, GPIOF_OUT_INIT_HIGH, "user1"},
373 {TEGRA_GPIO_PX5, GPIOF_OUT_INIT_HIGH, "user2"},
374 {TEGRA_GPIO_PX6, GPIOF_OUT_INIT_HIGH, "user3"},
375 {TEGRA_GPIO_PX7, GPIOF_OUT_INIT_HIGH, "user4"},
376};
377
378int __init p1852_gpio_init(void)
379{
380 int i, pin_count = 0;
381 struct gpio *gpios_info = NULL;
382 gpios_info = p1852_sku8_gpios;
383 pin_count = ARRAY_SIZE(p1852_sku8_gpios);
384
385 gpio_request_array(gpios_info, pin_count);
386 for (i = 0; i < pin_count; i++) {
387 tegra_gpio_enable(gpios_info[i].gpio);
388 gpio_export(gpios_info[i].gpio, true);
389 }
390 return 0;
391}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 00:27:14 -0400