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-rw-r--r--arch/arm/mach-tegra/board-kai-power.c658
1 files changed, 658 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-kai-power.c b/arch/arm/mach-tegra/board-kai-power.c
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1/*
2 * arch/arm/mach-tegra/board-kai-power.c
3 *
4 * Copyright (C) 2012 NVIDIA, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18 * 02111-1307, USA
19 */
20#include <linux/i2c.h>
21#include <linux/pda_power.h>
22#include <linux/platform_device.h>
23#include <linux/resource.h>
24#include <linux/regulator/machine.h>
25#include <linux/mfd/max77663-core.h>
26#include <linux/regulator/max77663-regulator.h>
27#include <linux/gpio.h>
28#include <linux/io.h>
29#include <linux/regulator/fixed.h>
30#include <linux/power/gpio-charger.h>
31
32#include <asm/mach-types.h>
33
34#include <mach/iomap.h>
35#include <mach/irqs.h>
36#include <mach/pinmux.h>
37#include <mach/edp.h>
38
39#include "gpio-names.h"
40#include "board.h"
41#include "board-kai.h"
42#include "pm.h"
43#include "wakeups-t3.h"
44#include "tegra3_tsensor.h"
45
46#define PMC_CTRL 0x0
47#define PMC_CTRL_INTR_LOW (1 << 17)
48
49static struct regulator_consumer_supply max77663_sd0_supply[] = {
50 REGULATOR_SUPPLY("vdd_cpu", NULL),
51};
52
53static struct regulator_consumer_supply max77663_sd1_supply[] = {
54 REGULATOR_SUPPLY("vdd_core", NULL),
55};
56
57static struct regulator_consumer_supply max77663_sd2_supply[] = {
58 REGULATOR_SUPPLY("vdd_gen1v8", NULL),
59 REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
60 REGULATOR_SUPPLY("avdd_usb_pll", NULL),
61 REGULATOR_SUPPLY("avdd_osc", NULL),
62 REGULATOR_SUPPLY("vddio_sys", NULL),
63 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
64 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
65 REGULATOR_SUPPLY("vddio_uart", NULL),
66 REGULATOR_SUPPLY("pwrdet_uart", NULL),
67 REGULATOR_SUPPLY("vddio_bb", NULL),
68 REGULATOR_SUPPLY("pwrdet_bb", NULL),
69 REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
70 REGULATOR_SUPPLY("pwrdet_lcd", NULL),
71 REGULATOR_SUPPLY("vddio_audio", NULL),
72 REGULATOR_SUPPLY("pwrdet_audio", NULL),
73 REGULATOR_SUPPLY("vddio_cam", NULL),
74 REGULATOR_SUPPLY("pwrdet_cam", NULL),
75 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
76 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
77 REGULATOR_SUPPLY("vddio_vi", NULL),
78 REGULATOR_SUPPLY("pwrdet_vi", NULL),
79 REGULATOR_SUPPLY("vcore_nand", NULL),
80 REGULATOR_SUPPLY("pwrdet_nand", NULL),
81};
82
83static struct regulator_consumer_supply max77663_sd3_supply[] = {
84 REGULATOR_SUPPLY("vdd_ddr3l_1v35", NULL),
85};
86
87static struct regulator_consumer_supply max77663_ldo0_supply[] = {
88 REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
89};
90
91static struct regulator_consumer_supply max77663_ldo1_supply[] = {
92};
93
94static struct regulator_consumer_supply max77663_ldo2_supply[] = {
95 REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
96};
97
98static struct regulator_consumer_supply max77663_ldo3_supply[] = {
99 REGULATOR_SUPPLY("vmmc", NULL),
100};
101
102static struct regulator_consumer_supply max77663_ldo4_supply[] = {
103 REGULATOR_SUPPLY("vdd_rtc", NULL),
104};
105
106static struct regulator_consumer_supply max77663_ldo5_supply[] = {
107 REGULATOR_SUPPLY("vdd_sensor_2v8", NULL),
108};
109
110static struct regulator_consumer_supply max77663_ldo6_supply[] = {
111 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
112 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
113};
114
115static struct regulator_consumer_supply max77663_ldo7_supply[] = {
116 REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
117 REGULATOR_SUPPLY("pwrdet_mipi", NULL),
118};
119
120static struct regulator_consumer_supply max77663_ldo8_supply[] = {
121 REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
122 REGULATOR_SUPPLY("avdd_pllm", NULL),
123 REGULATOR_SUPPLY("avdd_pllu_d", NULL),
124 REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
125 REGULATOR_SUPPLY("avdd_pllx", NULL),
126};
127
128static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
129 {
130 .src = FPS_SRC_0,
131 .en_src = FPS_EN_SRC_EN0,
132 .time_period = FPS_TIME_PERIOD_DEF,
133 },
134 {
135 .src = FPS_SRC_1,
136 .en_src = FPS_EN_SRC_EN1,
137 .time_period = FPS_TIME_PERIOD_DEF,
138 },
139 {
140 .src = FPS_SRC_2,
141 .en_src = FPS_EN_SRC_EN0,
142 .time_period = FPS_TIME_PERIOD_DEF,
143 },
144};
145
146#define MAX77663_PDATA_INIT(_id, _min_uV, _max_uV, _supply_reg, \
147 _always_on, _boot_on, _apply_uV, \
148 _init_apply, _init_enable, _init_uV, \
149 _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
150 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id = \
151 { \
152 .init_data = { \
153 .constraints = { \
154 .min_uV = _min_uV, \
155 .max_uV = _max_uV, \
156 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
157 REGULATOR_MODE_STANDBY), \
158 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
159 REGULATOR_CHANGE_STATUS | \
160 REGULATOR_CHANGE_VOLTAGE), \
161 .always_on = _always_on, \
162 .boot_on = _boot_on, \
163 .apply_uV = _apply_uV, \
164 }, \
165 .num_consumer_supplies = \
166 ARRAY_SIZE(max77663_##_id##_supply), \
167 .consumer_supplies = max77663_##_id##_supply, \
168 .supply_regulator = _supply_reg, \
169 }, \
170 .init_apply = _init_apply, \
171 .init_enable = _init_enable, \
172 .init_uV = _init_uV, \
173 .fps_src = _fps_src, \
174 .fps_pu_period = _fps_pu_period, \
175 .fps_pd_period = _fps_pd_period, \
176 .fps_cfgs = max77663_fps_cfgs, \
177 .flags = _flags, \
178 }
179
180MAX77663_PDATA_INIT(sd0, 600000, 3387500, NULL, 1, 0, 0,
181 0, 0, -1, FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0 | SD_FSRADE_DISABLE);
182
183MAX77663_PDATA_INIT(sd1, 800000, 1587500, NULL, 1, 0, 0,
184 1, 1, -1, FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
185
186MAX77663_PDATA_INIT(sd2, 1800000, 1800000, NULL, 1, 0, 0,
187 1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
188
189MAX77663_PDATA_INIT(sd3, 600000, 3387500, NULL, 1, 0, 0,
190 1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
191
192MAX77663_PDATA_INIT(ldo0, 800000, 2350000, max77663_rails(sd3), 1, 0, 0,
193 1, 1, -1, FPS_SRC_1, -1, -1, 0);
194
195MAX77663_PDATA_INIT(ldo1, 800000, 2350000, max77663_rails(sd3), 0, 0, 0,
196 0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
197
198MAX77663_PDATA_INIT(ldo2, 800000, 3950000, NULL, 1, 0, 0,
199 1, 1, -1, FPS_SRC_1, -1, -1, 0);
200
201MAX77663_PDATA_INIT(ldo3, 800000, 3950000, NULL, 1, 0, 0,
202 1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
203
204MAX77663_PDATA_INIT(ldo4, 800000, 1587500, NULL, 0, 0, 0,
205 1, 1, 1000000, FPS_SRC_NONE, -1, -1, LDO4_EN_TRACKING);
206
207MAX77663_PDATA_INIT(ldo5, 800000, 2800000, NULL, 0, 0, 0,
208 1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
209
210MAX77663_PDATA_INIT(ldo6, 800000, 3950000, NULL, 0, 0, 0,
211 0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
212
213MAX77663_PDATA_INIT(ldo7, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
214 0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
215
216MAX77663_PDATA_INIT(ldo8, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
217 1, 1, -1, FPS_SRC_1, -1, -1, 0);
218
219#define MAX77663_REG(_id, _data) \
220 { \
221 .name = "max77663-regulator", \
222 .id = MAX77663_REGULATOR_ID_##_id, \
223 .platform_data = &max77663_regulator_pdata_##_data, \
224 .pdata_size = sizeof(max77663_regulator_pdata_##_data), \
225 }
226
227#define MAX77663_RTC() \
228 { \
229 .name = "max77663-rtc", \
230 .id = 0, \
231 }
232
233static struct mfd_cell max77663_subdevs[] = {
234 MAX77663_REG(SD0, sd0),
235 MAX77663_REG(SD1, sd1),
236 MAX77663_REG(SD2, sd2),
237 MAX77663_REG(SD3, sd3),
238 MAX77663_REG(LDO0, ldo0),
239 MAX77663_REG(LDO1, ldo1),
240 MAX77663_REG(LDO2, ldo2),
241 MAX77663_REG(LDO3, ldo3),
242 MAX77663_REG(LDO4, ldo4),
243 MAX77663_REG(LDO5, ldo5),
244 MAX77663_REG(LDO6, ldo6),
245 MAX77663_REG(LDO7, ldo7),
246 MAX77663_REG(LDO8, ldo8),
247 MAX77663_RTC(),
248};
249
250static struct max77663_gpio_config max77663_gpio_cfgs[] = {
251 {
252 .gpio = MAX77663_GPIO0,
253 .dir = GPIO_DIR_OUT,
254 .dout = GPIO_DOUT_LOW,
255 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
256 .alternate = GPIO_ALT_DISABLE,
257 },
258 {
259 .gpio = MAX77663_GPIO1,
260 .dir = GPIO_DIR_IN,
261 .dout = GPIO_DOUT_LOW,
262 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
263 .alternate = GPIO_ALT_DISABLE,
264 },
265 {
266 .gpio = MAX77663_GPIO2,
267 .dir = GPIO_DIR_OUT,
268 .dout = GPIO_DOUT_HIGH,
269 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
270 .alternate = GPIO_ALT_DISABLE,
271 },
272 {
273 .gpio = MAX77663_GPIO3,
274 .dir = GPIO_DIR_OUT,
275 .dout = GPIO_DOUT_HIGH,
276 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
277 .alternate = GPIO_ALT_DISABLE,
278 },
279 {
280 .gpio = MAX77663_GPIO4,
281 .dir = GPIO_DIR_OUT,
282 .dout = GPIO_DOUT_HIGH,
283 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
284 .alternate = GPIO_ALT_ENABLE,
285 },
286 {
287 .gpio = MAX77663_GPIO5,
288 .dir = GPIO_DIR_OUT,
289 .dout = GPIO_DOUT_LOW,
290 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
291 .alternate = GPIO_ALT_DISABLE,
292 },
293 {
294 .gpio = MAX77663_GPIO6,
295 .dir = GPIO_DIR_IN,
296 .alternate = GPIO_ALT_DISABLE,
297 },
298 {
299 .gpio = MAX77663_GPIO7,
300 .dir = GPIO_DIR_OUT,
301 .dout = GPIO_DOUT_LOW,
302 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
303 .alternate = GPIO_ALT_DISABLE,
304 },
305};
306
307static struct max77663_platform_data max7763_pdata = {
308 .irq_base = MAX77663_IRQ_BASE,
309 .gpio_base = MAX77663_GPIO_BASE,
310
311 .num_gpio_cfgs = ARRAY_SIZE(max77663_gpio_cfgs),
312 .gpio_cfgs = max77663_gpio_cfgs,
313
314 .num_subdevs = ARRAY_SIZE(max77663_subdevs),
315 .sub_devices = max77663_subdevs,
316
317 .rtc_i2c_addr = 0x68,
318
319 .use_power_off = true,
320};
321
322static struct i2c_board_info __initdata max77663_regulators[] = {
323 {
324 /* The I2C address was determined by OTP factory setting */
325 I2C_BOARD_INFO("max77663", 0x3c),
326 .irq = INT_EXTERNAL_PMU,
327 .platform_data = &max7763_pdata,
328 },
329};
330
331static int __init kai_max77663_regulator_init(void)
332{
333 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
334 u32 pmc_ctrl;
335
336 /* configure the power management controller to trigger PMU
337 * interrupts when low */
338 pmc_ctrl = readl(pmc + PMC_CTRL);
339 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
340
341 i2c_register_board_info(4, max77663_regulators,
342 ARRAY_SIZE(max77663_regulators));
343
344 return 0;
345}
346
347static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a00_supply[] = {
348 REGULATOR_SUPPLY("vdd_3v3", NULL),
349 REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
350 REGULATOR_SUPPLY("debug_cons", NULL),
351 REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
352};
353
354static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a01_supply[] = {
355 REGULATOR_SUPPLY("vdd_3v3", NULL),
356 REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
357 REGULATOR_SUPPLY("debug_cons", NULL),
358 REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
359 REGULATOR_SUPPLY("vddio_gmi", NULL),
360};
361
362static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a00_supply[] = {
363 REGULATOR_SUPPLY("avdd_hdmi", NULL),
364 REGULATOR_SUPPLY("avdd_usb", NULL),
365 REGULATOR_SUPPLY("vddio_gmi", NULL),
366};
367
368static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a01_supply[] = {
369 REGULATOR_SUPPLY("avdd_hdmi", NULL),
370 REGULATOR_SUPPLY("avdd_usb", NULL),
371};
372
373static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
374 REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
375 REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
376 REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
377};
378
379static struct regulator_consumer_supply fixed_reg_en_vddio_vid_supply[] = {
380 REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
381};
382
383static struct regulator_consumer_supply fixed_reg_en_3v3_modem_supply[] = {
384 REGULATOR_SUPPLY("vdd_mini_card", NULL),
385};
386
387static struct regulator_consumer_supply fixed_reg_en_vdd_pnl_supply[] = {
388 REGULATOR_SUPPLY("vdd_lvds", NULL),
389 REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
390 REGULATOR_SUPPLY("vdd_touch", NULL),
391 REGULATOR_SUPPLY("vddio_ts", NULL),
392};
393
394static struct regulator_consumer_supply fixed_reg_en_cam3_ldo_supply[] = {
395 REGULATOR_SUPPLY("vdd_cam3", NULL),
396};
397
398static struct regulator_consumer_supply fixed_reg_en_vdd_com_supply[] = {
399 REGULATOR_SUPPLY("vdd_com_bd", NULL),
400};
401
402static struct regulator_consumer_supply fixed_reg_en_vdd_sdmmc1_supply[] = {
403 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.0"),
404};
405
406static struct regulator_consumer_supply fixed_reg_en_3v3_fuse_supply[] = {
407 REGULATOR_SUPPLY("vdd_fuse", NULL),
408};
409
410static struct regulator_consumer_supply fixed_reg_cdc_en_supply[] = {
411 REGULATOR_SUPPLY("cdc_en", NULL),
412};
413
414/* Macro for defining fixed regulator sub device data */
415#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
416#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
417 _gpio_nr, _active_high, _boot_state, _millivolts) \
418 static struct regulator_init_data ri_data_##_var = \
419 { \
420 .supply_regulator = _in_supply, \
421 .num_consumer_supplies = \
422 ARRAY_SIZE(fixed_reg_##_name##_supply), \
423 .consumer_supplies = fixed_reg_##_name##_supply, \
424 .constraints = { \
425 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
426 REGULATOR_MODE_STANDBY), \
427 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
428 REGULATOR_CHANGE_STATUS | \
429 REGULATOR_CHANGE_VOLTAGE), \
430 .always_on = _always_on, \
431 .boot_on = _boot_on, \
432 }, \
433 }; \
434 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
435 { \
436 .supply_name = FIXED_SUPPLY(_name), \
437 .microvolts = _millivolts * 1000, \
438 .gpio = _gpio_nr, \
439 .enable_high = _active_high, \
440 .enabled_at_boot = _boot_state, \
441 .init_data = &ri_data_##_var, \
442 }; \
443 static struct platform_device fixed_reg_##_var##_dev = { \
444 .name = "reg-fixed-voltage", \
445 .id = _id, \
446 .dev = { \
447 .platform_data = &fixed_reg_##_var##_pdata, \
448 }, \
449 }
450
451
452/* A00 specific */
453FIXED_REG(1, en_3v3_sys_a00, en_3v3_sys_a00, NULL,
454 1, 0, MAX77663_GPIO_BASE + MAX77663_GPIO3, true, 1, 3300);
455FIXED_REG(2, en_avdd_hdmi_usb_a00, en_avdd_hdmi_usb_a00, FIXED_SUPPLY(en_3v3_sys_a00),
456 1, 0, MAX77663_GPIO_BASE + MAX77663_GPIO2, true, 1, 3300);
457FIXED_REG(3, en_1v8_cam_a00, en_1v8_cam, max77663_rails(sd2),
458 0, 0, TEGRA_GPIO_PS0, true, 0, 1800);
459FIXED_REG(4, en_vddio_vid_a00, en_vddio_vid, NULL,
460 0, 0, TEGRA_GPIO_PB2, true, 0, 5000);
461FIXED_REG(5, en_3v3_modem_a00, en_3v3_modem, NULL,
462 1, 1, TEGRA_GPIO_PP0, true, 0, 3300);
463FIXED_REG(6, en_vdd_pnl_a00, en_vdd_pnl, FIXED_SUPPLY(en_3v3_sys_a00),
464 0, 0, TEGRA_GPIO_PW1, true, 0, 3300);
465FIXED_REG(7, en_cam3_ldo_a00, en_cam3_ldo, FIXED_SUPPLY(en_3v3_sys_a00),
466 0, 0, TEGRA_GPIO_PR7, true, 0, 3300);
467FIXED_REG(8, en_vdd_com_a00, en_vdd_com, FIXED_SUPPLY(en_3v3_sys_a00),
468 1, 0, TEGRA_GPIO_PD0, true, 0, 3300);
469FIXED_REG(9, en_vdd_sdmmc1_a00, en_vdd_sdmmc1, FIXED_SUPPLY(en_3v3_sys_a00),
470 0, 0, TEGRA_GPIO_PC6, true, 0, 3300);
471FIXED_REG(10, en_3v3_fuse_a00, en_3v3_fuse, FIXED_SUPPLY(en_3v3_sys_a00),
472 0, 0, TEGRA_GPIO_PC1, true, 0, 3300);
473FIXED_REG(11, cdc_en_a00, cdc_en, max77663_rails(sd2),
474 0, 1, TEGRA_GPIO_PX2, true, 0, 1200);
475
476/* A01 specific */
477FIXED_REG(1, en_3v3_sys_a01, en_3v3_sys_a01, NULL,
478 1, 0, MAX77663_GPIO_BASE + MAX77663_GPIO3, true, 1, 3300);
479FIXED_REG(2, en_avdd_hdmi_usb_a01, en_avdd_hdmi_usb_a01, FIXED_SUPPLY(en_3v3_sys_a01),
480 0, 0, MAX77663_GPIO_BASE + MAX77663_GPIO2, true, 0, 3300);
481FIXED_REG(3, en_1v8_cam_a01, en_1v8_cam, max77663_rails(sd2),
482 0, 0, TEGRA_GPIO_PS0, true, 0, 1800);
483FIXED_REG(4, en_vddio_vid_a01, en_vddio_vid, NULL,
484 0, 0, TEGRA_GPIO_PB2, true, 0, 5000);
485FIXED_REG(5, en_3v3_modem_a01, en_3v3_modem, NULL,
486 1, 1, TEGRA_GPIO_PP0, true, 0, 3300);
487FIXED_REG(6, en_vdd_pnl_a01, en_vdd_pnl, FIXED_SUPPLY(en_3v3_sys_a01),
488 0, 0, TEGRA_GPIO_PW1, true, 0, 3300);
489FIXED_REG(7, en_cam3_ldo_a01, en_cam3_ldo, FIXED_SUPPLY(en_3v3_sys_a01),
490 0, 0, TEGRA_GPIO_PR7, true, 0, 3300);
491FIXED_REG(8, en_vdd_com_a01, en_vdd_com, FIXED_SUPPLY(en_3v3_sys_a01),
492 1, 0, TEGRA_GPIO_PD0, true, 0, 3300);
493FIXED_REG(9, en_vdd_sdmmc1_a01, en_vdd_sdmmc1, FIXED_SUPPLY(en_3v3_sys_a01),
494 0, 0, TEGRA_GPIO_PC6, true, 0, 3300);
495FIXED_REG(10, en_3v3_fuse_a01, en_3v3_fuse, FIXED_SUPPLY(en_3v3_sys_a01),
496 0, 0, TEGRA_GPIO_PC1, true, 0, 3300);
497FIXED_REG(11, cdc_en_a01, cdc_en, max77663_rails(sd2),
498 0, 1, TEGRA_GPIO_PX2, true, 0, 1200);
499
500/*
501 * Creating the fixed regulator device tables
502 */
503
504#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
505
506/* A00 specific */
507#define E1565_A00_FIXED_REG \
508 ADD_FIXED_REG(en_3v3_sys_a00), \
509 ADD_FIXED_REG(en_avdd_hdmi_usb_a00), \
510 ADD_FIXED_REG(en_1v8_cam_a00), \
511 ADD_FIXED_REG(en_vddio_vid_a00), \
512 ADD_FIXED_REG(en_3v3_modem_a00), \
513 ADD_FIXED_REG(en_vdd_pnl_a00), \
514 ADD_FIXED_REG(en_cam3_ldo_a00), \
515 ADD_FIXED_REG(en_vdd_com_a00), \
516 ADD_FIXED_REG(en_vdd_sdmmc1_a00), \
517 ADD_FIXED_REG(en_3v3_fuse_a00), \
518 ADD_FIXED_REG(cdc_en_a00), \
519
520/* A01 specific */
521#define E1565_A01_FIXED_REG \
522 ADD_FIXED_REG(en_3v3_sys_a01), \
523 ADD_FIXED_REG(en_avdd_hdmi_usb_a01), \
524 ADD_FIXED_REG(en_1v8_cam_a01), \
525 ADD_FIXED_REG(en_vddio_vid_a01), \
526 ADD_FIXED_REG(en_3v3_modem_a01), \
527 ADD_FIXED_REG(en_vdd_pnl_a01), \
528 ADD_FIXED_REG(en_cam3_ldo_a01), \
529 ADD_FIXED_REG(en_vdd_com_a01), \
530 ADD_FIXED_REG(en_vdd_sdmmc1_a01), \
531 ADD_FIXED_REG(en_3v3_fuse_a01), \
532 ADD_FIXED_REG(cdc_en_a01), \
533
534/* Gpio switch regulator platform data for Kai A00 */
535static struct platform_device *fixed_reg_devs_a00[] = {
536 E1565_A00_FIXED_REG
537};
538
539/* Gpio switch regulator platform data for Kai A01 */
540static struct platform_device *fixed_reg_devs_a01[] = {
541 E1565_A01_FIXED_REG
542};
543
544static int __init kai_fixed_regulator_init(void)
545{
546 int i;
547 struct board_info board_info;
548 struct platform_device **fixed_reg_devs;
549 int nfixreg_devs;
550
551 tegra_get_board_info(&board_info);
552
553 if (board_info.fab == BOARD_FAB_A00) {
554 fixed_reg_devs = fixed_reg_devs_a00;
555 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a00);
556 } else {
557 fixed_reg_devs = fixed_reg_devs_a01;
558 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a01);
559 }
560
561 if (!machine_is_kai())
562 return 0;
563
564 for (i = 0; i < nfixreg_devs; ++i) {
565 int gpio_nr;
566 struct fixed_voltage_config *fixed_reg_pdata =
567 fixed_reg_devs[i]->dev.platform_data;
568 gpio_nr = fixed_reg_pdata->gpio;
569
570 if (gpio_nr < TEGRA_NR_GPIOS)
571 tegra_gpio_enable(gpio_nr);
572 }
573
574 return platform_add_devices(fixed_reg_devs, nfixreg_devs);
575}
576subsys_initcall_sync(kai_fixed_regulator_init);
577
578int __init kai_regulator_init(void)
579{
580 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
581 u32 pmc_ctrl;
582 int ret;
583
584 /* configure the power management controller to trigger PMU
585 * interrupts when low */
586
587 pmc_ctrl = readl(pmc + PMC_CTRL);
588 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
589
590 ret = kai_max77663_regulator_init();
591 if (ret < 0)
592 return ret;
593
594 return 0;
595}
596
597static void kai_board_suspend(int lp_state, enum suspend_stage stg)
598{
599 if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
600 tegra_console_uart_suspend();
601}
602
603static void kai_board_resume(int lp_state, enum resume_stage stg)
604{
605 if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
606 tegra_console_uart_resume();
607}
608
609static struct tegra_suspend_platform_data kai_suspend_data = {
610 .cpu_timer = 2000,
611 .cpu_off_timer = 200,
612 .suspend_mode = TEGRA_SUSPEND_LP0,
613 .core_timer = 0x7e7e,
614 .core_off_timer = 0,
615 .corereq_high = true,
616 .sysclkreq_high = true,
617 .cpu_lp2_min_residency = 2000,
618 .board_suspend = kai_board_suspend,
619 .board_resume = kai_board_resume,
620};
621
622int __init kai_suspend_init(void)
623{
624 tegra_init_suspend(&kai_suspend_data);
625 return 0;
626}
627
628static struct tegra_tsensor_pmu_data tpdata = {
629 .poweroff_reg_addr = 0x3F,
630 .poweroff_reg_data = 0x80,
631 .reset_tegra = 1,
632 .controller_type = 0,
633 .i2c_controller_id = 4,
634 .pinmux = 0,
635 .pmu_16bit_ops = 0,
636 .pmu_i2c_addr = 0x2D,
637};
638
639void __init kai_tsensor_init(void)
640{
641 tegra3_tsensor_init(&tpdata);
642}
643
644#ifdef CONFIG_TEGRA_EDP_LIMITS
645
646int __init kai_edp_init(void)
647{
648 unsigned int regulator_mA;
649
650 regulator_mA = get_maximum_cpu_current_supported();
651 if (!regulator_mA)
652 regulator_mA = 6000; /* regular T30/s */
653 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
654
655 tegra_init_cpu_edp_limits(regulator_mA);
656 return 0;
657}
658#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 11:32:38 -0400