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-rw-r--r--arch/arm/mach-tegra/board-enterprise-pinmux.c568
1 files changed, 568 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c
new file mode 100644
index 00000000000..8d18e3296af
--- /dev/null
+++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c
@@ -0,0 +1,568 @@
1/*
2 * arch/arm/mach-tegra/board-enterprise-pinmux.c
3 *
4 * Copyright (C) 2011 NVIDIA Corporation
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <mach/pinmux.h>
20#include "board.h"
21#include "board-enterprise.h"
22#include "gpio-names.h"
23
24#define DEFAULT_DRIVE(_name) \
25 { \
26 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
27 .hsm = TEGRA_HSM_DISABLE, \
28 .schmitt = TEGRA_SCHMITT_ENABLE, \
29 .drive = TEGRA_DRIVE_DIV_1, \
30 .pull_down = TEGRA_PULL_31, \
31 .pull_up = TEGRA_PULL_31, \
32 .slew_rising = TEGRA_SLEW_SLOWEST, \
33 .slew_falling = TEGRA_SLEW_SLOWEST, \
34 }
35/* Setting the drive strength of pins
36 * hsm: Enable High speed mode (ENABLE/DISABLE)
37 * Schimit: Enable/disable schimit (ENABLE/DISABLE)
38 * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
39 * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
40 * strength code. Value from 0 to 31.
41 * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
42 * strength code. Value from 0 to 31.
43 * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
44 * code 11 is least slewing of signal. code 00 is highest
45 * slewing of the signal.
46 * Value - FASTEST, FAST, SLOW, SLOWEST
47 * pullup_slew - Driver Output Pull-Down slew control code -
48 * code 11 is least slewing of signal. code 00 is highest
49 * slewing of the signal.
50 * Value - FASTEST, FAST, SLOW, SLOWEST
51 */
52#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
53 { \
54 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
55 .hsm = TEGRA_HSM_##_hsm, \
56 .schmitt = TEGRA_SCHMITT_##_schmitt, \
57 .drive = TEGRA_DRIVE_##_drive, \
58 .pull_down = TEGRA_PULL_##_pulldn_drive, \
59 .pull_up = TEGRA_PULL_##_pullup_drive, \
60 .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
61 .slew_falling = TEGRA_SLEW_##_pullup_slew, \
62 }
63
64/* !!!FIXME!!!! POPULATE THIS TABLE */
65static __initdata struct tegra_drive_pingroup_config enterprise_drive_pinmux[] = {
66 /* DEFAULT_DRIVE(<pin_group>), */
67 /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */
68
69 /* All I2C pins are driven to maximum drive strength */
70 /* GEN1 I2C */
71 SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
72
73 /* GEN2 I2C */
74 SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
75
76 /* CAM I2C */
77 SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
78
79 /* DDC I2C */
80 SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
81
82 /* PWR_I2C */
83 SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
84
85 /* UART3 */
86 SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
87};
88
89#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \
90 { \
91 .pingroup = TEGRA_PINGROUP_##_pingroup, \
92 .func = TEGRA_MUX_##_mux, \
93 .pupd = TEGRA_PUPD_##_pupd, \
94 .tristate = TEGRA_TRI_##_tri, \
95 .io = TEGRA_PIN_##_io, \
96 .lock = TEGRA_PIN_LOCK_DEFAULT, \
97 .od = TEGRA_PIN_OD_DEFAULT, \
98 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
99 }
100
101#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
102 { \
103 .pingroup = TEGRA_PINGROUP_##_pingroup, \
104 .func = TEGRA_MUX_##_mux, \
105 .pupd = TEGRA_PUPD_##_pupd, \
106 .tristate = TEGRA_TRI_##_tri, \
107 .io = TEGRA_PIN_##_io, \
108 .lock = TEGRA_PIN_LOCK_##_lock, \
109 .od = TEGRA_PIN_OD_##_od, \
110 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
111 }
112
113#define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
114 { \
115 .pingroup = TEGRA_PINGROUP_##_pingroup, \
116 .func = TEGRA_MUX_##_mux, \
117 .pupd = TEGRA_PUPD_##_pupd, \
118 .tristate = TEGRA_TRI_##_tri, \
119 .io = TEGRA_PIN_##_io, \
120 .lock = TEGRA_PIN_LOCK_##_lock, \
121 .od = TEGRA_PIN_OD_##_od, \
122 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
123 }
124
125#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
126 { \
127 .pingroup = TEGRA_PINGROUP_##_pingroup, \
128 .func = TEGRA_MUX_##_mux, \
129 .pupd = TEGRA_PUPD_##_pupd, \
130 .tristate = TEGRA_TRI_##_tri, \
131 .io = TEGRA_PIN_##_io, \
132 .lock = TEGRA_PIN_LOCK_##_lock, \
133 .od = TEGRA_PIN_OD_DEFAULT, \
134 .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \
135 }
136
137static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = {
138 /* SDMMC1 pinmux */
139 DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
140 DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT),
141 DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT),
142 DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT),
143 DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT),
144 DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT),
145
146 /* SDMMC3 pinmux */
147 DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
148 DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT),
149 DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT),
150 DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT),
151 DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT),
152 DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT),
153
154 /* SDMMC4 pinmux */
155 DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
156 DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT),
157 DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT),
158 DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT),
159 DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT),
160 DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT),
161 DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT),
162 DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT),
163 DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT),
164 DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT),
165 DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT),
166
167 /* I2C1 pinmux */
168 I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
169 I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
170
171 /* I2C2 pinmux */
172 I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
173 I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
174
175 /* I2C3 pinmux */
176 I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
177 I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
178
179 /* I2C4 pinmux */
180 I2C_PINMUX(DDC_SCL, I2C4, PULL_UP,NORMAL, INPUT, DISABLE, DISABLE),
181 I2C_PINMUX(DDC_SDA, I2C4, PULL_UP,NORMAL, INPUT, DISABLE, DISABLE),
182
183 /* Power I2C pinmux */
184 I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
185 I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
186
187 DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
188 DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
189 DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
190 DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
191 DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT),
192 DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT),
193 DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
194 DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT),
195 DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT),
196 DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT),
197 DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT),
198 DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT),
199 DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
200 DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
201 DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
202 DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
203 DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
204 DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
205 DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
206 DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT),
207 DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT),
208 DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT),
209 DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT),
210 DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT),
211 DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
212 DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT),
213 DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT),
214 DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT),
215 DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT),
216 DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, INPUT),
217 DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT),
218 DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT),
219 DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT),
220 DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT),
221 DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT),
222 DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT),
223 DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT),
224 DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT),
225 DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT),
226 DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT),
227 DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT),
228 DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT),
229 DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT),
230 DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT),
231 DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT),
232 DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT),
233 DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT),
234 DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
235 DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT),
236 DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT),
237 DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT),
238 DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT),
239 DEFAULT_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT),
240 DEFAULT_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT),
241 DEFAULT_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT),
242 DEFAULT_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT),
243 DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT),
244 DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT),
245
246 DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
247 DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
248 DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
249 DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
250 DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
251 DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
252 DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
253 DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
254 DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT),
255 DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT),
256 DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT),
257 DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT),
258 DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
259 DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT),
260 DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT),
261 DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
262 DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
263 DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
264 DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
265 DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
266 DEFAULT_PINMUX(GMI_AD9, NAND, NORMAL, NORMAL, OUTPUT),
267 DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
268 DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
272 DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT),
273 DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
274 DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
276 DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
277 DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
278 DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
279 DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT),
280 DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT),
281 DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT),
282 DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT),
283 DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT),
284 DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT),
285 DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT),
286 DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT),
287 DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT),
288 DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT),
289 DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT),
290 DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT),
291 DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT),
292 DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT),
293 DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
294 DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
295 DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
296 DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
297 DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
298 DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
299 DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
300 DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
301#if 0 /* For HDA realtek Codec */
302 DEFAULT_PINMUX(SPDIF_IN, DAP2, PULL_DOWN, NORMAL, INPUT),
303#else
304 DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
305#endif
306#if 0 /* For HDA realtek Codec */
307 DEFAULT_PINMUX(DAP2_FS, HDA, PULL_DOWN, NORMAL, INPUT),
308 DEFAULT_PINMUX(DAP2_DIN, HDA, PULL_DOWN, NORMAL, INPUT),
309 DEFAULT_PINMUX(DAP2_DOUT, HDA, PULL_DOWN, NORMAL, INPUT),
310 DEFAULT_PINMUX(DAP2_SCLK, HDA, PULL_DOWN, NORMAL, INPUT),
311#else
312 DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
313 DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
314 DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
315 DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
316#endif
317 DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT),
318 DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
319 DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
320 DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
321 DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
322 DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
323 DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
324 DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
325 DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
326 DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
327 DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
328 DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
329 DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
330 DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
331 CEC_PINMUX(HDMI_CEC, CEC, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE),
332 DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT),
333
334 /* Gpios */
335 /* SDMMC1 CD gpio */
336 DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT),
337 /* SDMMC1 WP gpio */
338 DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT),
339
340 /* Touch panel GPIO */
341 /* Touch IRQ */
342 DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT),
343
344 /* Touch RESET */
345 DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT),
346
347 DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT),
348
349 /* Power rails GPIO */
350 DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT),
351
352 VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
353 VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
354 VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
355 VI_PINMUX(VI_PCLK, RSVD1, PULL_UP, TRISTATE, INPUT, DISABLE, ENABLE),
356 VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
357 VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
358};
359
360static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = {
361 DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, OUTPUT),
362 DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, OUTPUT),
363};
364
365static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_common[] = {
366 DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, PULL_DOWN, TRISTATE, OUTPUT),
367 DEFAULT_PINMUX(CLK2_REQ, DAP, PULL_DOWN, TRISTATE, OUTPUT),
368 DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, PULL_DOWN, TRISTATE, OUTPUT),
369 DEFAULT_PINMUX(CLK3_REQ, DEV3, PULL_DOWN, TRISTATE, OUTPUT),
370 DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT),
371 DEFAULT_PINMUX(GPIO_PBB4, VGP4, PULL_DOWN, TRISTATE, OUTPUT),
372 DEFAULT_PINMUX(GPIO_PBB5, VGP5, PULL_DOWN, TRISTATE, OUTPUT),
373 DEFAULT_PINMUX(GPIO_PBB6, VGP6, PULL_DOWN, TRISTATE, OUTPUT),
374 DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, TRISTATE, OUTPUT),
375 DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, TRISTATE, OUTPUT),
376 DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, TRISTATE, OUTPUT),
377 DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, TRISTATE, OUTPUT),
378 DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, TRISTATE, OUTPUT),
379 DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, TRISTATE, OUTPUT),
380 DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, TRISTATE, OUTPUT),
381 DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, TRISTATE, OUTPUT),
382 DEFAULT_PINMUX(GMI_AD11, GMI, PULL_DOWN, TRISTATE, OUTPUT),
383 DEFAULT_PINMUX(GMI_CS0_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
384 DEFAULT_PINMUX(GMI_CS2_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
385 DEFAULT_PINMUX(GMI_CS3_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
386 DEFAULT_PINMUX(GMI_CS6_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
387 DEFAULT_PINMUX(GMI_CS7_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
388 DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, TRISTATE, OUTPUT),
389 DEFAULT_PINMUX(GMI_DQS, RSVD3, PULL_DOWN, TRISTATE, OUTPUT),
390 DEFAULT_PINMUX(GMI_RST_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
391 DEFAULT_PINMUX(GMI_WAIT, GMI, PULL_DOWN, TRISTATE, OUTPUT),
392 DEFAULT_PINMUX(GMI_WP_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),
393 DEFAULT_PINMUX(KB_ROW6, KBC, PULL_DOWN, TRISTATE, OUTPUT),
394 DEFAULT_PINMUX(KB_ROW7, KBC, PULL_DOWN, TRISTATE, OUTPUT),
395 DEFAULT_PINMUX(KB_ROW9, KBC, PULL_DOWN, TRISTATE, OUTPUT),
396 DEFAULT_PINMUX(KB_ROW11, KBC, PULL_DOWN, TRISTATE, OUTPUT),
397 DEFAULT_PINMUX(KB_ROW13, KBC, PULL_DOWN, TRISTATE, OUTPUT),
398 DEFAULT_PINMUX(KB_ROW14, KBC, PULL_DOWN, TRISTATE, OUTPUT),
399 DEFAULT_PINMUX(KB_ROW15, KBC, PULL_DOWN, TRISTATE, OUTPUT),
400 DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
401 DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
402 DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
403 DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
404 DEFAULT_PINMUX(LCD_SCK, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
405 DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
406 DEFAULT_PINMUX(LCD_SDIN, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
407 DEFAULT_PINMUX(CRT_HSYNC, CRT, PULL_DOWN, TRISTATE, OUTPUT),
408 DEFAULT_PINMUX(CRT_VSYNC, CRT, PULL_DOWN, TRISTATE, OUTPUT),
409 DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT),
410 DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT),
411 DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT),
412 DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT),
413 DEFAULT_PINMUX(SPDIF_OUT, SPDIF, PULL_DOWN, TRISTATE, OUTPUT),
414 DEFAULT_PINMUX(SPI1_CS0_N, SPI1, PULL_DOWN, TRISTATE, OUTPUT),
415 DEFAULT_PINMUX(SPI2_SCK, SPI2, PULL_DOWN, TRISTATE, OUTPUT),
416 DEFAULT_PINMUX(SPI2_CS0_N, SPI2, PULL_DOWN, TRISTATE, OUTPUT),
417 DEFAULT_PINMUX(SPI2_MOSI, SPI2, PULL_DOWN, TRISTATE, OUTPUT),
418 DEFAULT_PINMUX(SPI2_MISO, SPI2, PULL_DOWN, TRISTATE, OUTPUT),
419};
420
421static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_a02[] = {
422 DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
423 DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT),
424};
425
426static struct tegra_gpio_table gpio_table[] = {
427 { .gpio = TEGRA_GPIO_HP_DET, .enable = true },
428};
429
430struct pin_info_low_power_mode {
431 char name[16];
432 int gpio_nr;
433 bool is_gpio;
434 bool is_input;
435 int value; /* Value if it is output*/
436};
437
438#define PIN_GPIO_LPM(_name, _gpio, _is_input, _value) \
439 { \
440 .name = _name, \
441 .gpio_nr = _gpio, \
442 .is_gpio = true, \
443 .is_input = _is_input, \
444 .value = _value, \
445 }
446static __initdata struct pin_info_low_power_mode enterprise_unused_gpio_pins_common[] = {
447 PIN_GPIO_LPM("CLK2_OUT", TEGRA_GPIO_PW5, 0, 0),
448 PIN_GPIO_LPM("CLK2_REQ", TEGRA_GPIO_PCC5, 0, 0),
449 PIN_GPIO_LPM("CLK3_OUT", TEGRA_GPIO_PEE0, 0, 0),
450 PIN_GPIO_LPM("CLK3_REQ", TEGRA_GPIO_PEE1, 0, 0),
451 PIN_GPIO_LPM("CLK_32K_OUT", TEGRA_GPIO_PA0, 0, 0),
452 PIN_GPIO_LPM("GPIO_PBB4", TEGRA_GPIO_PBB4, 0, 0),
453 PIN_GPIO_LPM("GPIO_PBB5", TEGRA_GPIO_PBB5, 0, 0),
454 PIN_GPIO_LPM("GPIO_PBB6", TEGRA_GPIO_PBB6, 0, 0),
455 PIN_GPIO_LPM("GMI_AD0", TEGRA_GPIO_PG0, 0, 0),
456 PIN_GPIO_LPM("GMI_AD1", TEGRA_GPIO_PG1, 0, 0),
457 PIN_GPIO_LPM("GMI_AD2", TEGRA_GPIO_PG2, 0, 0),
458 PIN_GPIO_LPM("GMI_AD3", TEGRA_GPIO_PG3, 0, 0),
459 PIN_GPIO_LPM("GMI_AD4", TEGRA_GPIO_PG4, 0, 0),
460 PIN_GPIO_LPM("GMI_AD5", TEGRA_GPIO_PG5, 0, 0),
461 PIN_GPIO_LPM("GMI_AD6", TEGRA_GPIO_PG6, 0, 0),
462 PIN_GPIO_LPM("GMI_AD7", TEGRA_GPIO_PG7, 0, 0),
463 PIN_GPIO_LPM("GMI_AD11", TEGRA_GPIO_PH3, 0, 0),
464 PIN_GPIO_LPM("GMI_CS0_N", TEGRA_GPIO_PJ0, 0, 0),
465 PIN_GPIO_LPM("GMI_CS2_N", TEGRA_GPIO_PK3, 0, 0),
466 PIN_GPIO_LPM("GMI_CS3_N", TEGRA_GPIO_PK4, 0, 0),
467 PIN_GPIO_LPM("GMI_CS6_N", TEGRA_GPIO_PI3, 0, 0),
468 PIN_GPIO_LPM("GMI_CS7_N", TEGRA_GPIO_PI6, 0, 0),
469 PIN_GPIO_LPM("GMI_ADV", TEGRA_GPIO_PK0, 0, 0),
470 PIN_GPIO_LPM("GMI_CLK", TEGRA_GPIO_PK1, 0, 0),
471 PIN_GPIO_LPM("GMI_DQS", TEGRA_GPIO_PI2, 0, 0),
472 PIN_GPIO_LPM("GMI_RST_N", TEGRA_GPIO_PI4, 0, 0),
473 PIN_GPIO_LPM("GMI_WAIT", TEGRA_GPIO_PI7, 0, 0),
474 PIN_GPIO_LPM("GMI_WP_N", TEGRA_GPIO_PC7, 0, 0),
475 PIN_GPIO_LPM("KB_ROW6", TEGRA_GPIO_PR6, 0, 0),
476 PIN_GPIO_LPM("KB_ROW7", TEGRA_GPIO_PR7, 0, 0),
477 PIN_GPIO_LPM("KB_ROW9", TEGRA_GPIO_PS1, 0, 0),
478 PIN_GPIO_LPM("KB_ROW11", TEGRA_GPIO_PS3, 0, 0),
479 PIN_GPIO_LPM("KB_ROW13", TEGRA_GPIO_PS5, 0, 0),
480 PIN_GPIO_LPM("KB_ROW14", TEGRA_GPIO_PS6, 0, 0),
481 PIN_GPIO_LPM("KB_ROW15", TEGRA_GPIO_PS7, 0, 0),
482 PIN_GPIO_LPM("LCD_PCLK", TEGRA_GPIO_PB3, 0, 0),
483 PIN_GPIO_LPM("LCD_WR_N", TEGRA_GPIO_PZ3, 0, 0),
484 PIN_GPIO_LPM("LCD_HSYNC", TEGRA_GPIO_PJ3, 0, 0),
485 PIN_GPIO_LPM("LCD_VSYNC", TEGRA_GPIO_PJ4, 0, 0),
486 PIN_GPIO_LPM("LCD_SCK", TEGRA_GPIO_PZ4, 0, 0),
487 PIN_GPIO_LPM("LCD_SDOUT", TEGRA_GPIO_PN5, 0, 0),
488 PIN_GPIO_LPM("LCD_SDIN", TEGRA_GPIO_PZ2, 0, 0),
489 PIN_GPIO_LPM("CRT_HSYNC", TEGRA_GPIO_PV6, 0, 0),
490 PIN_GPIO_LPM("CRT_VSYNC", TEGRA_GPIO_PV7, 0, 0),
491 PIN_GPIO_LPM("SDMMC3_DAT4", TEGRA_GPIO_PD1, 0, 0),
492 PIN_GPIO_LPM("SDMMC3_DAT5", TEGRA_GPIO_PD0, 0, 0),
493 PIN_GPIO_LPM("SDMMC3_DAT6", TEGRA_GPIO_PD3, 0, 0),
494 PIN_GPIO_LPM("SDMMC3_DAT7", TEGRA_GPIO_PD4, 0, 0),
495 PIN_GPIO_LPM("SPDIF_OUT", TEGRA_GPIO_PK5, 0, 0),
496 PIN_GPIO_LPM("SPI1_CS0_N", TEGRA_GPIO_PX6, 0, 0),
497 PIN_GPIO_LPM("SPI2_SCK", TEGRA_GPIO_PX2, 0, 0),
498 PIN_GPIO_LPM("SPI2_CS0_N", TEGRA_GPIO_PX3, 0, 0),
499 PIN_GPIO_LPM("SPI2_MOSI", TEGRA_GPIO_PX0, 0, 0),
500 PIN_GPIO_LPM("SPI2_MISO", TEGRA_GPIO_PX1, 0, 0),
501};
502
503static __initdata struct pin_info_low_power_mode enterprise_unused_gpio_pins_a02[] = {
504 PIN_GPIO_LPM("LCD_D10", TEGRA_GPIO_PF2, 0, 0),
505 PIN_GPIO_LPM("LCD_PWR0", TEGRA_GPIO_PB2, 0, 0),
506};
507
508static void enterprise_set_unused_pin_gpio(struct pin_info_low_power_mode *lpm_pin_info,
509 int list_count)
510{
511 int i;
512 struct pin_info_low_power_mode *pin_info;
513 int ret;
514
515 for (i = 0; i < list_count; ++i) {
516 pin_info = (struct pin_info_low_power_mode *)(lpm_pin_info + i);
517 if (!pin_info->is_gpio)
518 continue;
519
520 ret = gpio_request(pin_info->gpio_nr, pin_info->name);
521 if (ret < 0) {
522 pr_err("%s() Error in gpio_request() for gpio %d\n",
523 __func__, pin_info->gpio_nr);
524 continue;
525 }
526 if (pin_info->is_input)
527 ret = gpio_direction_input(pin_info->gpio_nr);
528 else
529 ret = gpio_direction_output(pin_info->gpio_nr,
530 pin_info->value);
531 if (ret < 0) {
532 pr_err("%s() Error in setting gpio %d to in/out\n",
533 __func__, pin_info->gpio_nr);
534 gpio_free(pin_info->gpio_nr);
535 continue;
536 }
537 tegra_gpio_enable(pin_info->gpio_nr);
538 }
539}
540
541int __init enterprise_pinmux_init(void)
542{
543 struct board_info board_info;
544 tegra_get_board_info(&board_info);
545
546 tegra_pinmux_config_table(enterprise_pinmux_common,
547 ARRAY_SIZE(enterprise_pinmux_common));
548 tegra_drive_pinmux_config_table(enterprise_drive_pinmux,
549 ARRAY_SIZE(enterprise_drive_pinmux));
550 tegra_pinmux_config_table(enterprise_unused_pinmux_common,
551 ARRAY_SIZE(enterprise_unused_pinmux_common));
552
553 tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
554 enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_common,
555 ARRAY_SIZE(enterprise_unused_gpio_pins_common));
556
557 if (board_info.fab < BOARD_FAB_A03) {
558 tegra_pinmux_config_table(enterprise_unused_pinmux_a02,
559 ARRAY_SIZE(enterprise_unused_pinmux_a02));
560 enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_a02,
561 ARRAY_SIZE(enterprise_unused_gpio_pins_a02));
562 } else {
563 tegra_pinmux_config_table(enterprise_pinmux_a03,
564 ARRAY_SIZE(enterprise_pinmux_a03));
565 }
566
567 return 0;
568}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-23 19:53:11 -0400