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Diffstat (limited to 'arch/arm/mach-tegra/board-enterprise-memory.c')
-rw-r--r--arch/arm/mach-tegra/board-enterprise-memory.c761
1 files changed, 761 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c
new file mode 100644
index 00000000000..fca1a08ed70
--- /dev/null
+++ b/arch/arm/mach-tegra/board-enterprise-memory.c
@@ -0,0 +1,761 @@
1/*
2 * Copyright (C) 2011 NVIDIA, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16 * 02111-1307, USA
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21
22#include "board-enterprise.h"
23#include "tegra3_emc.h"
24#include "board.h"
25
26
27static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = {
28 {
29 0x32, /* Rev 3.2 */
30 12750, /* SDRAM frequency */
31 {
32 0x00000000, /* EMC_RC */
33 0x00000001, /* EMC_RFC */
34 0x00000002, /* EMC_RAS */
35 0x00000002, /* EMC_RP */
36 0x00000004, /* EMC_R2W */
37 0x00000004, /* EMC_W2R */
38 0x00000001, /* EMC_R2P */
39 0x00000005, /* EMC_W2P */
40 0x00000002, /* EMC_RD_RCD */
41 0x00000002, /* EMC_WR_RCD */
42 0x00000001, /* EMC_RRD */
43 0x00000001, /* EMC_REXT */
44 0x00000000, /* EMC_WEXT */
45 0x00000001, /* EMC_WDV */
46 0x00000003, /* EMC_QUSE */
47 0x00000001, /* EMC_QRST */
48 0x00000009, /* EMC_QSAFE */
49 0x0000000a, /* EMC_RDV */
50 0x0000002f, /* EMC_REFRESH */
51 0x00000000, /* EMC_BURST_REFRESH_NUM */
52 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
53 0x00000001, /* EMC_PDEX2WR */
54 0x00000001, /* EMC_PDEX2RD */
55 0x00000002, /* EMC_PCHG2PDEN */
56 0x00000000, /* EMC_ACT2PDEN */
57 0x00000001, /* EMC_AR2PDEN */
58 0x00000007, /* EMC_RW2PDEN */
59 0x00000002, /* EMC_TXSR */
60 0x00000002, /* EMC_TXSRDLL */
61 0x00000003, /* EMC_TCKE */
62 0x00000008, /* EMC_TFAW */
63 0x00000004, /* EMC_TRPAB */
64 0x00000001, /* EMC_TCLKSTABLE */
65 0x00000002, /* EMC_TCLKSTOP */
66 0x00000036, /* EMC_TREFBW */
67 0x00000004, /* EMC_QUSE_EXTRA */
68 0x00000004, /* EMC_FBIO_CFG6 */
69 0x00000000, /* EMC_ODT_WRITE */
70 0x00000000, /* EMC_ODT_READ */
71 0x00004282, /* EMC_FBIO_CFG5 */
72 0x007800a4, /* EMC_CFG_DIG_DLL */
73 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
74 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
75 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
76 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
77 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
78 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
79 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
80 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
81 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
82 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
83 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
84 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
85 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
86 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
87 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
88 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
89 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
90 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
91 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
92 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
93 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
94 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
95 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
96 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
97 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
98 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
99 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
100 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
101 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
102 0x00100220, /* EMC_XM2CMDPADCTRL */
103 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
104 0x00000000, /* EMC_XM2DQPADCTRL2 */
105 0x77ffc004, /* EMC_XM2CLKPADCTRL */
106 0x01f1f008, /* EMC_XM2COMPPADCTRL */
107 0x00000000, /* EMC_XM2VTTGENPADCTRL */
108 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
109 0x08000068, /* EMC_XM2QUSEPADCTRL */
110 0x08000000, /* EMC_XM2DQSPADCTRL3 */
111 0x00000802, /* EMC_CTT_TERM_CTRL */
112 0x00064000, /* EMC_ZCAL_INTERVAL */
113 0x00000009, /* EMC_ZCAL_WAIT_CNT */
114 0x00090009, /* EMC_MRS_WAIT_CNT */
115 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
116 0x00000000, /* EMC_CTT */
117 0x00000000, /* EMC_CTT_DURATION */
118 0x80000164, /* EMC_DYN_SELF_REF_CONTROL */
119 0x00050001, /* MC_EMEM_ARB_CFG */
120 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
121 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
122 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
123 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
124 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
125 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
126 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
127 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
128 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
129 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
130 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
131 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
132 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
133 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
134 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
135 0x77230303, /* MC_EMEM_ARB_MISC0 */
136 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
137 0x50000000, /* EMC_FBIO_SPARE */
138 0xff00ff00, /* EMC_CFG_RSV */
139 },
140 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
141 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
142 0x00000001, /* EMC_CFG.PERIODIC_QRST */
143 0x00000000, /* Mode Register 0 */
144 0x00010022, /* Mode Register 1 */
145 0x00020001, /* Mode Register 2 */
146 0x00000001, /* EMC_CFG.DYN_SELF_REF */
147 },
148 {
149 0x32, /* Rev 3.2 */
150 25500, /* SDRAM frequency */
151 {
152 0x00000001, /* EMC_RC */
153 0x00000003, /* EMC_RFC */
154 0x00000002, /* EMC_RAS */
155 0x00000002, /* EMC_RP */
156 0x00000004, /* EMC_R2W */
157 0x00000004, /* EMC_W2R */
158 0x00000001, /* EMC_R2P */
159 0x00000005, /* EMC_W2P */
160 0x00000002, /* EMC_RD_RCD */
161 0x00000002, /* EMC_WR_RCD */
162 0x00000001, /* EMC_RRD */
163 0x00000001, /* EMC_REXT */
164 0x00000000, /* EMC_WEXT */
165 0x00000001, /* EMC_WDV */
166 0x00000003, /* EMC_QUSE */
167 0x00000001, /* EMC_QRST */
168 0x00000009, /* EMC_QSAFE */
169 0x0000000a, /* EMC_RDV */
170 0x0000005e, /* EMC_REFRESH */
171 0x00000000, /* EMC_BURST_REFRESH_NUM */
172 0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
173 0x00000001, /* EMC_PDEX2WR */
174 0x00000001, /* EMC_PDEX2RD */
175 0x00000002, /* EMC_PCHG2PDEN */
176 0x00000000, /* EMC_ACT2PDEN */
177 0x00000001, /* EMC_AR2PDEN */
178 0x00000007, /* EMC_RW2PDEN */
179 0x00000004, /* EMC_TXSR */
180 0x00000004, /* EMC_TXSRDLL */
181 0x00000003, /* EMC_TCKE */
182 0x00000008, /* EMC_TFAW */
183 0x00000004, /* EMC_TRPAB */
184 0x00000004, /* EMC_TCLKSTABLE */
185 0x00000002, /* EMC_TCLKSTOP */
186 0x00000068, /* EMC_TREFBW */
187 0x00000004, /* EMC_QUSE_EXTRA */
188 0x00000004, /* EMC_FBIO_CFG6 */
189 0x00000000, /* EMC_ODT_WRITE */
190 0x00000000, /* EMC_ODT_READ */
191 0x00004282, /* EMC_FBIO_CFG5 */
192 0x007800a4, /* EMC_CFG_DIG_DLL */
193 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
194 0x00090000, /* EMC_DLL_XFORM_DQS0 */
195 0x00090000, /* EMC_DLL_XFORM_DQS1 */
196 0x00090000, /* EMC_DLL_XFORM_DQS2 */
197 0x00090000, /* EMC_DLL_XFORM_DQS3 */
198 0x00000010, /* EMC_DLL_XFORM_DQS4 */
199 0x00000010, /* EMC_DLL_XFORM_DQS5 */
200 0x00000010, /* EMC_DLL_XFORM_DQS6 */
201 0x00000010, /* EMC_DLL_XFORM_DQS7 */
202 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
203 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
204 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
205 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
206 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
207 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
208 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
209 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
210 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
211 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
212 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
213 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
214 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
215 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
216 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
217 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
218 0x00088000, /* EMC_DLL_XFORM_DQ0 */
219 0x00088000, /* EMC_DLL_XFORM_DQ1 */
220 0x00088000, /* EMC_DLL_XFORM_DQ2 */
221 0x00088000, /* EMC_DLL_XFORM_DQ3 */
222 0x00100220, /* EMC_XM2CMDPADCTRL */
223 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
224 0x00000000, /* EMC_XM2DQPADCTRL2 */
225 0x77ffc004, /* EMC_XM2CLKPADCTRL */
226 0x01f1f008, /* EMC_XM2COMPPADCTRL */
227 0x00000000, /* EMC_XM2VTTGENPADCTRL */
228 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
229 0x08000068, /* EMC_XM2QUSEPADCTRL */
230 0x08000000, /* EMC_XM2DQSPADCTRL3 */
231 0x00000802, /* EMC_CTT_TERM_CTRL */
232 0x00064000, /* EMC_ZCAL_INTERVAL */
233 0x0000000a, /* EMC_ZCAL_WAIT_CNT */
234 0x00090009, /* EMC_MRS_WAIT_CNT */
235 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
236 0x00000000, /* EMC_CTT */
237 0x00000000, /* EMC_CTT_DURATION */
238 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
239 0x00020001, /* MC_EMEM_ARB_CFG */
240 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
241 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
242 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
243 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
244 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
245 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
246 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
247 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
248 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
249 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
250 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
251 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
252 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
253 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
254 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
255 0x74030303, /* MC_EMEM_ARB_MISC0 */
256 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
257 0x50000000, /* EMC_FBIO_SPARE */
258 0xff00ff00, /* EMC_CFG_RSV */
259 },
260 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
261 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
262 0x00000001, /* EMC_CFG.PERIODIC_QRST */
263 0x00000000, /* Mode Register 0 */
264 0x00010022, /* Mode Register 1 */
265 0x00020001, /* Mode Register 2 */
266 0x00000001, /* EMC_CFG.DYN_SELF_REF */
267 },
268 {
269 0x32, /* Rev 3.2 */
270 51000, /* SDRAM frequency */
271 {
272 0x00000003, /* EMC_RC */
273 0x00000006, /* EMC_RFC */
274 0x00000002, /* EMC_RAS */
275 0x00000002, /* EMC_RP */
276 0x00000004, /* EMC_R2W */
277 0x00000004, /* EMC_W2R */
278 0x00000001, /* EMC_R2P */
279 0x00000005, /* EMC_W2P */
280 0x00000002, /* EMC_RD_RCD */
281 0x00000002, /* EMC_WR_RCD */
282 0x00000001, /* EMC_RRD */
283 0x00000001, /* EMC_REXT */
284 0x00000000, /* EMC_WEXT */
285 0x00000001, /* EMC_WDV */
286 0x00000003, /* EMC_QUSE */
287 0x00000001, /* EMC_QRST */
288 0x00000009, /* EMC_QSAFE */
289 0x0000000a, /* EMC_RDV */
290 0x000000c0, /* EMC_REFRESH */
291 0x00000000, /* EMC_BURST_REFRESH_NUM */
292 0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
293 0x00000001, /* EMC_PDEX2WR */
294 0x00000001, /* EMC_PDEX2RD */
295 0x00000002, /* EMC_PCHG2PDEN */
296 0x00000000, /* EMC_ACT2PDEN */
297 0x00000001, /* EMC_AR2PDEN */
298 0x00000007, /* EMC_RW2PDEN */
299 0x00000008, /* EMC_TXSR */
300 0x00000008, /* EMC_TXSRDLL */
301 0x00000003, /* EMC_TCKE */
302 0x00000008, /* EMC_TFAW */
303 0x00000004, /* EMC_TRPAB */
304 0x00000004, /* EMC_TCLKSTABLE */
305 0x00000002, /* EMC_TCLKSTOP */
306 0x000000d5, /* EMC_TREFBW */
307 0x00000004, /* EMC_QUSE_EXTRA */
308 0x00000004, /* EMC_FBIO_CFG6 */
309 0x00000000, /* EMC_ODT_WRITE */
310 0x00000000, /* EMC_ODT_READ */
311 0x00004282, /* EMC_FBIO_CFG5 */
312 0x007800a4, /* EMC_CFG_DIG_DLL */
313 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
314 0x00090000, /* EMC_DLL_XFORM_DQS0 */
315 0x00090000, /* EMC_DLL_XFORM_DQS1 */
316 0x00090000, /* EMC_DLL_XFORM_DQS2 */
317 0x00090000, /* EMC_DLL_XFORM_DQS3 */
318 0x00000010, /* EMC_DLL_XFORM_DQS4 */
319 0x00000010, /* EMC_DLL_XFORM_DQS5 */
320 0x00000010, /* EMC_DLL_XFORM_DQS6 */
321 0x00000010, /* EMC_DLL_XFORM_DQS7 */
322 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
323 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
324 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
325 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
326 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
327 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
328 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
329 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
330 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
331 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
332 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
333 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
334 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
335 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
336 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
337 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
338 0x00088000, /* EMC_DLL_XFORM_DQ0 */
339 0x00088000, /* EMC_DLL_XFORM_DQ1 */
340 0x00088000, /* EMC_DLL_XFORM_DQ2 */
341 0x00088000, /* EMC_DLL_XFORM_DQ3 */
342 0x00100220, /* EMC_XM2CMDPADCTRL */
343 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
344 0x00000000, /* EMC_XM2DQPADCTRL2 */
345 0x77ffc004, /* EMC_XM2CLKPADCTRL */
346 0x01f1f008, /* EMC_XM2COMPPADCTRL */
347 0x00000000, /* EMC_XM2VTTGENPADCTRL */
348 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
349 0x08000068, /* EMC_XM2QUSEPADCTRL */
350 0x08000000, /* EMC_XM2DQSPADCTRL3 */
351 0x00000802, /* EMC_CTT_TERM_CTRL */
352 0x00064000, /* EMC_ZCAL_INTERVAL */
353 0x00000013, /* EMC_ZCAL_WAIT_CNT */
354 0x00090009, /* EMC_MRS_WAIT_CNT */
355 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
356 0x00000000, /* EMC_CTT */
357 0x00000000, /* EMC_CTT_DURATION */
358 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
359 0x00010001, /* MC_EMEM_ARB_CFG */
360 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
361 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
362 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
363 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
364 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
365 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
366 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
367 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
368 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
369 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
370 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
371 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
372 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
373 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
374 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
375 0x72c30303, /* MC_EMEM_ARB_MISC0 */
376 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
377 0x50000000, /* EMC_FBIO_SPARE */
378 0xff00ff00, /* EMC_CFG_RSV */
379 },
380 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
381 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
382 0x00000001, /* EMC_CFG.PERIODIC_QRST */
383 0x00000000, /* Mode Register 0 */
384 0x00010022, /* Mode Register 1 */
385 0x00020001, /* Mode Register 2 */
386 0x00000001, /* EMC_CFG.DYN_SELF_REF */
387 },
388 {
389 0x32, /* Rev 3.2 */
390 102000, /* SDRAM frequency */
391 {
392 0x00000006, /* EMC_RC */
393 0x0000000d, /* EMC_RFC */
394 0x00000004, /* EMC_RAS */
395 0x00000002, /* EMC_RP */
396 0x00000004, /* EMC_R2W */
397 0x00000004, /* EMC_W2R */
398 0x00000001, /* EMC_R2P */
399 0x00000005, /* EMC_W2P */
400 0x00000002, /* EMC_RD_RCD */
401 0x00000002, /* EMC_WR_RCD */
402 0x00000001, /* EMC_RRD */
403 0x00000001, /* EMC_REXT */
404 0x00000000, /* EMC_WEXT */
405 0x00000001, /* EMC_WDV */
406 0x00000003, /* EMC_QUSE */
407 0x00000001, /* EMC_QRST */
408 0x00000009, /* EMC_QSAFE */
409 0x0000000a, /* EMC_RDV */
410 0x00000181, /* EMC_REFRESH */
411 0x00000000, /* EMC_BURST_REFRESH_NUM */
412 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
413 0x00000001, /* EMC_PDEX2WR */
414 0x00000001, /* EMC_PDEX2RD */
415 0x00000002, /* EMC_PCHG2PDEN */
416 0x00000000, /* EMC_ACT2PDEN */
417 0x00000001, /* EMC_AR2PDEN */
418 0x00000007, /* EMC_RW2PDEN */
419 0x0000000f, /* EMC_TXSR */
420 0x0000000f, /* EMC_TXSRDLL */
421 0x00000003, /* EMC_TCKE */
422 0x00000008, /* EMC_TFAW */
423 0x00000004, /* EMC_TRPAB */
424 0x00000004, /* EMC_TCLKSTABLE */
425 0x00000002, /* EMC_TCLKSTOP */
426 0x000001a9, /* EMC_TREFBW */
427 0x00000004, /* EMC_QUSE_EXTRA */
428 0x00000006, /* EMC_FBIO_CFG6 */
429 0x00000000, /* EMC_ODT_WRITE */
430 0x00000000, /* EMC_ODT_READ */
431 0x00004282, /* EMC_FBIO_CFG5 */
432 0x007800a4, /* EMC_CFG_DIG_DLL */
433 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
434 0x00090000, /* EMC_DLL_XFORM_DQS0 */
435 0x00090000, /* EMC_DLL_XFORM_DQS1 */
436 0x00090000, /* EMC_DLL_XFORM_DQS2 */
437 0x00090000, /* EMC_DLL_XFORM_DQS3 */
438 0x00000010, /* EMC_DLL_XFORM_DQS4 */
439 0x00000010, /* EMC_DLL_XFORM_DQS5 */
440 0x00000010, /* EMC_DLL_XFORM_DQS6 */
441 0x00000010, /* EMC_DLL_XFORM_DQS7 */
442 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
443 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
444 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
445 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
446 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
447 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
448 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
449 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
450 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
451 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
452 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
453 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
454 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
455 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
456 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
457 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
458 0x00088000, /* EMC_DLL_XFORM_DQ0 */
459 0x00088000, /* EMC_DLL_XFORM_DQ1 */
460 0x00088000, /* EMC_DLL_XFORM_DQ2 */
461 0x00088000, /* EMC_DLL_XFORM_DQ3 */
462 0x00100220, /* EMC_XM2CMDPADCTRL */
463 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
464 0x00000000, /* EMC_XM2DQPADCTRL2 */
465 0x77ffc004, /* EMC_XM2CLKPADCTRL */
466 0x01f1f008, /* EMC_XM2COMPPADCTRL */
467 0x00000000, /* EMC_XM2VTTGENPADCTRL */
468 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
469 0x08000068, /* EMC_XM2QUSEPADCTRL */
470 0x08000000, /* EMC_XM2DQSPADCTRL3 */
471 0x00000802, /* EMC_CTT_TERM_CTRL */
472 0x00064000, /* EMC_ZCAL_INTERVAL */
473 0x00000025, /* EMC_ZCAL_WAIT_CNT */
474 0x00090009, /* EMC_MRS_WAIT_CNT */
475 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
476 0x00000000, /* EMC_CTT */
477 0x00000000, /* EMC_CTT_DURATION */
478 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
479 0x00000001, /* MC_EMEM_ARB_CFG */
480 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
481 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
482 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
483 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
484 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
485 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
486 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
487 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
488 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
489 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
490 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
491 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
492 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
493 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
494 0x00060403, /* MC_EMEM_ARB_DA_COVERS */
495 0x72430504, /* MC_EMEM_ARB_MISC0 */
496 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
497 0x50000000, /* EMC_FBIO_SPARE */
498 0xff00ff00, /* EMC_CFG_RSV */
499 },
500 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
501 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
502 0x00000001, /* EMC_CFG.PERIODIC_QRST */
503 0x00000000, /* Mode Register 0 */
504 0x00010022, /* Mode Register 1 */
505 0x00020001, /* Mode Register 2 */
506 0x00000001, /* EMC_CFG.DYN_SELF_REF */
507 },
508 {
509 0x32, /* Rev 3.2 */
510 204000, /* SDRAM frequency */
511 {
512 0x0000000c, /* EMC_RC */
513 0x0000001a, /* EMC_RFC */
514 0x00000008, /* EMC_RAS */
515 0x00000003, /* EMC_RP */
516 0x00000005, /* EMC_R2W */
517 0x00000004, /* EMC_W2R */
518 0x00000001, /* EMC_R2P */
519 0x00000006, /* EMC_W2P */
520 0x00000003, /* EMC_RD_RCD */
521 0x00000003, /* EMC_WR_RCD */
522 0x00000002, /* EMC_RRD */
523 0x00000002, /* EMC_REXT */
524 0x00000000, /* EMC_WEXT */
525 0x00000001, /* EMC_WDV */
526 0x00000003, /* EMC_QUSE */
527 0x00000001, /* EMC_QRST */
528 0x0000000b, /* EMC_QSAFE */
529 0x0000000a, /* EMC_RDV */
530 0x00000303, /* EMC_REFRESH */
531 0x00000000, /* EMC_BURST_REFRESH_NUM */
532 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
533 0x00000001, /* EMC_PDEX2WR */
534 0x00000001, /* EMC_PDEX2RD */
535 0x00000003, /* EMC_PCHG2PDEN */
536 0x00000000, /* EMC_ACT2PDEN */
537 0x00000001, /* EMC_AR2PDEN */
538 0x00000007, /* EMC_RW2PDEN */
539 0x0000001d, /* EMC_TXSR */
540 0x0000001d, /* EMC_TXSRDLL */
541 0x00000004, /* EMC_TCKE */
542 0x0000000b, /* EMC_TFAW */
543 0x00000005, /* EMC_TRPAB */
544 0x00000004, /* EMC_TCLKSTABLE */
545 0x00000002, /* EMC_TCLKSTOP */
546 0x00000351, /* EMC_TREFBW */
547 0x00000004, /* EMC_QUSE_EXTRA */
548 0x00000006, /* EMC_FBIO_CFG6 */
549 0x00000000, /* EMC_ODT_WRITE */
550 0x00000000, /* EMC_ODT_READ */
551 0x00004282, /* EMC_FBIO_CFG5 */
552 0x004400a4, /* EMC_CFG_DIG_DLL */
553 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
554 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
555 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
556 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
557 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
558 0x00000010, /* EMC_DLL_XFORM_DQS4 */
559 0x00000010, /* EMC_DLL_XFORM_DQS5 */
560 0x00000010, /* EMC_DLL_XFORM_DQS6 */
561 0x00000010, /* EMC_DLL_XFORM_DQS7 */
562 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
563 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
564 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
565 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
566 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
567 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
568 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
569 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
570 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
571 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
572 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
573 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
574 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
575 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
576 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
577 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
578 0x00088000, /* EMC_DLL_XFORM_DQ0 */
579 0x00088000, /* EMC_DLL_XFORM_DQ1 */
580 0x00088000, /* EMC_DLL_XFORM_DQ2 */
581 0x00088000, /* EMC_DLL_XFORM_DQ3 */
582 0x000f0220, /* EMC_XM2CMDPADCTRL */
583 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
584 0x00000000, /* EMC_XM2DQPADCTRL2 */
585 0x77ffc004, /* EMC_XM2CLKPADCTRL */
586 0x01f1f008, /* EMC_XM2COMPPADCTRL */
587 0x00000000, /* EMC_XM2VTTGENPADCTRL */
588 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
589 0x08000068, /* EMC_XM2QUSEPADCTRL */
590 0x08000000, /* EMC_XM2DQSPADCTRL3 */
591 0x00000802, /* EMC_CTT_TERM_CTRL */
592 0x00064000, /* EMC_ZCAL_INTERVAL */
593 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
594 0x00090009, /* EMC_MRS_WAIT_CNT */
595 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
596 0x00000000, /* EMC_CTT */
597 0x00000000, /* EMC_CTT_DURATION */
598 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
599 0x00000003, /* MC_EMEM_ARB_CFG */
600 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
601 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
602 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
603 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
604 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
605 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
606 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
607 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
608 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
609 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
610 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
611 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
612 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
613 0x02030001, /* MC_EMEM_ARB_DA_TURNS */
614 0x00070506, /* MC_EMEM_ARB_DA_COVERS */
615 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
616 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
617 0x50000000, /* EMC_FBIO_SPARE */
618 0xff00ff00, /* EMC_CFG_RSV */
619 },
620 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
621 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
622 0x00000001, /* EMC_CFG.PERIODIC_QRST */
623 0x00000000, /* Mode Register 0 */
624 0x00010042, /* Mode Register 1 */
625 0x00020001, /* Mode Register 2 */
626 0x00000001, /* EMC_CFG.DYN_SELF_REF */
627 },
628 {
629 0x32, /* Rev 3.2 */
630 400000, /* SDRAM frequency */
631 {
632 0x00000017, /* EMC_RC */
633 0x00000033, /* EMC_RFC */
634 0x00000010, /* EMC_RAS */
635 0x00000007, /* EMC_RP */
636 0x00000007, /* EMC_R2W */
637 0x00000007, /* EMC_W2R */
638 0x00000002, /* EMC_R2P */
639 0x0000000a, /* EMC_W2P */
640 0x00000007, /* EMC_RD_RCD */
641 0x00000007, /* EMC_WR_RCD */
642 0x00000003, /* EMC_RRD */
643 0x00000002, /* EMC_REXT */
644 0x00000000, /* EMC_WEXT */
645 0x00000003, /* EMC_WDV */
646 0x00000007, /* EMC_QUSE */
647 0x00000004, /* EMC_QRST */
648 0x0000000b, /* EMC_QSAFE */
649 0x0000000e, /* EMC_RDV */
650 0x000005e9, /* EMC_REFRESH */
651 0x00000000, /* EMC_BURST_REFRESH_NUM */
652 0x0000017a, /* EMC_PRE_REFRESH_REQ_CNT */
653 0x00000002, /* EMC_PDEX2WR */
654 0x00000002, /* EMC_PDEX2RD */
655 0x00000007, /* EMC_PCHG2PDEN */
656 0x00000000, /* EMC_ACT2PDEN */
657 0x00000001, /* EMC_AR2PDEN */
658 0x0000000c, /* EMC_RW2PDEN */
659 0x00000038, /* EMC_TXSR */
660 0x00000038, /* EMC_TXSRDLL */
661 0x00000006, /* EMC_TCKE */
662 0x00000014, /* EMC_TFAW */
663 0x00000009, /* EMC_TRPAB */
664 0x00000004, /* EMC_TCLKSTABLE */
665 0x00000002, /* EMC_TCLKSTOP */
666 0x00000680, /* EMC_TREFBW */
667 0x00000000, /* EMC_QUSE_EXTRA */
668 0x00000006, /* EMC_FBIO_CFG6 */
669 0x00000000, /* EMC_ODT_WRITE */
670 0x00000000, /* EMC_ODT_READ */
671 0x00006282, /* EMC_FBIO_CFG5 */
672 0x001d0084, /* EMC_CFG_DIG_DLL */
673 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
674 0x00024000, /* EMC_DLL_XFORM_DQS0 */
675 0x00024000, /* EMC_DLL_XFORM_DQS1 */
676 0x00024000, /* EMC_DLL_XFORM_DQS2 */
677 0x00024000, /* EMC_DLL_XFORM_DQS3 */
678 0x00000010, /* EMC_DLL_XFORM_DQS4 */
679 0x00000010, /* EMC_DLL_XFORM_DQS5 */
680 0x00000010, /* EMC_DLL_XFORM_DQS6 */
681 0x00000010, /* EMC_DLL_XFORM_DQS7 */
682 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
683 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
684 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
685 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
686 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
687 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
688 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
689 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
690 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
691 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
692 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
693 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
694 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
695 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
696 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
697 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
698 0x00048000, /* EMC_DLL_XFORM_DQ0 */
699 0x00048000, /* EMC_DLL_XFORM_DQ1 */
700 0x00048000, /* EMC_DLL_XFORM_DQ2 */
701 0x00048000, /* EMC_DLL_XFORM_DQ3 */
702 0x00060220, /* EMC_XM2CMDPADCTRL */
703 0x0800003d, /* EMC_XM2DQSPADCTRL2 */
704 0x00000000, /* EMC_XM2DQPADCTRL2 */
705 0x77ffc004, /* EMC_XM2CLKPADCTRL */
706 0x01f1f408, /* EMC_XM2COMPPADCTRL */
707 0x00000000, /* EMC_XM2VTTGENPADCTRL */
708 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
709 0x08000068, /* EMC_XM2QUSEPADCTRL */
710 0x08000000, /* EMC_XM2DQSPADCTRL3 */
711 0x00000802, /* EMC_CTT_TERM_CTRL */
712 0x00064000, /* EMC_ZCAL_INTERVAL */
713 0x00000090, /* EMC_ZCAL_WAIT_CNT */
714 0x000c000c, /* EMC_MRS_WAIT_CNT */
715 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
716 0x00000000, /* EMC_CTT */
717 0x00000000, /* EMC_CTT_DURATION */
718 0x80000ce6, /* EMC_DYN_SELF_REF_CONTROL */
719 0x00000006, /* MC_EMEM_ARB_CFG */
720 0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
721 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
722 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
723 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
724 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
725 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */
726 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
727 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
728 0x00000006, /* MC_EMEM_ARB_TIMING_WAP2PRE */
729 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
730 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
731 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
732 0x00000004, /* MC_EMEM_ARB_TIMING_W2R */
733 0x04040001, /* MC_EMEM_ARB_DA_TURNS */
734 0x000d090c, /* MC_EMEM_ARB_DA_COVERS */
735 0x71c6120d, /* MC_EMEM_ARB_MISC0 */
736 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
737 0x10000000, /* EMC_FBIO_SPARE */
738 0xff00ff00, /* EMC_CFG_RSV */
739 },
740 0x00000024, /* EMC_ZCAL_WAIT_CNT after clock change */
741 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
742 0x00000001, /* EMC_CFG.PERIODIC_QRST */
743 0x00000000, /* Mode Register 0 */
744 0x00010082, /* Mode Register 1 */
745 0x00020004, /* Mode Register 2 */
746 0x00000000, /* EMC_CFG.DYN_SELF_REF */
747 },
748};
749
750int enterprise_emc_init(void)
751{
752 struct board_info board_info;
753
754 tegra_get_board_info(&board_info);
755
756 if (board_info.fab <= BOARD_FAB_A02)
757 tegra_init_emc(enterprise_emc_tables_h5tc2g,
758 ARRAY_SIZE(enterprise_emc_tables_h5tc2g));
759
760 return 0;
761}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 17:39:27 -0400