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diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
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1/*
2 * arch/arm/mach-tegra/board-cardhu.c
3 *
4 * Copyright (c) 2011-2012, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/ctype.h>
25#include <linux/platform_device.h>
26#include <linux/clk.h>
27#include <linux/serial_8250.h>
28#include <linux/i2c.h>
29#include <linux/i2c/panjit_ts.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/i2c-tegra.h>
33#include <linux/gpio.h>
34#include <linux/input.h>
35#include <linux/platform_data/tegra_usb.h>
36#include <linux/spi/spi.h>
37#include <linux/i2c/atmel_mxt_ts.h>
38#include <linux/tegra_uart.h>
39#include <linux/memblock.h>
40#include <linux/spi-tegra.h>
41#include <linux/nfc/pn544.h>
42
43#include <sound/wm8903.h>
44#include <sound/max98095.h>
45#include <media/tegra_dtv.h>
46
47#include <mach/clk.h>
48#include <mach/iomap.h>
49#include <mach/irqs.h>
50#include <mach/pinmux.h>
51#include <mach/iomap.h>
52#include <mach/io.h>
53#include <mach/i2s.h>
54#include <mach/tegra_asoc_pdata.h>
55#include <mach/tegra_wm8903_pdata.h>
56#include <asm/mach-types.h>
57#include <asm/mach/arch.h>
58#include <mach/usb_phy.h>
59#include <mach/thermal.h>
60#include <mach/pci.h>
61
62#include "board.h"
63#include "clock.h"
64#include "board-cardhu.h"
65#include "devices.h"
66#include "gpio-names.h"
67#include "fuse.h"
68#include "pm.h"
69#include "baseband-xmm-power.h"
70#include "wdt-recovery.h"
71
72#define PEX_EN TEGRA_GPIO_PQ0
73
74/* All units are in millicelsius */
75static struct tegra_thermal_data thermal_data = {
76 .temp_throttle = 85000,
77 .temp_shutdown = 90000,
78 .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
79#ifdef CONFIG_TEGRA_EDP_LIMITS
80 .edp_offset = TDIODE_OFFSET, /* edp based on tdiode */
81 .hysteresis_edp = 3000,
82#endif
83#ifdef CONFIG_TEGRA_THERMAL_SYSFS
84 .tc1 = 0,
85 .tc2 = 1,
86 .passive_delay = 2000,
87#else
88 .hysteresis_throttle = 1000,
89#endif
90};
91
92/* !!!TODO: Change for cardhu (Taken from Ventana) */
93static struct tegra_utmip_config utmi_phy_config[] = {
94 [0] = {
95 .hssync_start_delay = 0,
96 .idle_wait_delay = 17,
97 .elastic_limit = 16,
98 .term_range_adj = 6,
99 .xcvr_setup = 15,
100 .xcvr_setup_offset = 0,
101 .xcvr_use_fuses = 1,
102 .xcvr_lsfslew = 2,
103 .xcvr_lsrslew = 2,
104 },
105 [1] = {
106 .hssync_start_delay = 0,
107 .idle_wait_delay = 17,
108 .elastic_limit = 16,
109 .term_range_adj = 6,
110 .xcvr_setup = 15,
111 .xcvr_setup_offset = 0,
112 .xcvr_use_fuses = 1,
113 .xcvr_lsfslew = 2,
114 .xcvr_lsrslew = 2,
115 },
116 [2] = {
117 .hssync_start_delay = 0,
118 .idle_wait_delay = 17,
119 .elastic_limit = 16,
120 .term_range_adj = 6,
121 .xcvr_setup = 8,
122 .xcvr_setup_offset = 0,
123 .xcvr_use_fuses = 1,
124 .xcvr_lsfslew = 2,
125 .xcvr_lsrslew = 2,
126 },
127};
128
129static struct resource cardhu_bcm4329_rfkill_resources[] = {
130 {
131 .name = "bcm4329_nshutdown_gpio",
132 .start = TEGRA_GPIO_PU0,
133 .end = TEGRA_GPIO_PU0,
134 .flags = IORESOURCE_IO,
135 },
136};
137
138static struct platform_device cardhu_bcm4329_rfkill_device = {
139 .name = "bcm4329_rfkill",
140 .id = -1,
141 .num_resources = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
142 .resource = cardhu_bcm4329_rfkill_resources,
143};
144
145static struct resource cardhu_bluesleep_resources[] = {
146 [0] = {
147 .name = "gpio_host_wake",
148 .start = TEGRA_GPIO_PU6,
149 .end = TEGRA_GPIO_PU6,
150 .flags = IORESOURCE_IO,
151 },
152 [1] = {
153 .name = "gpio_ext_wake",
154 .start = TEGRA_GPIO_PU1,
155 .end = TEGRA_GPIO_PU1,
156 .flags = IORESOURCE_IO,
157 },
158 [2] = {
159 .name = "host_wake",
160 .start = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
161 .end = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
162 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
163 },
164};
165
166static struct platform_device cardhu_bluesleep_device = {
167 .name = "bluesleep",
168 .id = -1,
169 .num_resources = ARRAY_SIZE(cardhu_bluesleep_resources),
170 .resource = cardhu_bluesleep_resources,
171};
172
173static noinline void __init cardhu_setup_bluesleep(void)
174{
175 platform_device_register(&cardhu_bluesleep_device);
176 tegra_gpio_enable(TEGRA_GPIO_PU6);
177 tegra_gpio_enable(TEGRA_GPIO_PU1);
178 return;
179}
180
181static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
182 /* name parent rate enabled */
183 { "pll_m", NULL, 0, false},
184 { "hda", "pll_p", 108000000, false},
185 { "hda2codec_2x","pll_p", 48000000, false},
186 { "pwm", "pll_p", 3187500, false},
187 { "blink", "clk_32k", 32768, true},
188 { "i2s0", "pll_a_out0", 0, false},
189 { "i2s1", "pll_a_out0", 0, false},
190 { "i2s3", "pll_a_out0", 0, false},
191 { "spdif_out", "pll_a_out0", 0, false},
192 { "d_audio", "clk_m", 12000000, false},
193 { "dam0", "clk_m", 12000000, false},
194 { "dam1", "clk_m", 12000000, false},
195 { "dam2", "clk_m", 12000000, false},
196 { "audio1", "i2s1_sync", 0, false},
197 { "audio3", "i2s3_sync", 0, false},
198 { "vi_sensor", "pll_p", 150000000, false},
199 { "i2c1", "pll_p", 3200000, false},
200 { "i2c2", "pll_p", 3200000, false},
201 { "i2c3", "pll_p", 3200000, false},
202 { "i2c4", "pll_p", 3200000, false},
203 { "i2c5", "pll_p", 3200000, false},
204 { NULL, NULL, 0, 0},
205};
206
207static struct pn544_i2c_platform_data nfc_pdata = {
208 .irq_gpio = TEGRA_GPIO_PX0,
209 .ven_gpio = TEGRA_GPIO_PP3,
210 .firm_gpio = TEGRA_GPIO_PO7,
211 };
212
213static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
214 {
215 I2C_BOARD_INFO("pn544", 0x28),
216 .platform_data = &nfc_pdata,
217 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
218 },
219};
220static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
221 .adapter_nr = 0,
222 .bus_count = 1,
223 .bus_clk_rate = { 100000, 0 },
224 .scl_gpio = {TEGRA_GPIO_PC4, 0},
225 .sda_gpio = {TEGRA_GPIO_PC5, 0},
226 .arb_recovery = arb_lost_recovery,
227};
228
229static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
230 .adapter_nr = 1,
231 .bus_count = 1,
232 .bus_clk_rate = { 100000, 0 },
233 .is_clkon_always = true,
234 .scl_gpio = {TEGRA_GPIO_PT5, 0},
235 .sda_gpio = {TEGRA_GPIO_PT6, 0},
236 .arb_recovery = arb_lost_recovery,
237};
238
239static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
240 .adapter_nr = 2,
241 .bus_count = 1,
242 .bus_clk_rate = { 100000, 0 },
243 .scl_gpio = {TEGRA_GPIO_PBB1, 0},
244 .sda_gpio = {TEGRA_GPIO_PBB2, 0},
245 .arb_recovery = arb_lost_recovery,
246};
247
248static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
249 .adapter_nr = 3,
250 .bus_count = 1,
251 .bus_clk_rate = { 100000, 0 },
252 .scl_gpio = {TEGRA_GPIO_PV4, 0},
253 .sda_gpio = {TEGRA_GPIO_PV5, 0},
254 .arb_recovery = arb_lost_recovery,
255};
256
257static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
258 .adapter_nr = 4,
259 .bus_count = 1,
260 .bus_clk_rate = { 400000, 0 },
261 .scl_gpio = {TEGRA_GPIO_PZ6, 0},
262 .sda_gpio = {TEGRA_GPIO_PZ7, 0},
263 .arb_recovery = arb_lost_recovery,
264};
265
266
267#if 0
268struct tegra_wired_jack_conf audio_wr_jack_conf = {
269 .hp_det_n = TEGRA_GPIO_PW2,
270 .en_mic_ext = TEGRA_GPIO_PX1,
271 .en_mic_int = TEGRA_GPIO_PX0,
272};
273#endif
274
275static struct wm8903_platform_data cardhu_wm8903_pdata = {
276 .irq_active_low = 0,
277 .micdet_cfg = 0,
278 .micdet_delay = 100,
279 .gpio_base = CARDHU_GPIO_WM8903(0),
280 .gpio_cfg = {
281 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
282 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
283 WM8903_GP2_DIR,
284 0,
285 WM8903_GPIO_NO_CONFIG,
286 WM8903_GPIO_NO_CONFIG,
287 },
288};
289
290/* Equalizer filter coefs generated from the MAXIM MAX98095
291 * evkit software tool */
292static struct max98095_eq_cfg max98095_eq_cfg[] = {
293 {
294 .name = "FLAT",
295 .rate = 44100,
296 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
297 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
298 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
299 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
300 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
301 },
302 {
303 .name = "LOWPASS1K",
304 .rate = 44100,
305 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
306 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
307 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
308 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
309 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
310 },
311 { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
312 .name = "HIBOOST",
313 .rate = 44100,
314 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
315 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
316 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
317 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
318 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
319 },
320 { /* BASS=12dB, TREBLE=+12dB */
321 .name = "LOUD12DB",
322 .rate = 44100,
323 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
324 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
325 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
326 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
327 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
328 },
329 {
330 .name = "FLAT",
331 .rate = 16000,
332 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
333 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
334 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
335 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
336 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
337 },
338 {
339 .name = "LOWPASS1K",
340 .rate = 16000,
341 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
342 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
343 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
344 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
345 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
346 },
347 { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
348 .name = "HIBOOST",
349 .rate = 16000,
350 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
351 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
352 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
353 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
354 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
355 },
356 { /* BASS=12dB, TREBLE=+12dB */
357 .name = "LOUD12DB",
358 .rate = 16000,
359 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
360 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
361 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
362 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
363 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
364 },
365};
366
367static struct max98095_pdata cardhu_max98095_pdata = {
368 /* equalizer configuration */
369 .eq_cfg = max98095_eq_cfg,
370 .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
371
372 /* Biquad filter response configuration */
373 .bq_cfg = NULL,
374 .bq_cfgcnt = 0,
375
376 /* microphone configuration */
377 .digmic_left_mode = 1,
378 .digmic_right_mode = 1,
379};
380
381static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
382 I2C_BOARD_INFO("wm8903", 0x1a),
383 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
384 .platform_data = &cardhu_wm8903_pdata,
385};
386
387static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
388 I2C_BOARD_INFO("aic3262-codec", 0x18),
389 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
390};
391
392static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
393 I2C_BOARD_INFO("max98095", 0x10),
394 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
395 .platform_data = &cardhu_max98095_pdata,
396};
397
398// Configura il pinmux come gpio di output e asserisce il reset del codec
399static void hda_init(void)
400{
401 int rc;
402 rc = gpio_request(HDA_RESET, "hda_reset");
403 if (rc)
404 pr_err("HDA_RESET gpio request failed:%d\n", rc);
405 tegra_gpio_enable(HDA_RESET);
406 rc = gpio_direction_output(HDA_RESET, 1);
407 if (rc)
408 pr_err("HDA_RESET gpio direction configuration failed:%d\n", rc);
409}
410
411static void cardhu_audio_init(void)
412{
413 hda_init();
414}
415
416static void cardhu_i2c_init(void)
417{
418 tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
419 tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
420 tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
421 tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
422 tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
423
424 platform_device_register(&tegra_i2c_device5);
425 platform_device_register(&tegra_i2c_device4);
426 platform_device_register(&tegra_i2c_device3);
427 platform_device_register(&tegra_i2c_device2);
428 platform_device_register(&tegra_i2c_device1);
429
430 i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
431 i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
432 i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
433
434 i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
435}
436
437static struct platform_device *cardhu_uart_devices[] __initdata = {
438 //&tegra_uarta_device,
439 //&tegra_uartb_device,
440 //&tegra_uartc_device,
441 //&tegra_uartd_device,
442 //&tegra_uarte_device,
443};
444static struct uart_clk_parent uart_parent_clk[] = {
445 [0] = {.name = "clk_m"},
446 [1] = {.name = "pll_p"},
447#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
448 [2] = {.name = "pll_m"},
449#endif
450};
451
452static struct tegra_uart_platform_data cardhu_uart_pdata;
453static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
454
455static void __init uart_debug_init(void)
456{
457 struct board_info board_info;
458 int debug_port_id;
459
460 tegra_get_board_info(&board_info);
461
462 debug_port_id = get_tegra_uart_debug_port_id();
463 if (debug_port_id < 0) {
464 debug_port_id = 0;
465 /* UARTB is debug port
466 * for SLT - E1186/E1187/PM269
467 * for E1256/E1257
468 */
469 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
470 ((board_info.board_id == BOARD_E1186) ||
471 (board_info.board_id == BOARD_E1187) ||
472 (board_info.board_id == BOARD_PM269))) ||
473 (board_info.board_id == BOARD_E1256) ||
474 (board_info.board_id == BOARD_E1257))
475 debug_port_id = 1;
476 }
477
478 switch (debug_port_id) {
479 case 0:
480 /* UARTA is the debug port. */
481 pr_info("Selecting UARTA as the debug console\n");
482 cardhu_uart_devices[0] = &debug_uarta_device;
483 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
484 debug_uart_port_base = ((struct plat_serial8250_port *)(
485 debug_uarta_device.dev.platform_data))->mapbase;
486 break;
487
488 case 1:
489 /* UARTB is the debug port. */
490 pr_info("Selecting UARTB as the debug console\n");
491 cardhu_uart_devices[1] = &debug_uartb_device;
492 debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
493 debug_uart_port_base = ((struct plat_serial8250_port *)(
494 debug_uartb_device.dev.platform_data))->mapbase;
495 break;
496
497 case 2:
498 /* UARTC is the debug port. */
499 pr_info("Selecting UARTC as the debug console\n");
500 cardhu_uart_devices[2] = &debug_uartc_device;
501 debug_uart_clk = clk_get_sys("serial8250.0", "uartc");
502 debug_uart_port_base = ((struct plat_serial8250_port *)(
503 debug_uartc_device.dev.platform_data))->mapbase;
504 break;
505
506 case 3:
507 /* UARTD is the debug port. */
508 pr_info("Selecting UARTD as the debug console\n");
509 cardhu_uart_devices[3] = &debug_uartd_device;
510 debug_uart_clk = clk_get_sys("serial8250.0", "uartd");
511 debug_uart_port_base = ((struct plat_serial8250_port *)(
512 debug_uartd_device.dev.platform_data))->mapbase;
513 break;
514
515 case 4:
516 /* UARTE is the debug port. */
517 pr_info("Selecting UARTE as the debug console\n");
518 cardhu_uart_devices[4] = &debug_uarte_device;
519 debug_uart_clk = clk_get_sys("serial8250.0", "uarte");
520 debug_uart_port_base = ((struct plat_serial8250_port *)(
521 debug_uarte_device.dev.platform_data))->mapbase;
522 break;
523
524 default:
525 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
526 cardhu_uart_devices[0] = &debug_uarta_device;
527 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
528 debug_uart_port_base = ((struct plat_serial8250_port *)(
529 debug_uarta_device.dev.platform_data))->mapbase;
530 break;
531 }
532 return;
533}
534
535static void __init cardhu_uart_init(void)
536{
537 struct clk *c;
538 int i;
539
540 for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
541 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
542 if (IS_ERR_OR_NULL(c)) {
543 pr_err("Not able to get the clock for %s\n",
544 uart_parent_clk[i].name);
545 continue;
546 }
547 uart_parent_clk[i].parent_clk = c;
548 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
549 }
550 cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
551 cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
552 cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
553 cardhu_loopback_uart_pdata.parent_clk_count =
554 ARRAY_SIZE(uart_parent_clk);
555 cardhu_loopback_uart_pdata.is_loopback = true;
556 tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
557 tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
558 tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
559 tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
560 /* UARTE is used for loopback test purpose */
561 tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
562
563 /* Register low speed only if it is selected */
564 if (!is_tegra_debug_uartport_hs()) {
565 uart_debug_init();
566 /* Clock enable for the debug channel */
567 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
568 pr_info("The debug console clock name is %s\n",
569 debug_uart_clk->name);
570 c = tegra_get_clock_by_name("pll_p");
571 if (IS_ERR_OR_NULL(c))
572 pr_err("Not getting the parent clock pll_p\n");
573 else
574 clk_set_parent(debug_uart_clk, c);
575
576 clk_enable(debug_uart_clk);
577 clk_set_rate(debug_uart_clk, clk_get_rate(c));
578 } else {
579 pr_err("Not getting the clock %s for debug console\n",
580 debug_uart_clk->name);
581 }
582 }
583
584 platform_add_devices(cardhu_uart_devices,
585 ARRAY_SIZE(cardhu_uart_devices));
586}
587
588static struct platform_device tegra_camera = {
589 .name = "tegra_camera",
590 .id = -1,
591};
592
593static struct platform_device *cardhu_spi_devices[] __initdata = {
594 &tegra_spi_device4,
595};
596
597struct spi_clk_parent spi_parent_clk[] = {
598 [0] = {.name = "pll_p"},
599#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
600 [1] = {.name = "pll_m"},
601 [2] = {.name = "clk_m"},
602#else
603 [1] = {.name = "clk_m"},
604#endif
605};
606
607static struct tegra_spi_platform_data cardhu_spi_pdata = {
608 .is_dma_based = true,
609 .max_dma_buffer = (16 * 1024),
610 .is_clkon_always = false,
611 .max_rate = 100000000,
612};
613
614static void __init cardhu_spi_init(void)
615{
616 int i;
617 struct clk *c;
618 struct board_info board_info;
619
620 tegra_get_board_info(&board_info);
621
622 for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
623 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
624 if (IS_ERR_OR_NULL(c)) {
625 pr_err("Not able to get the clock for %s\n",
626 spi_parent_clk[i].name);
627 continue;
628 }
629 spi_parent_clk[i].parent_clk = c;
630 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
631 }
632 cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
633 cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
634 tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
635 platform_add_devices(cardhu_spi_devices,
636 ARRAY_SIZE(cardhu_spi_devices));
637
638 if (board_info.board_id == BOARD_E1198) {
639 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
640 platform_device_register(&tegra_spi_device2);
641 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
642 platform_device_register(&tegra_spi_slave_device1);
643 }
644}
645
646static void __init cardhu_dtv_init(void)
647{
648 struct board_info board_info;
649
650 tegra_get_board_info(&board_info);
651
652 if (board_info.board_id == BOARD_E1186)
653 platform_device_register(&tegra_dtv_device);
654}
655
656static struct resource tegra_rtc_resources[] = {
657 [0] = {
658 .start = TEGRA_RTC_BASE,
659 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 [1] = {
663 .start = INT_RTC,
664 .end = INT_RTC,
665 .flags = IORESOURCE_IRQ,
666 },
667};
668
669static struct platform_device tegra_rtc_device = {
670 .name = "tegra_rtc",
671 .id = -1,
672 .resource = tegra_rtc_resources,
673 .num_resources = ARRAY_SIZE(tegra_rtc_resources),
674};
675
676static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
677 .gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
678 .gpio_hp_det = TEGRA_GPIO_HP_DET,
679 .gpio_hp_mute = -1,
680 .gpio_int_mic_en = -1,
681 .gpio_ext_mic_en = -1,
682};
683
684static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
685 .gpio_spkr_en = -1,
686 .gpio_hp_det = TEGRA_GPIO_HP_DET,
687 .gpio_hp_mute = -1,
688 .gpio_int_mic_en = -1,
689 .gpio_ext_mic_en = -1,
690};
691
692static struct platform_device cardhu_audio_wm8903_device = {
693 .name = "tegra-snd-wm8903",
694 .id = 0,
695 .dev = {
696 .platform_data = &cardhu_audio_wm8903_pdata,
697 },
698};
699
700static struct platform_device cardhu_audio_max98095_device = {
701 .name = "tegra-snd-max98095",
702 .id = 0,
703 .dev = {
704 .platform_data = &cardhu_audio_max98095_pdata,
705 },
706};
707
708static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
709 .gpio_spkr_en = -1,
710 .gpio_hp_det = TEGRA_GPIO_HP_DET,
711 .gpio_hp_mute = -1,
712 .gpio_int_mic_en = -1,
713 .gpio_ext_mic_en = -1,
714 /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
715 .audio_port_id = {
716 [HIFI_CODEC] = 0,
717 [BASEBAND] = -1,
718 [BT_SCO] = 3,
719 },
720 .baseband_param = {
721 .rate = -1,
722 .channels = -1,
723 },
724};
725
726static struct platform_device cardhu_audio_aic326x_device = {
727 .name = "tegra-snd-aic326x",
728 .id = 0,
729 .dev = {
730 .platform_data = &cardhu_audio_aic326x_pdata,
731 },
732};
733
734static struct platform_device *cardhu_devices[] __initdata = {
735 &tegra_pmu_device,
736 &tegra_rtc_device,
737#ifndef CONFIG_TEGRA_USB0_EHCI1_HOST
738 &tegra_udc_device,
739#endif
740#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
741 &tegra_smmu_device,
742#endif
743 &tegra_wdt_device,
744#if defined(CONFIG_TEGRA_AVP)
745 &tegra_avp_device,
746#endif
747 &tegra_camera,
748#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
749 &tegra_se_device,
750#endif
751 &tegra_ahub_device,
752 &tegra_dam_device0,
753 &tegra_dam_device1,
754 &tegra_dam_device2,
755 &tegra_i2s_device0,
756 &tegra_i2s_device1,
757 &tegra_i2s_device3,
758 &tegra_spdif_device,
759 &spdif_dit_device,
760 &bluetooth_dit_device,
761 &baseband_dit_device,
762 &cardhu_bcm4329_rfkill_device,
763 &tegra_pcm_device,
764 &cardhu_audio_wm8903_device,
765 &cardhu_audio_max98095_device,
766 &cardhu_audio_aic326x_device,
767 &tegra_hda_device,
768#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
769 &tegra_aes_device,
770#endif
771};
772
773#define MXT_CONFIG_CRC 0xD62DE8
774static const u8 config[] = {
775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
776 0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
777 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
778 0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
779 0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
780 0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
781 0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
786 0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
787 0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
788 0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
789 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792 0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
793 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
795};
796
797#define MXT_CONFIG_CRC_SKU2000 0xA24D9A
798static const u8 config_sku2000[] = {
799 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800 0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
801 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
802 0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00, //23=thr 2 di
803 0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
804 0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
805 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, //0A=limit
806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
810 0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
811 0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
812 0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
813 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816 0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
819};
820
821static struct mxt_platform_data atmel_mxt_info = {
822 .x_line = 27,
823 .y_line = 42,
824 .x_size = 768,
825 .y_size = 1366,
826 .blen = 0x20,
827 .threshold = 0x3C,
828 .voltage = 3300000, /* 3.3V */
829 .orient = 5,
830 .config = config,
831 .config_length = 157,
832 .config_crc = MXT_CONFIG_CRC,
833 .irqflags = IRQF_TRIGGER_FALLING,
834/* .read_chg = &read_chg, */
835 .read_chg = NULL,
836};
837
838static struct i2c_board_info __initdata atmel_i2c_info[] = {
839 {
840 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
841 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
842 .platform_data = &atmel_mxt_info,
843 }
844};
845
846static int __init cardhu_touch_init(void)
847{
848 struct board_info BoardInfo;
849
850 tegra_gpio_enable(TEGRA_GPIO_PH4);
851 tegra_gpio_enable(TEGRA_GPIO_PH6);
852
853 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
854 gpio_direction_input(TEGRA_GPIO_PH4);
855
856 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
857 gpio_direction_output(TEGRA_GPIO_PH6, 0);
858 msleep(1);
859 gpio_set_value(TEGRA_GPIO_PH6, 1);
860 msleep(100);
861
862 tegra_get_board_info(&BoardInfo);
863 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
864 atmel_mxt_info.config = config_sku2000;
865 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
866 }
867
868 i2c_register_board_info(1, atmel_i2c_info, 1);
869
870 return 0;
871}
872
873static struct tegra_uhsic_config uhsic_phy_config = {
874 .enable_gpio = EN_HSIC_GPIO,
875 .reset_gpio = -1,
876 .sync_start_delay = 9,
877 .idle_wait_delay = 17,
878 .term_range_adj = 0,
879 .elastic_underrun_limit = 16,
880 .elastic_overrun_limit = 16,
881};
882
883static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
884 .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
885 .phy_config = &uhsic_phy_config,
886 .operating_mode = TEGRA_USB_HOST,
887 .power_down_on_bus_suspend = 1,
888 .default_enable = true,
889};
890
891static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
892 [0] = {
893 .phy_config = &utmi_phy_config[0],
894 .operating_mode = TEGRA_USB_HOST,
895 .power_down_on_bus_suspend = 1,
896 .default_enable = true,
897 },
898 [1] = {
899 .phy_config = &utmi_phy_config[1],
900 .operating_mode = TEGRA_USB_HOST,
901 .power_down_on_bus_suspend = 1,
902 .default_enable = true,
903 },
904 [2] = {
905 .phy_config = &utmi_phy_config[2],
906 .operating_mode = TEGRA_USB_HOST,
907 .power_down_on_bus_suspend = 1,
908 .hotplug = 1,
909 .default_enable = true,
910 },
911};
912
913static struct tegra_otg_platform_data tegra_otg_pdata = {
914 .ehci_device = &tegra_ehci1_device,
915 .ehci_pdata = &tegra_ehci_pdata[0],
916};
917
918#ifdef CONFIG_USB_SUPPORT
919static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
920 [0] = {
921 .instance = 0,
922 .vbus_gpio = -1,
923 .vbus_reg_supply = "vdd_vbus_micro_usb",
924 },
925 [1] = {
926 .instance = 1,
927 .vbus_gpio = -1,
928 },
929 [2] = {
930 .instance = 2,
931 .vbus_gpio = -1,
932 .vbus_reg_supply = "vdd_vbus_typea_usb",
933 },
934};
935
936static int cardhu_usb_hsic_postsupend(void)
937{
938#ifdef CONFIG_TEGRA_BB_XMM_POWER
939 baseband_xmm_set_power_status(BBXMM_PS_L2);
940#endif
941 return 0;
942}
943
944static int cardhu_usb_hsic_preresume(void)
945{
946#ifdef CONFIG_TEGRA_BB_XMM_POWER
947 baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
948#endif
949 return 0;
950}
951
952static int cardhu_usb_hsic_phy_ready(void)
953{
954#ifdef CONFIG_TEGRA_BB_XMM_POWER
955 baseband_xmm_set_power_status(BBXMM_PS_L0);
956#endif
957 return 0;
958}
959
960static int cardhu_usb_hsic_phy_off(void)
961{
962#ifdef CONFIG_TEGRA_BB_XMM_POWER
963 baseband_xmm_set_power_status(BBXMM_PS_L3);
964#endif
965 return 0;
966}
967
968static void cardhu_usb_init(void)
969{
970 struct board_info bi;
971
972 tegra_get_board_info(&bi);
973
974 tegra_usb_phy_init(tegra_usb_phy_pdata,
975 ARRAY_SIZE(tegra_usb_phy_pdata));
976
977#ifndef CONFIG_TEGRA_USB0_EHCI1_HOST
978 tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
979 platform_device_register(&tegra_otg_device);
980#else
981 tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
982 platform_device_register(&tegra_ehci1_device);
983#endif
984
985 if (bi.board_id == BOARD_PM267) {
986 uhsic_phy_config.reset_gpio =
987 PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
988 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
989 platform_device_register(&tegra_ehci2_device);
990 } else if (bi.board_id == BOARD_E1256) {
991 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
992 platform_device_register(&tegra_ehci2_device);
993 } else if (bi.board_id == BOARD_E1186) {
994 /* for baseband devices do not switch off phy during suspend */
995 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
996 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
997 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
998 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
999 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
1000 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
1001 /* baseband registration happens in baseband-xmm-power */
1002 } else {
1003 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
1004 platform_device_register(&tegra_ehci2_device);
1005 }
1006
1007 tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
1008 platform_device_register(&tegra_ehci3_device);
1009
1010}
1011#else
1012static void cardhu_usb_init(void) { }
1013#endif
1014
1015static void cardhu_gps_init(void)
1016{
1017 tegra_gpio_enable(TEGRA_GPIO_PU2);
1018 tegra_gpio_enable(TEGRA_GPIO_PU3);
1019}
1020
1021static void cardhu_nfc_init(void)
1022{
1023 tegra_gpio_enable(TEGRA_GPIO_PX0);
1024 tegra_gpio_enable(TEGRA_GPIO_PP3);
1025 tegra_gpio_enable(TEGRA_GPIO_PO7);
1026}
1027
1028static struct baseband_power_platform_data tegra_baseband_power_data = {
1029 .baseband_type = BASEBAND_XMM,
1030 .modem = {
1031 .xmm = {
1032 .bb_rst = XMM_GPIO_BB_RST,
1033 .bb_on = XMM_GPIO_BB_ON,
1034 .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1035 .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1036 .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1037 .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1038 .hsic_device = &tegra_ehci2_device,
1039 },
1040 },
1041};
1042
1043static struct platform_device tegra_baseband_power_device = {
1044 .name = "baseband_xmm_power",
1045 .id = -1,
1046 .dev = {
1047 .platform_data = &tegra_baseband_power_data,
1048 },
1049};
1050
1051static struct platform_device tegra_baseband_power2_device = {
1052 .name = "baseband_xmm_power2",
1053 .id = -1,
1054 .dev = {
1055 .platform_data = &tegra_baseband_power_data,
1056 },
1057};
1058
1059
1060static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1061 .port_status[0] = 1,
1062 .port_status[1] = 1,
1063 .port_status[2] = 1,
1064 .use_dock_detect = 0,
1065 .gpio = 0,
1066};
1067
1068static void cardhu_pci_init(void)
1069{
1070 struct board_info board_info;
1071
1072 int rc;
1073
1074 // NOTE
1075 // VDD_1V2_GEN HAS TO BE PROGRAMMED TO PROVIDE PROPER VOLTAGE LEVEL BY THE BOOTLOADER
1076
1077 // Enable PEX logic power supply on Carma
1078 rc = gpio_request(PEX_EN, "pex_power");
1079 if (rc)
1080 pr_err("PEX_EN gpio request failed:%d\n", rc);
1081
1082 tegra_gpio_enable(PEX_EN);
1083 rc = gpio_direction_output(PEX_EN, 0);
1084 if (rc)
1085 pr_err("PEX gpio direction configuration failed:%d\n", rc);
1086
1087 tegra_get_board_info(&board_info);
1088 if (board_info.board_id == BOARD_E1291) {
1089 cardhu_pci_platform_data.port_status[0] = 1;
1090 cardhu_pci_platform_data.port_status[1] = 1;
1091 cardhu_pci_platform_data.port_status[2] = 1;
1092 cardhu_pci_platform_data.use_dock_detect = 1;
1093 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1094 }
1095 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1096 platform_device_register(&tegra_pci_device);
1097}
1098
1099static void cardhu_modem_init(void)
1100{
1101 struct board_info board_info;
1102 int w_disable_gpio, ret;
1103
1104 tegra_get_board_info(&board_info);
1105 switch (board_info.board_id) {
1106 case BOARD_E1291:
1107 case BOARD_E1198:
1108 if (((board_info.board_id == BOARD_E1291) &&
1109 (board_info.fab < BOARD_FAB_A03)) ||
1110 ((board_info.board_id == BOARD_E1198) &&
1111 (board_info.fab < BOARD_FAB_A02))) {
1112 w_disable_gpio = TEGRA_GPIO_PH5;
1113 } else {
1114 w_disable_gpio = TEGRA_GPIO_PDD5;
1115 }
1116 tegra_gpio_enable(w_disable_gpio);
1117 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1118 if (ret < 0)
1119 pr_err("%s: gpio_request failed for gpio %d\n",
1120 __func__, w_disable_gpio);
1121 else
1122 gpio_direction_input(w_disable_gpio);
1123
1124 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1125 if (((board_info.board_id == BOARD_E1291) &&
1126 (board_info.fab >= BOARD_FAB_A04)) ||
1127 ((board_info.board_id == BOARD_E1198) &&
1128 (board_info.fab >= BOARD_FAB_A02))) {
1129 ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1130 if (ret < 0) {
1131 pr_err("%s(): Error in allocating gpio "
1132 "TEGRA_GPIO_PH7\n", __func__);
1133 break;
1134 }
1135 gpio_direction_output(TEGRA_GPIO_PH7, 1);
1136 tegra_gpio_enable(TEGRA_GPIO_PH7);
1137 }
1138 break;
1139 case BOARD_E1186:
1140 tegra_gpio_enable(
1141 tegra_baseband_power_data.modem.xmm.bb_rst);
1142 tegra_gpio_enable(
1143 tegra_baseband_power_data.modem.xmm.bb_on);
1144 tegra_gpio_enable(
1145 tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1146 tegra_gpio_enable(
1147 tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1148 tegra_gpio_enable(
1149 tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1150 tegra_gpio_enable(
1151 tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1152 platform_device_register(&tegra_baseband_power_device);
1153 platform_device_register(&tegra_baseband_power2_device);
1154 break;
1155 default:
1156 break;
1157 }
1158
1159}
1160
1161#ifdef CONFIG_SATA_AHCI_TEGRA
1162static void cardhu_sata_init(void)
1163{
1164 platform_device_register(&tegra_sata_device);
1165}
1166#else
1167static void cardhu_sata_init(void) { }
1168#endif
1169
1170static void __init tegra_cardhu_init(void)
1171{
1172 tegra_thermal_init(&thermal_data);
1173 tegra_clk_init_from_table(cardhu_clk_init_table);
1174 cardhu_pinmux_init();
1175 cardhu_i2c_init();
1176 cardhu_spi_init();
1177 cardhu_usb_init();
1178#ifdef CONFIG_TEGRA_EDP_LIMITS
1179 cardhu_edp_init();
1180#endif
1181 cardhu_uart_init();
1182 platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1183 cardhu_audio_init();
1184 tegra_ram_console_debug_init();
1185 cardhu_sdhci_init();
1186 cardhu_regulator_init();
1187 //cardhu_dtv_init();
1188 cardhu_suspend_init();
1189 //cardhu_touch_init();
1190 //cardhu_gps_init();
1191 //cardhu_modem_init();
1192 //cardhu_kbc_init();
1193 //cardhu_scroll_init();
1194 //cardhu_keys_init();
1195 cardhu_panel_init();
1196 //cardhu_pmon_init();
1197 cardhu_sensors_init();
1198 //cardhu_setup_bluesleep();
1199 cardhu_sata_init();
1200 //audio_wired_jack_init();
1201 cardhu_pins_state_init();
1202 cardhu_emc_init();
1203 tegra_release_bootloader_fb();
1204 //cardhu_nfc_init();
1205 cardhu_pci_init();
1206#ifdef CONFIG_TEGRA_WDT_RECOVERY
1207 tegra_wdt_recovery_init();
1208#endif
1209}
1210
1211static void __init tegra_cardhu_reserve(void)
1212{
1213#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1214 /* support 1920X1200 with 24bpp */
1215 tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1216#else
1217 tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1218#endif
1219 tegra_ram_console_debug_reserve(SZ_1M);
1220}
1221
1222MACHINE_START(CARDHU, "cardhu")
1223 .boot_params = 0x80000100,
1224 .map_io = tegra_map_common_io,
1225 .reserve = tegra_cardhu_reserve,
1226 .init_early = tegra_init_early,
1227 .init_irq = tegra_init_irq,
1228 .timer = &tegra_timer,
1229 .init_machine = tegra_cardhu_init,
1230MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-17 20:37:39 -0400