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-rw-r--r--arch/arm/mach-tegra/board-cardhu-power.c1321
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diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
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1/*
2 * arch/arm/mach-tegra/board-cardhu-power.c
3 *
4 * Copyright (C) 2011 NVIDIA, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18 * 02111-1307, USA
19 */
20#include <linux/i2c.h>
21#include <linux/pda_power.h>
22#include <linux/platform_device.h>
23#include <linux/resource.h>
24#include <linux/regulator/machine.h>
25#include <linux/mfd/tps6591x.h>
26#include <linux/mfd/max77663-core.h>
27#include <linux/gpio.h>
28#include <linux/io.h>
29#include <linux/regulator/gpio-switch-regulator.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/tps6591x-regulator.h>
32#include <linux/regulator/tps62360.h>
33#include <linux/power/gpio-charger.h>
34
35#include <asm/mach-types.h>
36
37#include <mach/iomap.h>
38#include <mach/irqs.h>
39#include <mach/pinmux.h>
40#include <mach/edp.h>
41
42#include "gpio-names.h"
43#include "board.h"
44#include "board-cardhu.h"
45#include "pm.h"
46#include "wakeups-t3.h"
47#include "tegra3_tsensor.h"
48
49#define PMC_CTRL 0x0
50#define PMC_CTRL_INTR_LOW (1 << 17)
51
52static struct regulator_consumer_supply tps6591x_vdd1_supply_skubit0_0[] = {
53 REGULATOR_SUPPLY("vdd_core", NULL),
54 REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
55};
56
57static struct regulator_consumer_supply tps6591x_vdd1_supply_skubit0_1[] = {
58 REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
59};
60
61static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = {
62 REGULATOR_SUPPLY("vdd_gen1v5", NULL),
63 REGULATOR_SUPPLY("vcore_lcd", NULL),
64 REGULATOR_SUPPLY("track_ldo1", NULL),
65 REGULATOR_SUPPLY("external_ldo_1v2", NULL),
66 REGULATOR_SUPPLY("vcore_cam1", NULL),
67 REGULATOR_SUPPLY("vcore_cam2", NULL),
68};
69
70static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = {
71 REGULATOR_SUPPLY("vdd_cpu_pmu", NULL),
72 REGULATOR_SUPPLY("vdd_cpu", NULL),
73 REGULATOR_SUPPLY("vdd_sys", NULL),
74};
75
76static struct regulator_consumer_supply tps6591x_vio_supply_0[] = {
77 REGULATOR_SUPPLY("vdd_gen1v8", NULL),
78 REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
79 REGULATOR_SUPPLY("avdd_usb_pll", NULL),
80 REGULATOR_SUPPLY("avdd_osc", NULL),
81 REGULATOR_SUPPLY("vddio_sys", NULL),
82 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
83 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
84 REGULATOR_SUPPLY("vdd1v8_satelite", NULL),
85 REGULATOR_SUPPLY("vddio_uart", NULL),
86 REGULATOR_SUPPLY("pwrdet_uart", NULL),
87 REGULATOR_SUPPLY("vddio_audio", NULL),
88 REGULATOR_SUPPLY("pwrdet_audio", NULL),
89 REGULATOR_SUPPLY("vddio_bb", NULL),
90 REGULATOR_SUPPLY("pwrdet_bb", NULL),
91 REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
92 REGULATOR_SUPPLY("pwrdet_lcd", NULL),
93 REGULATOR_SUPPLY("vddio_cam", NULL),
94 REGULATOR_SUPPLY("pwrdet_cam", NULL),
95 REGULATOR_SUPPLY("vddio_vi", NULL),
96 REGULATOR_SUPPLY("pwrdet_vi", NULL),
97 REGULATOR_SUPPLY("ldo6", NULL),
98 REGULATOR_SUPPLY("ldo7", NULL),
99 REGULATOR_SUPPLY("ldo8", NULL),
100 REGULATOR_SUPPLY("vcore_audio", NULL),
101 REGULATOR_SUPPLY("avcore_audio", NULL),
102 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
103 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
104 REGULATOR_SUPPLY("vcore1_lpddr2", NULL),
105 REGULATOR_SUPPLY("vcom_1v8", NULL),
106 REGULATOR_SUPPLY("pmuio_1v8", NULL),
107 REGULATOR_SUPPLY("avdd_ic_usb", NULL),
108};
109
110static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = {
111 REGULATOR_SUPPLY("avdd_pexb", NULL),
112 REGULATOR_SUPPLY("vdd_pexb", NULL),
113 REGULATOR_SUPPLY("avdd_pex_pll", NULL),
114 REGULATOR_SUPPLY("avdd_pexa", NULL),
115 REGULATOR_SUPPLY("vdd_pexa", NULL),
116};
117
118static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = {
119 REGULATOR_SUPPLY("avdd_sata", NULL),
120 REGULATOR_SUPPLY("vdd_sata", NULL),
121 REGULATOR_SUPPLY("avdd_sata_pll", NULL),
122 REGULATOR_SUPPLY("avdd_plle", NULL),
123};
124
125static struct regulator_consumer_supply tps6591x_ldo3_supply_e118x[] = {
126 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
127 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
128};
129
130static struct regulator_consumer_supply tps6591x_ldo3_supply_e1198[] = {
131 REGULATOR_SUPPLY("unused_rail_ldo3", NULL),
132};
133
134static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = {
135 REGULATOR_SUPPLY("vdd_rtc", NULL),
136};
137
138static struct regulator_consumer_supply tps6591x_ldo5_supply_e118x[] = {
139 REGULATOR_SUPPLY("avdd_vdac", NULL),
140};
141
142static struct regulator_consumer_supply tps6591x_ldo5_supply_e1198[] = {
143 REGULATOR_SUPPLY("avdd_vdac", NULL),
144 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
145 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
146};
147
148static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = {
149 REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
150 REGULATOR_SUPPLY("pwrdet_mipi", NULL),
151};
152static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = {
153 REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
154 REGULATOR_SUPPLY("avdd_pllm", NULL),
155 REGULATOR_SUPPLY("avdd_pllu_d", NULL),
156 REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
157 REGULATOR_SUPPLY("avdd_pllx", NULL),
158};
159
160static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = {
161 REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
162};
163
164#define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \
165 _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl, _flags) \
166 static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \
167 { \
168 .regulator = { \
169 .constraints = { \
170 .min_uV = (_minmv)*1000, \
171 .max_uV = (_maxmv)*1000, \
172 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
173 REGULATOR_MODE_STANDBY), \
174 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
175 REGULATOR_CHANGE_STATUS | \
176 REGULATOR_CHANGE_VOLTAGE), \
177 .always_on = _always_on, \
178 .boot_on = _boot_on, \
179 .apply_uV = _apply_uv, \
180 }, \
181 .num_consumer_supplies = \
182 ARRAY_SIZE(tps6591x_##_name##_supply_##_sname), \
183 .consumer_supplies = tps6591x_##_name##_supply_##_sname, \
184 .supply_regulator = _supply_reg, \
185 }, \
186 .init_uV = _init_uV * 1000, \
187 .init_enable = _init_enable, \
188 .init_apply = _init_apply, \
189 .ectrl = _ectrl, \
190 .flags = _flags, \
191 }
192
193TPS_PDATA_INIT(vdd1, skubit0_0, 600, 1500, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0);
194TPS_PDATA_INIT(vdd1, skubit0_1, 600, 1500, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0);
195TPS_PDATA_INIT(vdd2, 0, 600, 1500, 0, 1, 1, 0, -1, 0, 0, 0, 0);
196TPS_PDATA_INIT(vddctrl, 0, 600, 1400, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1, 0);
197TPS_PDATA_INIT(vio, 0, 1500, 3300, 0, 1, 1, 0, -1, 0, 0, 0, 0);
198
199TPS_PDATA_INIT(ldo1, 0, 1000, 3300, tps6591x_rails(VDD_2), 0, 0, 0, -1, 0, 1, 0, 0);
200TPS_PDATA_INIT(ldo2, 0, 1050, 1050, tps6591x_rails(VDD_2), 0, 0, 1, -1, 0, 1, 0, 0);
201
202TPS_PDATA_INIT(ldo3, e118x, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0);
203TPS_PDATA_INIT(ldo3, e1198, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0);
204TPS_PDATA_INIT(ldo4, 0, 1000, 3300, 0, 1, 0, 0, -1, 0, 0, 0, 0);
205TPS_PDATA_INIT(ldo5, e118x, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0);
206TPS_PDATA_INIT(ldo5, e1198, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0);
207
208TPS_PDATA_INIT(ldo6, 0, 1200, 1200, tps6591x_rails(VIO), 0, 0, 1, -1, 0, 0, 0, 0);
209TPS_PDATA_INIT(ldo7, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
210TPS_PDATA_INIT(ldo8, 0, 1000, 3300, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
211
212#if defined(CONFIG_RTC_DRV_TPS6591x)
213static struct tps6591x_rtc_platform_data rtc_data = {
214 .irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM,
215 .time = {
216 .tm_year = 2000,
217 .tm_mon = 0,
218 .tm_mday = 1,
219 .tm_hour = 0,
220 .tm_min = 0,
221 .tm_sec = 0,
222 },
223};
224
225#define TPS_RTC_REG() \
226 { \
227 .id = 0, \
228 .name = "rtc_tps6591x", \
229 .platform_data = &rtc_data, \
230 }
231#endif
232
233#define TPS_REG(_id, _name, _sname) \
234 { \
235 .id = TPS6591X_ID_##_id, \
236 .name = "tps6591x-regulator", \
237 .platform_data = &pdata_##_name##_##_sname, \
238 }
239
240#define TPS6591X_DEV_COMMON_E118X \
241 TPS_REG(VDD_2, vdd2, 0), \
242 TPS_REG(VDDCTRL, vddctrl, 0), \
243 TPS_REG(LDO_1, ldo1, 0), \
244 TPS_REG(LDO_2, ldo2, 0), \
245 TPS_REG(LDO_3, ldo3, e118x), \
246 TPS_REG(LDO_4, ldo4, 0), \
247 TPS_REG(LDO_5, ldo5, e118x), \
248 TPS_REG(LDO_6, ldo6, 0), \
249 TPS_REG(LDO_7, ldo7, 0), \
250 TPS_REG(LDO_8, ldo8, 0)
251
252static struct tps6591x_subdev_info tps_devs_e118x_skubit0_0[] = {
253 TPS_REG(VIO, vio, 0),
254 TPS_REG(VDD_1, vdd1, skubit0_0),
255 TPS6591X_DEV_COMMON_E118X,
256#if defined(CONFIG_RTC_DRV_TPS6591x)
257 TPS_RTC_REG(),
258#endif
259};
260
261static struct tps6591x_subdev_info tps_devs_e118x_skubit0_1[] = {
262 TPS_REG(VIO, vio, 0),
263 TPS_REG(VDD_1, vdd1, skubit0_1),
264 TPS6591X_DEV_COMMON_E118X,
265#if defined(CONFIG_RTC_DRV_TPS6591x)
266 TPS_RTC_REG(),
267#endif
268};
269
270#define TPS6591X_DEV_COMMON_CARDHU \
271 TPS_REG(VDD_2, vdd2, 0), \
272 TPS_REG(VDDCTRL, vddctrl, 0), \
273 TPS_REG(LDO_1, ldo1, 0), \
274 TPS_REG(LDO_2, ldo2, 0), \
275 TPS_REG(LDO_3, ldo3, e1198), \
276 TPS_REG(LDO_4, ldo4, 0), \
277 TPS_REG(LDO_5, ldo5, e1198), \
278 TPS_REG(LDO_6, ldo6, 0), \
279 TPS_REG(LDO_7, ldo7, 0), \
280 TPS_REG(LDO_8, ldo8, 0)
281
282static struct tps6591x_subdev_info tps_devs_e1198_skubit0_0[] = {
283 TPS_REG(VIO, vio, 0),
284 TPS_REG(VDD_1, vdd1, skubit0_0),
285 TPS6591X_DEV_COMMON_CARDHU,
286#if defined(CONFIG_RTC_DRV_TPS6591x)
287 TPS_RTC_REG(),
288#endif
289};
290
291static struct tps6591x_subdev_info tps_devs_e1198_skubit0_1[] = {
292 TPS_REG(VIO, vio, 0),
293 TPS_REG(VDD_1, vdd1, skubit0_1),
294 TPS6591X_DEV_COMMON_CARDHU,
295#if defined(CONFIG_RTC_DRV_TPS6591x)
296 TPS_RTC_REG(),
297#endif
298};
299
300#define TPS_GPIO_INIT_PDATA(gpio_nr, _init_apply, _sleep_en, _pulldn_en, _output_en, _output_val) \
301 [gpio_nr] = { \
302 .sleep_en = _sleep_en, \
303 .pulldn_en = _pulldn_en, \
304 .output_mode_en = _output_en, \
305 .output_val = _output_val, \
306 .init_apply = _init_apply, \
307 }
308static struct tps6591x_gpio_init_data tps_gpio_pdata_e1291_a04[] = {
309 TPS_GPIO_INIT_PDATA(0, 0, 0, 0, 0, 0),
310 TPS_GPIO_INIT_PDATA(1, 0, 0, 0, 0, 0),
311 TPS_GPIO_INIT_PDATA(2, 1, 1, 0, 1, 1),
312 TPS_GPIO_INIT_PDATA(3, 0, 0, 0, 0, 0),
313 TPS_GPIO_INIT_PDATA(4, 0, 0, 0, 0, 0),
314 TPS_GPIO_INIT_PDATA(5, 0, 0, 0, 0, 0),
315 TPS_GPIO_INIT_PDATA(6, 0, 0, 0, 0, 0),
316 TPS_GPIO_INIT_PDATA(7, 0, 0, 0, 0, 0),
317 TPS_GPIO_INIT_PDATA(8, 0, 0, 0, 0, 0),
318};
319
320static struct tps6591x_sleep_keepon_data tps_slp_keepon = {
321 .clkout32k_keepon = 1,
322};
323
324static struct tps6591x_platform_data tps_platform = {
325 .irq_base = TPS6591X_IRQ_BASE,
326 .gpio_base = TPS6591X_GPIO_BASE,
327 .dev_slp_en = true,
328 .slp_keepon = &tps_slp_keepon,
329 .use_power_off = true,
330};
331
332static struct i2c_board_info __initdata cardhu_regulators[] = {
333 {
334 I2C_BOARD_INFO("tps6591x", 0x2D),
335 .irq = INT_EXTERNAL_PMU,
336 .platform_data = &tps_platform,
337 },
338};
339
340/* TPS62361B DC-DC converter */
341static struct regulator_consumer_supply tps62361_dcdc_supply[] = {
342 REGULATOR_SUPPLY("vdd_core", NULL),
343};
344
345static struct tps62360_regulator_platform_data tps62361_pdata = {
346 .reg_init_data = { \
347 .constraints = { \
348 .min_uV = 500000, \
349 .max_uV = 1770000, \
350 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
351 REGULATOR_MODE_STANDBY), \
352 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
353 REGULATOR_CHANGE_STATUS | \
354 REGULATOR_CHANGE_VOLTAGE), \
355 .always_on = 1, \
356 .boot_on = 1, \
357 .apply_uV = 0, \
358 }, \
359 .num_consumer_supplies = ARRAY_SIZE(tps62361_dcdc_supply), \
360 .consumer_supplies = tps62361_dcdc_supply, \
361 }, \
362 .en_discharge = true, \
363 .vsel0_gpio = -1, \
364 .vsel1_gpio = -1, \
365 .vsel0_def_state = 1, \
366 .vsel1_def_state = 1, \
367};
368
369static struct i2c_board_info __initdata tps62361_boardinfo[] = {
370 {
371 I2C_BOARD_INFO("tps62361", 0x60),
372 .platform_data = &tps62361_pdata,
373 },
374};
375
376int __init cardhu_regulator_init(void)
377{
378 struct board_info board_info;
379 struct board_info pmu_board_info;
380 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
381 u32 pmc_ctrl;
382 bool ext_core_regulator = false;
383
384 /* configure the power management controller to trigger PMU
385 * interrupts when low */
386
387 pmc_ctrl = readl(pmc + PMC_CTRL);
388 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
389
390 tegra_get_board_info(&board_info);
391 tegra_get_pmu_board_info(&pmu_board_info);
392
393 if (pmu_board_info.board_id == BOARD_PMU_PM298)
394 return cardhu_pm298_regulator_init();
395
396 if (pmu_board_info.board_id == BOARD_PMU_PM299)
397 return cardhu_pm299_regulator_init();
398
399 /* The regulator details have complete constraints */
400 regulator_has_full_constraints();
401
402 /* PMU-E1208, the ldo2 should be set to 1200mV */
403 if (pmu_board_info.board_id == BOARD_E1208) {
404 pdata_ldo2_0.regulator.constraints.min_uV = 1200000;
405 pdata_ldo2_0.regulator.constraints.max_uV = 1200000;
406 }
407
408 /*
409 * E1198 will have different core regulator decoding.
410 * A01/A02: Based on sku bit 0.
411 * A03: Based on bit 2 and bit 0
412 * 2,0: 00 no core regulator,
413 * 01:TPS62365
414 * 10:TPS62366
415 * 11:TPS623850
416 */
417 if (board_info.board_id == BOARD_E1198) {
418 int vsels;
419 switch(board_info.fab) {
420 case BOARD_FAB_A00:
421 case BOARD_FAB_A01:
422 case BOARD_FAB_A02:
423 if (board_info.sku & SKU_DCDC_TPS62361_SUPPORT)
424 ext_core_regulator = true;
425 break;
426
427 case BOARD_FAB_A03:
428 vsels = ((board_info.sku >> 1) & 0x2) | (board_info.sku & 1);
429 switch(vsels) {
430 case 1:
431 ext_core_regulator = true;
432 tps62361_pdata.vsel0_def_state = 1;
433 tps62361_pdata.vsel1_def_state = 1;
434 break;
435 case 2:
436 ext_core_regulator = true;
437 tps62361_pdata.vsel0_def_state = 0;
438 tps62361_pdata.vsel1_def_state = 0;
439 break;
440 case 3:
441 ext_core_regulator = true;
442 tps62361_pdata.vsel0_def_state = 1;
443 tps62361_pdata.vsel1_def_state = 0;
444 break;
445 }
446 break;
447 }
448
449 pr_info("BoardId:SKU:Fab 0x%04x:0x%04x:0x%02x\n",
450 board_info.board_id, board_info.sku , board_info.fab);
451 pr_info("Core regulator %s\n",
452 (ext_core_regulator)? "true": "false");
453 pr_info("VSEL 1:0 %d%d\n",
454 tps62361_pdata.vsel1_def_state,
455 tps62361_pdata.vsel0_def_state);
456 }
457
458 if ((board_info.board_id == BOARD_E1291) &&
459 (board_info.sku & SKU_DCDC_TPS62361_SUPPORT))
460 ext_core_regulator = true;
461
462 if ((board_info.board_id == BOARD_E1198) ||
463 (board_info.board_id == BOARD_E1291)) {
464 if (ext_core_regulator) {
465 tps_platform.num_subdevs =
466 ARRAY_SIZE(tps_devs_e1198_skubit0_1);
467 tps_platform.subdevs = tps_devs_e1198_skubit0_1;
468 } else {
469 tps_platform.num_subdevs =
470 ARRAY_SIZE(tps_devs_e1198_skubit0_0);
471 tps_platform.subdevs = tps_devs_e1198_skubit0_0;
472 }
473 } else {
474 if (board_info.board_id == BOARD_PM269)
475 pdata_ldo3_e118x.slew_rate_uV_per_us = 250;
476
477 if (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT) {
478 tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_1);
479 tps_platform.subdevs = tps_devs_e118x_skubit0_1;
480 ext_core_regulator = true;
481 } else {
482 tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_0);
483 tps_platform.subdevs = tps_devs_e118x_skubit0_0;
484 }
485 }
486
487 /* E1291-A04/A05: Enable DEV_SLP and enable sleep on GPIO2 */
488 if ((board_info.board_id == BOARD_E1291) &&
489 ((board_info.fab == BOARD_FAB_A04) ||
490 (board_info.fab == BOARD_FAB_A05))) {
491 tps_platform.dev_slp_en = true;
492 tps_platform.gpio_init_data = tps_gpio_pdata_e1291_a04;
493 tps_platform.num_gpioinit_data =
494 ARRAY_SIZE(tps_gpio_pdata_e1291_a04);
495 }
496
497 i2c_register_board_info(4, cardhu_regulators, 1);
498
499 /* Register the external core regulator if it is require */
500 if (ext_core_regulator) {
501 pr_info("Registering the core regulator\n");
502 i2c_register_board_info(4, tps62361_boardinfo, 1);
503 }
504 return 0;
505}
506
507
508/**************** GPIO based fixed regulator *****************/
509/* EN_5V_CP from PMU GP0 */
510static struct regulator_consumer_supply fixed_reg_en_5v_cp_supply[] = {
511 REGULATOR_SUPPLY("vdd_5v0_sby", NULL),
512 REGULATOR_SUPPLY("vdd_hall", NULL),
513 REGULATOR_SUPPLY("vterm_ddr", NULL),
514 REGULATOR_SUPPLY("v2ref_ddr", NULL),
515};
516
517/* EN_5V0 From PMU GP2 */
518static struct regulator_consumer_supply fixed_reg_en_5v0_supply[] = {
519 REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
520};
521
522/* EN_DDR From PMU GP6 */
523static struct regulator_consumer_supply fixed_reg_en_ddr_supply[] = {
524 REGULATOR_SUPPLY("mem_vddio_ddr", NULL),
525 REGULATOR_SUPPLY("t30_vddio_ddr", NULL),
526};
527
528/* EN_3V3_SYS From PMU GP7 */
529static struct regulator_consumer_supply fixed_reg_en_3v3_sys_supply[] = {
530 REGULATOR_SUPPLY("vdd_lvds", NULL),
531 REGULATOR_SUPPLY("vdd_pnl", NULL),
532 REGULATOR_SUPPLY("vcom_3v3", NULL),
533 REGULATOR_SUPPLY("vdd_3v3", NULL),
534 REGULATOR_SUPPLY("vcore_mmc", NULL),
535 REGULATOR_SUPPLY("vddio_pex_ctl", NULL),
536 REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
537 REGULATOR_SUPPLY("hvdd_pex_pmu", NULL),
538 REGULATOR_SUPPLY("avdd_hdmi", NULL),
539 REGULATOR_SUPPLY("vpp_fuse", NULL),
540// REGULATOR_SUPPLY("avdd_usb", NULL),
541 REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
542 REGULATOR_SUPPLY("vcore_nand", NULL),
543 REGULATOR_SUPPLY("hvdd_sata", NULL),
544 REGULATOR_SUPPLY("vddio_gmi_pmu", NULL),
545 REGULATOR_SUPPLY("pwrdet_nand", NULL),
546 REGULATOR_SUPPLY("avdd_cam1", NULL),
547 REGULATOR_SUPPLY("vdd_af", NULL),
548 REGULATOR_SUPPLY("avdd_cam2", NULL),
549 REGULATOR_SUPPLY("vdd_acc", NULL),
550 REGULATOR_SUPPLY("vdd_phtl", NULL),
551 REGULATOR_SUPPLY("vddio_tp", NULL),
552 REGULATOR_SUPPLY("vdd_led", NULL),
553 REGULATOR_SUPPLY("vddio_cec", NULL),
554 REGULATOR_SUPPLY("vdd_cmps", NULL),
555 REGULATOR_SUPPLY("vdd_temp", NULL),
556 REGULATOR_SUPPLY("vpp_kfuse", NULL),
557 REGULATOR_SUPPLY("vddio_ts", NULL),
558 REGULATOR_SUPPLY("vdd_ir_led", NULL),
559 REGULATOR_SUPPLY("vddio_1wire", NULL),
560 REGULATOR_SUPPLY("avddio_audio", NULL),
561 REGULATOR_SUPPLY("vdd_ec", NULL),
562 REGULATOR_SUPPLY("vcom_pa", NULL),
563 REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
564 REGULATOR_SUPPLY("vdd_3v3_dock", NULL),
565 REGULATOR_SUPPLY("vdd_3v3_edid", NULL),
566 REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL),
567 REGULATOR_SUPPLY("vdd_3v3_gmi", NULL),
568 REGULATOR_SUPPLY("vdd_spk_amp", "tegra-snd-wm8903.0"),
569 REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
570 REGULATOR_SUPPLY("vdd_3v3_cam", NULL),
571 REGULATOR_SUPPLY("vdd_3v3_als", NULL),
572 REGULATOR_SUPPLY("debug_cons", NULL),
573 REGULATOR_SUPPLY("vdd", "1-004c"),
574};
575
576/* DIS_5V_SWITCH from AP SPI2_SCK X02 */
577static struct regulator_consumer_supply fixed_reg_dis_5v_switch_supply[] = {
578 REGULATOR_SUPPLY("master_5v_switch", NULL),
579};
580
581/* EN_VDD_BL */
582static struct regulator_consumer_supply fixed_reg_en_vdd_bl_supply[] = {
583 REGULATOR_SUPPLY("vdd_backlight", NULL),
584 REGULATOR_SUPPLY("vdd_backlight1", NULL),
585};
586
587/* EN_VDD_BL2 (E1291-A03) from AP PEX_L0_PRSNT_N DD.00 */
588static struct regulator_consumer_supply fixed_reg_en_vdd_bl2_supply[] = {
589 REGULATOR_SUPPLY("vdd_backlight2", NULL),
590};
591
592/* EN_3V3_MODEM from AP GPIO VI_VSYNCH D06*/
593static struct regulator_consumer_supply fixed_reg_en_3v3_modem_supply[] = {
594 REGULATOR_SUPPLY("vdd_3v3_mini_card", NULL),
595 REGULATOR_SUPPLY("vdd_mini_card", NULL),
596};
597
598/* EN_VDD_PNL1 from AP GPIO VI_D6 L04*/
599static struct regulator_consumer_supply fixed_reg_en_vdd_pnl1_supply[] = {
600 REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
601};
602
603/* CAM1_LDO_EN from AP GPIO KB_ROW6 R06*/
604static struct regulator_consumer_supply fixed_reg_cam1_ldo_en_supply[] = {
605 REGULATOR_SUPPLY("vdd_2v8_cam1", NULL),
606 REGULATOR_SUPPLY("vdd", "6-0072"),
607};
608
609/* CAM2_LDO_EN from AP GPIO KB_ROW7 R07*/
610static struct regulator_consumer_supply fixed_reg_cam2_ldo_en_supply[] = {
611 REGULATOR_SUPPLY("vdd_2v8_cam2", NULL),
612 REGULATOR_SUPPLY("vdd", "7-0072"),
613};
614
615/* CAM3_LDO_EN from AP GPIO KB_ROW8 S00*/
616static struct regulator_consumer_supply fixed_reg_cam3_ldo_en_supply[] = {
617 REGULATOR_SUPPLY("vdd_cam3", NULL),
618};
619
620/* EN_VDD_COM from AP GPIO SDMMC3_DAT5 D00*/
621static struct regulator_consumer_supply fixed_reg_en_vdd_com_supply[] = {
622 REGULATOR_SUPPLY("vdd_com_bd", NULL),
623};
624
625/* EN_VDD_SDMMC1 from AP GPIO VI_HSYNC D07*/
626static struct regulator_consumer_supply fixed_reg_en_vdd_sdmmc1_supply[] = {
627 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.0"),
628};
629
630/* EN_3V3_EMMC from AP GPIO SDMMC3_DAT4 D01*/
631static struct regulator_consumer_supply fixed_reg_en_3v3_emmc_supply[] = {
632 REGULATOR_SUPPLY("vdd_emmc_core", NULL),
633};
634
635/* EN_3V3_PEX_HVDD from AP GPIO VI_D09 L07*/
636static struct regulator_consumer_supply fixed_reg_en_3v3_pex_hvdd_supply[] = {
637 REGULATOR_SUPPLY("hvdd_pex", NULL),
638};
639
640/* EN_3v3_FUSE from AP GPIO VI_D08 L06*/
641static struct regulator_consumer_supply fixed_reg_en_3v3_fuse_supply[] = {
642 REGULATOR_SUPPLY("vdd_fuse", NULL),
643};
644
645/* EN_1V8_CAM from AP GPIO GPIO_PBB4 PBB04*/
646static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
647 REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
648 REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
649 REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
650 REGULATOR_SUPPLY("vdd_i2c", "6-0072"),
651 REGULATOR_SUPPLY("vdd_i2c", "7-0072"),
652 REGULATOR_SUPPLY("vdd_i2c", "2-0033"),
653};
654
655static struct regulator_consumer_supply fixed_reg_en_vbrtr_supply[] = {
656 REGULATOR_SUPPLY("vdd_vbrtr", NULL),
657};
658
659/* EN_USB1_VBUS_OC*/
660static struct regulator_consumer_supply gpio_switch_en_usb1_vbus_oc_supply[] = {
661 REGULATOR_SUPPLY("vdd_vbus_micro_usb", NULL),
662};
663static int gpio_switch_en_usb1_vbus_oc_voltages[] = { 5000};
664
665/*EN_USB3_VBUS_OC*/
666static struct regulator_consumer_supply gpio_switch_en_usb3_vbus_oc_supply[] = {
667 REGULATOR_SUPPLY("vdd_vbus_typea_usb", NULL),
668};
669static int gpio_switch_en_usb3_vbus_oc_voltages[] = { 5000};
670
671/* EN_VDDIO_VID_OC from AP GPIO VI_PCLK T00*/
672static struct regulator_consumer_supply gpio_switch_en_vddio_vid_oc_supply[] = {
673 REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
674};
675static int gpio_switch_en_vddio_vid_oc_voltages[] = { 5000};
676
677static int enable_load_switch_rail(
678 struct gpio_switch_regulator_subdev_data *psubdev_data)
679{
680 int ret;
681
682 if (psubdev_data->pin_group <= 0)
683 return -EINVAL;
684
685 /* Tristate and make pin as input*/
686 ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
687 TEGRA_TRI_TRISTATE);
688 if (ret < 0)
689 return ret;
690 return gpio_direction_input(psubdev_data->gpio_nr);
691}
692
693static int disable_load_switch_rail(
694 struct gpio_switch_regulator_subdev_data *psubdev_data)
695{
696 int ret;
697
698 if (psubdev_data->pin_group <= 0)
699 return -EINVAL;
700
701 /* Un-tristate and driver low */
702 ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
703 TEGRA_TRI_NORMAL);
704 if (ret < 0)
705 return ret;
706 return gpio_direction_output(psubdev_data->gpio_nr, 0);
707}
708
709/* Macro for defining gpio switch regulator sub device data */
710#define GREG_INIT(_id, _var, _name, _input_supply, _always_on, _boot_on, \
711 _gpio_nr, _active_low, _init_state, _pg, _enable, _disable) \
712 static struct gpio_switch_regulator_subdev_data gpio_pdata_##_var = \
713 { \
714 .regulator_name = "gpio-switch-"#_name, \
715 .input_supply = _input_supply, \
716 .id = _id, \
717 .gpio_nr = _gpio_nr, \
718 .pin_group = _pg, \
719 .active_low = _active_low, \
720 .init_state = _init_state, \
721 .voltages = gpio_switch_##_name##_voltages, \
722 .n_voltages = ARRAY_SIZE(gpio_switch_##_name##_voltages), \
723 .num_consumer_supplies = \
724 ARRAY_SIZE(gpio_switch_##_name##_supply), \
725 .consumer_supplies = gpio_switch_##_name##_supply, \
726 .constraints = { \
727 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
728 REGULATOR_MODE_STANDBY), \
729 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
730 REGULATOR_CHANGE_STATUS | \
731 REGULATOR_CHANGE_VOLTAGE), \
732 .always_on = _always_on, \
733 .boot_on = _boot_on, \
734 }, \
735 .enable_rail = _enable, \
736 .disable_rail = _disable, \
737 }; \
738 static struct gpio_switch_regulator_subdev_data \
739 *gpio_pdata_##_var##_list[] = { \
740 &gpio_pdata_##_var, \
741 }; \
742 static struct gpio_switch_regulator_platform_data gs_##_var##_pdata = \
743 { \
744 .num_subdevs = 1, \
745 .subdevs = gpio_pdata_##_var##_list, \
746 }; \
747 static struct platform_device gswitch_reg_##_var##_dev = { \
748 .name = "gpio-switch-regulator", \
749 .id = _id, \
750 .dev = { \
751 .platform_data = &gs_##_var##_pdata, \
752 }, \
753 }
754
755/* Macro for defining fixed regulator sub device data */
756#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
757#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
758 _gpio_nr, _active_high, _boot_state, _millivolts) \
759 static struct regulator_init_data ri_data_##_var = \
760 { \
761 .supply_regulator = _in_supply, \
762 .num_consumer_supplies = \
763 ARRAY_SIZE(fixed_reg_##_name##_supply), \
764 .consumer_supplies = fixed_reg_##_name##_supply, \
765 .constraints = { \
766 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
767 REGULATOR_MODE_STANDBY), \
768 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
769 REGULATOR_CHANGE_STATUS | \
770 REGULATOR_CHANGE_VOLTAGE), \
771 .always_on = _always_on, \
772 .boot_on = _boot_on, \
773 }, \
774 }; \
775 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
776 { \
777 .supply_name = FIXED_SUPPLY(_name), \
778 .microvolts = _millivolts * 1000, \
779 .gpio = _gpio_nr, \
780 .enable_high = _active_high, \
781 .enabled_at_boot = _boot_state, \
782 .init_data = &ri_data_##_var, \
783 }; \
784 static struct platform_device fixed_reg_##_var##_dev = { \
785 .name = "reg-fixed-voltage", \
786 .id = _id, \
787 .dev = { \
788 .platform_data = &fixed_reg_##_var##_pdata, \
789 }, \
790 }
791
792/* common to most of boards*/
793FIXED_REG(0, en_5v_cp, en_5v_cp, NULL, 1, 0, TPS6591X_GPIO_0, true, 1, 5000);
794FIXED_REG(1, en_5v0, en_5v0, NULL, 0, 0, TPS6591X_GPIO_2, true, 0, 5000);
795FIXED_REG(2, en_ddr, en_ddr, NULL, 1, 0, TPS6591X_GPIO_6, true, 1, 1500);
796FIXED_REG(3, en_3v3_sys, en_3v3_sys, NULL, 0, 0, TPS6591X_GPIO_7, true, 1, 3300);
797//FIXED_REG(4, en_vdd_bl, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PK3, true, 1, 5000);
798FIXED_REG(4, en_vdd_bl, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PQ7, true, 1, 5000);
799FIXED_REG(5, en_3v3_modem, en_3v3_modem, NULL, 1, 0, TEGRA_GPIO_PD6, true, 1, 3300);
800//FIXED_REG(6, en_vdd_pnl1, en_vdd_pnl1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PL4, true, 1, 3300);
801FIXED_REG(6, en_vdd_pnl1, en_vdd_pnl1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PQ5, true, 1, 3300);
802FIXED_REG(7, cam3_ldo_en, cam3_ldo_en, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PS0, true, 0, 3300);
803FIXED_REG(8, en_vdd_com, en_vdd_com, FIXED_SUPPLY(en_3v3_sys), 1, 0, TEGRA_GPIO_PD0, true, 1, 3300);
804//FIXED_REG(9, en_3v3_fuse, en_3v3_fuse, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PL6, true, 0, 3300);
805FIXED_REG(9, en_3v3_fuse, en_3v3_fuse, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PP7, true, 0, 3300);
806FIXED_REG(10, en_3v3_emmc, en_3v3_emmc, FIXED_SUPPLY(en_3v3_sys), 1, 0, TEGRA_GPIO_PD1, true, 1, 3300);
807//FIXED_REG(11, en_vdd_sdmmc1, en_vdd_sdmmc1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PD7, true, 1, 3300);
808FIXED_REG(11, en_vdd_sdmmc1, en_vdd_sdmmc1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PD4, false, 1, 3300);
809FIXED_REG(12, en_3v3_pex_hvdd, en_3v3_pex_hvdd, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PD3, true, 0, 3300);
810FIXED_REG(13, en_1v8_cam, en_1v8_cam, tps6591x_rails(VIO), 0, 0, TEGRA_GPIO_PBB4, true, 0, 1800);
811
812/* Specific to E1187/E1186/E1256 */
813FIXED_REG(14, dis_5v_switch_e118x, dis_5v_switch, FIXED_SUPPLY(en_5v0), 0, 0, TEGRA_GPIO_PX2, false, 0, 5000);
814
815/* E1291-A04/A05 specific */
816FIXED_REG(1, en_5v0_a04, en_5v0, NULL, 0, 0, TPS6591X_GPIO_8, true, 0, 5000);
817FIXED_REG(2, en_ddr_a04, en_ddr, NULL, 1, 0, TPS6591X_GPIO_7, true, 1, 1500);
818FIXED_REG(3, en_3v3_sys_a04, en_3v3_sys, NULL, 0, 0, TPS6591X_GPIO_6, true, 1, 3300);
819
820/* Specific to pm269 */
821FIXED_REG(4, en_vdd_bl_pm269, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PH3, true, 1, 5000);
822#ifndef CONFIG_TEGRA_CARDHU_DSI
823FIXED_REG(6, en_vdd_pnl1_pm269, en_vdd_pnl1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PW1, true, 1, 3300);
824#endif
825FIXED_REG(9, en_3v3_fuse_pm269, en_3v3_fuse, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PC1, true, 0, 3300);
826FIXED_REG(12, en_3v3_pex_hvdd_pm269, en_3v3_pex_hvdd, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PC6, true, 0, 3300);
827
828/* E1198/E1291 specific*/
829FIXED_REG(18, cam1_ldo_en, cam1_ldo_en, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PR6, true, 0, 2800);
830FIXED_REG(19, cam2_ldo_en, cam2_ldo_en, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PR7, true, 0, 2800);
831
832/* E1291 A03 specific */
833FIXED_REG(20, en_vdd_bl1_a03, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PDD2, true, 1, 5000);
834FIXED_REG(21, en_vdd_bl2_a03, en_vdd_bl2, NULL, 0, 0, TEGRA_GPIO_PDD0, true, 1, 5000);
835FIXED_REG(22, en_vbrtr, en_vbrtr, FIXED_SUPPLY(en_3v3_sys), 0, 0, PMU_TCA6416_GPIO_PORT12,true, 0, 3300);
836
837/* PM313 display board specific */
838FIXED_REG(4, en_vdd_bl_pm313, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PK3, true, 1, 5000);
839FIXED_REG(6, en_vdd_pnl1_pm313, en_vdd_pnl1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PH3, true, 1, 3300);
840
841
842/****************** Open collector Load switches *******/
843/*Specific to pm269*/
844GREG_INIT(17, en_vddio_vid_oc_pm269, en_vddio_vid_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PP2, false, 0, TEGRA_PINGROUP_DAP3_DOUT,
845 enable_load_switch_rail, disable_load_switch_rail);
846
847/* Specific to pm311 */
848GREG_INIT(15, en_usb1_vbus_oc_pm311, en_usb1_vbus_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PCC7, false, 0, TEGRA_PINGROUP_GMI_RST_N,
849 enable_load_switch_rail, disable_load_switch_rail);
850GREG_INIT(16, en_usb3_vbus_oc_pm311, en_usb3_vbus_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PCC6, false, 0, TEGRA_PINGROUP_GMI_AD15,
851 enable_load_switch_rail, disable_load_switch_rail);
852
853/* Specific to E1187/E1186/E1256 */
854GREG_INIT(15, en_usb1_vbus_oc_e118x, en_usb1_vbus_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PI4, false, 0, TEGRA_PINGROUP_GMI_RST_N,
855 enable_load_switch_rail, disable_load_switch_rail);
856GREG_INIT(16, en_usb3_vbus_oc_e118x, en_usb3_vbus_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PH7, false, 0, TEGRA_PINGROUP_GMI_AD15,
857 enable_load_switch_rail, disable_load_switch_rail);
858GREG_INIT(17, en_vddio_vid_oc_e118x, en_vddio_vid_oc, "master_5v_switch", 0, 0, TEGRA_GPIO_PT0, false, 0, TEGRA_PINGROUP_VI_PCLK,
859 enable_load_switch_rail, disable_load_switch_rail);
860
861/* E1198/E1291 specific fab < A03 */
862GREG_INIT(15, en_usb1_vbus_oc, en_usb1_vbus_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PI4, false, 0, TEGRA_PINGROUP_GMI_RST_N,
863 enable_load_switch_rail, disable_load_switch_rail);
864GREG_INIT(16, en_usb3_vbus_oc, en_usb3_vbus_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PH7, false, 0, TEGRA_PINGROUP_GMI_AD15,
865 enable_load_switch_rail, disable_load_switch_rail);
866
867/* E1198/E1291 specific fab >= A03 */
868GREG_INIT(15, en_usb1_vbus_oc_a03, en_usb1_vbus_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PDD6, false, 0, TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
869 enable_load_switch_rail, disable_load_switch_rail);
870GREG_INIT(16, en_usb3_vbus_oc_a03, en_usb3_vbus_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PDD4, false, 0, TEGRA_PINGROUP_PEX_L1_PRSNT_N,
871 enable_load_switch_rail, disable_load_switch_rail);
872
873/* E1198/E1291 specific */
874//GREG_INIT(17, en_vddio_vid_oc, en_vddio_vid_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PT0, false, 0, TEGRA_PINGROUP_VI_PCLK,
875// enable_load_switch_rail, disable_load_switch_rail);
876
877GREG_INIT(17, en_vddio_vid_oc, en_vddio_vid_oc, "vdd_5v0_sys", 0, 0, TEGRA_GPIO_PQ6, false, 0, TEGRA_PINGROUP_VI_PCLK,
878 enable_load_switch_rail, disable_load_switch_rail);
879
880/*
881 * Creating the fixed/gpio-switch regulator device tables for different boards
882 */
883#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
884#define ADD_GPIO_REG(_name) (&gswitch_reg_##_name##_dev)
885
886#define COMMON_FIXED_REG \
887 ADD_FIXED_REG(en_5v_cp), \
888 ADD_FIXED_REG(en_5v0), \
889 ADD_FIXED_REG(en_ddr), \
890 ADD_FIXED_REG(en_3v3_sys), \
891 ADD_FIXED_REG(en_3v3_modem), \
892 ADD_FIXED_REG(en_vdd_pnl1), \
893 ADD_FIXED_REG(cam3_ldo_en), \
894 ADD_FIXED_REG(en_vdd_com), \
895 ADD_FIXED_REG(en_3v3_fuse), \
896 ADD_FIXED_REG(en_3v3_emmc), \
897 ADD_FIXED_REG(en_vdd_sdmmc1), \
898 ADD_FIXED_REG(en_3v3_pex_hvdd), \
899 ADD_FIXED_REG(en_1v8_cam),
900
901#define COMMON_FIXED_REG_E1291_A04 \
902 ADD_FIXED_REG(en_5v_cp), \
903 ADD_FIXED_REG(en_5v0_a04), \
904 ADD_FIXED_REG(en_ddr_a04), \
905 ADD_FIXED_REG(en_3v3_sys_a04), \
906 ADD_FIXED_REG(en_vdd_pnl1), \
907 ADD_FIXED_REG(en_3v3_fuse), \
908 ADD_FIXED_REG(en_3v3_emmc), \
909 ADD_FIXED_REG(en_vdd_sdmmc1), \
910 ADD_FIXED_REG(en_3v3_pex_hvdd),
911
912/*
913#define COMMON_FIXED_REG_E1291_A04 \
914 ADD_FIXED_REG(en_5v_cp), \
915 ADD_FIXED_REG(en_5v0_a04), \
916 ADD_FIXED_REG(en_ddr_a04), \
917 ADD_FIXED_REG(en_3v3_sys_a04), \
918 ADD_FIXED_REG(en_3v3_modem), \ //not used Carma
919 ADD_FIXED_REG(en_vdd_pnl1), \ //not used Carma
920 ADD_FIXED_REG(cam3_ldo_en), \ //not used Carma
921 ADD_FIXED_REG(en_vdd_com), \ //not used Carma
922 ADD_FIXED_REG(en_3v3_fuse), \
923 ADD_FIXED_REG(en_3v3_emmc), \
924 ADD_FIXED_REG(en_vdd_sdmmc1), \
925 ADD_FIXED_REG(en_3v3_pex_hvdd), \
926 ADD_FIXED_REG(en_1v8_cam), //not used Carma
927*/
928
929#define PM269_FIXED_REG \
930 ADD_FIXED_REG(en_5v_cp), \
931 ADD_FIXED_REG(en_5v0), \
932 ADD_FIXED_REG(en_ddr), \
933 ADD_FIXED_REG(en_3v3_sys), \
934 ADD_FIXED_REG(en_3v3_modem), \
935 ADD_FIXED_REG(cam1_ldo_en), \
936 ADD_FIXED_REG(cam2_ldo_en), \
937 ADD_FIXED_REG(cam3_ldo_en), \
938 ADD_FIXED_REG(en_vdd_com), \
939 ADD_FIXED_REG(en_3v3_fuse_pm269), \
940 ADD_FIXED_REG(en_3v3_emmc), \
941 ADD_FIXED_REG(en_3v3_pex_hvdd_pm269), \
942 ADD_FIXED_REG(en_1v8_cam), \
943 ADD_FIXED_REG(dis_5v_switch_e118x), \
944 ADD_GPIO_REG(en_usb1_vbus_oc_e118x), \
945 ADD_GPIO_REG(en_usb3_vbus_oc_e118x), \
946 ADD_GPIO_REG(en_vddio_vid_oc_pm269),
947
948#define PM311_FIXED_REG \
949 ADD_FIXED_REG(en_5v_cp), \
950 ADD_FIXED_REG(en_5v0), \
951 ADD_FIXED_REG(en_ddr), \
952 ADD_FIXED_REG(en_3v3_sys), \
953 ADD_FIXED_REG(en_3v3_modem), \
954 ADD_FIXED_REG(cam1_ldo_en), \
955 ADD_FIXED_REG(cam2_ldo_en), \
956 ADD_FIXED_REG(cam3_ldo_en), \
957 ADD_FIXED_REG(en_vdd_com), \
958 ADD_FIXED_REG(en_3v3_fuse_pm269), \
959 ADD_FIXED_REG(en_3v3_emmc), \
960 ADD_FIXED_REG(en_3v3_pex_hvdd_pm269), \
961 ADD_FIXED_REG(en_1v8_cam), \
962 ADD_FIXED_REG(dis_5v_switch_e118x), \
963 ADD_GPIO_REG(en_usb1_vbus_oc_pm311), \
964 ADD_GPIO_REG(en_usb3_vbus_oc_pm311), \
965 ADD_GPIO_REG(en_vddio_vid_oc_pm269),
966
967
968#ifndef CONFIG_TEGRA_CARDHU_DSI
969#define E1247_DISPLAY_FIXED_REG \
970 ADD_FIXED_REG(en_vdd_bl_pm269), \
971 ADD_FIXED_REG(en_vdd_pnl1_pm269),
972#else
973#define E1247_DISPLAY_FIXED_REG \
974 ADD_FIXED_REG(en_vdd_bl_pm269),
975#endif
976
977#define PM313_DISPLAY_FIXED_REG \
978 ADD_FIXED_REG(en_vdd_bl_pm313), \
979 ADD_FIXED_REG(en_vdd_pnl1_pm313),
980
981#define E118x_FIXED_REG \
982 ADD_FIXED_REG(en_5v_cp), \
983 ADD_FIXED_REG(en_5v0), \
984 ADD_FIXED_REG(en_ddr), \
985 ADD_FIXED_REG(en_3v3_sys), \
986 ADD_FIXED_REG(en_3v3_modem), \
987 ADD_FIXED_REG(cam3_ldo_en), \
988 ADD_FIXED_REG(en_vdd_com), \
989 ADD_FIXED_REG(en_3v3_fuse), \
990 ADD_FIXED_REG(en_3v3_emmc), \
991 ADD_FIXED_REG(en_vdd_sdmmc1), \
992 ADD_FIXED_REG(en_3v3_pex_hvdd), \
993 ADD_FIXED_REG(en_1v8_cam), \
994 ADD_FIXED_REG(dis_5v_switch_e118x), \
995 ADD_FIXED_REG(en_vbrtr), \
996 ADD_GPIO_REG(en_usb1_vbus_oc_e118x), \
997 ADD_GPIO_REG(en_usb3_vbus_oc_e118x), \
998 ADD_GPIO_REG(en_vddio_vid_oc_e118x),
999
1000#define E1198_FIXED_REG \
1001 ADD_GPIO_REG(en_vddio_vid_oc),
1002
1003#define E1291_1198_A00_FIXED_REG \
1004 ADD_FIXED_REG(en_vdd_bl), \
1005 ADD_GPIO_REG(en_usb1_vbus_oc), \
1006 ADD_GPIO_REG(en_usb3_vbus_oc),
1007
1008#define E1291_A03_FIXED_REG \
1009 ADD_FIXED_REG(en_vdd_bl1_a03), \
1010 ADD_FIXED_REG(en_vdd_bl2_a03), \
1011 ADD_GPIO_REG(en_usb1_vbus_oc_a03), \
1012 ADD_GPIO_REG(en_usb3_vbus_oc_a03),
1013
1014/* Fixed regulator devices for E1186/E1187/E1256 */
1015static struct platform_device *fixed_reg_devs_e118x[] = {
1016 E118x_FIXED_REG
1017 E1247_DISPLAY_FIXED_REG
1018};
1019
1020/* Fixed regulator devices for E1186/E1187/E1256 */
1021static struct platform_device *fixed_reg_devs_e118x_pm313[] = {
1022 E118x_FIXED_REG
1023 PM313_DISPLAY_FIXED_REG
1024};
1025
1026/* Fixed regulator devices for E1198 and E1291 */
1027static struct platform_device *fixed_reg_devs_e1198_base[] = {
1028 COMMON_FIXED_REG
1029 E1291_1198_A00_FIXED_REG
1030 E1198_FIXED_REG
1031};
1032
1033static struct platform_device *fixed_reg_devs_e1198_a02[] = {
1034 ADD_FIXED_REG(en_5v_cp),
1035 ADD_FIXED_REG(en_5v0),
1036 ADD_FIXED_REG(en_ddr_a04),
1037 ADD_FIXED_REG(en_3v3_sys_a04),
1038 ADD_FIXED_REG(en_3v3_modem),
1039 ADD_FIXED_REG(en_vdd_pnl1),
1040 ADD_FIXED_REG(cam3_ldo_en),
1041 ADD_FIXED_REG(en_vdd_com),
1042 ADD_FIXED_REG(en_3v3_fuse),
1043 ADD_FIXED_REG(en_3v3_emmc),
1044 ADD_FIXED_REG(en_vdd_sdmmc1),
1045 ADD_FIXED_REG(en_3v3_pex_hvdd),
1046 ADD_FIXED_REG(en_1v8_cam),
1047 ADD_FIXED_REG(en_vdd_bl1_a03),
1048 ADD_FIXED_REG(en_vdd_bl2_a03),
1049 ADD_FIXED_REG(cam1_ldo_en),
1050 ADD_FIXED_REG(cam2_ldo_en),
1051 ADD_GPIO_REG(en_usb1_vbus_oc_a03),
1052 ADD_GPIO_REG(en_usb3_vbus_oc_a03),
1053 ADD_GPIO_REG(en_vddio_vid_oc),
1054};
1055
1056/* Fixed regulator devices for PM269 */
1057static struct platform_device *fixed_reg_devs_pm269[] = {
1058 PM269_FIXED_REG
1059 E1247_DISPLAY_FIXED_REG
1060};
1061
1062/* Fixed regulator devices for PM269 */
1063static struct platform_device *fixed_reg_devs_pm269_pm313[] = {
1064 PM269_FIXED_REG
1065 PM313_DISPLAY_FIXED_REG
1066};
1067
1068/* Fixed regulator devices for PM311 */
1069static struct platform_device *fixed_reg_devs_pm311[] = {
1070 PM311_FIXED_REG
1071 E1247_DISPLAY_FIXED_REG
1072};
1073
1074/* Fixed regulator devices for PM11 */
1075static struct platform_device *fixed_reg_devs_pm311_pm313[] = {
1076 PM311_FIXED_REG
1077 PM313_DISPLAY_FIXED_REG
1078};
1079
1080/* Fixed regulator devices for E1291 A03 */
1081static struct platform_device *fixed_reg_devs_e1291_a03[] = {
1082 COMMON_FIXED_REG
1083 E1291_A03_FIXED_REG
1084 E1198_FIXED_REG
1085};
1086
1087/* Fixed regulator devices for E1291 A04/A05 */
1088static struct platform_device *fixed_reg_devs_e1291_a04[] = {
1089 COMMON_FIXED_REG_E1291_A04
1090 E1291_A03_FIXED_REG
1091 E1198_FIXED_REG
1092};
1093
1094int __init cardhu_fixed_regulator_init(void)
1095{
1096 int i;
1097 struct board_info board_info;
1098 struct board_info pmu_board_info;
1099 struct board_info display_board_info;
1100 struct platform_device **fixed_reg_devs;
1101 int nfixreg_devs;
1102
1103 if (!machine_is_cardhu())
1104 return 0;
1105
1106 tegra_get_board_info(&board_info);
1107 tegra_get_pmu_board_info(&pmu_board_info);
1108 tegra_get_display_board_info(&display_board_info);
1109
1110 if (pmu_board_info.board_id == BOARD_PMU_PM298)
1111 return cardhu_pm298_gpio_switch_regulator_init();
1112
1113 if (pmu_board_info.board_id == BOARD_PMU_PM299)
1114 return cardhu_pm299_gpio_switch_regulator_init();
1115
1116 switch (board_info.board_id) {
1117 case BOARD_E1198:
1118 if (board_info.fab <= BOARD_FAB_A01) {
1119 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_base);
1120 fixed_reg_devs = fixed_reg_devs_e1198_base;
1121 } else {
1122 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_a02);
1123 fixed_reg_devs = fixed_reg_devs_e1198_a02;
1124 }
1125 break;
1126
1127 case BOARD_E1291:
1128 if (board_info.fab == BOARD_FAB_A03) {
1129 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1291_a03);
1130 fixed_reg_devs = fixed_reg_devs_e1291_a03;
1131 } else if ((board_info.fab == BOARD_FAB_A04) ||
1132 (board_info.fab == BOARD_FAB_A05)) {
1133 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1291_a04);
1134 fixed_reg_devs = fixed_reg_devs_e1291_a04;
1135 } else {
1136 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e1198_base);
1137 fixed_reg_devs = fixed_reg_devs_e1198_base;
1138 }
1139 break;
1140
1141 case BOARD_PM311:
1142 case BOARD_PM305:
1143 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm311);
1144 fixed_reg_devs = fixed_reg_devs_pm311;
1145 if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1146 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm311_pm313);
1147 fixed_reg_devs = fixed_reg_devs_pm311_pm313;
1148 }
1149 break;
1150
1151 case BOARD_PM269:
1152 case BOARD_E1257:
1153 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269);
1154 fixed_reg_devs = fixed_reg_devs_pm269;
1155 if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1156 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269_pm313);
1157 fixed_reg_devs = fixed_reg_devs_pm269_pm313;
1158 } else {
1159 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm269);
1160 fixed_reg_devs = fixed_reg_devs_pm269;
1161 }
1162 break;
1163
1164 default:
1165 if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1166 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e118x_pm313);
1167 fixed_reg_devs = fixed_reg_devs_e118x_pm313;
1168 } else {
1169 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_e118x);
1170 fixed_reg_devs = fixed_reg_devs_e118x;
1171 }
1172 break;
1173 }
1174
1175 for (i = 0; i < nfixreg_devs; ++i) {
1176 int gpio_nr;
1177 if (!strncmp(fixed_reg_devs[i]->name, "gpio", 4)) {
1178 struct gpio_switch_regulator_platform_data *gs_pdata =
1179 fixed_reg_devs[i]->dev.platform_data;
1180 gpio_nr = gs_pdata->subdevs[0]->gpio_nr;
1181 } else {
1182 struct fixed_voltage_config *fixed_reg_pdata =
1183 fixed_reg_devs[i]->dev.platform_data;
1184 gpio_nr = fixed_reg_pdata->gpio;
1185 }
1186
1187 if (gpio_nr < TEGRA_NR_GPIOS)
1188 tegra_gpio_enable(gpio_nr);
1189 }
1190 return platform_add_devices(fixed_reg_devs, nfixreg_devs);
1191}
1192subsys_initcall_sync(cardhu_fixed_regulator_init);
1193
1194static void cardhu_board_suspend(int lp_state, enum suspend_stage stg)
1195{
1196 if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
1197 tegra_console_uart_suspend();
1198}
1199
1200static void cardhu_board_resume(int lp_state, enum resume_stage stg)
1201{
1202 if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
1203 tegra_console_uart_resume();
1204}
1205
1206static struct tegra_suspend_platform_data cardhu_suspend_data = {
1207 .cpu_timer = 2000,
1208 .cpu_off_timer = 200,
1209 .suspend_mode = TEGRA_SUSPEND_LP0,
1210 .core_timer = 0x7e7e,
1211 .core_off_timer = 0,
1212 .corereq_high = true,
1213 .sysclkreq_high = true,
1214 .cpu_lp2_min_residency = 2000,
1215 .board_suspend = cardhu_board_suspend,
1216 .board_resume = cardhu_board_resume,
1217};
1218
1219int __init cardhu_suspend_init(void)
1220{
1221 struct board_info board_info;
1222 struct board_info pmu_board_info;
1223
1224 tegra_get_board_info(&board_info);
1225 tegra_get_pmu_board_info(&pmu_board_info);
1226
1227 /* For PMU Fab A03, A04 and A05 make core_pwr_req to high */
1228 if ((pmu_board_info.fab == BOARD_FAB_A03) ||
1229 (pmu_board_info.fab == BOARD_FAB_A04) ||
1230 (pmu_board_info.fab == BOARD_FAB_A05))
1231 cardhu_suspend_data.corereq_high = true;
1232
1233 /* CORE_PWR_REQ to be high for all processor/pmu board whose sku bit 0
1234 * is set. This is require to enable the dc-dc converter tps62361x */
1235 if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) || (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT))
1236 cardhu_suspend_data.corereq_high = true;
1237
1238 switch (board_info.board_id) {
1239 case BOARD_E1291:
1240 /* CORE_PWR_REQ to be high for E1291-A03 */
1241 if (board_info.fab == BOARD_FAB_A03)
1242 cardhu_suspend_data.corereq_high = true;
1243 break;
1244 case BOARD_E1198:
1245 case BOARD_PM269:
1246 case BOARD_PM305:
1247 case BOARD_PM311:
1248 break;
1249 case BOARD_E1187:
1250 case BOARD_E1186:
1251 case BOARD_E1256:
1252 case BOARD_E1257:
1253 cardhu_suspend_data.cpu_timer = 5000;
1254 cardhu_suspend_data.cpu_off_timer = 5000;
1255 break;
1256 default:
1257 break;
1258 }
1259
1260 tegra_init_suspend(&cardhu_suspend_data);
1261 return 0;
1262}
1263
1264static struct tegra_tsensor_pmu_data tpdata = {
1265 .poweroff_reg_addr = 0x3F,
1266 .poweroff_reg_data = 0x80,
1267 .reset_tegra = 1,
1268 .controller_type = 0,
1269 .i2c_controller_id = 1,
1270 .pinmux = 0,
1271 .pmu_16bit_ops = 0,
1272 .pmu_i2c_addr = 0x2D,
1273};
1274
1275#ifdef CONFIG_TEGRA_EDP_LIMITS
1276
1277int __init cardhu_edp_init(void)
1278{
1279 unsigned int regulator_mA;
1280
1281 regulator_mA = get_maximum_cpu_current_supported();
1282 if (!regulator_mA) {
1283 regulator_mA = 6000; /* regular T30/s */
1284 }
1285 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1286
1287 tegra_init_cpu_edp_limits(regulator_mA);
1288 return 0;
1289}
1290#endif
1291
1292static char *cardhu_battery[] = {
1293 "bq27510-0",
1294};
1295
1296static struct gpio_charger_platform_data cardhu_charger_pdata = {
1297 .name = "ac",
1298 .type = POWER_SUPPLY_TYPE_MAINS,
1299 .gpio = AC_PRESENT_GPIO,
1300 .gpio_active_low = 0,
1301 .supplied_to = cardhu_battery,
1302 .num_supplicants = ARRAY_SIZE(cardhu_battery),
1303};
1304
1305static struct platform_device cardhu_charger_device = {
1306 .name = "gpio-charger",
1307 .dev = {
1308 .platform_data = &cardhu_charger_pdata,
1309 },
1310};
1311
1312static int __init cardhu_charger_late_init(void)
1313{
1314 if (!machine_is_cardhu())
1315 return 0;
1316
1317 platform_device_register(&cardhu_charger_device);
1318 return 0;
1319}
1320
1321late_initcall(cardhu_charger_late_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 21:15:29 -0400