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-rw-r--r--arch/arm/mach-tegra/board-cardhu-pinmux.c796
1 files changed, 796 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c
new file mode 100644
index 00000000000..de6f8d269b5
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+++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c
@@ -0,0 +1,796 @@
1/*
2 * arch/arm/mach-tegra/board-cardhu-pinmux.c
3 *
4 * Copyright (C) 2010 NVIDIA Corporation
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <mach/pinmux.h>
20#include "board.h"
21#include "board-cardhu.h"
22#include "gpio-names.h"
23
24#define DEFAULT_DRIVE(_name) \
25 { \
26 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
27 .hsm = TEGRA_HSM_DISABLE, \
28 .schmitt = TEGRA_SCHMITT_ENABLE, \
29 .drive = TEGRA_DRIVE_DIV_1, \
30 .pull_down = TEGRA_PULL_31, \
31 .pull_up = TEGRA_PULL_31, \
32 .slew_rising = TEGRA_SLEW_SLOWEST, \
33 .slew_falling = TEGRA_SLEW_SLOWEST, \
34 }
35/* Setting the drive strength of pins
36 * hsm: Enable High speed mode (ENABLE/DISABLE)
37 * Schimit: Enable/disable schimit (ENABLE/DISABLE)
38 * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
39 * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
40 * strength code. Value from 0 to 31.
41 * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
42 * strength code. Value from 0 to 31.
43 * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
44 * code 11 is least slewing of signal. code 00 is highest
45 * slewing of the signal.
46 * Value - FASTEST, FAST, SLOW, SLOWEST
47 * pullup_slew - Driver Output Pull-Down slew control code -
48 * code 11 is least slewing of signal. code 00 is highest
49 * slewing of the signal.
50 * Value - FASTEST, FAST, SLOW, SLOWEST
51 */
52#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
53 { \
54 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
55 .hsm = TEGRA_HSM_##_hsm, \
56 .schmitt = TEGRA_SCHMITT_##_schmitt, \
57 .drive = TEGRA_DRIVE_##_drive, \
58 .pull_down = TEGRA_PULL_##_pulldn_drive, \
59 .pull_up = TEGRA_PULL_##_pullup_drive, \
60 .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
61 .slew_falling = TEGRA_SLEW_##_pullup_slew, \
62 }
63
64/* !!!FIXME!!!! POPULATE THIS TABLE */
65static __initdata struct tegra_drive_pingroup_config cardhu_drive_pinmux[] = {
66 /* DEFAULT_DRIVE(<pin_group>), */
67 /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */
68 SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
69
70 /* All I2C pins are driven to maximum drive strength */
71 /* GEN1 I2C */
72 SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
73
74 /* GEN2 I2C */
75 SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
76
77 /* CAM I2C */
78 SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
79
80 /* DDC I2C */
81 SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
82
83 /* PWR_I2C */
84 SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
85
86 /* UART3 */
87 SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
88
89 /* SDMMC1 */
90 SET_DRIVE(SDIO1, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
91
92 /* SDMMC3 */
93 SET_DRIVE(SDIO3, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
94
95 /* SDMMC4 */
96 SET_DRIVE(GMA, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
97 SET_DRIVE(GMB, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
98 SET_DRIVE(GMC, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
99 SET_DRIVE(GMD, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
100
101};
102
103#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \
104 { \
105 .pingroup = TEGRA_PINGROUP_##_pingroup, \
106 .func = TEGRA_MUX_##_mux, \
107 .pupd = TEGRA_PUPD_##_pupd, \
108 .tristate = TEGRA_TRI_##_tri, \
109 .io = TEGRA_PIN_##_io, \
110 .lock = TEGRA_PIN_LOCK_DEFAULT, \
111 .od = TEGRA_PIN_OD_DEFAULT, \
112 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
113 }
114
115#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
116 { \
117 .pingroup = TEGRA_PINGROUP_##_pingroup, \
118 .func = TEGRA_MUX_##_mux, \
119 .pupd = TEGRA_PUPD_##_pupd, \
120 .tristate = TEGRA_TRI_##_tri, \
121 .io = TEGRA_PIN_##_io, \
122 .lock = TEGRA_PIN_LOCK_##_lock, \
123 .od = TEGRA_PIN_OD_##_od, \
124 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
125 }
126
127#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
128 { \
129 .pingroup = TEGRA_PINGROUP_##_pingroup, \
130 .func = TEGRA_MUX_##_mux, \
131 .pupd = TEGRA_PUPD_##_pupd, \
132 .tristate = TEGRA_TRI_##_tri, \
133 .io = TEGRA_PIN_##_io, \
134 .lock = TEGRA_PIN_LOCK_##_lock, \
135 .od = TEGRA_PIN_OD_DEFAULT, \
136 .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \
137 }
138
139static __initdata struct tegra_pingroup_config cardhu_pinmux_common[] = {
140 /* SDMMC1 pinmux */
141 DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
142 DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT),
143 DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT),
144 DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT),
145 DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT),
146 DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT),
147
148 /* SDMMC3 pinmux */
149 DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
150 DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT),
151 DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT),
152 DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT),
153 DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT),
154 DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT),
155 DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, PULL_UP, NORMAL, INPUT),
156 DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, PULL_UP, NORMAL, INPUT),
157
158 /* SDMMC4 pinmux */
159 DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
160 DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT),
161 DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT),
162 DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT),
163 DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT),
164 DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT),
165 DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT),
166 DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT),
167 DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT),
168 DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT),
169 DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT),
170
171 /* I2C1 pinmux */
172 I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
173 I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
174
175 /* I2C2 pinmux */
176 I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
177 I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
178
179 /* I2C3 pinmux */
180 I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
181 I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
182
183 /* I2C4 pinmux */
184 I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
185 I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
186
187 /* Power I2C pinmux */
188 I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
189 I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
190
191 //ULPI I/F
192 //just ULPI_CLK/_DIR used on Carma
193 DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, TRISTATE, OUTPUT),
194 DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, TRISTATE, OUTPUT),
195 DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, TRISTATE, OUTPUT),
196 DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, TRISTATE, OUTPUT),
197 DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, TRISTATE, OUTPUT),
198 DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, TRISTATE, OUTPUT),
199 DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, TRISTATE, OUTPUT),
200 DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, TRISTATE, OUTPUT),
201 DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
202 DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
203 DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, TRISTATE, OUTPUT),
204 DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, TRISTATE, OUTPUT),
205 //DAP3 I/F
206 // not used on Carma
207 DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, TRISTATE, OUTPUT),
208 DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, TRISTATE, OUTPUT),
209 DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, TRISTATE, OUTPUT),
210 DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, TRISTATE, OUTPUT),
211
212 //DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
213 //DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
214 DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
215 DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
216 DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, INPUT),
217 DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT),
218 DEFAULT_PINMUX(LCD_SDIN, DISPLAYA, NORMAL, NORMAL, INPUT),
219 DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, NORMAL, NORMAL, INPUT),
220 DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT),
221 DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT),
222 DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, INPUT),
223 DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT),
224 DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT),
225 DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
226 DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
227 DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT),
228 DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT),
229 DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT),
230 DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT),
231 DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT),
232 DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT),
233 DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT),
234 DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT),
235 DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT),
236 DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT),
237 DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT),
238 DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT),
239 DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT),
240 DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT),
241 DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT),
242 DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT),
243 DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT),
244 DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT),
245 DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT),
246 DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT),
247 DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT),
248 DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT),
249 DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT),
250 DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT),
251 DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT),
252 DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
253 DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
254 //VI I/F (up to 10 bits)
255 DEFAULT_PINMUX(VI_D0, VI, PULL_DOWN, NORMAL, INPUT),
256 DEFAULT_PINMUX(VI_D1, VI, PULL_DOWN, NORMAL, INPUT),
257 DEFAULT_PINMUX(VI_D2, VI, PULL_DOWN, NORMAL, INPUT),
258 DEFAULT_PINMUX(VI_D3, VI, PULL_DOWN, NORMAL, INPUT),
259 DEFAULT_PINMUX(VI_D4, VI, PULL_DOWN, NORMAL, INPUT),
260 DEFAULT_PINMUX(VI_D5, VI, PULL_DOWN, NORMAL, INPUT),
261 DEFAULT_PINMUX(VI_D6, VI, PULL_DOWN, NORMAL, INPUT),
262 DEFAULT_PINMUX(VI_D7, VI, PULL_DOWN, NORMAL, INPUT),
263 DEFAULT_PINMUX(VI_D8, VI, PULL_DOWN, NORMAL, INPUT),
264 DEFAULT_PINMUX(VI_D9, VI, PULL_DOWN, NORMAL, INPUT),
265 DEFAULT_PINMUX(VI_D10, VI, NORMAL, TRISTATE, OUTPUT),
266 DEFAULT_PINMUX(VI_D11, VI, NORMAL, TRISTATE, OUTPUT),
267 DEFAULT_PINMUX(VI_MCLK, VI, PULL_DOWN, NORMAL, INPUT),
268 DEFAULT_PINMUX(VI_PCLK, VI, PULL_UP, NORMAL, INPUT),
269 DEFAULT_PINMUX(VI_HSYNC, VI, PULL_UP, NORMAL, INPUT),
270 DEFAULT_PINMUX(VI_VSYNC, VI, PULL_UP, NORMAL, INPUT),
271
272 //UART2
273 DEFAULT_PINMUX(UART2_RXD, UARTA, NORMAL, NORMAL, INPUT),
274 DEFAULT_PINMUX(UART2_TXD, UARTA, NORMAL, NORMAL, OUTPUT),
275 DEFAULT_PINMUX(UART2_RTS_N, UARTA, NORMAL, NORMAL, OUTPUT),
276 DEFAULT_PINMUX(UART2_CTS_N, UARTA, NORMAL, NORMAL, INPUT),
277 //UART3
278 DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
279 DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
280 DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
281 DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
282
283 DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
284 DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, TRISTATE, OUTPUT),
285 DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, TRISTATE, INPUT),
286 DEFAULT_PINMUX(GPIO_PU3, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
287 //DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
288 DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, TRISTATE, INPUT),
289 //DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
290 DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT),
291 DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT),
292 DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
293 DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
294 DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
295 DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
296 //DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
297 DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
298 DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
299 DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
300
301 //inputs on Carma
302 //DEFAULT_PINMUX(KB_ROW5, OWR, NORMAL, NORMAL, OUTPUT),
303 //DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, OUTPUT),
304 //DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, NORMAL, OUTPUT),
305 //DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, NORMAL, OUTPUT),
306 DEFAULT_PINMUX(KB_ROW5, OWR, NORMAL, NORMAL, INPUT),
307 DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT),
308 DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, NORMAL, INPUT),
309 DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, NORMAL, INPUT),
310
311 //////////////////
312 // FIXME:
313 //
314 // set up GMI bus
315
316#if 0 /* for testing on Verbier */
317 DEFAULT_PINMUX(GMI_WAIT, NAND, NORMAL, NORMAL, INPUT),
318 DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, OUTPUT),
319 DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, OUTPUT),
320 DEFAULT_PINMUX(GMI_CS0_N, NAND, NORMAL, NORMAL, OUTPUT),
321 DEFAULT_PINMUX(GMI_CS1_N, NAND, NORMAL, NORMAL, OUTPUT),
322 DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
323 DEFAULT_PINMUX(GMI_CS4_N, NAND, NORMAL, NORMAL, OUTPUT),
324 DEFAULT_PINMUX(GMI_CS6_N, NAND_ALT, NORMAL, NORMAL, OUTPUT),
325 DEFAULT_PINMUX(GMI_CS7_N, NAND_ALT, NORMAL, NORMAL, OUTPUT),
326 DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, NORMAL, INPUT),
327 DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, NORMAL, INPUT),
328 DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, NORMAL, INPUT),
329 DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, NORMAL, INPUT),
330 DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, NORMAL, INPUT),
331 DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, NORMAL, INPUT),
332 DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, NORMAL, INPUT),
333 DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, NORMAL, INPUT),
334 DEFAULT_PINMUX(GMI_AD8, NAND, NORMAL, NORMAL, OUTPUT),
335 DEFAULT_PINMUX(GMI_AD9, NAND, NORMAL, NORMAL, INPUT),
336 DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
337 DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, INPUT),
338 DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT),
339 DEFAULT_PINMUX(GMI_AD13, NAND, NORMAL, NORMAL, INPUT),
340 DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT),
341 DEFAULT_PINMUX(GMI_AD15, NAND, NORMAL, NORMAL, INPUT),
342 DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, NORMAL, OUTPUT),
343 DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, NORMAL, OUTPUT),
344 DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, NORMAL, INPUT),
345#else
346 //LCD1_BL_PWM on GPIO_PU3
347 //DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
348#endif
349
350 //
351
352 //DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
353 //DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
354 //DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
355 //DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
356 DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, PULL_UP, NORMAL, INPUT),
357 //DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
358 //DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
359 DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, OUTPUT),
360 DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, TRISTATE, OUTPUT),
361 //DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
362 DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, TRISTATE, OUTPUT),
363 DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, TRISTATE, OUTPUT),
364 DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
365 DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
366 DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
367 DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
368 DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
369
370 /* KBC keys */
371 DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT),
372 DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT),
373 DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT),
374 DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT),
375 DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT),
376 DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT),
377 DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT),
378 DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT),
379 DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT),
380 DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT),
381 DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT),
382
383 DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
384 DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
385 DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
386 DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
387 DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
388 DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
389 DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
390 DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
391 DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
392#ifdef CONFIG_SND_HDA_CODEC_REALTEK
393 DEFAULT_PINMUX(SPDIF_IN, DAPSDMMC2, PULL_DOWN, NORMAL, INPUT),
394#else
395 DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
396#endif
397 DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
398#ifdef CONFIG_SND_HDA_CODEC_REALTEK
399 DEFAULT_PINMUX(DAP2_FS, HDA, PULL_DOWN, NORMAL, INPUT),
400 DEFAULT_PINMUX(DAP2_DIN, HDA, PULL_DOWN, NORMAL, INPUT),
401 DEFAULT_PINMUX(DAP2_DOUT, HDA, PULL_DOWN, NORMAL, INPUT),
402 DEFAULT_PINMUX(DAP2_SCLK, HDA, PULL_DOWN, NORMAL, INPUT),
403#else
404 DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
405 DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
406 DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
407 DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
408#endif
409 DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT),
410 DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
411 DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
412 DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
413 DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
414 DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
415 DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
416 DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
417 DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
418 DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
419 DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
420 DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
421 DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
422 DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
423 DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
424 DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
425 DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT),
426
427 /* Gpios */
428 /* SDMMC1 CD gpio */
429 DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
430 //DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT),
431 /* SDMMC1 WP gpio */
432 //DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT),
433 DEFAULT_PINMUX(GPIO_PV2, RSVD1, PULL_UP, NORMAL, INPUT),
434
435 /* Touch panel GPIO */
436 /* Touch IRQ */
437 //DEFAULT_PINMUX(GMI_AD12, NAND, PULL_UP, NORMAL, INPUT),
438
439 /* Touch RESET */
440 //DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
441
442 /* Power rails GPIO */
443 //DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
444 //DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
445 DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT),
446 DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_UP, NORMAL, INPUT),
447 DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, PULL_UP, NORMAL, INPUT),
448
449 //VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
450 //VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
451 //VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
452 //VI_PINMUX(VI_PCLK, RSVD1, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE),
453 //VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
454 //VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
455};
456
457static __initdata struct tegra_pingroup_config cardhu_pinmux_e118x[] = {
458 /* Power rails GPIO */
459 DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT),
460 DEFAULT_PINMUX(GMI_RST_N, RSVD3, PULL_UP, TRISTATE, INPUT),
461 DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT),
462};
463
464static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu[] = {
465 DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT),
466 DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT),
467 DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT),
468 DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, INPUT),
469
470 DEFAULT_PINMUX(GMI_CS2_N, RSVD1, PULL_UP, NORMAL, INPUT),
471 DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
472 DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
473
474 /* Power rails GPIO */
475 DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT),
476 DEFAULT_PINMUX(GMI_RST_N, RSVD3, PULL_UP, TRISTATE, INPUT),
477 DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT),
478
479 DEFAULT_PINMUX(GMI_CS0_N, GMI, PULL_UP, NORMAL, INPUT),
480 DEFAULT_PINMUX(GMI_CS1_N, GMI, PULL_UP, TRISTATE, INPUT),
481 /*TP_IRQ*/
482 DEFAULT_PINMUX(GMI_CS4_N, GMI, PULL_UP, NORMAL, INPUT),
483 /*PCIE dock detect*/
484 DEFAULT_PINMUX(GPIO_PU4, PWM1, PULL_UP, NORMAL, INPUT),
485};
486
487static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu_a03[] = {
488 DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT),
489 DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT),
490 DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT),
491 DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, INPUT),
492
493 DEFAULT_PINMUX(GMI_CS2_N, RSVD1, PULL_UP, NORMAL, INPUT),
494 //DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
495 //DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
496
497 /* Power rails GPIO */
498 //DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
499 //DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
500 //DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD3, PULL_UP, TRISTATE, INPUT),
501 //DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD3, PULL_UP, TRISTATE, INPUT),
502};
503
504static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = {
505 //DEFAULT_PINMUX(GMI_AD15, NAND, PULL_DOWN, NORMAL, OUTPUT),
506};
507
508static __initdata struct tegra_pingroup_config cardhu_pinmux_e1198[] = {
509 DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT),
510 DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT),
511 DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT),
512 DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, INPUT),
513
514 DEFAULT_PINMUX(GMI_CS2_N, RSVD1, PULL_UP, NORMAL, INPUT),
515 DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
516 DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
517
518 /* SPI2 */
519 DEFAULT_PINMUX(SPI2_SCK, SPI2, PULL_UP, NORMAL, INPUT),
520 DEFAULT_PINMUX(SPI2_MOSI, SPI2, PULL_UP, NORMAL, INPUT),
521 DEFAULT_PINMUX(SPI2_MISO, SPI2, PULL_UP, NORMAL, INPUT),
522 DEFAULT_PINMUX(SPI2_CS0_N, SPI2, PULL_UP, NORMAL, INPUT),
523 DEFAULT_PINMUX(SPI2_CS2_N, SPI2, PULL_UP, NORMAL, INPUT),
524};
525
526static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
527 DEFAULT_PINMUX(GMI_WAIT, NAND, PULL_UP, TRISTATE, OUTPUT),
528 DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
529 DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
530 DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
531 DEFAULT_PINMUX(GMI_CS6_N, SATA, NORMAL, NORMAL, OUTPUT),
532 DEFAULT_PINMUX(GMI_CS7_N, NAND, PULL_UP, NORMAL, INPUT),
533 DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
534 DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
535 DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
536 DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
537 DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
538 DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
539 DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
540 DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
541 DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
542 DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
543 DEFAULT_PINMUX(GMI_AD13, NAND, PULL_UP, NORMAL, INPUT),
544 DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
545 DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
546 DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
547};
548
549static __initdata struct tegra_pingroup_config gmi_pins_269[] = {
550 /* Continuation of table unused_pins_lowpower only for PM269 */
551 DEFAULT_PINMUX(GMI_CS0_N, NAND, PULL_UP, NORMAL, OUTPUT),
552 DEFAULT_PINMUX(GMI_CS1_N, NAND, PULL_UP, TRISTATE, OUTPUT),
553 DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
554 DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, TRISTATE, OUTPUT),
555 DEFAULT_PINMUX(GMI_CS4_N, NAND, PULL_UP, NORMAL, INPUT),
556 DEFAULT_PINMUX(GMI_CS6_N, SATA, NORMAL, TRISTATE, OUTPUT),
557 DEFAULT_PINMUX(GMI_CS7_N, NAND, PULL_UP, NORMAL, INPUT),
558 DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
559 DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
560 DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
561 DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
562 DEFAULT_PINMUX(GMI_AD13, NAND, PULL_UP, TRISTATE, OUTPUT),
563 DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT),
564 DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
565 DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
566 DEFAULT_PINMUX(GMI_A18, SPI4, PULL_UP, NORMAL, INPUT),
567 DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
568 DEFAULT_PINMUX(GMI_RST_N, NAND, PULL_UP, NORMAL, INPUT),
569 DEFAULT_PINMUX(GMI_WP_N, NAND, NORMAL, NORMAL, INPUT),
570};
571
572
573#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \
574 { \
575 .gpio_nr = _gpio, \
576 .is_input = _is_input, \
577 .value = _value, \
578 }
579
580
581/* E1198-A01/E1291 specific fab < A03 */
582static struct gpio_init_pin_info init_gpio_mode_e1291_a02[] = {
583 GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH7, false, 0),
584 GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, false, 0),
585};
586
587/* E1198-A02/E1291 specific fab >= A03 */
588static struct gpio_init_pin_info init_gpio_mode_e1291_a03[] = {
589 //GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD6, false, 0),
590 //GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD4, false, 0),
591};
592
593static void __init cardhu_gpio_init_configure(void)
594{
595 struct board_info board_info;
596 int len;
597 int i;
598 struct gpio_init_pin_info *pins_info;
599
600 tegra_get_board_info(&board_info);
601
602 switch (board_info.board_id) {
603 case BOARD_E1198:
604 if (board_info.fab < BOARD_FAB_A02) {
605 len = ARRAY_SIZE(init_gpio_mode_e1291_a02);
606 pins_info = init_gpio_mode_e1291_a02;
607 } else {
608 len = ARRAY_SIZE(init_gpio_mode_e1291_a03);
609 pins_info = init_gpio_mode_e1291_a03;
610 }
611 break;
612 case BOARD_E1291:
613 if (board_info.fab < BOARD_FAB_A03) {
614 len = ARRAY_SIZE(init_gpio_mode_e1291_a02);
615 pins_info = init_gpio_mode_e1291_a02;
616 } else {
617 len = ARRAY_SIZE(init_gpio_mode_e1291_a03);
618 pins_info = init_gpio_mode_e1291_a03;
619 }
620 break;
621 default:
622 return;
623 }
624
625 for (i = 0; i < len; ++i) {
626 tegra_gpio_init_configure(pins_info->gpio_nr,
627 pins_info->is_input, pins_info->value);
628 pins_info++;
629 }
630}
631
632int __init cardhu_pinmux_init(void)
633{
634 struct board_info board_info;
635
636 cardhu_gpio_init_configure();
637
638 tegra_pinmux_config_table(cardhu_pinmux_common, ARRAY_SIZE(cardhu_pinmux_common));
639 tegra_drive_pinmux_config_table(cardhu_drive_pinmux,
640 ARRAY_SIZE(cardhu_drive_pinmux));
641
642 tegra_get_board_info(&board_info);
643 switch (board_info.board_id) {
644 case BOARD_E1198:
645 tegra_pinmux_config_table(cardhu_pinmux_e1198,
646 ARRAY_SIZE(cardhu_pinmux_e1198));
647 tegra_pinmux_config_table(unused_pins_lowpower,
648 ARRAY_SIZE(unused_pins_lowpower));
649 if (board_info.fab >= BOARD_FAB_A02)
650 tegra_pinmux_config_table(cardhu_pinmux_cardhu_a03,
651 ARRAY_SIZE(cardhu_pinmux_cardhu_a03));
652 break;
653 case BOARD_E1291:
654 if (board_info.fab < BOARD_FAB_A03) {
655 tegra_pinmux_config_table(cardhu_pinmux_cardhu,
656 ARRAY_SIZE(cardhu_pinmux_cardhu));
657 tegra_pinmux_config_table(unused_pins_lowpower,
658 ARRAY_SIZE(unused_pins_lowpower));
659 } else {
660 tegra_pinmux_config_table(cardhu_pinmux_cardhu_a03,
661 ARRAY_SIZE(cardhu_pinmux_cardhu_a03));
662 }
663 if (board_info.fab >= BOARD_FAB_A04)
664 tegra_pinmux_config_table(cardhu_pinmux_e1291_a04,
665 ARRAY_SIZE(cardhu_pinmux_e1291_a04));
666 break;
667
668 case BOARD_PM269:
669 case BOARD_PM305:
670 case BOARD_PM311:
671 case BOARD_E1257:
672 tegra_pinmux_config_table(cardhu_pinmux_e118x,
673 ARRAY_SIZE(cardhu_pinmux_e118x));
674 tegra_pinmux_config_table(unused_pins_lowpower,
675 ARRAY_SIZE(unused_pins_lowpower));
676 tegra_pinmux_config_table(gmi_pins_269,
677 ARRAY_SIZE(gmi_pins_269));
678 break;
679 default:
680 tegra_pinmux_config_table(cardhu_pinmux_e118x,
681 ARRAY_SIZE(cardhu_pinmux_e118x));
682 break;
683 }
684 return 0;
685}
686
687#define PIN_GPIO_LPM(_name, _gpio, _is_input, _value) \
688 { \
689 .name = _name, \
690 .gpio_nr = _gpio, \
691 .is_gpio = true, \
692 .is_input = _is_input, \
693 .value = _value, \
694 }
695
696struct gpio_init_pin_info pin_lpm_cardhu_common[] = {
697 PIN_GPIO_LPM("GMI_CS3_N", TEGRA_GPIO_PK4, 0, 0),
698 PIN_GPIO_LPM("GMI_CS4_N", TEGRA_GPIO_PK2, 1, 0),
699 PIN_GPIO_LPM("GMI_AD9", TEGRA_GPIO_PH1, 0, 0),
700 PIN_GPIO_LPM("GMI_AD11", TEGRA_GPIO_PH3, 0, 0),
701 PIN_GPIO_LPM("GMI_CS7", TEGRA_GPIO_PI6, 1, 0),
702 PIN_GPIO_LPM("GMI_CS0", TEGRA_GPIO_PJ0, 1, 0),
703 PIN_GPIO_LPM("GMI_CS1", TEGRA_GPIO_PJ2, 1, 0),
704 PIN_GPIO_LPM("GMI_WP_N", TEGRA_GPIO_PC7, 1, 0),
705};
706
707struct gpio_init_pin_info vddio_gmi_pins_pm269[] = {
708 PIN_GPIO_LPM("GMI_CS2", TEGRA_GPIO_PK3, 1, 0),
709 PIN_GPIO_LPM("GMI_CS3_N", TEGRA_GPIO_PK4, 0, 0),
710 PIN_GPIO_LPM("GMI_CS4_N", TEGRA_GPIO_PK2, 1, 0),
711 PIN_GPIO_LPM("GMI_AD9", TEGRA_GPIO_PH1, 0, 0),
712 PIN_GPIO_LPM("GMI_CS7", TEGRA_GPIO_PI6, 1, 0),
713 PIN_GPIO_LPM("GMI_CS0", TEGRA_GPIO_PJ0, 1, 0),
714 PIN_GPIO_LPM("GMI_CS1", TEGRA_GPIO_PJ2, 1, 0),
715 PIN_GPIO_LPM("GMI_WP_N", TEGRA_GPIO_PC7, 1, 0),
716 PIN_GPIO_LPM("GMI_A16", TEGRA_GPIO_PJ7, 0, 0),
717 PIN_GPIO_LPM("GMI_A17", TEGRA_GPIO_PB0, 0, 0),
718 PIN_GPIO_LPM("GMI_A18", TEGRA_GPIO_PB1, 1, 0),
719 PIN_GPIO_LPM("GMI_A19", TEGRA_GPIO_PK7, 0, 0),
720};
721
722struct gpio_init_pin_info vddio_gmi_pins_pm269_pm313[] = {
723 PIN_GPIO_LPM("GMI_CS3_N", TEGRA_GPIO_PK4, 0, 0),
724 PIN_GPIO_LPM("GMI_CS4_N", TEGRA_GPIO_PK2, 1, 0),
725 PIN_GPIO_LPM("GMI_CS7", TEGRA_GPIO_PI6, 1, 0),
726 PIN_GPIO_LPM("GMI_CS0", TEGRA_GPIO_PJ0, 1, 0),
727 PIN_GPIO_LPM("GMI_CS1", TEGRA_GPIO_PJ2, 1, 0),
728 PIN_GPIO_LPM("GMI_WP_N", TEGRA_GPIO_PC7, 1, 0),
729 PIN_GPIO_LPM("GMI_A16", TEGRA_GPIO_PJ7, 0, 0),
730 PIN_GPIO_LPM("GMI_A17", TEGRA_GPIO_PB0, 0, 0),
731 PIN_GPIO_LPM("GMI_A18", TEGRA_GPIO_PB1, 1, 0),
732 PIN_GPIO_LPM("GMI_A19", TEGRA_GPIO_PK7, 0, 0),
733};
734
735static void set_unused_pin_gpio(struct gpio_init_pin_info *lpm_pin_info,
736 int list_count)
737{
738 int i;
739 struct gpio_init_pin_info *pin_info;
740 int ret;
741
742 for (i = 0; i < list_count; ++i) {
743 pin_info = (struct gpio_init_pin_info *)(lpm_pin_info + i);
744 if (!pin_info->is_gpio)
745 continue;
746
747 ret = gpio_request(pin_info->gpio_nr, pin_info->name);
748 if (ret < 0) {
749 pr_err("%s() Error in gpio_request() for gpio %d\n",
750 __func__, pin_info->gpio_nr);
751 continue;
752 }
753 if (pin_info->is_input)
754 ret = gpio_direction_input(pin_info->gpio_nr);
755 else
756 ret = gpio_direction_output(pin_info->gpio_nr,
757 pin_info->value);
758 if (ret < 0) {
759 pr_err("%s() Error in setting gpio %d to in/out\n",
760 __func__, pin_info->gpio_nr);
761 gpio_free(pin_info->gpio_nr);
762 continue;
763 }
764 tegra_gpio_enable(pin_info->gpio_nr);
765 }
766}
767
768/* Initialize the pins to desired state as per power/asic/system-eng
769 * recomendation */
770int __init cardhu_pins_state_init(void)
771{
772 struct board_info board_info;
773 struct board_info display_board_info;
774
775 tegra_get_board_info(&board_info);
776 tegra_get_display_board_info(&display_board_info);
777 if ((board_info.board_id == BOARD_E1291) ||
778 (board_info.board_id == BOARD_E1198))
779 set_unused_pin_gpio(&pin_lpm_cardhu_common[0],
780 ARRAY_SIZE(pin_lpm_cardhu_common));
781
782 if ((board_info.board_id == BOARD_PM269) ||
783 (board_info.board_id == BOARD_E1257) ||
784 (board_info.board_id == BOARD_PM305) ||
785 (board_info.board_id == BOARD_PM311)) {
786 if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
787 set_unused_pin_gpio(&vddio_gmi_pins_pm269_pm313[0],
788 ARRAY_SIZE(vddio_gmi_pins_pm269_pm313));
789 } else {
790 set_unused_pin_gpio(&vddio_gmi_pins_pm269[0],
791 ARRAY_SIZE(vddio_gmi_pins_pm269));
792 }
793 }
794
795 return 0;
796}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 08:55:26 -0400