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Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-memory.c')
-rw-r--r--arch/arm/mach-tegra/board-cardhu-memory.c5518
1 files changed, 5518 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
new file mode 100644
index 00000000000..21c98216ce7
--- /dev/null
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -0,0 +1,5518 @@
1/*
2 * Copyright (C) 2011 NVIDIA, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16 * 02111-1307, USA
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21
22#include "board.h"
23#include "board-cardhu.h"
24#include "tegra3_emc.h"
25#include "fuse.h"
26
27
28static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
29 {
30 0x30, /* Rev 3.0 */
31 27000, /* SDRAM frquency */
32 {
33 0x00000001, /* EMC_RC */
34 0x00000004, /* EMC_RFC */
35 0x00000000, /* EMC_RAS */
36 0x00000000, /* EMC_RP */
37 0x00000002, /* EMC_R2W */
38 0x0000000a, /* EMC_W2R */
39 0x00000003, /* EMC_R2P */
40 0x0000000b, /* EMC_W2P */
41 0x00000000, /* EMC_RD_RCD */
42 0x00000000, /* EMC_WR_RCD */
43 0x00000003, /* EMC_RRD */
44 0x00000001, /* EMC_REXT */
45 0x00000000, /* EMC_WEXT */
46 0x00000005, /* EMC_WDV */
47 0x00000005, /* EMC_QUSE */
48 0x00000004, /* EMC_QRST */
49 0x00000007, /* EMC_QSAFE */
50 0x0000000d, /* EMC_RDV */
51 0x000000cb, /* EMC_REFRESH */
52 0x00000000, /* EMC_BURST_REFRESH_NUM */
53 0x00000032, /* EMC_PRE_REFRESH_REQ_CNT */
54 0x00000002, /* EMC_PDEX2WR */
55 0x00000002, /* EMC_PDEX2RD */
56 0x00000001, /* EMC_PCHG2PDEN */
57 0x00000000, /* EMC_ACT2PDEN */
58 0x00000007, /* EMC_AR2PDEN */
59 0x0000000f, /* EMC_RW2PDEN */
60 0x00000005, /* EMC_TXSR */
61 0x00000005, /* EMC_TXSRDLL */
62 0x00000004, /* EMC_TCKE */
63 0x00000001, /* EMC_TFAW */
64 0x00000000, /* EMC_TRPAB */
65 0x00000004, /* EMC_TCLKSTABLE */
66 0x00000005, /* EMC_TCLKSTOP */
67 0x000000d3, /* EMC_TREFBW */
68 0x00000000, /* EMC_QUSE_EXTRA */
69 0x00000004, /* EMC_FBIO_CFG6 */
70 0x00000000, /* EMC_ODT_WRITE */
71 0x00000000, /* EMC_ODT_READ */
72 0x00006288, /* EMC_FBIO_CFG5 */
73 0xd0780421, /* EMC_CFG_DIG_DLL */
74 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
75 0x00080000, /* EMC_DLL_XFORM_DQS0 */
76 0x00080000, /* EMC_DLL_XFORM_DQS1 */
77 0x00080000, /* EMC_DLL_XFORM_DQS2 */
78 0x00080000, /* EMC_DLL_XFORM_DQS3 */
79 0x00080000, /* EMC_DLL_XFORM_DQS4 */
80 0x00080000, /* EMC_DLL_XFORM_DQS5 */
81 0x00080000, /* EMC_DLL_XFORM_DQS6 */
82 0x00080000, /* EMC_DLL_XFORM_DQS7 */
83 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
84 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
85 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
86 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
87 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
88 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
89 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
90 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
91 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
92 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
93 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
94 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
95 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
96 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
97 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
98 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
99 0x00080000, /* EMC_DLL_XFORM_DQ0 */
100 0x00080000, /* EMC_DLL_XFORM_DQ1 */
101 0x00080000, /* EMC_DLL_XFORM_DQ2 */
102 0x00080000, /* EMC_DLL_XFORM_DQ3 */
103 0x000003e0, /* EMC_XM2CMDPADCTRL */
104 0x0800211d, /* EMC_XM2DQSPADCTRL2 */
105 0x00000000, /* EMC_XM2DQPADCTRL2 */
106 0x77ffc084, /* EMC_XM2CLKPADCTRL */
107 0x01f1f108, /* EMC_XM2COMPPADCTRL */
108 0x07075504, /* EMC_XM2VTTGENPADCTRL */
109 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
110 0x0800012d, /* EMC_XM2QUSEPADCTRL */
111 0x08000000, /* EMC_XM2DQSPADCTRL3 */
112 0x00000802, /* EMC_CTT_TERM_CTRL */
113 0x00000000, /* EMC_ZCAL_INTERVAL */
114 0x00000040, /* EMC_ZCAL_WAIT_CNT */
115 0x000c000c, /* EMC_MRS_WAIT_CNT */
116 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
117 0x00000000, /* EMC_CTT */
118 0x00000000, /* EMC_CTT_DURATION */
119 0x8000029e, /* EMC_DYN_SELF_REF_CONTROL */
120 0x00000001, /* MC_EMEM_ARB_CFG */
121 0x8000000d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
122 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
123 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
124 0x00000005, /* MC_EMEM_ARB_TIMING_RC */
125 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
126 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
127 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
128 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
129 0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */
130 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */
131 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */
132 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
133 0x0000000f, /* MC_EMEM_ARB_TIMING_W2R */
134 0x0f070506, /* MC_EMEM_ARB_DA_TURNS */
135 0x00140905, /* MC_EMEM_ARB_DA_COVERS */
136 0x78430306, /* MC_EMEM_ARB_MISC0 */
137 0x001f0001, /* MC_EMEM_ARB_RING1_THROTTLE */
138 },
139 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
140 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
141 0x00000000, /* EMC_CFG.PERIODIC_QRST */
142 0x00001221, /* Mode Register 0 */
143 0x00100003, /* Mode Register 1 */
144 0x00200008, /* Mode Register 2 */
145 },
146 {
147 0x30, /* Rev 3.0 */
148 54000, /* SDRAM frquency */
149 {
150 0x00000002, /* EMC_RC */
151 0x00000008, /* EMC_RFC */
152 0x00000001, /* EMC_RAS */
153 0x00000000, /* EMC_RP */
154 0x00000002, /* EMC_R2W */
155 0x0000000a, /* EMC_W2R */
156 0x00000003, /* EMC_R2P */
157 0x0000000b, /* EMC_W2P */
158 0x00000000, /* EMC_RD_RCD */
159 0x00000000, /* EMC_WR_RCD */
160 0x00000003, /* EMC_RRD */
161 0x00000001, /* EMC_REXT */
162 0x00000000, /* EMC_WEXT */
163 0x00000005, /* EMC_WDV */
164 0x00000005, /* EMC_QUSE */
165 0x00000004, /* EMC_QRST */
166 0x00000007, /* EMC_QSAFE */
167 0x0000000d, /* EMC_RDV */
168 0x00000198, /* EMC_REFRESH */
169 0x00000000, /* EMC_BURST_REFRESH_NUM */
170 0x00000066, /* EMC_PRE_REFRESH_REQ_CNT */
171 0x00000002, /* EMC_PDEX2WR */
172 0x00000002, /* EMC_PDEX2RD */
173 0x00000001, /* EMC_PCHG2PDEN */
174 0x00000000, /* EMC_ACT2PDEN */
175 0x00000007, /* EMC_AR2PDEN */
176 0x0000000f, /* EMC_RW2PDEN */
177 0x0000000a, /* EMC_TXSR */
178 0x0000000a, /* EMC_TXSRDLL */
179 0x00000004, /* EMC_TCKE */
180 0x00000002, /* EMC_TFAW */
181 0x00000000, /* EMC_TRPAB */
182 0x00000004, /* EMC_TCLKSTABLE */
183 0x00000005, /* EMC_TCLKSTOP */
184 0x000001a6, /* EMC_TREFBW */
185 0x00000000, /* EMC_QUSE_EXTRA */
186 0x00000004, /* EMC_FBIO_CFG6 */
187 0x00000000, /* EMC_ODT_WRITE */
188 0x00000000, /* EMC_ODT_READ */
189 0x00006288, /* EMC_FBIO_CFG5 */
190 0xd0780421, /* EMC_CFG_DIG_DLL */
191 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
192 0x00080000, /* EMC_DLL_XFORM_DQS0 */
193 0x00080000, /* EMC_DLL_XFORM_DQS1 */
194 0x00080000, /* EMC_DLL_XFORM_DQS2 */
195 0x00080000, /* EMC_DLL_XFORM_DQS3 */
196 0x00080000, /* EMC_DLL_XFORM_DQS4 */
197 0x00080000, /* EMC_DLL_XFORM_DQS5 */
198 0x00080000, /* EMC_DLL_XFORM_DQS6 */
199 0x00080000, /* EMC_DLL_XFORM_DQS7 */
200 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
201 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
202 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
203 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
204 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
205 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
206 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
207 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
208 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
209 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
210 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
211 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
212 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
213 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
214 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
215 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
216 0x00080000, /* EMC_DLL_XFORM_DQ0 */
217 0x00080000, /* EMC_DLL_XFORM_DQ1 */
218 0x00080000, /* EMC_DLL_XFORM_DQ2 */
219 0x00080000, /* EMC_DLL_XFORM_DQ3 */
220 0x000003e0, /* EMC_XM2CMDPADCTRL */
221 0x0800211d, /* EMC_XM2DQSPADCTRL2 */
222 0x00000000, /* EMC_XM2DQPADCTRL2 */
223 0x77ffc084, /* EMC_XM2CLKPADCTRL */
224 0x01f1f108, /* EMC_XM2COMPPADCTRL */
225 0x07075504, /* EMC_XM2VTTGENPADCTRL */
226 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
227 0x0800012d, /* EMC_XM2QUSEPADCTRL */
228 0x08000000, /* EMC_XM2DQSPADCTRL3 */
229 0x00000802, /* EMC_CTT_TERM_CTRL */
230 0x00000000, /* EMC_ZCAL_INTERVAL */
231 0x00000040, /* EMC_ZCAL_WAIT_CNT */
232 0x000c000c, /* EMC_MRS_WAIT_CNT */
233 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
234 0x00000000, /* EMC_CTT */
235 0x00000000, /* EMC_CTT_DURATION */
236 0x80000439, /* EMC_DYN_SELF_REF_CONTROL */
237 0x00000001, /* MC_EMEM_ARB_CFG */
238 0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */
239 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
240 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
241 0x00000005, /* MC_EMEM_ARB_TIMING_RC */
242 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
243 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
244 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
245 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
246 0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */
247 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */
248 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */
249 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
250 0x0000000f, /* MC_EMEM_ARB_TIMING_W2R */
251 0x0f070506, /* MC_EMEM_ARB_DA_TURNS */
252 0x00140905, /* MC_EMEM_ARB_DA_COVERS */
253 0x78430506, /* MC_EMEM_ARB_MISC0 */
254 0x001f0001, /* MC_EMEM_ARB_RING1_THROTTLE */
255 },
256 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
257 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
258 0x00000000, /* EMC_CFG.PERIODIC_QRST */
259 0x00001221, /* Mode Register 0 */
260 0x00100003, /* Mode Register 1 */
261 0x00200008, /* Mode Register 2 */
262 },
263 {
264 0x30, /* Rev 3.0 */
265 108000, /* SDRAM frquency */
266 {
267 0x00000005, /* EMC_RC */
268 0x00000011, /* EMC_RFC */
269 0x00000003, /* EMC_RAS */
270 0x00000001, /* EMC_RP */
271 0x00000002, /* EMC_R2W */
272 0x0000000a, /* EMC_W2R */
273 0x00000003, /* EMC_R2P */
274 0x0000000b, /* EMC_W2P */
275 0x00000001, /* EMC_RD_RCD */
276 0x00000001, /* EMC_WR_RCD */
277 0x00000003, /* EMC_RRD */
278 0x00000001, /* EMC_REXT */
279 0x00000000, /* EMC_WEXT */
280 0x00000005, /* EMC_WDV */
281 0x00000005, /* EMC_QUSE */
282 0x00000004, /* EMC_QRST */
283 0x00000007, /* EMC_QSAFE */
284 0x0000000d, /* EMC_RDV */
285 0x00000330, /* EMC_REFRESH */
286 0x00000000, /* EMC_BURST_REFRESH_NUM */
287 0x000000cc, /* EMC_PRE_REFRESH_REQ_CNT */
288 0x00000002, /* EMC_PDEX2WR */
289 0x00000002, /* EMC_PDEX2RD */
290 0x00000001, /* EMC_PCHG2PDEN */
291 0x00000000, /* EMC_ACT2PDEN */
292 0x00000007, /* EMC_AR2PDEN */
293 0x0000000f, /* EMC_RW2PDEN */
294 0x00000013, /* EMC_TXSR */
295 0x00000013, /* EMC_TXSRDLL */
296 0x00000004, /* EMC_TCKE */
297 0x00000004, /* EMC_TFAW */
298 0x00000000, /* EMC_TRPAB */
299 0x00000004, /* EMC_TCLKSTABLE */
300 0x00000005, /* EMC_TCLKSTOP */
301 0x0000034b, /* EMC_TREFBW */
302 0x00000000, /* EMC_QUSE_EXTRA */
303 0x00000004, /* EMC_FBIO_CFG6 */
304 0x00000000, /* EMC_ODT_WRITE */
305 0x00000000, /* EMC_ODT_READ */
306 0x00006288, /* EMC_FBIO_CFG5 */
307 0xd0780421, /* EMC_CFG_DIG_DLL */
308 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
309 0x00080000, /* EMC_DLL_XFORM_DQS0 */
310 0x00080000, /* EMC_DLL_XFORM_DQS1 */
311 0x00080000, /* EMC_DLL_XFORM_DQS2 */
312 0x00080000, /* EMC_DLL_XFORM_DQS3 */
313 0x00080000, /* EMC_DLL_XFORM_DQS4 */
314 0x00080000, /* EMC_DLL_XFORM_DQS5 */
315 0x00080000, /* EMC_DLL_XFORM_DQS6 */
316 0x00080000, /* EMC_DLL_XFORM_DQS7 */
317 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
318 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
319 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
320 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
321 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
322 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
323 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
324 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
325 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
326 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
327 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
328 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
329 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
330 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
331 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
332 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
333 0x00080000, /* EMC_DLL_XFORM_DQ0 */
334 0x00080000, /* EMC_DLL_XFORM_DQ1 */
335 0x00080000, /* EMC_DLL_XFORM_DQ2 */
336 0x00080000, /* EMC_DLL_XFORM_DQ3 */
337 0x000003e0, /* EMC_XM2CMDPADCTRL */
338 0x0800211d, /* EMC_XM2DQSPADCTRL2 */
339 0x00000000, /* EMC_XM2DQPADCTRL2 */
340 0x77ffc084, /* EMC_XM2CLKPADCTRL */
341 0x01f1f108, /* EMC_XM2COMPPADCTRL */
342 0x07075504, /* EMC_XM2VTTGENPADCTRL */
343 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
344 0x0800012d, /* EMC_XM2QUSEPADCTRL */
345 0x08000000, /* EMC_XM2DQSPADCTRL3 */
346 0x00000802, /* EMC_CTT_TERM_CTRL */
347 0x00000000, /* EMC_ZCAL_INTERVAL */
348 0x00000040, /* EMC_ZCAL_WAIT_CNT */
349 0x000c000c, /* EMC_MRS_WAIT_CNT */
350 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
351 0x00000000, /* EMC_CTT */
352 0x00000000, /* EMC_CTT_DURATION */
353 0x8000076e, /* EMC_DYN_SELF_REF_CONTROL */
354 0x00000003, /* MC_EMEM_ARB_CFG */
355 0x80000027, /* MC_EMEM_ARB_OUTSTANDING_REQ */
356 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
357 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
358 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
359 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
360 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
361 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
362 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
363 0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */
364 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */
365 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */
366 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
367 0x0000000f, /* MC_EMEM_ARB_TIMING_W2R */
368 0x0f070506, /* MC_EMEM_ARB_DA_TURNS */
369 0x00140906, /* MC_EMEM_ARB_DA_COVERS */
370 0x78440a07, /* MC_EMEM_ARB_MISC0 */
371 0x001f0001, /* MC_EMEM_ARB_RING1_THROTTLE */
372 },
373 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
374 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
375 0x00000000, /* EMC_CFG.PERIODIC_QRST */
376 0x00001221, /* Mode Register 0 */
377 0x00100003, /* Mode Register 1 */
378 0x00200008, /* Mode Register 2 */
379 },
380 {
381 0x30, /* Rev 3.0 */
382 416000, /* SDRAM frequency */
383 {
384 0x00000013, /* EMC_RC */
385 0x00000041, /* EMC_RFC */
386 0x0000000d, /* EMC_RAS */
387 0x00000004, /* EMC_RP */
388 0x00000002, /* EMC_R2W */
389 0x00000009, /* EMC_W2R */
390 0x00000002, /* EMC_R2P */
391 0x0000000c, /* EMC_W2P */
392 0x00000004, /* EMC_RD_RCD */
393 0x00000004, /* EMC_WR_RCD */
394 0x00000002, /* EMC_RRD */
395 0x00000001, /* EMC_REXT */
396 0x00000000, /* EMC_WEXT */
397 0x00000005, /* EMC_WDV */
398 0x00000008, /* EMC_QUSE */
399 0x00000006, /* EMC_QRST */
400 0x00000008, /* EMC_QSAFE */
401 0x00000010, /* EMC_RDV */
402 0x00000c6c, /* EMC_REFRESH */
403 0x00000000, /* EMC_BURST_REFRESH_NUM */
404 0x0000031b, /* EMC_PRE_REFRESH_REQ_CNT */
405 0x00000001, /* EMC_PDEX2WR */
406 0x00000001, /* EMC_PDEX2RD */
407 0x00000001, /* EMC_PCHG2PDEN */
408 0x00000000, /* EMC_ACT2PDEN */
409 0x00000008, /* EMC_AR2PDEN */
410 0x00000011, /* EMC_RW2PDEN */
411 0x00000047, /* EMC_TXSR */
412 0x00000200, /* EMC_TXSRDLL */
413 0x00000004, /* EMC_TCKE */
414 0x0000000d, /* EMC_TFAW */
415 0x00000000, /* EMC_TRPAB */
416 0x00000004, /* EMC_TCLKSTABLE */
417 0x00000005, /* EMC_TCLKSTOP */
418 0x00000cad, /* EMC_TREFBW */
419 0x00000000, /* EMC_QUSE_EXTRA */
420 0x00000006, /* EMC_FBIO_CFG6 */
421 0x00000000, /* EMC_ODT_WRITE */
422 0x00000000, /* EMC_ODT_READ */
423 0x00007088, /* EMC_FBIO_CFG5 */
424 0xf0120441, /* EMC_CFG_DIG_DLL */
425 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
426 0x00010000, /* EMC_DLL_XFORM_DQS0 */
427 0x00010000, /* EMC_DLL_XFORM_DQS1 */
428 0x00010000, /* EMC_DLL_XFORM_DQS2 */
429 0x00010000, /* EMC_DLL_XFORM_DQS3 */
430 0x00010000, /* EMC_DLL_XFORM_DQS4 */
431 0x00010000, /* EMC_DLL_XFORM_DQS5 */
432 0x00010000, /* EMC_DLL_XFORM_DQS6 */
433 0x00010000, /* EMC_DLL_XFORM_DQS7 */
434 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
435 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
436 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
437 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
438 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
439 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
440 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
441 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
442 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
443 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
444 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
445 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
446 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
447 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
448 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
449 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
450 0x00020000, /* EMC_DLL_XFORM_DQ0 */
451 0x00020000, /* EMC_DLL_XFORM_DQ1 */
452 0x00020000, /* EMC_DLL_XFORM_DQ2 */
453 0x00020000, /* EMC_DLL_XFORM_DQ3 */
454 0x000006a0, /* EMC_XM2CMDPADCTRL */
455 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
456 0x00000000, /* EMC_XM2DQPADCTRL2 */
457 0x77ffc084, /* EMC_XM2CLKPADCTRL */
458 0x01f1f50f, /* EMC_XM2COMPPADCTRL */
459 0x07077404, /* EMC_XM2VTTGENPADCTRL */
460 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
461 0x0800011d, /* EMC_XM2QUSEPADCTRL */
462 0x08000021, /* EMC_XM2DQSPADCTRL3 */
463 0x00000802, /* EMC_CTT_TERM_CTRL */
464 0x00000000, /* EMC_ZCAL_INTERVAL */
465 0x00000040, /* EMC_ZCAL_WAIT_CNT */
466 0x01be000c, /* EMC_MRS_WAIT_CNT */
467 0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
468 0x00000000, /* EMC_CTT */
469 0x00000000, /* EMC_CTT_DURATION */
470 0x000020ae, /* EMC_DYN_SELF_REF_CONTROL */
471 0x00000006, /* MC_EMEM_ARB_CFG */
472 0x8000004b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
473 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
474 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
475 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
476 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
477 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
478 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
479 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
480 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
481 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
482 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
483 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
484 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
485 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
486 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
487 0x7027130b, /* MC_EMEM_ARB_MISC0 */
488 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
489 },
490 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
491 0x00000010, /* EMC_AUTO_CAL_INTERVAL */
492 0x00000000, /* EMC_CFG.PERIODIC_QRST */
493 0x00001941, /* Mode Register 0 */
494 0x00100002, /* Mode Register 1 */
495 0x00200008, /* Mode Register 2 */
496 },
497 {
498 0x30, /* Rev 3.0 */
499 533000, /* SDRAM frquency */
500 {
501 0x00000018, /* EMC_RC */
502 0x00000054, /* EMC_RFC */
503 0x00000011, /* EMC_RAS */
504 0x00000006, /* EMC_RP */
505 0x00000003, /* EMC_R2W */
506 0x00000009, /* EMC_W2R */
507 0x00000002, /* EMC_R2P */
508 0x0000000d, /* EMC_W2P */
509 0x00000006, /* EMC_RD_RCD */
510 0x00000006, /* EMC_WR_RCD */
511 0x00000002, /* EMC_RRD */
512 0x00000001, /* EMC_REXT */
513 0x00000000, /* EMC_WEXT */
514 0x00000005, /* EMC_WDV */
515 0x00000008, /* EMC_QUSE */
516 0x00000006, /* EMC_QRST */
517 0x00000008, /* EMC_QSAFE */
518 0x00000010, /* EMC_RDV */
519 0x00000ffd, /* EMC_REFRESH */
520 0x00000000, /* EMC_BURST_REFRESH_NUM */
521 0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
522 0x00000002, /* EMC_PDEX2WR */
523 0x00000002, /* EMC_PDEX2RD */
524 0x00000001, /* EMC_PCHG2PDEN */
525 0x00000000, /* EMC_ACT2PDEN */
526 0x0000000a, /* EMC_AR2PDEN */
527 0x00000012, /* EMC_RW2PDEN */
528 0x0000005b, /* EMC_TXSR */
529 0x00000200, /* EMC_TXSRDLL */
530 0x00000004, /* EMC_TCKE */
531 0x00000010, /* EMC_TFAW */
532 0x00000000, /* EMC_TRPAB */
533 0x00000005, /* EMC_TCLKSTABLE */
534 0x00000006, /* EMC_TCLKSTOP */
535 0x0000103e, /* EMC_TREFBW */
536 0x00000000, /* EMC_QUSE_EXTRA */
537 0x00000006, /* EMC_FBIO_CFG6 */
538 0x00000000, /* EMC_ODT_WRITE */
539 0x00000000, /* EMC_ODT_READ */
540 0x00007088, /* EMC_FBIO_CFG5 */
541 0xf0120441, /* EMC_CFG_DIG_DLL */
542 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
543 0x00010000, /* EMC_DLL_XFORM_DQS0 */
544 0x00010000, /* EMC_DLL_XFORM_DQS1 */
545 0x00010000, /* EMC_DLL_XFORM_DQS2 */
546 0x00010000, /* EMC_DLL_XFORM_DQS3 */
547 0x00010000, /* EMC_DLL_XFORM_DQS4 */
548 0x00010000, /* EMC_DLL_XFORM_DQS5 */
549 0x00010000, /* EMC_DLL_XFORM_DQS6 */
550 0x00010000, /* EMC_DLL_XFORM_DQS7 */
551 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
552 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
553 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
554 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
555 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
556 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
557 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
558 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
559 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
560 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
561 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
562 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
563 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
564 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
565 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
566 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
567 0x00020000, /* EMC_DLL_XFORM_DQ0 */
568 0x00020000, /* EMC_DLL_XFORM_DQ1 */
569 0x00020000, /* EMC_DLL_XFORM_DQ2 */
570 0x00020000, /* EMC_DLL_XFORM_DQ3 */
571 0x000006a0, /* EMC_XM2CMDPADCTRL */
572 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
573 0x00000000, /* EMC_XM2DQPADCTRL2 */
574 0x77ffc084, /* EMC_XM2CLKPADCTRL */
575 0x01f1f50f, /* EMC_XM2COMPPADCTRL */
576 0x07077404, /* EMC_XM2VTTGENPADCTRL */
577 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
578 0x0800011d, /* EMC_XM2QUSEPADCTRL */
579 0x08000021, /* EMC_XM2DQSPADCTRL3 */
580 0x00000802, /* EMC_CTT_TERM_CTRL */
581 0x00000000, /* EMC_ZCAL_INTERVAL */
582 0x00000040, /* EMC_ZCAL_WAIT_CNT */
583 0x01ab000c, /* EMC_MRS_WAIT_CNT */
584 0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
585 0x00000000, /* EMC_CTT */
586 0x00000000, /* EMC_CTT_DURATION */
587 0x000020ae, /* EMC_DYN_SELF_REF_CONTROL */
588 0x00000008, /* MC_EMEM_ARB_CFG */
589 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
590 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
591 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
592 0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
593 0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
594 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
595 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
596 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
597 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
598 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
599 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
600 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
601 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
602 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
603 0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
604 0x7028180e, /* MC_EMEM_ARB_MISC0 */
605 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
606 },
607 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
608 0x00000010, /* EMC_AUTO_CAL_INTERVAL */
609 0x00000000, /* EMC_CFG.PERIODIC_QRST */
610 0x00001941, /* Mode Register 0 */
611 0x00100002, /* Mode Register 1 */
612 0x00200008, /* Mode Register 2 */
613 },
614};
615
616static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
617 {
618 0x32, /* Rev 3.2 */
619 25500, /* SDRAM frequency */
620 {
621 0x00000001, /* EMC_RC */
622 0x00000003, /* EMC_RFC */
623 0x00000000, /* EMC_RAS */
624 0x00000000, /* EMC_RP */
625 0x00000002, /* EMC_R2W */
626 0x0000000a, /* EMC_W2R */
627 0x00000003, /* EMC_R2P */
628 0x0000000b, /* EMC_W2P */
629 0x00000000, /* EMC_RD_RCD */
630 0x00000000, /* EMC_WR_RCD */
631 0x00000003, /* EMC_RRD */
632 0x00000001, /* EMC_REXT */
633 0x00000000, /* EMC_WEXT */
634 0x00000005, /* EMC_WDV */
635 0x00000005, /* EMC_QUSE */
636 0x00000004, /* EMC_QRST */
637 0x00000007, /* EMC_QSAFE */
638 0x0000000c, /* EMC_RDV */
639 0x000000bd, /* EMC_REFRESH */
640 0x00000000, /* EMC_BURST_REFRESH_NUM */
641 0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */
642 0x00000002, /* EMC_PDEX2WR */
643 0x00000002, /* EMC_PDEX2RD */
644 0x00000001, /* EMC_PCHG2PDEN */
645 0x00000000, /* EMC_ACT2PDEN */
646 0x00000007, /* EMC_AR2PDEN */
647 0x0000000f, /* EMC_RW2PDEN */
648 0x00000005, /* EMC_TXSR */
649 0x00000005, /* EMC_TXSRDLL */
650 0x00000004, /* EMC_TCKE */
651 0x00000001, /* EMC_TFAW */
652 0x00000000, /* EMC_TRPAB */
653 0x00000004, /* EMC_TCLKSTABLE */
654 0x00000005, /* EMC_TCLKSTOP */
655 0x000000c3, /* EMC_TREFBW */
656 0x00000000, /* EMC_QUSE_EXTRA */
657 0x00000004, /* EMC_FBIO_CFG6 */
658 0x00000000, /* EMC_ODT_WRITE */
659 0x00000000, /* EMC_ODT_READ */
660 0x00006288, /* EMC_FBIO_CFG5 */
661 0x007800a4, /* EMC_CFG_DIG_DLL */
662 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
663 0x00080000, /* EMC_DLL_XFORM_DQS0 */
664 0x00080000, /* EMC_DLL_XFORM_DQS1 */
665 0x00080000, /* EMC_DLL_XFORM_DQS2 */
666 0x00080000, /* EMC_DLL_XFORM_DQS3 */
667 0x00080000, /* EMC_DLL_XFORM_DQS4 */
668 0x00080000, /* EMC_DLL_XFORM_DQS5 */
669 0x00080000, /* EMC_DLL_XFORM_DQS6 */
670 0x00080000, /* EMC_DLL_XFORM_DQS7 */
671 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
672 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
673 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
674 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
675 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
676 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
677 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
678 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
679 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
680 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
681 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
682 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
683 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
684 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
685 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
686 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
687 0x00080000, /* EMC_DLL_XFORM_DQ0 */
688 0x00080000, /* EMC_DLL_XFORM_DQ1 */
689 0x00080000, /* EMC_DLL_XFORM_DQ2 */
690 0x00080000, /* EMC_DLL_XFORM_DQ3 */
691 0x000002a0, /* EMC_XM2CMDPADCTRL */
692 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
693 0x00000000, /* EMC_XM2DQPADCTRL2 */
694 0x77ffc084, /* EMC_XM2CLKPADCTRL */
695 0x01f1f108, /* EMC_XM2COMPPADCTRL */
696 0x05057404, /* EMC_XM2VTTGENPADCTRL */
697 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
698 0x08000168, /* EMC_XM2QUSEPADCTRL */
699 0x08000000, /* EMC_XM2DQSPADCTRL3 */
700 0x00000802, /* EMC_CTT_TERM_CTRL */
701 0x00000000, /* EMC_ZCAL_INTERVAL */
702 0x00000040, /* EMC_ZCAL_WAIT_CNT */
703 0x000c000c, /* EMC_MRS_WAIT_CNT */
704 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
705 0x00000000, /* EMC_CTT */
706 0x00000000, /* EMC_CTT_DURATION */
707 0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
708 0x00020001, /* MC_EMEM_ARB_CFG */
709 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
710 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
711 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
712 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
713 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
714 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
715 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
716 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
717 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
718 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
719 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
720 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
721 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
722 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
723 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
724 0x74430303, /* MC_EMEM_ARB_MISC0 */
725 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
726 0xd8000000, /* EMC_FBIO_SPARE */
727 0xff00ff00, /* EMC_CFG_RSV */
728 },
729 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
730 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
731 0x00000000, /* EMC_CFG.PERIODIC_QRST */
732 0x80001221, /* Mode Register 0 */
733 0x80100003, /* Mode Register 1 */
734 0x80200008, /* Mode Register 2 */
735 0x00000001, /* EMC_CFG.DYN_SELF_REF */
736 },
737 {
738 0x32, /* Rev 3.2 */
739 51000, /* SDRAM frequency */
740 {
741 0x00000002, /* EMC_RC */
742 0x00000008, /* EMC_RFC */
743 0x00000001, /* EMC_RAS */
744 0x00000000, /* EMC_RP */
745 0x00000002, /* EMC_R2W */
746 0x0000000a, /* EMC_W2R */
747 0x00000003, /* EMC_R2P */
748 0x0000000b, /* EMC_W2P */
749 0x00000000, /* EMC_RD_RCD */
750 0x00000000, /* EMC_WR_RCD */
751 0x00000003, /* EMC_RRD */
752 0x00000001, /* EMC_REXT */
753 0x00000000, /* EMC_WEXT */
754 0x00000005, /* EMC_WDV */
755 0x00000005, /* EMC_QUSE */
756 0x00000004, /* EMC_QRST */
757 0x00000007, /* EMC_QSAFE */
758 0x0000000c, /* EMC_RDV */
759 0x00000181, /* EMC_REFRESH */
760 0x00000000, /* EMC_BURST_REFRESH_NUM */
761 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
762 0x00000002, /* EMC_PDEX2WR */
763 0x00000002, /* EMC_PDEX2RD */
764 0x00000001, /* EMC_PCHG2PDEN */
765 0x00000000, /* EMC_ACT2PDEN */
766 0x00000007, /* EMC_AR2PDEN */
767 0x0000000f, /* EMC_RW2PDEN */
768 0x00000009, /* EMC_TXSR */
769 0x00000009, /* EMC_TXSRDLL */
770 0x00000004, /* EMC_TCKE */
771 0x00000002, /* EMC_TFAW */
772 0x00000000, /* EMC_TRPAB */
773 0x00000004, /* EMC_TCLKSTABLE */
774 0x00000005, /* EMC_TCLKSTOP */
775 0x0000018e, /* EMC_TREFBW */
776 0x00000000, /* EMC_QUSE_EXTRA */
777 0x00000004, /* EMC_FBIO_CFG6 */
778 0x00000000, /* EMC_ODT_WRITE */
779 0x00000000, /* EMC_ODT_READ */
780 0x00006288, /* EMC_FBIO_CFG5 */
781 0x007800a4, /* EMC_CFG_DIG_DLL */
782 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
783 0x00080000, /* EMC_DLL_XFORM_DQS0 */
784 0x00080000, /* EMC_DLL_XFORM_DQS1 */
785 0x00080000, /* EMC_DLL_XFORM_DQS2 */
786 0x00080000, /* EMC_DLL_XFORM_DQS3 */
787 0x00080000, /* EMC_DLL_XFORM_DQS4 */
788 0x00080000, /* EMC_DLL_XFORM_DQS5 */
789 0x00080000, /* EMC_DLL_XFORM_DQS6 */
790 0x00080000, /* EMC_DLL_XFORM_DQS7 */
791 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
792 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
793 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
794 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
795 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
796 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
797 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
798 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
799 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
800 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
801 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
802 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
803 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
804 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
805 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
806 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
807 0x00080000, /* EMC_DLL_XFORM_DQ0 */
808 0x00080000, /* EMC_DLL_XFORM_DQ1 */
809 0x00080000, /* EMC_DLL_XFORM_DQ2 */
810 0x00080000, /* EMC_DLL_XFORM_DQ3 */
811 0x000002a0, /* EMC_XM2CMDPADCTRL */
812 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
813 0x00000000, /* EMC_XM2DQPADCTRL2 */
814 0x77ffc084, /* EMC_XM2CLKPADCTRL */
815 0x01f1f108, /* EMC_XM2COMPPADCTRL */
816 0x05057404, /* EMC_XM2VTTGENPADCTRL */
817 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
818 0x08000168, /* EMC_XM2QUSEPADCTRL */
819 0x08000000, /* EMC_XM2DQSPADCTRL3 */
820 0x00000802, /* EMC_CTT_TERM_CTRL */
821 0x00000000, /* EMC_ZCAL_INTERVAL */
822 0x00000040, /* EMC_ZCAL_WAIT_CNT */
823 0x000c000c, /* EMC_MRS_WAIT_CNT */
824 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
825 0x00000000, /* EMC_CTT */
826 0x00000000, /* EMC_CTT_DURATION */
827 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
828 0x00000001, /* MC_EMEM_ARB_CFG */
829 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
830 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
831 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
832 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
833 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
834 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
835 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
836 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
837 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
838 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
839 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
840 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
841 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
842 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
843 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
844 0x73430303, /* MC_EMEM_ARB_MISC0 */
845 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
846 0xd8000000, /* EMC_FBIO_SPARE */
847 0xff00ff00, /* EMC_CFG_RSV */
848 },
849 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
850 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
851 0x00000000, /* EMC_CFG.PERIODIC_QRST */
852 0x80001221, /* Mode Register 0 */
853 0x80100003, /* Mode Register 1 */
854 0x80200008, /* Mode Register 2 */
855 0x00000001, /* EMC_CFG.DYN_SELF_REF */
856 },
857 {
858 0x32, /* Rev 3.2 */
859 102000, /* SDRAM frequency */
860 {
861 0x00000004, /* EMC_RC */
862 0x00000010, /* EMC_RFC */
863 0x00000003, /* EMC_RAS */
864 0x00000001, /* EMC_RP */
865 0x00000002, /* EMC_R2W */
866 0x0000000a, /* EMC_W2R */
867 0x00000003, /* EMC_R2P */
868 0x0000000b, /* EMC_W2P */
869 0x00000001, /* EMC_RD_RCD */
870 0x00000001, /* EMC_WR_RCD */
871 0x00000003, /* EMC_RRD */
872 0x00000001, /* EMC_REXT */
873 0x00000000, /* EMC_WEXT */
874 0x00000005, /* EMC_WDV */
875 0x00000005, /* EMC_QUSE */
876 0x00000004, /* EMC_QRST */
877 0x00000007, /* EMC_QSAFE */
878 0x0000000c, /* EMC_RDV */
879 0x00000303, /* EMC_REFRESH */
880 0x00000000, /* EMC_BURST_REFRESH_NUM */
881 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
882 0x00000002, /* EMC_PDEX2WR */
883 0x00000002, /* EMC_PDEX2RD */
884 0x00000001, /* EMC_PCHG2PDEN */
885 0x00000000, /* EMC_ACT2PDEN */
886 0x00000007, /* EMC_AR2PDEN */
887 0x0000000f, /* EMC_RW2PDEN */
888 0x00000012, /* EMC_TXSR */
889 0x00000012, /* EMC_TXSRDLL */
890 0x00000004, /* EMC_TCKE */
891 0x00000004, /* EMC_TFAW */
892 0x00000000, /* EMC_TRPAB */
893 0x00000004, /* EMC_TCLKSTABLE */
894 0x00000005, /* EMC_TCLKSTOP */
895 0x0000031c, /* EMC_TREFBW */
896 0x00000000, /* EMC_QUSE_EXTRA */
897 0x00000004, /* EMC_FBIO_CFG6 */
898 0x00000000, /* EMC_ODT_WRITE */
899 0x00000000, /* EMC_ODT_READ */
900 0x00006288, /* EMC_FBIO_CFG5 */
901 0x007800a4, /* EMC_CFG_DIG_DLL */
902 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
903 0x00080000, /* EMC_DLL_XFORM_DQS0 */
904 0x00080000, /* EMC_DLL_XFORM_DQS1 */
905 0x00080000, /* EMC_DLL_XFORM_DQS2 */
906 0x00080000, /* EMC_DLL_XFORM_DQS3 */
907 0x00080000, /* EMC_DLL_XFORM_DQS4 */
908 0x00080000, /* EMC_DLL_XFORM_DQS5 */
909 0x00080000, /* EMC_DLL_XFORM_DQS6 */
910 0x00080000, /* EMC_DLL_XFORM_DQS7 */
911 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
912 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
913 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
914 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
915 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
916 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
917 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
918 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
919 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
920 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
921 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
922 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
923 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
924 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
925 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
926 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
927 0x00080000, /* EMC_DLL_XFORM_DQ0 */
928 0x00080000, /* EMC_DLL_XFORM_DQ1 */
929 0x00080000, /* EMC_DLL_XFORM_DQ2 */
930 0x00080000, /* EMC_DLL_XFORM_DQ3 */
931 0x000002a0, /* EMC_XM2CMDPADCTRL */
932 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
933 0x00000000, /* EMC_XM2DQPADCTRL2 */
934 0x77ffc084, /* EMC_XM2CLKPADCTRL */
935 0x01f1f108, /* EMC_XM2COMPPADCTRL */
936 0x05057404, /* EMC_XM2VTTGENPADCTRL */
937 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
938 0x08000168, /* EMC_XM2QUSEPADCTRL */
939 0x08000000, /* EMC_XM2DQSPADCTRL3 */
940 0x00000802, /* EMC_CTT_TERM_CTRL */
941 0x00000000, /* EMC_ZCAL_INTERVAL */
942 0x00000040, /* EMC_ZCAL_WAIT_CNT */
943 0x000c000c, /* EMC_MRS_WAIT_CNT */
944 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
945 0x00000000, /* EMC_CTT */
946 0x00000000, /* EMC_CTT_DURATION */
947 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
948 0x00000001, /* MC_EMEM_ARB_CFG */
949 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
950 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
951 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
952 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
953 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
954 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
955 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
956 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
957 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
958 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
959 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
960 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
961 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
962 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
963 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
964 0x72830504, /* MC_EMEM_ARB_MISC0 */
965 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
966 0xd8000000, /* EMC_FBIO_SPARE */
967 0xff00ff00, /* EMC_CFG_RSV */
968 },
969 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
970 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
971 0x00000000, /* EMC_CFG.PERIODIC_QRST */
972 0x80001221, /* Mode Register 0 */
973 0x80100003, /* Mode Register 1 */
974 0x80200008, /* Mode Register 2 */
975 0x00000001, /* EMC_CFG.DYN_SELF_REF */
976 },
977 {
978 0x32, /* Rev 3.2 */
979 375000, /* SDRAM frequency */
980 {
981 0x00000011, /* EMC_RC */
982 0x0000003a, /* EMC_RFC */
983 0x0000000c, /* EMC_RAS */
984 0x00000004, /* EMC_RP */
985 0x00000003, /* EMC_R2W */
986 0x00000008, /* EMC_W2R */
987 0x00000002, /* EMC_R2P */
988 0x0000000a, /* EMC_W2P */
989 0x00000004, /* EMC_RD_RCD */
990 0x00000004, /* EMC_WR_RCD */
991 0x00000002, /* EMC_RRD */
992 0x00000001, /* EMC_REXT */
993 0x00000000, /* EMC_WEXT */
994 0x00000004, /* EMC_WDV */
995 0x00000006, /* EMC_QUSE */
996 0x00000004, /* EMC_QRST */
997 0x00000008, /* EMC_QSAFE */
998 0x0000000d, /* EMC_RDV */
999 0x00000b2d, /* EMC_REFRESH */
1000 0x00000000, /* EMC_BURST_REFRESH_NUM */
1001 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
1002 0x00000008, /* EMC_PDEX2WR */
1003 0x00000008, /* EMC_PDEX2RD */
1004 0x00000001, /* EMC_PCHG2PDEN */
1005 0x00000000, /* EMC_ACT2PDEN */
1006 0x00000007, /* EMC_AR2PDEN */
1007 0x0000000f, /* EMC_RW2PDEN */
1008 0x00000040, /* EMC_TXSR */
1009 0x00000200, /* EMC_TXSRDLL */
1010 0x00000009, /* EMC_TCKE */
1011 0x0000000c, /* EMC_TFAW */
1012 0x00000000, /* EMC_TRPAB */
1013 0x00000004, /* EMC_TCLKSTABLE */
1014 0x00000005, /* EMC_TCLKSTOP */
1015 0x00000b6d, /* EMC_TREFBW */
1016 0x00000000, /* EMC_QUSE_EXTRA */
1017 0x00000006, /* EMC_FBIO_CFG6 */
1018 0x00000000, /* EMC_ODT_WRITE */
1019 0x00000000, /* EMC_ODT_READ */
1020 0x00007088, /* EMC_FBIO_CFG5 */
1021 0x00200084, /* EMC_CFG_DIG_DLL */
1022 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1023 0x0003c000, /* EMC_DLL_XFORM_DQS0 */
1024 0x0003c000, /* EMC_DLL_XFORM_DQS1 */
1025 0x0003c000, /* EMC_DLL_XFORM_DQS2 */
1026 0x0003c000, /* EMC_DLL_XFORM_DQS3 */
1027 0x0003c000, /* EMC_DLL_XFORM_DQS4 */
1028 0x0003c000, /* EMC_DLL_XFORM_DQS5 */
1029 0x0003c000, /* EMC_DLL_XFORM_DQS6 */
1030 0x0003c000, /* EMC_DLL_XFORM_DQS7 */
1031 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1032 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1033 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1034 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1035 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1036 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1037 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1038 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1039 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1040 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1041 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1042 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1043 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1044 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1045 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1046 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1047 0x00040000, /* EMC_DLL_XFORM_DQ0 */
1048 0x00040000, /* EMC_DLL_XFORM_DQ1 */
1049 0x00040000, /* EMC_DLL_XFORM_DQ2 */
1050 0x00040000, /* EMC_DLL_XFORM_DQ3 */
1051 0x000002a0, /* EMC_XM2CMDPADCTRL */
1052 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1053 0x00000000, /* EMC_XM2DQPADCTRL2 */
1054 0x77fff884, /* EMC_XM2CLKPADCTRL */
1055 0x01f1f508, /* EMC_XM2COMPPADCTRL */
1056 0x05057404, /* EMC_XM2VTTGENPADCTRL */
1057 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1058 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1059 0x08000021, /* EMC_XM2DQSPADCTRL3 */
1060 0x00000802, /* EMC_CTT_TERM_CTRL */
1061 0x00020000, /* EMC_ZCAL_INTERVAL */
1062 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1063 0x0184000c, /* EMC_MRS_WAIT_CNT */
1064 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1065 0x00000000, /* EMC_CTT */
1066 0x00000000, /* EMC_CTT_DURATION */
1067 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
1068 0x00000005, /* MC_EMEM_ARB_CFG */
1069 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1070 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1071 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1072 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
1073 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
1074 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1075 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1076 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1077 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1078 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1079 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1080 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1081 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1082 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1083 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
1084 0x75c6110a, /* MC_EMEM_ARB_MISC0 */
1085 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1086 0x58000000, /* EMC_FBIO_SPARE */
1087 0xff00ff88, /* EMC_CFG_RSV */
1088 },
1089 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1090 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1091 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1092 0x80000521, /* Mode Register 0 */
1093 0x80100002, /* Mode Register 1 */
1094 0x80200000, /* Mode Register 2 */
1095 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1096 },
1097 {
1098 0x32, /* Rev 3.2 */
1099 400000, /* SDRAM frequency */
1100 {
1101 0x00000012, /* EMC_RC */
1102 0x00000040, /* EMC_RFC */
1103 0x0000000d, /* EMC_RAS */
1104 0x00000004, /* EMC_RP */
1105 0x00000002, /* EMC_R2W */
1106 0x00000009, /* EMC_W2R */
1107 0x00000002, /* EMC_R2P */
1108 0x0000000c, /* EMC_W2P */
1109 0x00000004, /* EMC_RD_RCD */
1110 0x00000004, /* EMC_WR_RCD */
1111 0x00000002, /* EMC_RRD */
1112 0x00000001, /* EMC_REXT */
1113 0x00000000, /* EMC_WEXT */
1114 0x00000005, /* EMC_WDV */
1115 0x00000007, /* EMC_QUSE */
1116 0x00000005, /* EMC_QRST */
1117 0x00000008, /* EMC_QSAFE */
1118 0x0000000e, /* EMC_RDV */
1119 0x00000c2e, /* EMC_REFRESH */
1120 0x00000000, /* EMC_BURST_REFRESH_NUM */
1121 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1122 0x00000008, /* EMC_PDEX2WR */
1123 0x00000008, /* EMC_PDEX2RD */
1124 0x00000001, /* EMC_PCHG2PDEN */
1125 0x00000000, /* EMC_ACT2PDEN */
1126 0x00000008, /* EMC_AR2PDEN */
1127 0x00000011, /* EMC_RW2PDEN */
1128 0x00000046, /* EMC_TXSR */
1129 0x00000200, /* EMC_TXSRDLL */
1130 0x0000000a, /* EMC_TCKE */
1131 0x0000000d, /* EMC_TFAW */
1132 0x00000000, /* EMC_TRPAB */
1133 0x00000004, /* EMC_TCLKSTABLE */
1134 0x00000005, /* EMC_TCLKSTOP */
1135 0x00000c6f, /* EMC_TREFBW */
1136 0x00000000, /* EMC_QUSE_EXTRA */
1137 0x00000006, /* EMC_FBIO_CFG6 */
1138 0x00000000, /* EMC_ODT_WRITE */
1139 0x00000000, /* EMC_ODT_READ */
1140 0x00007088, /* EMC_FBIO_CFG5 */
1141 0x001c0084, /* EMC_CFG_DIG_DLL */
1142 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1143 0x00034000, /* EMC_DLL_XFORM_DQS0 */
1144 0x00034000, /* EMC_DLL_XFORM_DQS1 */
1145 0x00034000, /* EMC_DLL_XFORM_DQS2 */
1146 0x00034000, /* EMC_DLL_XFORM_DQS3 */
1147 0x00034000, /* EMC_DLL_XFORM_DQS4 */
1148 0x00034000, /* EMC_DLL_XFORM_DQS5 */
1149 0x00034000, /* EMC_DLL_XFORM_DQS6 */
1150 0x00034000, /* EMC_DLL_XFORM_DQS7 */
1151 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1152 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1153 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1154 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1155 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1156 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1157 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1158 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1159 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1160 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1161 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1162 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1163 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1164 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1165 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1166 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1167 0x00040000, /* EMC_DLL_XFORM_DQ0 */
1168 0x00040000, /* EMC_DLL_XFORM_DQ1 */
1169 0x00040000, /* EMC_DLL_XFORM_DQ2 */
1170 0x00040000, /* EMC_DLL_XFORM_DQ3 */
1171 0x000002a0, /* EMC_XM2CMDPADCTRL */
1172 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1173 0x00000000, /* EMC_XM2DQPADCTRL2 */
1174 0x77fff884, /* EMC_XM2CLKPADCTRL */
1175 0x01f1f508, /* EMC_XM2COMPPADCTRL */
1176 0x05057404, /* EMC_XM2VTTGENPADCTRL */
1177 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1178 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1179 0x08000021, /* EMC_XM2DQSPADCTRL3 */
1180 0x00000802, /* EMC_CTT_TERM_CTRL */
1181 0x00020000, /* EMC_ZCAL_INTERVAL */
1182 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1183 0x017f000c, /* EMC_MRS_WAIT_CNT */
1184 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1185 0x00000000, /* EMC_CTT */
1186 0x00000000, /* EMC_CTT_DURATION */
1187 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1188 0x00000006, /* MC_EMEM_ARB_CFG */
1189 0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1190 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1191 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1192 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1193 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1194 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1195 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1196 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1197 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1198 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1199 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1200 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1201 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1202 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1203 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1204 0x7547130b, /* MC_EMEM_ARB_MISC0 */
1205 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1206 0x58000000, /* EMC_FBIO_SPARE */
1207 0xff00ff88, /* EMC_CFG_RSV */
1208 },
1209 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1210 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1211 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1212 0x80000731, /* Mode Register 0 */
1213 0x80100002, /* Mode Register 1 */
1214 0x80200008, /* Mode Register 2 */
1215 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1216 },
1217 {
1218 0x32, /* Rev 3.2 */
1219 425000, /* SDRAM frequency */
1220 {
1221 0x00000012, /* EMC_RC */
1222 0x00000040, /* EMC_RFC */
1223 0x0000000d, /* EMC_RAS */
1224 0x00000004, /* EMC_RP */
1225 0x00000002, /* EMC_R2W */
1226 0x00000009, /* EMC_W2R */
1227 0x00000002, /* EMC_R2P */
1228 0x0000000c, /* EMC_W2P */
1229 0x00000004, /* EMC_RD_RCD */
1230 0x00000004, /* EMC_WR_RCD */
1231 0x00000002, /* EMC_RRD */
1232 0x00000001, /* EMC_REXT */
1233 0x00000000, /* EMC_WEXT */
1234 0x00000005, /* EMC_WDV */
1235 0x00000007, /* EMC_QUSE */
1236 0x00000005, /* EMC_QRST */
1237 0x00000008, /* EMC_QSAFE */
1238 0x0000000e, /* EMC_RDV */
1239 0x00000c2e, /* EMC_REFRESH */
1240 0x00000000, /* EMC_BURST_REFRESH_NUM */
1241 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1242 0x00000008, /* EMC_PDEX2WR */
1243 0x00000008, /* EMC_PDEX2RD */
1244 0x00000001, /* EMC_PCHG2PDEN */
1245 0x00000000, /* EMC_ACT2PDEN */
1246 0x00000008, /* EMC_AR2PDEN */
1247 0x00000011, /* EMC_RW2PDEN */
1248 0x00000046, /* EMC_TXSR */
1249 0x00000200, /* EMC_TXSRDLL */
1250 0x0000000a, /* EMC_TCKE */
1251 0x0000000d, /* EMC_TFAW */
1252 0x00000000, /* EMC_TRPAB */
1253 0x00000004, /* EMC_TCLKSTABLE */
1254 0x00000005, /* EMC_TCLKSTOP */
1255 0x00000c6f, /* EMC_TREFBW */
1256 0x00000000, /* EMC_QUSE_EXTRA */
1257 0x00000006, /* EMC_FBIO_CFG6 */
1258 0x00000000, /* EMC_ODT_WRITE */
1259 0x00000000, /* EMC_ODT_READ */
1260 0x00007088, /* EMC_FBIO_CFG5 */
1261 0x001c0084, /* EMC_CFG_DIG_DLL */
1262 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1263 0x00034000, /* EMC_DLL_XFORM_DQS0 */
1264 0x00034000, /* EMC_DLL_XFORM_DQS1 */
1265 0x00034000, /* EMC_DLL_XFORM_DQS2 */
1266 0x00034000, /* EMC_DLL_XFORM_DQS3 */
1267 0x00034000, /* EMC_DLL_XFORM_DQS4 */
1268 0x00034000, /* EMC_DLL_XFORM_DQS5 */
1269 0x00034000, /* EMC_DLL_XFORM_DQS6 */
1270 0x00034000, /* EMC_DLL_XFORM_DQS7 */
1271 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1272 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1273 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1274 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1275 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1276 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1277 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1278 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1279 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1280 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1281 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1282 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1283 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1284 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1285 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1286 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1287 0x00040000, /* EMC_DLL_XFORM_DQ0 */
1288 0x00040000, /* EMC_DLL_XFORM_DQ1 */
1289 0x00040000, /* EMC_DLL_XFORM_DQ2 */
1290 0x00040000, /* EMC_DLL_XFORM_DQ3 */
1291 0x000002a0, /* EMC_XM2CMDPADCTRL */
1292 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1293 0x00000000, /* EMC_XM2DQPADCTRL2 */
1294 0x77fff884, /* EMC_XM2CLKPADCTRL */
1295 0x01f1f508, /* EMC_XM2COMPPADCTRL */
1296 0x05057404, /* EMC_XM2VTTGENPADCTRL */
1297 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1298 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1299 0x08000021, /* EMC_XM2DQSPADCTRL3 */
1300 0x00000802, /* EMC_CTT_TERM_CTRL */
1301 0x00020000, /* EMC_ZCAL_INTERVAL */
1302 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1303 0x017f000c, /* EMC_MRS_WAIT_CNT */
1304 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1305 0x00000000, /* EMC_CTT */
1306 0x00000000, /* EMC_CTT_DURATION */
1307 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1308 0x00000006, /* MC_EMEM_ARB_CFG */
1309 0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1310 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1311 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1312 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1313 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1314 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1315 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1316 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1317 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1318 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1319 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1320 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1321 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1322 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1323 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1324 0x7547130b, /* MC_EMEM_ARB_MISC0 */
1325 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1326 0x58000000, /* EMC_FBIO_SPARE */
1327 0xff00ff88, /* EMC_CFG_RSV */
1328 },
1329 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1330 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1331 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1332 0x80000731, /* Mode Register 0 */
1333 0x80100002, /* Mode Register 1 */
1334 0x80200008, /* Mode Register 2 */
1335 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1336 },
1337 {
1338 0x32, /* Rev 3.2 */
1339 450000, /* SDRAM frequency */
1340 {
1341 0x00000014, /* EMC_RC */
1342 0x00000046, /* EMC_RFC */
1343 0x0000000e, /* EMC_RAS */
1344 0x00000005, /* EMC_RP */
1345 0x00000003, /* EMC_R2W */
1346 0x00000009, /* EMC_W2R */
1347 0x00000002, /* EMC_R2P */
1348 0x0000000c, /* EMC_W2P */
1349 0x00000005, /* EMC_RD_RCD */
1350 0x00000005, /* EMC_WR_RCD */
1351 0x00000002, /* EMC_RRD */
1352 0x00000001, /* EMC_REXT */
1353 0x00000000, /* EMC_WEXT */
1354 0x00000005, /* EMC_WDV */
1355 0x00000007, /* EMC_QUSE */
1356 0x00000005, /* EMC_QRST */
1357 0x0000000a, /* EMC_QSAFE */
1358 0x0000000e, /* EMC_RDV */
1359 0x00000d76, /* EMC_REFRESH */
1360 0x00000000, /* EMC_BURST_REFRESH_NUM */
1361 0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
1362 0x00000001, /* EMC_PDEX2WR */
1363 0x00000009, /* EMC_PDEX2RD */
1364 0x00000001, /* EMC_PCHG2PDEN */
1365 0x00000000, /* EMC_ACT2PDEN */
1366 0x00000009, /* EMC_AR2PDEN */
1367 0x00000011, /* EMC_RW2PDEN */
1368 0x0000004d, /* EMC_TXSR */
1369 0x00000200, /* EMC_TXSRDLL */
1370 0x00000004, /* EMC_TCKE */
1371 0x0000000e, /* EMC_TFAW */
1372 0x00000000, /* EMC_TRPAB */
1373 0x00000004, /* EMC_TCLKSTABLE */
1374 0x00000005, /* EMC_TCLKSTOP */
1375 0x00000db6, /* EMC_TREFBW */
1376 0x00000000, /* EMC_QUSE_EXTRA */
1377 0x00000006, /* EMC_FBIO_CFG6 */
1378 0x00000000, /* EMC_ODT_WRITE */
1379 0x00000000, /* EMC_ODT_READ */
1380 0x00007088, /* EMC_FBIO_CFG5 */
1381 0x00180084, /* EMC_CFG_DIG_DLL */
1382 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1383 0x00022000, /* EMC_DLL_XFORM_DQS0 */
1384 0x00022000, /* EMC_DLL_XFORM_DQS1 */
1385 0x00022000, /* EMC_DLL_XFORM_DQS2 */
1386 0x00022000, /* EMC_DLL_XFORM_DQS3 */
1387 0x00022000, /* EMC_DLL_XFORM_DQS4 */
1388 0x00022000, /* EMC_DLL_XFORM_DQS5 */
1389 0x00022000, /* EMC_DLL_XFORM_DQS6 */
1390 0x00022000, /* EMC_DLL_XFORM_DQS7 */
1391 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1392 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1393 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1394 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1395 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1396 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1397 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1398 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1399 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1400 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1401 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1402 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1403 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1404 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1405 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1406 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1407 0x00030000, /* EMC_DLL_XFORM_DQ0 */
1408 0x00030000, /* EMC_DLL_XFORM_DQ1 */
1409 0x00030000, /* EMC_DLL_XFORM_DQ2 */
1410 0x00030000, /* EMC_DLL_XFORM_DQ3 */
1411 0x000002a0, /* EMC_XM2CMDPADCTRL */
1412 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1413 0x00000000, /* EMC_XM2DQPADCTRL2 */
1414 0x77fff884, /* EMC_XM2CLKPADCTRL */
1415 0x01f1f508, /* EMC_XM2COMPPADCTRL */
1416 0x05057404, /* EMC_XM2VTTGENPADCTRL */
1417 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1418 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1419 0x08000021, /* EMC_XM2DQSPADCTRL3 */
1420 0x00000802, /* EMC_CTT_TERM_CTRL */
1421 0x00020000, /* EMC_ZCAL_INTERVAL */
1422 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1423 0x0178000c, /* EMC_MRS_WAIT_CNT */
1424 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1425 0x00000000, /* EMC_CTT */
1426 0x00000000, /* EMC_CTT_DURATION */
1427 0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
1428 0x00000006, /* MC_EMEM_ARB_CFG */
1429 0x80000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1430 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1431 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1432 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
1433 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1434 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1435 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1436 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1437 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1438 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1439 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1440 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1441 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1442 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1443 0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
1444 0x70a7150c, /* MC_EMEM_ARB_MISC0 */
1445 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1446 0xe8000000, /* EMC_FBIO_SPARE */
1447 0xff00ff8b, /* EMC_CFG_RSV */
1448 },
1449 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1450 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1451 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1452 0x80000731, /* Mode Register 0 */
1453 0x80100002, /* Mode Register 1 */
1454 0x80200008, /* Mode Register 2 */
1455 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1456 },
1457 {
1458 0x32, /* Rev 3.2 */
1459 533000, /* SDRAM frequency */
1460 {
1461 0x00000018, /* EMC_RC */
1462 0x00000054, /* EMC_RFC */
1463 0x00000011, /* EMC_RAS */
1464 0x00000006, /* EMC_RP */
1465 0x00000003, /* EMC_R2W */
1466 0x00000009, /* EMC_W2R */
1467 0x00000002, /* EMC_R2P */
1468 0x0000000d, /* EMC_W2P */
1469 0x00000006, /* EMC_RD_RCD */
1470 0x00000006, /* EMC_WR_RCD */
1471 0x00000002, /* EMC_RRD */
1472 0x00000001, /* EMC_REXT */
1473 0x00000000, /* EMC_WEXT */
1474 0x00000005, /* EMC_WDV */
1475 0x00000008, /* EMC_QUSE */
1476 0x00000006, /* EMC_QRST */
1477 0x00000008, /* EMC_QSAFE */
1478 0x00000010, /* EMC_RDV */
1479 0x00000ffd, /* EMC_REFRESH */
1480 0x00000000, /* EMC_BURST_REFRESH_NUM */
1481 0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
1482 0x0000000b, /* EMC_PDEX2WR */
1483 0x0000000b, /* EMC_PDEX2RD */
1484 0x00000001, /* EMC_PCHG2PDEN */
1485 0x00000000, /* EMC_ACT2PDEN */
1486 0x0000000a, /* EMC_AR2PDEN */
1487 0x00000012, /* EMC_RW2PDEN */
1488 0x0000005b, /* EMC_TXSR */
1489 0x00000200, /* EMC_TXSRDLL */
1490 0x0000000d, /* EMC_TCKE */
1491 0x00000010, /* EMC_TFAW */
1492 0x00000000, /* EMC_TRPAB */
1493 0x00000005, /* EMC_TCLKSTABLE */
1494 0x00000006, /* EMC_TCLKSTOP */
1495 0x0000103e, /* EMC_TREFBW */
1496 0x00000000, /* EMC_QUSE_EXTRA */
1497 0x00000006, /* EMC_FBIO_CFG6 */
1498 0x00000000, /* EMC_ODT_WRITE */
1499 0x00000000, /* EMC_ODT_READ */
1500 0x00007088, /* EMC_FBIO_CFG5 */
1501 0x00120084, /* EMC_CFG_DIG_DLL */
1502 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1503 0x00010000, /* EMC_DLL_XFORM_DQS0 */
1504 0x00010000, /* EMC_DLL_XFORM_DQS1 */
1505 0x00010000, /* EMC_DLL_XFORM_DQS2 */
1506 0x00010000, /* EMC_DLL_XFORM_DQS3 */
1507 0x00010000, /* EMC_DLL_XFORM_DQS4 */
1508 0x00010000, /* EMC_DLL_XFORM_DQS5 */
1509 0x00010000, /* EMC_DLL_XFORM_DQS6 */
1510 0x00010000, /* EMC_DLL_XFORM_DQS7 */
1511 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1512 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1513 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1514 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1515 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1516 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1517 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1518 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1519 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1520 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1521 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1522 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1523 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1524 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1525 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1526 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1527 0x00020000, /* EMC_DLL_XFORM_DQ0 */
1528 0x00020000, /* EMC_DLL_XFORM_DQ1 */
1529 0x00020000, /* EMC_DLL_XFORM_DQ2 */
1530 0x00020000, /* EMC_DLL_XFORM_DQ3 */
1531 0x000006a0, /* EMC_XM2CMDPADCTRL */
1532 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1533 0x00000000, /* EMC_XM2DQPADCTRL2 */
1534 0x77ffc084, /* EMC_XM2CLKPADCTRL */
1535 0x01f1f508, /* EMC_XM2COMPPADCTRL */
1536 0x05057404, /* EMC_XM2VTTGENPADCTRL */
1537 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1538 0x08000168, /* EMC_XM2QUSEPADCTRL */
1539 0x08000021, /* EMC_XM2DQSPADCTRL3 */
1540 0x00000802, /* EMC_CTT_TERM_CTRL */
1541 0x00000000, /* EMC_ZCAL_INTERVAL */
1542 0x00000040, /* EMC_ZCAL_WAIT_CNT */
1543 0x01ab000c, /* EMC_MRS_WAIT_CNT */
1544 0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
1545 0x00000000, /* EMC_CTT */
1546 0x00000000, /* EMC_CTT_DURATION */
1547 0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
1548 0x00000008, /* MC_EMEM_ARB_CFG */
1549 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1550 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1551 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1552 0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
1553 0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
1554 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
1555 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1556 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1557 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1558 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1559 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1560 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1561 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1562 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1563 0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
1564 0x7028180e, /* MC_EMEM_ARB_MISC0 */
1565 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1566 0x00000000, /* EMC_FBIO_SPARE */
1567 0xff00ff00, /* EMC_CFG_RSV */
1568 },
1569 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1570 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1571 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1572 0x80000941, /* Mode Register 0 */
1573 0x80100002, /* Mode Register 1 */
1574 0x80200008, /* Mode Register 2 */
1575 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1576 },
1577 {
1578 0x32, /* Rev 3.2 */
1579 750000, /* SDRAM frequency */
1580 {
1581 0x00000025, /* EMC_RC */
1582 0x0000007e, /* EMC_RFC */
1583 0x0000001a, /* EMC_RAS */
1584 0x00000009, /* EMC_RP */
1585 0x00000004, /* EMC_R2W */
1586 0x0000000d, /* EMC_W2R */
1587 0x00000004, /* EMC_R2P */
1588 0x00000013, /* EMC_W2P */
1589 0x00000009, /* EMC_RD_RCD */
1590 0x00000009, /* EMC_WR_RCD */
1591 0x00000003, /* EMC_RRD */
1592 0x00000001, /* EMC_REXT */
1593 0x00000000, /* EMC_WEXT */
1594 0x00000007, /* EMC_WDV */
1595 0x0000000b, /* EMC_QUSE */
1596 0x00000009, /* EMC_QRST */
1597 0x0000000c, /* EMC_QSAFE */
1598 0x00000011, /* EMC_RDV */
1599 0x0000169a, /* EMC_REFRESH */
1600 0x00000000, /* EMC_BURST_REFRESH_NUM */
1601 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
1602 0x00000012, /* EMC_PDEX2WR */
1603 0x00000012, /* EMC_PDEX2RD */
1604 0x00000001, /* EMC_PCHG2PDEN */
1605 0x00000000, /* EMC_ACT2PDEN */
1606 0x0000000f, /* EMC_AR2PDEN */
1607 0x00000018, /* EMC_RW2PDEN */
1608 0x00000088, /* EMC_TXSR */
1609 0x00000200, /* EMC_TXSRDLL */
1610 0x00000014, /* EMC_TCKE */
1611 0x00000018, /* EMC_TFAW */
1612 0x00000000, /* EMC_TRPAB */
1613 0x00000007, /* EMC_TCLKSTABLE */
1614 0x00000008, /* EMC_TCLKSTOP */
1615 0x00001860, /* EMC_TREFBW */
1616 0x0000000c, /* EMC_QUSE_EXTRA */
1617 0x00000004, /* EMC_FBIO_CFG6 */
1618 0x00000000, /* EMC_ODT_WRITE */
1619 0x00000000, /* EMC_ODT_READ */
1620 0x00005088, /* EMC_FBIO_CFG5 */
1621 0xf0080191, /* EMC_CFG_DIG_DLL */
1622 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1623 0x00000008, /* EMC_DLL_XFORM_DQS0 */
1624 0x00000008, /* EMC_DLL_XFORM_DQS1 */
1625 0x00000008, /* EMC_DLL_XFORM_DQS2 */
1626 0x00000008, /* EMC_DLL_XFORM_DQS3 */
1627 0x00000008, /* EMC_DLL_XFORM_DQS4 */
1628 0x00000008, /* EMC_DLL_XFORM_DQS5 */
1629 0x00000008, /* EMC_DLL_XFORM_DQS6 */
1630 0x00000008, /* EMC_DLL_XFORM_DQS7 */
1631 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1632 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1633 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1634 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1635 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1636 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1637 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1638 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1639 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1640 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1641 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1642 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1643 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1644 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1645 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1646 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1647 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
1648 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
1649 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
1650 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
1651 0x000002a0, /* EMC_XM2CMDPADCTRL */
1652 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1653 0x22220000, /* EMC_XM2DQPADCTRL2 */
1654 0x77fff884, /* EMC_XM2CLKPADCTRL */
1655 0x01f1f501, /* EMC_XM2COMPPADCTRL */
1656 0x07077404, /* EMC_XM2VTTGENPADCTRL */
1657 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1658 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1659 0x07000021, /* EMC_XM2DQSPADCTRL3 */
1660 0x00000802, /* EMC_CTT_TERM_CTRL */
1661 0x00020000, /* EMC_ZCAL_INTERVAL */
1662 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1663 0x0180000c, /* EMC_MRS_WAIT_CNT */
1664 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1665 0x00000000, /* EMC_CTT */
1666 0x00000000, /* EMC_CTT_DURATION */
1667 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
1668 0x0000000c, /* MC_EMEM_ARB_CFG */
1669 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1670 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1671 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1672 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
1673 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
1674 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
1675 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1676 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1677 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1678 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1679 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1680 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1681 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1682 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
1683 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
1684 0x72ac2414, /* MC_EMEM_ARB_MISC0 */
1685 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1686 0xf8000000, /* EMC_FBIO_SPARE */
1687 0xff00ff49, /* EMC_CFG_RSV */
1688 },
1689 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1690 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1691 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1692 0x80000d71, /* Mode Register 0 */
1693 0x80100002, /* Mode Register 1 */
1694 0x80200018, /* Mode Register 2 */
1695 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1696 },
1697 {
1698 0x32, /* Rev 3.2 */
1699 800000, /* SDRAM frequency */
1700 {
1701 0x00000025, /* EMC_RC */
1702 0x0000007e, /* EMC_RFC */
1703 0x0000001a, /* EMC_RAS */
1704 0x00000009, /* EMC_RP */
1705 0x00000004, /* EMC_R2W */
1706 0x0000000d, /* EMC_W2R */
1707 0x00000004, /* EMC_R2P */
1708 0x00000013, /* EMC_W2P */
1709 0x00000009, /* EMC_RD_RCD */
1710 0x00000009, /* EMC_WR_RCD */
1711 0x00000003, /* EMC_RRD */
1712 0x00000001, /* EMC_REXT */
1713 0x00000000, /* EMC_WEXT */
1714 0x00000007, /* EMC_WDV */
1715 0x0000000b, /* EMC_QUSE */
1716 0x00000009, /* EMC_QRST */
1717 0x0000000c, /* EMC_QSAFE */
1718 0x00000011, /* EMC_RDV */
1719 0x00001820, /* EMC_REFRESH */
1720 0x00000000, /* EMC_BURST_REFRESH_NUM */
1721 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
1722 0x00000012, /* EMC_PDEX2WR */
1723 0x00000012, /* EMC_PDEX2RD */
1724 0x00000001, /* EMC_PCHG2PDEN */
1725 0x00000000, /* EMC_ACT2PDEN */
1726 0x0000000f, /* EMC_AR2PDEN */
1727 0x00000018, /* EMC_RW2PDEN */
1728 0x00000088, /* EMC_TXSR */
1729 0x00000200, /* EMC_TXSRDLL */
1730 0x00000014, /* EMC_TCKE */
1731 0x00000018, /* EMC_TFAW */
1732 0x00000000, /* EMC_TRPAB */
1733 0x00000007, /* EMC_TCLKSTABLE */
1734 0x00000008, /* EMC_TCLKSTOP */
1735 0x00001860, /* EMC_TREFBW */
1736 0x0000000c, /* EMC_QUSE_EXTRA */
1737 0x00000004, /* EMC_FBIO_CFG6 */
1738 0x00000000, /* EMC_ODT_WRITE */
1739 0x00000000, /* EMC_ODT_READ */
1740 0x00005088, /* EMC_FBIO_CFG5 */
1741 0xf0070191, /* EMC_CFG_DIG_DLL */
1742 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1743 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1744 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1745 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1746 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1747 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1748 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1749 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1750 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1751 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1752 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1753 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1754 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1755 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1756 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1757 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1758 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1759 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1760 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1761 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1762 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1763 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1764 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1765 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1766 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1767 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
1768 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1769 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1770 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1771 0x000002a0, /* EMC_XM2CMDPADCTRL */
1772 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1773 0x22220000, /* EMC_XM2DQPADCTRL2 */
1774 0x77fff884, /* EMC_XM2CLKPADCTRL */
1775 0x01f1f501, /* EMC_XM2COMPPADCTRL */
1776 0x07077404, /* EMC_XM2VTTGENPADCTRL */
1777 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1778 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1779 0x07000021, /* EMC_XM2DQSPADCTRL3 */
1780 0x00000802, /* EMC_CTT_TERM_CTRL */
1781 0x00020000, /* EMC_ZCAL_INTERVAL */
1782 0x00000100, /* EMC_ZCAL_WAIT_CNT */
1783 0x0180000c, /* EMC_MRS_WAIT_CNT */
1784 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1785 0x00000000, /* EMC_CTT */
1786 0x00000000, /* EMC_CTT_DURATION */
1787 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
1788 0x0000000c, /* MC_EMEM_ARB_CFG */
1789 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1790 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1791 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1792 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
1793 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
1794 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
1795 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1796 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1797 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1798 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1799 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1800 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1801 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1802 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
1803 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
1804 0x72ac2414, /* MC_EMEM_ARB_MISC0 */
1805 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1806 0xf8000000, /* EMC_FBIO_SPARE */
1807 0xff00ff49, /* EMC_CFG_RSV */
1808 },
1809 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1810 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1811 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1812 0x80000d71, /* Mode Register 0 */
1813 0x80100002, /* Mode Register 1 */
1814 0x80200018, /* Mode Register 2 */
1815 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1816 },
1817 {
1818 0x32, /* Rev 3.2 */
1819 850000, /* SDRAM frequency */
1820 {
1821 0x00000028, /* EMC_RC */
1822 0x00000086, /* EMC_RFC */
1823 0x0000001c, /* EMC_RAS */
1824 0x0000000a, /* EMC_RP */
1825 0x00000006, /* EMC_R2W */
1826 0x0000000f, /* EMC_W2R */
1827 0x00000005, /* EMC_R2P */
1828 0x00000016, /* EMC_W2P */
1829 0x0000000a, /* EMC_RD_RCD */
1830 0x0000000a, /* EMC_WR_RCD */
1831 0x00000004, /* EMC_RRD */
1832 0x00000001, /* EMC_REXT */
1833 0x00000000, /* EMC_WEXT */
1834 0x00000008, /* EMC_WDV */
1835 0x0000000d, /* EMC_QUSE */
1836 0x0000000b, /* EMC_QRST */
1837 0x0000000b, /* EMC_QSAFE */
1838 0x00000014, /* EMC_RDV */
1839 0x000019a6, /* EMC_REFRESH */
1840 0x00000000, /* EMC_BURST_REFRESH_NUM */
1841 0x00000669, /* EMC_PRE_REFRESH_REQ_CNT */
1842 0x00000004, /* EMC_PDEX2WR */
1843 0x00000013, /* EMC_PDEX2RD */
1844 0x00000001, /* EMC_PCHG2PDEN */
1845 0x00000000, /* EMC_ACT2PDEN */
1846 0x00000010, /* EMC_AR2PDEN */
1847 0x0000001b, /* EMC_RW2PDEN */
1848 0x00000091, /* EMC_TXSR */
1849 0x00000200, /* EMC_TXSRDLL */
1850 0x00000006, /* EMC_TCKE */
1851 0x0000001a, /* EMC_TFAW */
1852 0x00000000, /* EMC_TRPAB */
1853 0x00000008, /* EMC_TCLKSTABLE */
1854 0x00000009, /* EMC_TCLKSTOP */
1855 0x000019e6, /* EMC_TREFBW */
1856 0x0000000e, /* EMC_QUSE_EXTRA */
1857 0x00000004, /* EMC_FBIO_CFG6 */
1858 0x00000000, /* EMC_ODT_WRITE */
1859 0x00000000, /* EMC_ODT_READ */
1860 0x00005088, /* EMC_FBIO_CFG5 */
1861 0xf0050191, /* EMC_CFG_DIG_DLL */
1862 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1863 0x0000c00a, /* EMC_DLL_XFORM_DQS0 */
1864 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1865 0x007fc008, /* EMC_DLL_XFORM_DQS2 */
1866 0x007fc008, /* EMC_DLL_XFORM_DQS3 */
1867 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1868 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1869 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1870 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1871 0x0000c000, /* EMC_DLL_XFORM_QUSE0 */
1872 0x0000c000, /* EMC_DLL_XFORM_QUSE1 */
1873 0x0000c000, /* EMC_DLL_XFORM_QUSE2 */
1874 0x0000c000, /* EMC_DLL_XFORM_QUSE3 */
1875 0x0000c000, /* EMC_DLL_XFORM_QUSE4 */
1876 0x0000c000, /* EMC_DLL_XFORM_QUSE5 */
1877 0x0000c000, /* EMC_DLL_XFORM_QUSE6 */
1878 0x0000c000, /* EMC_DLL_XFORM_QUSE7 */
1879 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1880 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1881 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1882 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1883 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1884 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1885 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1886 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1887 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
1888 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1889 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1890 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1891 0x000002a0, /* EMC_XM2CMDPADCTRL */
1892 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1893 0x22220000, /* EMC_XM2DQPADCTRL2 */
1894 0x77fff884, /* EMC_XM2CLKPADCTRL */
1895 0x01f1f501, /* EMC_XM2COMPPADCTRL */
1896 0x07077404, /* EMC_XM2VTTGENPADCTRL */
1897 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1898 0x080001e8, /* EMC_XM2QUSEPADCTRL */
1899 0x07000021, /* EMC_XM2DQSPADCTRL3 */
1900 0x00000802, /* EMC_CTT_TERM_CTRL */
1901 0x00020000, /* EMC_ZCAL_INTERVAL */
1902 0x00000110, /* EMC_ZCAL_WAIT_CNT */
1903 0x0134000c, /* EMC_MRS_WAIT_CNT */
1904 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1905 0x00000000, /* EMC_CTT */
1906 0x00000000, /* EMC_CTT_DURATION */
1907 0x80003384, /* EMC_DYN_SELF_REF_CONTROL */
1908 0x0000000c, /* MC_EMEM_ARB_CFG */
1909 0x80000099, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1910 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1911 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1912 0x00000014, /* MC_EMEM_ARB_TIMING_RC */
1913 0x0000000d, /* MC_EMEM_ARB_TIMING_RAS */
1914 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
1915 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1916 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1917 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1918 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1919 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1920 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1921 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
1922 0x09050202, /* MC_EMEM_ARB_DA_TURNS */
1923 0x00190f14, /* MC_EMEM_ARB_DA_COVERS */
1924 0x714d2715, /* MC_EMEM_ARB_MISC0 */
1925 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1926 0xe8000000, /* EMC_FBIO_SPARE */
1927 0xff00ff49, /* EMC_CFG_RSV */
1928 },
1929 0x00000044, /* EMC_ZCAL_WAIT_CNT after clock change */
1930 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1931 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1932 0x80000f15, /* Mode Register 0 */
1933 0x80100002, /* Mode Register 1 */
1934 0x80200020, /* Mode Register 2 */
1935 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1936 },
1937 {
1938 0x32, /* Rev 3.2 */
1939 900000, /* SDRAM frequency */
1940 {
1941 0x0000002a, /* EMC_RC */
1942 0x0000008e, /* EMC_RFC */
1943 0x0000001e, /* EMC_RAS */
1944 0x0000000b, /* EMC_RP */
1945 0x00000006, /* EMC_R2W */
1946 0x0000000f, /* EMC_W2R */
1947 0x00000005, /* EMC_R2P */
1948 0x00000016, /* EMC_W2P */
1949 0x0000000b, /* EMC_RD_RCD */
1950 0x0000000b, /* EMC_WR_RCD */
1951 0x00000004, /* EMC_RRD */
1952 0x00000001, /* EMC_REXT */
1953 0x00000000, /* EMC_WEXT */
1954 0x00000008, /* EMC_WDV */
1955 0x0000000d, /* EMC_QUSE */
1956 0x0000000b, /* EMC_QRST */
1957 0x0000000b, /* EMC_QSAFE */
1958 0x00000014, /* EMC_RDV */
1959 0x00001b2c, /* EMC_REFRESH */
1960 0x00000000, /* EMC_BURST_REFRESH_NUM */
1961 0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
1962 0x00000004, /* EMC_PDEX2WR */
1963 0x00000014, /* EMC_PDEX2RD */
1964 0x00000001, /* EMC_PCHG2PDEN */
1965 0x00000000, /* EMC_ACT2PDEN */
1966 0x00000011, /* EMC_AR2PDEN */
1967 0x0000001b, /* EMC_RW2PDEN */
1968 0x00000099, /* EMC_TXSR */
1969 0x00000200, /* EMC_TXSRDLL */
1970 0x00000006, /* EMC_TCKE */
1971 0x0000001b, /* EMC_TFAW */
1972 0x00000000, /* EMC_TRPAB */
1973 0x00000008, /* EMC_TCLKSTABLE */
1974 0x00000009, /* EMC_TCLKSTOP */
1975 0x00001b6c, /* EMC_TREFBW */
1976 0x0000000e, /* EMC_QUSE_EXTRA */
1977 0x00000004, /* EMC_FBIO_CFG6 */
1978 0x00000000, /* EMC_ODT_WRITE */
1979 0x00000000, /* EMC_ODT_READ */
1980 0x00005088, /* EMC_FBIO_CFG5 */
1981 0xf0040191, /* EMC_CFG_DIG_DLL */
1982 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1983 0x0000800a, /* EMC_DLL_XFORM_DQS0 */
1984 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1985 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
1986 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1987 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1988 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1989 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1990 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1991 0x0001c000, /* EMC_DLL_XFORM_QUSE0 */
1992 0x0001c000, /* EMC_DLL_XFORM_QUSE1 */
1993 0x0001c000, /* EMC_DLL_XFORM_QUSE2 */
1994 0x0001c000, /* EMC_DLL_XFORM_QUSE3 */
1995 0x0001c000, /* EMC_DLL_XFORM_QUSE4 */
1996 0x0001c000, /* EMC_DLL_XFORM_QUSE5 */
1997 0x0001c000, /* EMC_DLL_XFORM_QUSE6 */
1998 0x0001c000, /* EMC_DLL_XFORM_QUSE7 */
1999 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2000 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2001 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2002 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2003 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2004 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2005 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2006 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2007 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
2008 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2009 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2010 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2011 0x000002a0, /* EMC_XM2CMDPADCTRL */
2012 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2013 0x22220000, /* EMC_XM2DQPADCTRL2 */
2014 0x77fff884, /* EMC_XM2CLKPADCTRL */
2015 0x01f1f501, /* EMC_XM2COMPPADCTRL */
2016 0x07077404, /* EMC_XM2VTTGENPADCTRL */
2017 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2018 0x080001e8, /* EMC_XM2QUSEPADCTRL */
2019 0x07000021, /* EMC_XM2DQSPADCTRL3 */
2020 0x00000802, /* EMC_CTT_TERM_CTRL */
2021 0x00020000, /* EMC_ZCAL_INTERVAL */
2022 0x00000120, /* EMC_ZCAL_WAIT_CNT */
2023 0x0128000c, /* EMC_MRS_WAIT_CNT */
2024 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2025 0x00000000, /* EMC_CTT */
2026 0x00000000, /* EMC_CTT_DURATION */
2027 0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
2028 0x0000000d, /* MC_EMEM_ARB_CFG */
2029 0x800000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2030 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
2031 0x00000006, /* MC_EMEM_ARB_TIMING_RP */
2032 0x00000016, /* MC_EMEM_ARB_TIMING_RC */
2033 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
2034 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
2035 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2036 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2037 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2038 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2039 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2040 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
2041 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
2042 0x09050202, /* MC_EMEM_ARB_DA_TURNS */
2043 0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
2044 0x714e2917, /* MC_EMEM_ARB_MISC0 */
2045 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2046 0xe8000000, /* EMC_FBIO_SPARE */
2047 0xff00ff4b, /* EMC_CFG_RSV */
2048 },
2049 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
2050 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2051 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2052 0x80000f15, /* Mode Register 0 */
2053 0x80100002, /* Mode Register 1 */
2054 0x80200020, /* Mode Register 2 */
2055 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2056 },
2057};
2058
2059static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
2060 {
2061 0x32, /* Rev 3.2 */
2062 51000, /* SDRAM frequency */
2063 {
2064 0x00000002, /* EMC_RC */
2065 0x0000000d, /* EMC_RFC */
2066 0x00000001, /* EMC_RAS */
2067 0x00000000, /* EMC_RP */
2068 0x00000002, /* EMC_R2W */
2069 0x0000000a, /* EMC_W2R */
2070 0x00000003, /* EMC_R2P */
2071 0x0000000b, /* EMC_W2P */
2072 0x00000000, /* EMC_RD_RCD */
2073 0x00000000, /* EMC_WR_RCD */
2074 0x00000003, /* EMC_RRD */
2075 0x00000001, /* EMC_REXT */
2076 0x00000000, /* EMC_WEXT */
2077 0x00000005, /* EMC_WDV */
2078 0x00000005, /* EMC_QUSE */
2079 0x00000004, /* EMC_QRST */
2080 0x00000009, /* EMC_QSAFE */
2081 0x0000000b, /* EMC_RDV */
2082 0x00000181, /* EMC_REFRESH */
2083 0x00000000, /* EMC_BURST_REFRESH_NUM */
2084 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2085 0x00000002, /* EMC_PDEX2WR */
2086 0x00000002, /* EMC_PDEX2RD */
2087 0x00000001, /* EMC_PCHG2PDEN */
2088 0x00000000, /* EMC_ACT2PDEN */
2089 0x00000007, /* EMC_AR2PDEN */
2090 0x0000000f, /* EMC_RW2PDEN */
2091 0x0000000e, /* EMC_TXSR */
2092 0x0000000e, /* EMC_TXSRDLL */
2093 0x00000004, /* EMC_TCKE */
2094 0x00000002, /* EMC_TFAW */
2095 0x00000000, /* EMC_TRPAB */
2096 0x00000004, /* EMC_TCLKSTABLE */
2097 0x00000005, /* EMC_TCLKSTOP */
2098 0x0000018e, /* EMC_TREFBW */
2099 0x00000006, /* EMC_QUSE_EXTRA */
2100 0x00000004, /* EMC_FBIO_CFG6 */
2101 0x00000000, /* EMC_ODT_WRITE */
2102 0x00000000, /* EMC_ODT_READ */
2103 0x00004288, /* EMC_FBIO_CFG5 */
2104 0x007800a4, /* EMC_CFG_DIG_DLL */
2105 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2106 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2107 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2108 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2109 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2110 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2111 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2112 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2113 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2114 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2115 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2116 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2117 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2118 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2119 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2120 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2121 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2122 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2123 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2124 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2125 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2126 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2127 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2128 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2129 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2130 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2131 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2132 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2133 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2134 0x000002a0, /* EMC_XM2CMDPADCTRL */
2135 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2136 0x00000000, /* EMC_XM2DQPADCTRL2 */
2137 0x77fff884, /* EMC_XM2CLKPADCTRL */
2138 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2139 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2140 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2141 0x08000168, /* EMC_XM2QUSEPADCTRL */
2142 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2143 0x00000802, /* EMC_CTT_TERM_CTRL */
2144 0x00000000, /* EMC_ZCAL_INTERVAL */
2145 0x00000040, /* EMC_ZCAL_WAIT_CNT */
2146 0x000c000c, /* EMC_MRS_WAIT_CNT */
2147 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2148 0x00000000, /* EMC_CTT */
2149 0x00000000, /* EMC_CTT_DURATION */
2150 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
2151 0x00010001, /* MC_EMEM_ARB_CFG */
2152 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2153 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2154 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2155 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2156 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2157 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2158 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2159 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2160 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2161 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2162 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2163 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2164 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2165 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2166 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2167 0x74630303, /* MC_EMEM_ARB_MISC0 */
2168 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2169 0xe8000000, /* EMC_FBIO_SPARE */
2170 0xff00ff00, /* EMC_CFG_RSV */
2171 },
2172 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2173 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2174 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2175 0x80001221, /* Mode Register 0 */
2176 0x80100003, /* Mode Register 1 */
2177 0x80200008, /* Mode Register 2 */
2178 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2179 },
2180 {
2181 0x32, /* Rev 3.2 */
2182 102000, /* SDRAM frequency */
2183 {
2184 0x00000004, /* EMC_RC */
2185 0x0000001a, /* EMC_RFC */
2186 0x00000003, /* EMC_RAS */
2187 0x00000001, /* EMC_RP */
2188 0x00000002, /* EMC_R2W */
2189 0x0000000a, /* EMC_W2R */
2190 0x00000003, /* EMC_R2P */
2191 0x0000000b, /* EMC_W2P */
2192 0x00000001, /* EMC_RD_RCD */
2193 0x00000001, /* EMC_WR_RCD */
2194 0x00000003, /* EMC_RRD */
2195 0x00000001, /* EMC_REXT */
2196 0x00000000, /* EMC_WEXT */
2197 0x00000005, /* EMC_WDV */
2198 0x00000005, /* EMC_QUSE */
2199 0x00000004, /* EMC_QRST */
2200 0x00000009, /* EMC_QSAFE */
2201 0x0000000b, /* EMC_RDV */
2202 0x00000303, /* EMC_REFRESH */
2203 0x00000000, /* EMC_BURST_REFRESH_NUM */
2204 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
2205 0x00000002, /* EMC_PDEX2WR */
2206 0x00000002, /* EMC_PDEX2RD */
2207 0x00000001, /* EMC_PCHG2PDEN */
2208 0x00000000, /* EMC_ACT2PDEN */
2209 0x00000007, /* EMC_AR2PDEN */
2210 0x0000000f, /* EMC_RW2PDEN */
2211 0x0000001c, /* EMC_TXSR */
2212 0x0000001c, /* EMC_TXSRDLL */
2213 0x00000004, /* EMC_TCKE */
2214 0x00000004, /* EMC_TFAW */
2215 0x00000000, /* EMC_TRPAB */
2216 0x00000004, /* EMC_TCLKSTABLE */
2217 0x00000005, /* EMC_TCLKSTOP */
2218 0x0000031c, /* EMC_TREFBW */
2219 0x00000006, /* EMC_QUSE_EXTRA */
2220 0x00000004, /* EMC_FBIO_CFG6 */
2221 0x00000000, /* EMC_ODT_WRITE */
2222 0x00000000, /* EMC_ODT_READ */
2223 0x00004288, /* EMC_FBIO_CFG5 */
2224 0x007800a4, /* EMC_CFG_DIG_DLL */
2225 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2226 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2227 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2228 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2229 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2230 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2231 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2232 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2233 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2234 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2235 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2236 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2237 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2238 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2239 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2240 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2241 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2242 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2243 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2244 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2245 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2246 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2247 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2248 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2249 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2250 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2251 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2252 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2253 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2254 0x000002a0, /* EMC_XM2CMDPADCTRL */
2255 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2256 0x00000000, /* EMC_XM2DQPADCTRL2 */
2257 0x77fff884, /* EMC_XM2CLKPADCTRL */
2258 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2259 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2260 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2261 0x08000168, /* EMC_XM2QUSEPADCTRL */
2262 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2263 0x00000802, /* EMC_CTT_TERM_CTRL */
2264 0x00000000, /* EMC_ZCAL_INTERVAL */
2265 0x00000040, /* EMC_ZCAL_WAIT_CNT */
2266 0x000c000c, /* EMC_MRS_WAIT_CNT */
2267 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2268 0x00000000, /* EMC_CTT */
2269 0x00000000, /* EMC_CTT_DURATION */
2270 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
2271 0x00000001, /* MC_EMEM_ARB_CFG */
2272 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2273 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2274 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2275 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
2276 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2277 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2278 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2279 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2280 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2281 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2282 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2283 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2284 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2285 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2286 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
2287 0x73c30504, /* MC_EMEM_ARB_MISC0 */
2288 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2289 0xe8000000, /* EMC_FBIO_SPARE */
2290 0xff00ff00, /* EMC_CFG_RSV */
2291 },
2292 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2293 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2294 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2295 0x80001221, /* Mode Register 0 */
2296 0x80100003, /* Mode Register 1 */
2297 0x80200008, /* Mode Register 2 */
2298 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2299 },
2300 {
2301 0x32, /* Rev 3.2 */
2302 204000, /* SDRAM frequency */
2303 {
2304 0x00000009, /* EMC_RC */
2305 0x00000035, /* EMC_RFC */
2306 0x00000007, /* EMC_RAS */
2307 0x00000002, /* EMC_RP */
2308 0x00000002, /* EMC_R2W */
2309 0x0000000a, /* EMC_W2R */
2310 0x00000003, /* EMC_R2P */
2311 0x0000000b, /* EMC_W2P */
2312 0x00000002, /* EMC_RD_RCD */
2313 0x00000002, /* EMC_WR_RCD */
2314 0x00000003, /* EMC_RRD */
2315 0x00000001, /* EMC_REXT */
2316 0x00000000, /* EMC_WEXT */
2317 0x00000005, /* EMC_WDV */
2318 0x00000005, /* EMC_QUSE */
2319 0x00000004, /* EMC_QRST */
2320 0x00000009, /* EMC_QSAFE */
2321 0x0000000b, /* EMC_RDV */
2322 0x00000607, /* EMC_REFRESH */
2323 0x00000000, /* EMC_BURST_REFRESH_NUM */
2324 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
2325 0x00000002, /* EMC_PDEX2WR */
2326 0x00000002, /* EMC_PDEX2RD */
2327 0x00000001, /* EMC_PCHG2PDEN */
2328 0x00000000, /* EMC_ACT2PDEN */
2329 0x00000007, /* EMC_AR2PDEN */
2330 0x0000000f, /* EMC_RW2PDEN */
2331 0x00000038, /* EMC_TXSR */
2332 0x00000038, /* EMC_TXSRDLL */
2333 0x00000004, /* EMC_TCKE */
2334 0x00000007, /* EMC_TFAW */
2335 0x00000000, /* EMC_TRPAB */
2336 0x00000004, /* EMC_TCLKSTABLE */
2337 0x00000005, /* EMC_TCLKSTOP */
2338 0x00000638, /* EMC_TREFBW */
2339 0x00000006, /* EMC_QUSE_EXTRA */
2340 0x00000004, /* EMC_FBIO_CFG6 */
2341 0x00000000, /* EMC_ODT_WRITE */
2342 0x00000000, /* EMC_ODT_READ */
2343 0x00004288, /* EMC_FBIO_CFG5 */
2344 0x004400a4, /* EMC_CFG_DIG_DLL */
2345 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2346 0x00080000, /* EMC_DLL_XFORM_DQS0 */
2347 0x00080000, /* EMC_DLL_XFORM_DQS1 */
2348 0x00080000, /* EMC_DLL_XFORM_DQS2 */
2349 0x00080000, /* EMC_DLL_XFORM_DQS3 */
2350 0x00080000, /* EMC_DLL_XFORM_DQS4 */
2351 0x00080000, /* EMC_DLL_XFORM_DQS5 */
2352 0x00080000, /* EMC_DLL_XFORM_DQS6 */
2353 0x00080000, /* EMC_DLL_XFORM_DQS7 */
2354 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2355 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2356 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2357 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2358 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2359 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2360 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2361 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2362 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2363 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2364 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2365 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2366 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2367 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2368 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2369 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2370 0x00080000, /* EMC_DLL_XFORM_DQ0 */
2371 0x00080000, /* EMC_DLL_XFORM_DQ1 */
2372 0x00080000, /* EMC_DLL_XFORM_DQ2 */
2373 0x00080000, /* EMC_DLL_XFORM_DQ3 */
2374 0x000002a0, /* EMC_XM2CMDPADCTRL */
2375 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2376 0x00000000, /* EMC_XM2DQPADCTRL2 */
2377 0x77fff884, /* EMC_XM2CLKPADCTRL */
2378 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2379 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2380 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2381 0x08000168, /* EMC_XM2QUSEPADCTRL */
2382 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2383 0x00000802, /* EMC_CTT_TERM_CTRL */
2384 0x00020000, /* EMC_ZCAL_INTERVAL */
2385 0x00000100, /* EMC_ZCAL_WAIT_CNT */
2386 0x000c000c, /* EMC_MRS_WAIT_CNT */
2387 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2388 0x00000000, /* EMC_CTT */
2389 0x00000000, /* EMC_CTT_DURATION */
2390 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
2391 0x00000003, /* MC_EMEM_ARB_CFG */
2392 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2393 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2394 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2395 0x00000005, /* MC_EMEM_ARB_TIMING_RC */
2396 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
2397 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2398 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2399 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2400 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2401 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2402 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2403 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2404 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2405 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2406 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
2407 0x73840a06, /* MC_EMEM_ARB_MISC0 */
2408 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2409 0xe8000000, /* EMC_FBIO_SPARE */
2410 0xff00ff00, /* EMC_CFG_RSV */
2411 },
2412 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2413 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2414 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2415 0x80001221, /* Mode Register 0 */
2416 0x80100003, /* Mode Register 1 */
2417 0x80200008, /* Mode Register 2 */
2418 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2419 },
2420 {
2421 0x32, /* Rev 3.2 */
2422 375000, /* SDRAM frequency */
2423 {
2424 0x00000011, /* EMC_RC */
2425 0x0000006f, /* EMC_RFC */
2426 0x0000000c, /* EMC_RAS */
2427 0x00000004, /* EMC_RP */
2428 0x00000003, /* EMC_R2W */
2429 0x00000008, /* EMC_W2R */
2430 0x00000002, /* EMC_R2P */
2431 0x0000000a, /* EMC_W2P */
2432 0x00000004, /* EMC_RD_RCD */
2433 0x00000004, /* EMC_WR_RCD */
2434 0x00000002, /* EMC_RRD */
2435 0x00000001, /* EMC_REXT */
2436 0x00000000, /* EMC_WEXT */
2437 0x00000004, /* EMC_WDV */
2438 0x00000006, /* EMC_QUSE */
2439 0x00000004, /* EMC_QRST */
2440 0x0000000a, /* EMC_QSAFE */
2441 0x0000000d, /* EMC_RDV */
2442 0x00000b2d, /* EMC_REFRESH */
2443 0x00000000, /* EMC_BURST_REFRESH_NUM */
2444 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
2445 0x00000001, /* EMC_PDEX2WR */
2446 0x00000008, /* EMC_PDEX2RD */
2447 0x00000001, /* EMC_PCHG2PDEN */
2448 0x00000000, /* EMC_ACT2PDEN */
2449 0x00000007, /* EMC_AR2PDEN */
2450 0x0000000f, /* EMC_RW2PDEN */
2451 0x00000075, /* EMC_TXSR */
2452 0x00000200, /* EMC_TXSRDLL */
2453 0x00000004, /* EMC_TCKE */
2454 0x0000000c, /* EMC_TFAW */
2455 0x00000000, /* EMC_TRPAB */
2456 0x00000004, /* EMC_TCLKSTABLE */
2457 0x00000005, /* EMC_TCLKSTOP */
2458 0x00000b6d, /* EMC_TREFBW */
2459 0x00000000, /* EMC_QUSE_EXTRA */
2460 0x00000006, /* EMC_FBIO_CFG6 */
2461 0x00000000, /* EMC_ODT_WRITE */
2462 0x00000000, /* EMC_ODT_READ */
2463 0x00007088, /* EMC_FBIO_CFG5 */
2464 0x00200084, /* EMC_CFG_DIG_DLL */
2465 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2466 0x0003c000, /* EMC_DLL_XFORM_DQS0 */
2467 0x0003c000, /* EMC_DLL_XFORM_DQS1 */
2468 0x0003c000, /* EMC_DLL_XFORM_DQS2 */
2469 0x0003c000, /* EMC_DLL_XFORM_DQS3 */
2470 0x0003c000, /* EMC_DLL_XFORM_DQS4 */
2471 0x0003c000, /* EMC_DLL_XFORM_DQS5 */
2472 0x0003c000, /* EMC_DLL_XFORM_DQS6 */
2473 0x0003c000, /* EMC_DLL_XFORM_DQS7 */
2474 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2475 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2476 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2477 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2478 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2479 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2480 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2481 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2482 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2483 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2484 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2485 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2486 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2487 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2488 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2489 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2490 0x00040000, /* EMC_DLL_XFORM_DQ0 */
2491 0x00040000, /* EMC_DLL_XFORM_DQ1 */
2492 0x00040000, /* EMC_DLL_XFORM_DQ2 */
2493 0x00040000, /* EMC_DLL_XFORM_DQ3 */
2494 0x000002a0, /* EMC_XM2CMDPADCTRL */
2495 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
2496 0x00000000, /* EMC_XM2DQPADCTRL2 */
2497 0x77fff884, /* EMC_XM2CLKPADCTRL */
2498 0x01f1f508, /* EMC_XM2COMPPADCTRL */
2499 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2500 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2501 0x080001e8, /* EMC_XM2QUSEPADCTRL */
2502 0x08000021, /* EMC_XM2DQSPADCTRL3 */
2503 0x00000802, /* EMC_CTT_TERM_CTRL */
2504 0x00020000, /* EMC_ZCAL_INTERVAL */
2505 0x00000100, /* EMC_ZCAL_WAIT_CNT */
2506 0x0150000c, /* EMC_MRS_WAIT_CNT */
2507 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2508 0x00000000, /* EMC_CTT */
2509 0x00000000, /* EMC_CTT_DURATION */
2510 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
2511 0x00000005, /* MC_EMEM_ARB_CFG */
2512 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2513 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2514 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
2515 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
2516 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
2517 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
2518 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2519 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2520 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2521 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2522 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2523 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2524 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2525 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
2526 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
2527 0x75c6110a, /* MC_EMEM_ARB_MISC0 */
2528 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2529 0x58000000, /* EMC_FBIO_SPARE */
2530 0xff00ff88, /* EMC_CFG_RSV */
2531 },
2532 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2533 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2534 0x00000000, /* EMC_CFG.PERIODIC_QRST */
2535 0x80000521, /* Mode Register 0 */
2536 0x80100002, /* Mode Register 1 */
2537 0x80200000, /* Mode Register 2 */
2538 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2539 },
2540 {
2541 0x32, /* Rev 3.2 */
2542 750000, /* SDRAM frequency */
2543 {
2544 0x00000023, /* EMC_RC */
2545 0x000000df, /* EMC_RFC */
2546 0x00000019, /* EMC_RAS */
2547 0x00000009, /* EMC_RP */
2548 0x00000005, /* EMC_R2W */
2549 0x0000000d, /* EMC_W2R */
2550 0x00000004, /* EMC_R2P */
2551 0x00000013, /* EMC_W2P */
2552 0x00000009, /* EMC_RD_RCD */
2553 0x00000009, /* EMC_WR_RCD */
2554 0x00000003, /* EMC_RRD */
2555 0x00000001, /* EMC_REXT */
2556 0x00000000, /* EMC_WEXT */
2557 0x00000007, /* EMC_WDV */
2558 0x0000000b, /* EMC_QUSE */
2559 0x00000009, /* EMC_QRST */
2560 0x0000000c, /* EMC_QSAFE */
2561 0x00000011, /* EMC_RDV */
2562 0x0000169a, /* EMC_REFRESH */
2563 0x00000000, /* EMC_BURST_REFRESH_NUM */
2564 0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
2565 0x00000003, /* EMC_PDEX2WR */
2566 0x00000010, /* EMC_PDEX2RD */
2567 0x00000001, /* EMC_PCHG2PDEN */
2568 0x00000000, /* EMC_ACT2PDEN */
2569 0x0000000e, /* EMC_AR2PDEN */
2570 0x00000018, /* EMC_RW2PDEN */
2571 0x000000e9, /* EMC_TXSR */
2572 0x00000200, /* EMC_TXSRDLL */
2573 0x00000005, /* EMC_TCKE */
2574 0x00000017, /* EMC_TFAW */
2575 0x00000000, /* EMC_TRPAB */
2576 0x00000007, /* EMC_TCLKSTABLE */
2577 0x00000008, /* EMC_TCLKSTOP */
2578 0x000016da, /* EMC_TREFBW */
2579 0x0000000c, /* EMC_QUSE_EXTRA */
2580 0x00000004, /* EMC_FBIO_CFG6 */
2581 0x00000000, /* EMC_ODT_WRITE */
2582 0x00000000, /* EMC_ODT_READ */
2583 0x00005088, /* EMC_FBIO_CFG5 */
2584 0xf0080191, /* EMC_CFG_DIG_DLL */
2585 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2586 0x00000008, /* EMC_DLL_XFORM_DQS0 */
2587 0x00000008, /* EMC_DLL_XFORM_DQS1 */
2588 0x00000008, /* EMC_DLL_XFORM_DQS2 */
2589 0x00000008, /* EMC_DLL_XFORM_DQS3 */
2590 0x00000008, /* EMC_DLL_XFORM_DQS4 */
2591 0x00000008, /* EMC_DLL_XFORM_DQS5 */
2592 0x00000008, /* EMC_DLL_XFORM_DQS6 */
2593 0x00000008, /* EMC_DLL_XFORM_DQS7 */
2594 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2595 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2596 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2597 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2598 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2599 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2600 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2601 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2602 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2603 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2604 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2605 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2606 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2607 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2608 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2609 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2610 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
2611 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
2612 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
2613 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
2614 0x000002a0, /* EMC_XM2CMDPADCTRL */
2615 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2616 0x22220000, /* EMC_XM2DQPADCTRL2 */
2617 0x77fff884, /* EMC_XM2CLKPADCTRL */
2618 0x01f1f501, /* EMC_XM2COMPPADCTRL */
2619 0x07077404, /* EMC_XM2VTTGENPADCTRL */
2620 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2621 0x080001e8, /* EMC_XM2QUSEPADCTRL */
2622 0x07000021, /* EMC_XM2DQSPADCTRL3 */
2623 0x00000802, /* EMC_CTT_TERM_CTRL */
2624 0x00020000, /* EMC_ZCAL_INTERVAL */
2625 0x00000100, /* EMC_ZCAL_WAIT_CNT */
2626 0x00df000c, /* EMC_MRS_WAIT_CNT */
2627 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2628 0x00000000, /* EMC_CTT */
2629 0x00000000, /* EMC_CTT_DURATION */
2630 0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
2631 0x0000000b, /* MC_EMEM_ARB_CFG */
2632 0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2633 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2634 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2635 0x00000012, /* MC_EMEM_ARB_TIMING_RC */
2636 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2637 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
2638 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2639 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2640 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2641 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2642 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2643 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2644 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2645 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
2646 0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
2647 0x73cc2213, /* MC_EMEM_ARB_MISC0 */
2648 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2649 0xf8000000, /* EMC_FBIO_SPARE */
2650 0xff00ff49, /* EMC_CFG_RSV */
2651 },
2652 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2653 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2654 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2655 0x80000d71, /* Mode Register 0 */
2656 0x80100002, /* Mode Register 1 */
2657 0x80200018, /* Mode Register 2 */
2658 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2659 },
2660};
2661
2662static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
2663 {
2664 0x32, /* Rev 3.2 */
2665 25500, /* SDRAM frequency */
2666 {
2667 0x00000001, /* EMC_RC */
2668 0x00000006, /* EMC_RFC */
2669 0x00000000, /* EMC_RAS */
2670 0x00000000, /* EMC_RP */
2671 0x00000002, /* EMC_R2W */
2672 0x0000000a, /* EMC_W2R */
2673 0x00000005, /* EMC_R2P */
2674 0x0000000b, /* EMC_W2P */
2675 0x00000000, /* EMC_RD_RCD */
2676 0x00000000, /* EMC_WR_RCD */
2677 0x00000003, /* EMC_RRD */
2678 0x00000001, /* EMC_REXT */
2679 0x00000000, /* EMC_WEXT */
2680 0x00000005, /* EMC_WDV */
2681 0x00000005, /* EMC_QUSE */
2682 0x00000004, /* EMC_QRST */
2683 0x00000009, /* EMC_QSAFE */
2684 0x0000000b, /* EMC_RDV */
2685 0x000000c0, /* EMC_REFRESH */
2686 0x00000000, /* EMC_BURST_REFRESH_NUM */
2687 0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
2688 0x00000002, /* EMC_PDEX2WR */
2689 0x00000002, /* EMC_PDEX2RD */
2690 0x00000001, /* EMC_PCHG2PDEN */
2691 0x00000000, /* EMC_ACT2PDEN */
2692 0x00000007, /* EMC_AR2PDEN */
2693 0x0000000f, /* EMC_RW2PDEN */
2694 0x00000007, /* EMC_TXSR */
2695 0x00000007, /* EMC_TXSRDLL */
2696 0x00000004, /* EMC_TCKE */
2697 0x00000001, /* EMC_TFAW */
2698 0x00000000, /* EMC_TRPAB */
2699 0x00000004, /* EMC_TCLKSTABLE */
2700 0x00000005, /* EMC_TCLKSTOP */
2701 0x000000c7, /* EMC_TREFBW */
2702 0x00000006, /* EMC_QUSE_EXTRA */
2703 0x00000004, /* EMC_FBIO_CFG6 */
2704 0x00000000, /* EMC_ODT_WRITE */
2705 0x00000000, /* EMC_ODT_READ */
2706 0x00004288, /* EMC_FBIO_CFG5 */
2707 0x007800a4, /* EMC_CFG_DIG_DLL */
2708 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2709 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2710 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2711 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2712 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2713 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2714 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2715 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2716 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2717 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2718 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2719 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2720 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2721 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2722 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2723 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2724 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2725 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2726 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2727 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2728 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2729 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2730 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2731 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2732 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2733 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2734 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2735 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2736 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2737 0x000002a0, /* EMC_XM2CMDPADCTRL */
2738 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2739 0x00000000, /* EMC_XM2DQPADCTRL2 */
2740 0x77fff884, /* EMC_XM2CLKPADCTRL */
2741 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2742 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2743 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2744 0x08000168, /* EMC_XM2QUSEPADCTRL */
2745 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2746 0x00000802, /* EMC_CTT_TERM_CTRL */
2747 0x00000000, /* EMC_ZCAL_INTERVAL */
2748 0x00000040, /* EMC_ZCAL_WAIT_CNT */
2749 0x000c000c, /* EMC_MRS_WAIT_CNT */
2750 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2751 0x00000000, /* EMC_CTT */
2752 0x00000000, /* EMC_CTT_DURATION */
2753 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
2754 0x00020001, /* MC_EMEM_ARB_CFG */
2755 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2756 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2757 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2758 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2759 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2760 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2761 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2762 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2763 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2764 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2765 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2766 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2767 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2768 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2769 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2770 0x75830303, /* MC_EMEM_ARB_MISC0 */
2771 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2772 0xe8000000, /* EMC_FBIO_SPARE */
2773 0xff00ff00, /* EMC_CFG_RSV */
2774 },
2775 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2776 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2777 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2778 0x80001221, /* Mode Register 0 */
2779 0x80100003, /* Mode Register 1 */
2780 0x80200008, /* Mode Register 2 */
2781 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2782 },
2783 {
2784 0x32, /* Rev 3.2 */
2785 51000, /* SDRAM frequency */
2786 {
2787 0x00000002, /* EMC_RC */
2788 0x0000000d, /* EMC_RFC */
2789 0x00000001, /* EMC_RAS */
2790 0x00000000, /* EMC_RP */
2791 0x00000002, /* EMC_R2W */
2792 0x0000000a, /* EMC_W2R */
2793 0x00000005, /* EMC_R2P */
2794 0x0000000b, /* EMC_W2P */
2795 0x00000000, /* EMC_RD_RCD */
2796 0x00000000, /* EMC_WR_RCD */
2797 0x00000003, /* EMC_RRD */
2798 0x00000001, /* EMC_REXT */
2799 0x00000000, /* EMC_WEXT */
2800 0x00000005, /* EMC_WDV */
2801 0x00000005, /* EMC_QUSE */
2802 0x00000004, /* EMC_QRST */
2803 0x00000009, /* EMC_QSAFE */
2804 0x0000000b, /* EMC_RDV */
2805 0x00000181, /* EMC_REFRESH */
2806 0x00000000, /* EMC_BURST_REFRESH_NUM */
2807 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2808 0x00000002, /* EMC_PDEX2WR */
2809 0x00000002, /* EMC_PDEX2RD */
2810 0x00000001, /* EMC_PCHG2PDEN */
2811 0x00000000, /* EMC_ACT2PDEN */
2812 0x00000007, /* EMC_AR2PDEN */
2813 0x0000000f, /* EMC_RW2PDEN */
2814 0x0000000e, /* EMC_TXSR */
2815 0x0000000e, /* EMC_TXSRDLL */
2816 0x00000004, /* EMC_TCKE */
2817 0x00000002, /* EMC_TFAW */
2818 0x00000000, /* EMC_TRPAB */
2819 0x00000004, /* EMC_TCLKSTABLE */
2820 0x00000005, /* EMC_TCLKSTOP */
2821 0x0000018e, /* EMC_TREFBW */
2822 0x00000006, /* EMC_QUSE_EXTRA */
2823 0x00000004, /* EMC_FBIO_CFG6 */
2824 0x00000000, /* EMC_ODT_WRITE */
2825 0x00000000, /* EMC_ODT_READ */
2826 0x00004288, /* EMC_FBIO_CFG5 */
2827 0x007800a4, /* EMC_CFG_DIG_DLL */
2828 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2829 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2830 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2831 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2832 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2833 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2834 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2835 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2836 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2837 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2838 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2839 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2840 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2841 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2842 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2843 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2844 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2845 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2846 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2847 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2848 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2849 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2850 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2851 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2852 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2853 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2854 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2855 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2856 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2857 0x000002a0, /* EMC_XM2CMDPADCTRL */
2858 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2859 0x00000000, /* EMC_XM2DQPADCTRL2 */
2860 0x77fff884, /* EMC_XM2CLKPADCTRL */
2861 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2862 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2863 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2864 0x08000168, /* EMC_XM2QUSEPADCTRL */
2865 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2866 0x00000802, /* EMC_CTT_TERM_CTRL */
2867 0x00000000, /* EMC_ZCAL_INTERVAL */
2868 0x00000040, /* EMC_ZCAL_WAIT_CNT */
2869 0x000c000c, /* EMC_MRS_WAIT_CNT */
2870 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2871 0x00000000, /* EMC_CTT */
2872 0x00000000, /* EMC_CTT_DURATION */
2873 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
2874 0x00010001, /* MC_EMEM_ARB_CFG */
2875 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2876 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2877 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2878 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2879 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2880 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2881 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2882 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2883 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2884 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2885 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2886 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2887 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2888 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2889 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2890 0x74630303, /* MC_EMEM_ARB_MISC0 */
2891 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2892 0xe8000000, /* EMC_FBIO_SPARE */
2893 0xff00ff00, /* EMC_CFG_RSV */
2894 },
2895 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2896 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2897 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2898 0x80001221, /* Mode Register 0 */
2899 0x80100003, /* Mode Register 1 */
2900 0x80200008, /* Mode Register 2 */
2901 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2902 },
2903 {
2904 0x32, /* Rev 3.2 */
2905 102000, /* SDRAM frequency */
2906 {
2907 0x00000004, /* EMC_RC */
2908 0x0000001a, /* EMC_RFC */
2909 0x00000003, /* EMC_RAS */
2910 0x00000001, /* EMC_RP */
2911 0x00000002, /* EMC_R2W */
2912 0x0000000a, /* EMC_W2R */
2913 0x00000005, /* EMC_R2P */
2914 0x0000000b, /* EMC_W2P */
2915 0x00000001, /* EMC_RD_RCD */
2916 0x00000001, /* EMC_WR_RCD */
2917 0x00000003, /* EMC_RRD */
2918 0x00000001, /* EMC_REXT */
2919 0x00000000, /* EMC_WEXT */
2920 0x00000005, /* EMC_WDV */
2921 0x00000005, /* EMC_QUSE */
2922 0x00000004, /* EMC_QRST */
2923 0x00000009, /* EMC_QSAFE */
2924 0x0000000b, /* EMC_RDV */
2925 0x00000303, /* EMC_REFRESH */
2926 0x00000000, /* EMC_BURST_REFRESH_NUM */
2927 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
2928 0x00000002, /* EMC_PDEX2WR */
2929 0x00000002, /* EMC_PDEX2RD */
2930 0x00000001, /* EMC_PCHG2PDEN */
2931 0x00000000, /* EMC_ACT2PDEN */
2932 0x00000007, /* EMC_AR2PDEN */
2933 0x0000000f, /* EMC_RW2PDEN */
2934 0x0000001c, /* EMC_TXSR */
2935 0x0000001c, /* EMC_TXSRDLL */
2936 0x00000004, /* EMC_TCKE */
2937 0x00000004, /* EMC_TFAW */
2938 0x00000000, /* EMC_TRPAB */
2939 0x00000004, /* EMC_TCLKSTABLE */
2940 0x00000005, /* EMC_TCLKSTOP */
2941 0x0000031c, /* EMC_TREFBW */
2942 0x00000006, /* EMC_QUSE_EXTRA */
2943 0x00000004, /* EMC_FBIO_CFG6 */
2944 0x00000000, /* EMC_ODT_WRITE */
2945 0x00000000, /* EMC_ODT_READ */
2946 0x00004288, /* EMC_FBIO_CFG5 */
2947 0x007800a4, /* EMC_CFG_DIG_DLL */
2948 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2949 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2950 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2951 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2952 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2953 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2954 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2955 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2956 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2957 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2958 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2959 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2960 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2961 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2962 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2963 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2964 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2965 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2966 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2967 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2968 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2969 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2970 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2971 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2972 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2973 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2974 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2975 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2976 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2977 0x000002a0, /* EMC_XM2CMDPADCTRL */
2978 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2979 0x00000000, /* EMC_XM2DQPADCTRL2 */
2980 0x77fff884, /* EMC_XM2CLKPADCTRL */
2981 0x01f1f108, /* EMC_XM2COMPPADCTRL */
2982 0x05057404, /* EMC_XM2VTTGENPADCTRL */
2983 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2984 0x08000168, /* EMC_XM2QUSEPADCTRL */
2985 0x08000000, /* EMC_XM2DQSPADCTRL3 */
2986 0x00000802, /* EMC_CTT_TERM_CTRL */
2987 0x00000000, /* EMC_ZCAL_INTERVAL */
2988 0x00000040, /* EMC_ZCAL_WAIT_CNT */
2989 0x000c000c, /* EMC_MRS_WAIT_CNT */
2990 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2991 0x00000000, /* EMC_CTT */
2992 0x00000000, /* EMC_CTT_DURATION */
2993 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
2994 0x00000001, /* MC_EMEM_ARB_CFG */
2995 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2996 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2997 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2998 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
2999 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3000 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
3001 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3002 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3003 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3004 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3005 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3006 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3007 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3008 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3009 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
3010 0x73c30504, /* MC_EMEM_ARB_MISC0 */
3011 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3012 0xe8000000, /* EMC_FBIO_SPARE */
3013 0xff00ff00, /* EMC_CFG_RSV */
3014 },
3015 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3016 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3017 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3018 0x80001221, /* Mode Register 0 */
3019 0x80100003, /* Mode Register 1 */
3020 0x80200008, /* Mode Register 2 */
3021 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3022 },
3023 {
3024 0x32, /* Rev 3.2 */
3025 204000, /* SDRAM frequency */
3026 {
3027 0x00000009, /* EMC_RC */
3028 0x00000035, /* EMC_RFC */
3029 0x00000007, /* EMC_RAS */
3030 0x00000002, /* EMC_RP */
3031 0x00000002, /* EMC_R2W */
3032 0x0000000a, /* EMC_W2R */
3033 0x00000005, /* EMC_R2P */
3034 0x0000000b, /* EMC_W2P */
3035 0x00000002, /* EMC_RD_RCD */
3036 0x00000002, /* EMC_WR_RCD */
3037 0x00000003, /* EMC_RRD */
3038 0x00000001, /* EMC_REXT */
3039 0x00000000, /* EMC_WEXT */
3040 0x00000005, /* EMC_WDV */
3041 0x00000005, /* EMC_QUSE */
3042 0x00000004, /* EMC_QRST */
3043 0x00000009, /* EMC_QSAFE */
3044 0x0000000b, /* EMC_RDV */
3045 0x00000607, /* EMC_REFRESH */
3046 0x00000000, /* EMC_BURST_REFRESH_NUM */
3047 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
3048 0x00000002, /* EMC_PDEX2WR */
3049 0x00000002, /* EMC_PDEX2RD */
3050 0x00000001, /* EMC_PCHG2PDEN */
3051 0x00000000, /* EMC_ACT2PDEN */
3052 0x00000007, /* EMC_AR2PDEN */
3053 0x0000000f, /* EMC_RW2PDEN */
3054 0x00000038, /* EMC_TXSR */
3055 0x00000038, /* EMC_TXSRDLL */
3056 0x00000004, /* EMC_TCKE */
3057 0x00000007, /* EMC_TFAW */
3058 0x00000000, /* EMC_TRPAB */
3059 0x00000004, /* EMC_TCLKSTABLE */
3060 0x00000005, /* EMC_TCLKSTOP */
3061 0x00000638, /* EMC_TREFBW */
3062 0x00000006, /* EMC_QUSE_EXTRA */
3063 0x00000004, /* EMC_FBIO_CFG6 */
3064 0x00000000, /* EMC_ODT_WRITE */
3065 0x00000000, /* EMC_ODT_READ */
3066 0x00004288, /* EMC_FBIO_CFG5 */
3067 0x004400a4, /* EMC_CFG_DIG_DLL */
3068 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3069 0x00080000, /* EMC_DLL_XFORM_DQS0 */
3070 0x00080000, /* EMC_DLL_XFORM_DQS1 */
3071 0x00080000, /* EMC_DLL_XFORM_DQS2 */
3072 0x00080000, /* EMC_DLL_XFORM_DQS3 */
3073 0x00080000, /* EMC_DLL_XFORM_DQS4 */
3074 0x00080000, /* EMC_DLL_XFORM_DQS5 */
3075 0x00080000, /* EMC_DLL_XFORM_DQS6 */
3076 0x00080000, /* EMC_DLL_XFORM_DQS7 */
3077 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3078 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3079 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3080 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3081 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3082 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3083 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3084 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3085 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3086 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3087 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3088 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3089 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3090 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3091 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3092 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3093 0x00080000, /* EMC_DLL_XFORM_DQ0 */
3094 0x00080000, /* EMC_DLL_XFORM_DQ1 */
3095 0x00080000, /* EMC_DLL_XFORM_DQ2 */
3096 0x00080000, /* EMC_DLL_XFORM_DQ3 */
3097 0x000002a0, /* EMC_XM2CMDPADCTRL */
3098 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
3099 0x00000000, /* EMC_XM2DQPADCTRL2 */
3100 0x77fff884, /* EMC_XM2CLKPADCTRL */
3101 0x01f1f108, /* EMC_XM2COMPPADCTRL */
3102 0x05057404, /* EMC_XM2VTTGENPADCTRL */
3103 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3104 0x08000168, /* EMC_XM2QUSEPADCTRL */
3105 0x08000000, /* EMC_XM2DQSPADCTRL3 */
3106 0x00000802, /* EMC_CTT_TERM_CTRL */
3107 0x00020000, /* EMC_ZCAL_INTERVAL */
3108 0x00000100, /* EMC_ZCAL_WAIT_CNT */
3109 0x000c000c, /* EMC_MRS_WAIT_CNT */
3110 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3111 0x00000000, /* EMC_CTT */
3112 0x00000000, /* EMC_CTT_DURATION */
3113 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
3114 0x00000003, /* MC_EMEM_ARB_CFG */
3115 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3116 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3117 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3118 0x00000005, /* MC_EMEM_ARB_TIMING_RC */
3119 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
3120 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3121 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3122 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3123 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3124 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3125 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3126 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3127 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3128 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3129 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
3130 0x73840a06, /* MC_EMEM_ARB_MISC0 */
3131 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3132 0xe8000000, /* EMC_FBIO_SPARE */
3133 0xff00ff00, /* EMC_CFG_RSV */
3134 },
3135 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3136 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3137 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3138 0x80001221, /* Mode Register 0 */
3139 0x80100003, /* Mode Register 1 */
3140 0x80200008, /* Mode Register 2 */
3141 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3142 },
3143 {
3144 0x32, /* Rev 3.2 */
3145 375000, /* SDRAM frequency */
3146 {
3147 0x00000011, /* EMC_RC */
3148 0x00000060, /* EMC_RFC */
3149 0x0000000c, /* EMC_RAS */
3150 0x00000004, /* EMC_RP */
3151 0x00000003, /* EMC_R2W */
3152 0x00000008, /* EMC_W2R */
3153 0x00000002, /* EMC_R2P */
3154 0x0000000a, /* EMC_W2P */
3155 0x00000004, /* EMC_RD_RCD */
3156 0x00000004, /* EMC_WR_RCD */
3157 0x00000002, /* EMC_RRD */
3158 0x00000001, /* EMC_REXT */
3159 0x00000000, /* EMC_WEXT */
3160 0x00000004, /* EMC_WDV */
3161 0x00000006, /* EMC_QUSE */
3162 0x00000004, /* EMC_QRST */
3163 0x0000000a, /* EMC_QSAFE */
3164 0x0000000d, /* EMC_RDV */
3165 0x00000b2d, /* EMC_REFRESH */
3166 0x00000000, /* EMC_BURST_REFRESH_NUM */
3167 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
3168 0x00000001, /* EMC_PDEX2WR */
3169 0x00000008, /* EMC_PDEX2RD */
3170 0x00000001, /* EMC_PCHG2PDEN */
3171 0x00000000, /* EMC_ACT2PDEN */
3172 0x00000007, /* EMC_AR2PDEN */
3173 0x0000000f, /* EMC_RW2PDEN */
3174 0x00000066, /* EMC_TXSR */
3175 0x00000200, /* EMC_TXSRDLL */
3176 0x00000004, /* EMC_TCKE */
3177 0x0000000c, /* EMC_TFAW */
3178 0x00000000, /* EMC_TRPAB */
3179 0x00000004, /* EMC_TCLKSTABLE */
3180 0x00000005, /* EMC_TCLKSTOP */
3181 0x00000b6d, /* EMC_TREFBW */
3182 0x00000000, /* EMC_QUSE_EXTRA */
3183 0x00000006, /* EMC_FBIO_CFG6 */
3184 0x00000000, /* EMC_ODT_WRITE */
3185 0x00000000, /* EMC_ODT_READ */
3186 0x00007088, /* EMC_FBIO_CFG5 */
3187 0x00200084, /* EMC_CFG_DIG_DLL */
3188 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3189 0x00014000, /* EMC_DLL_XFORM_DQS0 */
3190 0x00014000, /* EMC_DLL_XFORM_DQS1 */
3191 0x00014000, /* EMC_DLL_XFORM_DQS2 */
3192 0x00014000, /* EMC_DLL_XFORM_DQS3 */
3193 0x00014000, /* EMC_DLL_XFORM_DQS4 */
3194 0x00014000, /* EMC_DLL_XFORM_DQS5 */
3195 0x00014000, /* EMC_DLL_XFORM_DQS6 */
3196 0x00014000, /* EMC_DLL_XFORM_DQS7 */
3197 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3198 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3199 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3200 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3201 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3202 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3203 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3204 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3205 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3206 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3207 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3208 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3209 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3210 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3211 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3212 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3213 0x00020000, /* EMC_DLL_XFORM_DQ0 */
3214 0x00020000, /* EMC_DLL_XFORM_DQ1 */
3215 0x00020000, /* EMC_DLL_XFORM_DQ2 */
3216 0x00020000, /* EMC_DLL_XFORM_DQ3 */
3217 0x000002a0, /* EMC_XM2CMDPADCTRL */
3218 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3219 0x00000000, /* EMC_XM2DQPADCTRL2 */
3220 0x77fff884, /* EMC_XM2CLKPADCTRL */
3221 0x01f1f508, /* EMC_XM2COMPPADCTRL */
3222 0x05057404, /* EMC_XM2VTTGENPADCTRL */
3223 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3224 0x080001e8, /* EMC_XM2QUSEPADCTRL */
3225 0x08000021, /* EMC_XM2DQSPADCTRL3 */
3226 0x00000802, /* EMC_CTT_TERM_CTRL */
3227 0x00020000, /* EMC_ZCAL_INTERVAL */
3228 0x00000100, /* EMC_ZCAL_WAIT_CNT */
3229 0x015f000c, /* EMC_MRS_WAIT_CNT */
3230 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3231 0x00000000, /* EMC_CTT */
3232 0x00000000, /* EMC_CTT_DURATION */
3233 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
3234 0x00000005, /* MC_EMEM_ARB_CFG */
3235 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3236 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3237 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3238 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3239 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3240 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3241 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3242 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3243 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3244 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3245 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3246 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3247 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3248 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3249 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3250 0x7086110a, /* MC_EMEM_ARB_MISC0 */
3251 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3252 0x58000000, /* EMC_FBIO_SPARE */
3253 0xff00ff88, /* EMC_CFG_RSV */
3254 },
3255 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3256 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3257 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3258 0x80000521, /* Mode Register 0 */
3259 0x80100002, /* Mode Register 1 */
3260 0x80200000, /* Mode Register 2 */
3261 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3262 },
3263 {
3264 0x32, /* Rev 3.2 */
3265 400000, /* SDRAM frequency */
3266 {
3267 0x00000012, /* EMC_RC */
3268 0x00000066, /* EMC_RFC */
3269 0x0000000c, /* EMC_RAS */
3270 0x00000004, /* EMC_RP */
3271 0x00000003, /* EMC_R2W */
3272 0x00000008, /* EMC_W2R */
3273 0x00000002, /* EMC_R2P */
3274 0x0000000a, /* EMC_W2P */
3275 0x00000004, /* EMC_RD_RCD */
3276 0x00000004, /* EMC_WR_RCD */
3277 0x00000002, /* EMC_RRD */
3278 0x00000001, /* EMC_REXT */
3279 0x00000000, /* EMC_WEXT */
3280 0x00000004, /* EMC_WDV */
3281 0x00000006, /* EMC_QUSE */
3282 0x00000004, /* EMC_QRST */
3283 0x0000000a, /* EMC_QSAFE */
3284 0x0000000c, /* EMC_RDV */
3285 0x00000bf0, /* EMC_REFRESH */
3286 0x00000000, /* EMC_BURST_REFRESH_NUM */
3287 0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
3288 0x00000001, /* EMC_PDEX2WR */
3289 0x00000008, /* EMC_PDEX2RD */
3290 0x00000001, /* EMC_PCHG2PDEN */
3291 0x00000000, /* EMC_ACT2PDEN */
3292 0x00000008, /* EMC_AR2PDEN */
3293 0x0000000f, /* EMC_RW2PDEN */
3294 0x0000006c, /* EMC_TXSR */
3295 0x00000200, /* EMC_TXSRDLL */
3296 0x00000004, /* EMC_TCKE */
3297 0x0000000c, /* EMC_TFAW */
3298 0x00000000, /* EMC_TRPAB */
3299 0x00000004, /* EMC_TCLKSTABLE */
3300 0x00000005, /* EMC_TCLKSTOP */
3301 0x00000c30, /* EMC_TREFBW */
3302 0x00000000, /* EMC_QUSE_EXTRA */
3303 0x00000006, /* EMC_FBIO_CFG6 */
3304 0x00000000, /* EMC_ODT_WRITE */
3305 0x00000000, /* EMC_ODT_READ */
3306 0x00007088, /* EMC_FBIO_CFG5 */
3307 0x001d0084, /* EMC_CFG_DIG_DLL */
3308 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3309 0x00034000, /* EMC_DLL_XFORM_DQS0 */
3310 0x00034000, /* EMC_DLL_XFORM_DQS1 */
3311 0x00034000, /* EMC_DLL_XFORM_DQS2 */
3312 0x00034000, /* EMC_DLL_XFORM_DQS3 */
3313 0x00034000, /* EMC_DLL_XFORM_DQS4 */
3314 0x00034000, /* EMC_DLL_XFORM_DQS5 */
3315 0x00034000, /* EMC_DLL_XFORM_DQS6 */
3316 0x00034000, /* EMC_DLL_XFORM_DQS7 */
3317 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3318 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3319 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3320 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3321 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3322 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3323 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3324 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3325 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3326 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3327 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3328 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3329 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3330 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3331 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3332 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3333 0x00040000, /* EMC_DLL_XFORM_DQ0 */
3334 0x00040000, /* EMC_DLL_XFORM_DQ1 */
3335 0x00040000, /* EMC_DLL_XFORM_DQ2 */
3336 0x00040000, /* EMC_DLL_XFORM_DQ3 */
3337 0x000002a0, /* EMC_XM2CMDPADCTRL */
3338 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3339 0x00000000, /* EMC_XM2DQPADCTRL2 */
3340 0x77fff884, /* EMC_XM2CLKPADCTRL */
3341 0x01f1f508, /* EMC_XM2COMPPADCTRL */
3342 0x05057404, /* EMC_XM2VTTGENPADCTRL */
3343 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3344 0x080001e8, /* EMC_XM2QUSEPADCTRL */
3345 0x08000021, /* EMC_XM2DQSPADCTRL3 */
3346 0x00000802, /* EMC_CTT_TERM_CTRL */
3347 0x00020000, /* EMC_ZCAL_INTERVAL */
3348 0x00000100, /* EMC_ZCAL_WAIT_CNT */
3349 0x0158000c, /* EMC_MRS_WAIT_CNT */
3350 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3351 0x00000000, /* EMC_CTT */
3352 0x00000000, /* EMC_CTT_DURATION */
3353 0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
3354 0x00000006, /* MC_EMEM_ARB_CFG */
3355 0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3356 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3357 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3358 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3359 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3360 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3361 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3362 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3363 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3364 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3365 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3366 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3367 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3368 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3369 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3370 0x7566120a, /* MC_EMEM_ARB_MISC0 */
3371 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3372 0xe8000000, /* EMC_FBIO_SPARE */
3373 0xff00ff89, /* EMC_CFG_RSV */
3374 },
3375 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3376 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3377 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3378 0x80000521, /* Mode Register 0 */
3379 0x80100002, /* Mode Register 1 */
3380 0x80200000, /* Mode Register 2 */
3381 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3382 },
3383 {
3384 0x32, /* Rev 3.2 */
3385 750000, /* SDRAM frequency */
3386 {
3387 0x00000023, /* EMC_RC */
3388 0x000000c1, /* EMC_RFC */
3389 0x00000019, /* EMC_RAS */
3390 0x00000009, /* EMC_RP */
3391 0x00000005, /* EMC_R2W */
3392 0x0000000d, /* EMC_W2R */
3393 0x00000004, /* EMC_R2P */
3394 0x00000013, /* EMC_W2P */
3395 0x00000009, /* EMC_RD_RCD */
3396 0x00000009, /* EMC_WR_RCD */
3397 0x00000003, /* EMC_RRD */
3398 0x00000001, /* EMC_REXT */
3399 0x00000000, /* EMC_WEXT */
3400 0x00000007, /* EMC_WDV */
3401 0x0000000b, /* EMC_QUSE */
3402 0x00000009, /* EMC_QRST */
3403 0x0000000c, /* EMC_QSAFE */
3404 0x00000011, /* EMC_RDV */
3405 0x0000169a, /* EMC_REFRESH */
3406 0x00000000, /* EMC_BURST_REFRESH_NUM */
3407 0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
3408 0x00000003, /* EMC_PDEX2WR */
3409 0x00000010, /* EMC_PDEX2RD */
3410 0x00000001, /* EMC_PCHG2PDEN */
3411 0x00000000, /* EMC_ACT2PDEN */
3412 0x0000000e, /* EMC_AR2PDEN */
3413 0x00000018, /* EMC_RW2PDEN */
3414 0x000000cb, /* EMC_TXSR */
3415 0x00000200, /* EMC_TXSRDLL */
3416 0x00000005, /* EMC_TCKE */
3417 0x00000017, /* EMC_TFAW */
3418 0x00000000, /* EMC_TRPAB */
3419 0x00000007, /* EMC_TCLKSTABLE */
3420 0x00000008, /* EMC_TCLKSTOP */
3421 0x000016da, /* EMC_TREFBW */
3422 0x0000000c, /* EMC_QUSE_EXTRA */
3423 0x00000004, /* EMC_FBIO_CFG6 */
3424 0x00000000, /* EMC_ODT_WRITE */
3425 0x00000000, /* EMC_ODT_READ */
3426 0x00005088, /* EMC_FBIO_CFG5 */
3427 0xf0080191, /* EMC_CFG_DIG_DLL */
3428 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3429 0x00000008, /* EMC_DLL_XFORM_DQS0 */
3430 0x00000008, /* EMC_DLL_XFORM_DQS1 */
3431 0x00000008, /* EMC_DLL_XFORM_DQS2 */
3432 0x00000008, /* EMC_DLL_XFORM_DQS3 */
3433 0x00000008, /* EMC_DLL_XFORM_DQS4 */
3434 0x00000008, /* EMC_DLL_XFORM_DQS5 */
3435 0x00000008, /* EMC_DLL_XFORM_DQS6 */
3436 0x00000008, /* EMC_DLL_XFORM_DQS7 */
3437 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3438 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3439 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3440 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3441 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3442 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3443 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3444 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3445 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3446 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3447 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3448 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3449 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3450 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3451 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3452 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3453 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
3454 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
3455 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
3456 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
3457 0x000002a0, /* EMC_XM2CMDPADCTRL */
3458 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3459 0x22220000, /* EMC_XM2DQPADCTRL2 */
3460 0x77fff884, /* EMC_XM2CLKPADCTRL */
3461 0x01f1f501, /* EMC_XM2COMPPADCTRL */
3462 0x07077404, /* EMC_XM2VTTGENPADCTRL */
3463 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3464 0x080001e8, /* EMC_XM2QUSEPADCTRL */
3465 0x08000021, /* EMC_XM2DQSPADCTRL3 */
3466 0x00000802, /* EMC_CTT_TERM_CTRL */
3467 0x00020000, /* EMC_ZCAL_INTERVAL */
3468 0x00000100, /* EMC_ZCAL_WAIT_CNT */
3469 0x00fd000c, /* EMC_MRS_WAIT_CNT */
3470 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3471 0x00000000, /* EMC_CTT */
3472 0x00000000, /* EMC_CTT_DURATION */
3473 0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
3474 0x0000000b, /* MC_EMEM_ARB_CFG */
3475 0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3476 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3477 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3478 0x00000012, /* MC_EMEM_ARB_TIMING_RC */
3479 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3480 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3481 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3482 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3483 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3484 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3485 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3486 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3487 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3488 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3489 0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
3490 0x710c2213, /* MC_EMEM_ARB_MISC0 */
3491 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3492 0xf8000000, /* EMC_FBIO_SPARE */
3493 0xff00ff49, /* EMC_CFG_RSV */
3494 },
3495 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3496 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3497 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3498 0x80000d71, /* Mode Register 0 */
3499 0x80100002, /* Mode Register 1 */
3500 0x80200018, /* Mode Register 2 */
3501 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3502 },
3503 {
3504 0x32, /* Rev 3.2 */
3505 800000, /* SDRAM frequency */
3506 {
3507 0x00000025, /* EMC_RC */
3508 0x000000ce, /* EMC_RFC */
3509 0x0000001a, /* EMC_RAS */
3510 0x00000009, /* EMC_RP */
3511 0x00000005, /* EMC_R2W */
3512 0x0000000d, /* EMC_W2R */
3513 0x00000004, /* EMC_R2P */
3514 0x00000013, /* EMC_W2P */
3515 0x00000009, /* EMC_RD_RCD */
3516 0x00000009, /* EMC_WR_RCD */
3517 0x00000003, /* EMC_RRD */
3518 0x00000001, /* EMC_REXT */
3519 0x00000000, /* EMC_WEXT */
3520 0x00000007, /* EMC_WDV */
3521 0x0000000b, /* EMC_QUSE */
3522 0x00000009, /* EMC_QRST */
3523 0x0000000b, /* EMC_QSAFE */
3524 0x00000011, /* EMC_RDV */
3525 0x00001820, /* EMC_REFRESH */
3526 0x00000000, /* EMC_BURST_REFRESH_NUM */
3527 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
3528 0x00000003, /* EMC_PDEX2WR */
3529 0x00000012, /* EMC_PDEX2RD */
3530 0x00000001, /* EMC_PCHG2PDEN */
3531 0x00000000, /* EMC_ACT2PDEN */
3532 0x0000000f, /* EMC_AR2PDEN */
3533 0x00000018, /* EMC_RW2PDEN */
3534 0x000000d8, /* EMC_TXSR */
3535 0x00000200, /* EMC_TXSRDLL */
3536 0x00000005, /* EMC_TCKE */
3537 0x00000018, /* EMC_TFAW */
3538 0x00000000, /* EMC_TRPAB */
3539 0x00000007, /* EMC_TCLKSTABLE */
3540 0x00000008, /* EMC_TCLKSTOP */
3541 0x00001860, /* EMC_TREFBW */
3542 0x0000000c, /* EMC_QUSE_EXTRA */
3543 0x00000004, /* EMC_FBIO_CFG6 */
3544 0x00000000, /* EMC_ODT_WRITE */
3545 0x00000000, /* EMC_ODT_READ */
3546 0x00005088, /* EMC_FBIO_CFG5 */
3547 0xf0070191, /* EMC_CFG_DIG_DLL */
3548 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3549 0x0000800a, /* EMC_DLL_XFORM_DQS0 */
3550 0x0000800a, /* EMC_DLL_XFORM_DQS1 */
3551 0x0000800a, /* EMC_DLL_XFORM_DQS2 */
3552 0x0000800a, /* EMC_DLL_XFORM_DQS3 */
3553 0x0000800a, /* EMC_DLL_XFORM_DQS4 */
3554 0x0000800a, /* EMC_DLL_XFORM_DQS5 */
3555 0x0000800a, /* EMC_DLL_XFORM_DQS6 */
3556 0x0000800a, /* EMC_DLL_XFORM_DQS7 */
3557 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3558 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3559 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3560 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3561 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3562 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3563 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3564 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3565 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3566 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3567 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3568 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3569 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3570 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3571 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3572 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3573 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
3574 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
3575 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
3576 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
3577 0x000002a0, /* EMC_XM2CMDPADCTRL */
3578 0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3579 0x22220000, /* EMC_XM2DQPADCTRL2 */
3580 0x77fff884, /* EMC_XM2CLKPADCTRL */
3581 0x01f1f501, /* EMC_XM2COMPPADCTRL */
3582 0x07077404, /* EMC_XM2VTTGENPADCTRL */
3583 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3584 0x080001e8, /* EMC_XM2QUSEPADCTRL */
3585 0x09000021, /* EMC_XM2DQSPADCTRL3 */
3586 0x00000802, /* EMC_CTT_TERM_CTRL */
3587 0x00020000, /* EMC_ZCAL_INTERVAL */
3588 0x00000100, /* EMC_ZCAL_WAIT_CNT */
3589 0x00f0000c, /* EMC_MRS_WAIT_CNT */
3590 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3591 0x00000000, /* EMC_CTT */
3592 0x00000000, /* EMC_CTT_DURATION */
3593 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
3594 0x0000000c, /* MC_EMEM_ARB_CFG */
3595 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3596 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3597 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3598 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
3599 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3600 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3601 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3602 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3603 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3604 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3605 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3606 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3607 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3608 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3609 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
3610 0x734c2414, /* MC_EMEM_ARB_MISC0 */
3611 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3612 0xf8000000, /* EMC_FBIO_SPARE */
3613 0xff00ff49, /* EMC_CFG_RSV */
3614 },
3615 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3616 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3617 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3618 0x80000d71, /* Mode Register 0 */
3619 0x80100002, /* Mode Register 1 */
3620 0x80200018, /* Mode Register 2 */
3621 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3622 },
3623};
3624
3625static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
3626 {
3627 0x32, /* Rev 3.2 */
3628 25500, /* SDRAM frequency */
3629 {
3630 0x00000001, /* EMC_RC */
3631 0x00000003, /* EMC_RFC */
3632 0x00000002, /* EMC_RAS */
3633 0x00000002, /* EMC_RP */
3634 0x00000004, /* EMC_R2W */
3635 0x00000004, /* EMC_W2R */
3636 0x00000001, /* EMC_R2P */
3637 0x00000005, /* EMC_W2P */
3638 0x00000002, /* EMC_RD_RCD */
3639 0x00000002, /* EMC_WR_RCD */
3640 0x00000001, /* EMC_RRD */
3641 0x00000001, /* EMC_REXT */
3642 0x00000000, /* EMC_WEXT */
3643 0x00000001, /* EMC_WDV */
3644 0x00000003, /* EMC_QUSE */
3645 0x00000001, /* EMC_QRST */
3646 0x00000009, /* EMC_QSAFE */
3647 0x0000000a, /* EMC_RDV */
3648 0x0000005e, /* EMC_REFRESH */
3649 0x00000000, /* EMC_BURST_REFRESH_NUM */
3650 0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
3651 0x00000001, /* EMC_PDEX2WR */
3652 0x00000001, /* EMC_PDEX2RD */
3653 0x00000002, /* EMC_PCHG2PDEN */
3654 0x00000000, /* EMC_ACT2PDEN */
3655 0x00000001, /* EMC_AR2PDEN */
3656 0x00000007, /* EMC_RW2PDEN */
3657 0x00000004, /* EMC_TXSR */
3658 0x00000004, /* EMC_TXSRDLL */
3659 0x00000003, /* EMC_TCKE */
3660 0x00000008, /* EMC_TFAW */
3661 0x00000004, /* EMC_TRPAB */
3662 0x00000004, /* EMC_TCLKSTABLE */
3663 0x00000002, /* EMC_TCLKSTOP */
3664 0x00000068, /* EMC_TREFBW */
3665 0x00000004, /* EMC_QUSE_EXTRA */
3666 0x00000004, /* EMC_FBIO_CFG6 */
3667 0x00000000, /* EMC_ODT_WRITE */
3668 0x00000000, /* EMC_ODT_READ */
3669 0x00004282, /* EMC_FBIO_CFG5 */
3670 0x007800a4, /* EMC_CFG_DIG_DLL */
3671 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3672 0x00098000, /* EMC_DLL_XFORM_DQS0 */
3673 0x00098000, /* EMC_DLL_XFORM_DQS1 */
3674 0x00098000, /* EMC_DLL_XFORM_DQS2 */
3675 0x00098000, /* EMC_DLL_XFORM_DQS3 */
3676 0x00000010, /* EMC_DLL_XFORM_DQS4 */
3677 0x00000010, /* EMC_DLL_XFORM_DQS5 */
3678 0x00000010, /* EMC_DLL_XFORM_DQS6 */
3679 0x00000010, /* EMC_DLL_XFORM_DQS7 */
3680 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3681 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3682 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3683 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3684 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
3685 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
3686 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
3687 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
3688 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3689 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3690 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3691 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3692 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3693 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3694 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3695 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3696 0x00080000, /* EMC_DLL_XFORM_DQ0 */
3697 0x00080000, /* EMC_DLL_XFORM_DQ1 */
3698 0x00080000, /* EMC_DLL_XFORM_DQ2 */
3699 0x00080000, /* EMC_DLL_XFORM_DQ3 */
3700 0x00100220, /* EMC_XM2CMDPADCTRL */
3701 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3702 0x00000000, /* EMC_XM2DQPADCTRL2 */
3703 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3704 0x01f1f008, /* EMC_XM2COMPPADCTRL */
3705 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3706 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3707 0x08000068, /* EMC_XM2QUSEPADCTRL */
3708 0x08000000, /* EMC_XM2DQSPADCTRL3 */
3709 0x00000802, /* EMC_CTT_TERM_CTRL */
3710 0x00064000, /* EMC_ZCAL_INTERVAL */
3711 0x0000000a, /* EMC_ZCAL_WAIT_CNT */
3712 0x00090009, /* EMC_MRS_WAIT_CNT */
3713 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3714 0x00000000, /* EMC_CTT */
3715 0x00000000, /* EMC_CTT_DURATION */
3716 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
3717 0x00020001, /* MC_EMEM_ARB_CFG */
3718 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3719 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3720 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3721 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3722 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3723 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3724 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3725 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3726 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3727 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3728 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3729 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3730 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3731 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3732 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
3733 0x74030303, /* MC_EMEM_ARB_MISC0 */
3734 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3735 0x50000000, /* EMC_FBIO_SPARE */
3736 0xff00ff00, /* EMC_CFG_RSV */
3737 },
3738 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
3739 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3740 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3741 0x00000000, /* Mode Register 0 */
3742 0x00010022, /* Mode Register 1 */
3743 0x00020001, /* Mode Register 2 */
3744 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3745 },
3746 {
3747 0x32, /* Rev 3.2 */
3748 51000, /* SDRAM frequency */
3749 {
3750 0x00000003, /* EMC_RC */
3751 0x00000006, /* EMC_RFC */
3752 0x00000002, /* EMC_RAS */
3753 0x00000002, /* EMC_RP */
3754 0x00000004, /* EMC_R2W */
3755 0x00000004, /* EMC_W2R */
3756 0x00000001, /* EMC_R2P */
3757 0x00000005, /* EMC_W2P */
3758 0x00000002, /* EMC_RD_RCD */
3759 0x00000002, /* EMC_WR_RCD */
3760 0x00000001, /* EMC_RRD */
3761 0x00000001, /* EMC_REXT */
3762 0x00000000, /* EMC_WEXT */
3763 0x00000001, /* EMC_WDV */
3764 0x00000003, /* EMC_QUSE */
3765 0x00000001, /* EMC_QRST */
3766 0x00000009, /* EMC_QSAFE */
3767 0x0000000a, /* EMC_RDV */
3768 0x000000c0, /* EMC_REFRESH */
3769 0x00000000, /* EMC_BURST_REFRESH_NUM */
3770 0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
3771 0x00000001, /* EMC_PDEX2WR */
3772 0x00000001, /* EMC_PDEX2RD */
3773 0x00000002, /* EMC_PCHG2PDEN */
3774 0x00000000, /* EMC_ACT2PDEN */
3775 0x00000001, /* EMC_AR2PDEN */
3776 0x00000007, /* EMC_RW2PDEN */
3777 0x00000008, /* EMC_TXSR */
3778 0x00000008, /* EMC_TXSRDLL */
3779 0x00000003, /* EMC_TCKE */
3780 0x00000008, /* EMC_TFAW */
3781 0x00000004, /* EMC_TRPAB */
3782 0x00000004, /* EMC_TCLKSTABLE */
3783 0x00000002, /* EMC_TCLKSTOP */
3784 0x000000d5, /* EMC_TREFBW */
3785 0x00000004, /* EMC_QUSE_EXTRA */
3786 0x00000004, /* EMC_FBIO_CFG6 */
3787 0x00000000, /* EMC_ODT_WRITE */
3788 0x00000000, /* EMC_ODT_READ */
3789 0x00004282, /* EMC_FBIO_CFG5 */
3790 0x007800a4, /* EMC_CFG_DIG_DLL */
3791 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3792 0x000a0000, /* EMC_DLL_XFORM_DQS0 */
3793 0x000a0000, /* EMC_DLL_XFORM_DQS1 */
3794 0x000a0000, /* EMC_DLL_XFORM_DQS2 */
3795 0x000a0000, /* EMC_DLL_XFORM_DQS3 */
3796 0x00000010, /* EMC_DLL_XFORM_DQS4 */
3797 0x00000010, /* EMC_DLL_XFORM_DQS5 */
3798 0x00000010, /* EMC_DLL_XFORM_DQS6 */
3799 0x00000010, /* EMC_DLL_XFORM_DQS7 */
3800 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3801 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3802 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3803 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3804 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
3805 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
3806 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
3807 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
3808 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3809 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3810 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3811 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3812 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3813 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3814 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3815 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3816 0x00080000, /* EMC_DLL_XFORM_DQ0 */
3817 0x00080000, /* EMC_DLL_XFORM_DQ1 */
3818 0x00080000, /* EMC_DLL_XFORM_DQ2 */
3819 0x00080000, /* EMC_DLL_XFORM_DQ3 */
3820 0x00100220, /* EMC_XM2CMDPADCTRL */
3821 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3822 0x00000000, /* EMC_XM2DQPADCTRL2 */
3823 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3824 0x01f1f008, /* EMC_XM2COMPPADCTRL */
3825 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3826 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3827 0x08000068, /* EMC_XM2QUSEPADCTRL */
3828 0x08000000, /* EMC_XM2DQSPADCTRL3 */
3829 0x00000802, /* EMC_CTT_TERM_CTRL */
3830 0x00064000, /* EMC_ZCAL_INTERVAL */
3831 0x00000013, /* EMC_ZCAL_WAIT_CNT */
3832 0x00090009, /* EMC_MRS_WAIT_CNT */
3833 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3834 0x00000000, /* EMC_CTT */
3835 0x00000000, /* EMC_CTT_DURATION */
3836 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
3837 0x00010001, /* MC_EMEM_ARB_CFG */
3838 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3839 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3840 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3841 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3842 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3843 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3844 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3845 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3846 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3847 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3848 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3849 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3850 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3851 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3852 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
3853 0x72c30303, /* MC_EMEM_ARB_MISC0 */
3854 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3855 0x50000000, /* EMC_FBIO_SPARE */
3856 0xff00ff00, /* EMC_CFG_RSV */
3857 },
3858 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
3859 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3860 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3861 0x00000000, /* Mode Register 0 */
3862 0x00010022, /* Mode Register 1 */
3863 0x00020001, /* Mode Register 2 */
3864 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3865 },
3866 {
3867 0x32, /* Rev 3.2 */
3868 102000, /* SDRAM frequency */
3869 {
3870 0x00000006, /* EMC_RC */
3871 0x0000000d, /* EMC_RFC */
3872 0x00000004, /* EMC_RAS */
3873 0x00000002, /* EMC_RP */
3874 0x00000004, /* EMC_R2W */
3875 0x00000004, /* EMC_W2R */
3876 0x00000001, /* EMC_R2P */
3877 0x00000005, /* EMC_W2P */
3878 0x00000002, /* EMC_RD_RCD */
3879 0x00000002, /* EMC_WR_RCD */
3880 0x00000001, /* EMC_RRD */
3881 0x00000001, /* EMC_REXT */
3882 0x00000000, /* EMC_WEXT */
3883 0x00000001, /* EMC_WDV */
3884 0x00000003, /* EMC_QUSE */
3885 0x00000001, /* EMC_QRST */
3886 0x00000009, /* EMC_QSAFE */
3887 0x00000009, /* EMC_RDV */
3888 0x00000181, /* EMC_REFRESH */
3889 0x00000000, /* EMC_BURST_REFRESH_NUM */
3890 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
3891 0x00000001, /* EMC_PDEX2WR */
3892 0x00000001, /* EMC_PDEX2RD */
3893 0x00000002, /* EMC_PCHG2PDEN */
3894 0x00000000, /* EMC_ACT2PDEN */
3895 0x00000001, /* EMC_AR2PDEN */
3896 0x00000007, /* EMC_RW2PDEN */
3897 0x0000000f, /* EMC_TXSR */
3898 0x0000000f, /* EMC_TXSRDLL */
3899 0x00000003, /* EMC_TCKE */
3900 0x00000008, /* EMC_TFAW */
3901 0x00000004, /* EMC_TRPAB */
3902 0x00000004, /* EMC_TCLKSTABLE */
3903 0x00000002, /* EMC_TCLKSTOP */
3904 0x000001a9, /* EMC_TREFBW */
3905 0x00000004, /* EMC_QUSE_EXTRA */
3906 0x00000004, /* EMC_FBIO_CFG6 */
3907 0x00000000, /* EMC_ODT_WRITE */
3908 0x00000000, /* EMC_ODT_READ */
3909 0x00004282, /* EMC_FBIO_CFG5 */
3910 0x007800a4, /* EMC_CFG_DIG_DLL */
3911 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3912 0x000a0000, /* EMC_DLL_XFORM_DQS0 */
3913 0x000a0000, /* EMC_DLL_XFORM_DQS1 */
3914 0x000a0000, /* EMC_DLL_XFORM_DQS2 */
3915 0x000a0000, /* EMC_DLL_XFORM_DQS3 */
3916 0x00000010, /* EMC_DLL_XFORM_DQS4 */
3917 0x00000010, /* EMC_DLL_XFORM_DQS5 */
3918 0x00000010, /* EMC_DLL_XFORM_DQS6 */
3919 0x00000010, /* EMC_DLL_XFORM_DQS7 */
3920 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3921 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3922 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3923 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3924 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
3925 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
3926 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
3927 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
3928 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3929 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3930 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3931 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3932 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3933 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3934 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3935 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3936 0x00080000, /* EMC_DLL_XFORM_DQ0 */
3937 0x00080000, /* EMC_DLL_XFORM_DQ1 */
3938 0x00080000, /* EMC_DLL_XFORM_DQ2 */
3939 0x00080000, /* EMC_DLL_XFORM_DQ3 */
3940 0x00120220, /* EMC_XM2CMDPADCTRL */
3941 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3942 0x00000000, /* EMC_XM2DQPADCTRL2 */
3943 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3944 0x01f1f008, /* EMC_XM2COMPPADCTRL */
3945 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3946 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3947 0x08000068, /* EMC_XM2QUSEPADCTRL */
3948 0x08000000, /* EMC_XM2DQSPADCTRL3 */
3949 0x00000802, /* EMC_CTT_TERM_CTRL */
3950 0x00064000, /* EMC_ZCAL_INTERVAL */
3951 0x00000025, /* EMC_ZCAL_WAIT_CNT */
3952 0x00090009, /* EMC_MRS_WAIT_CNT */
3953 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3954 0x00000000, /* EMC_CTT */
3955 0x00000000, /* EMC_CTT_DURATION */
3956 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
3957 0x00000001, /* MC_EMEM_ARB_CFG */
3958 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3959 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3960 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3961 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
3962 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
3963 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3964 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3965 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3966 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3967 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3968 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3969 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3970 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3971 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3972 0x00060403, /* MC_EMEM_ARB_DA_COVERS */
3973 0x72430504, /* MC_EMEM_ARB_MISC0 */
3974 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3975 0x10000000, /* EMC_FBIO_SPARE */
3976 0xff00ff00, /* EMC_CFG_RSV */
3977 },
3978 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
3979 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3980 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3981 0x00000000, /* Mode Register 0 */
3982 0x00010022, /* Mode Register 1 */
3983 0x00020001, /* Mode Register 2 */
3984 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3985 },
3986 {
3987 0x32, /* Rev 3.2 */
3988 204000, /* SDRAM frequency */
3989 {
3990 0x0000000c, /* EMC_RC */
3991 0x0000001a, /* EMC_RFC */
3992 0x00000008, /* EMC_RAS */
3993 0x00000003, /* EMC_RP */
3994 0x00000005, /* EMC_R2W */
3995 0x00000004, /* EMC_W2R */
3996 0x00000001, /* EMC_R2P */
3997 0x00000006, /* EMC_W2P */
3998 0x00000003, /* EMC_RD_RCD */
3999 0x00000003, /* EMC_WR_RCD */
4000 0x00000002, /* EMC_RRD */
4001 0x00000002, /* EMC_REXT */
4002 0x00000000, /* EMC_WEXT */
4003 0x00000001, /* EMC_WDV */
4004 0x00000003, /* EMC_QUSE */
4005 0x00000001, /* EMC_QRST */
4006 0x0000000a, /* EMC_QSAFE */
4007 0x0000000a, /* EMC_RDV */
4008 0x00000303, /* EMC_REFRESH */
4009 0x00000000, /* EMC_BURST_REFRESH_NUM */
4010 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
4011 0x00000001, /* EMC_PDEX2WR */
4012 0x00000001, /* EMC_PDEX2RD */
4013 0x00000003, /* EMC_PCHG2PDEN */
4014 0x00000000, /* EMC_ACT2PDEN */
4015 0x00000001, /* EMC_AR2PDEN */
4016 0x00000007, /* EMC_RW2PDEN */
4017 0x0000001d, /* EMC_TXSR */
4018 0x0000001d, /* EMC_TXSRDLL */
4019 0x00000004, /* EMC_TCKE */
4020 0x0000000b, /* EMC_TFAW */
4021 0x00000005, /* EMC_TRPAB */
4022 0x00000004, /* EMC_TCLKSTABLE */
4023 0x00000002, /* EMC_TCLKSTOP */
4024 0x00000351, /* EMC_TREFBW */
4025 0x00000004, /* EMC_QUSE_EXTRA */
4026 0x00000006, /* EMC_FBIO_CFG6 */
4027 0x00000000, /* EMC_ODT_WRITE */
4028 0x00000000, /* EMC_ODT_READ */
4029 0x00004282, /* EMC_FBIO_CFG5 */
4030 0x004400a4, /* EMC_CFG_DIG_DLL */
4031 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4032 0x00074000, /* EMC_DLL_XFORM_DQS0 */
4033 0x00074000, /* EMC_DLL_XFORM_DQS1 */
4034 0x00074000, /* EMC_DLL_XFORM_DQS2 */
4035 0x00074000, /* EMC_DLL_XFORM_DQS3 */
4036 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4037 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4038 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4039 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4040 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4041 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4042 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4043 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4044 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
4045 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
4046 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
4047 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
4048 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4049 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4050 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4051 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4052 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4053 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4054 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4055 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4056 0x00078000, /* EMC_DLL_XFORM_DQ0 */
4057 0x00078000, /* EMC_DLL_XFORM_DQ1 */
4058 0x00078000, /* EMC_DLL_XFORM_DQ2 */
4059 0x00078000, /* EMC_DLL_XFORM_DQ3 */
4060 0x00100220, /* EMC_XM2CMDPADCTRL */
4061 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
4062 0x00000000, /* EMC_XM2DQPADCTRL2 */
4063 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4064 0x01f1f008, /* EMC_XM2COMPPADCTRL */
4065 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4066 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4067 0x08000068, /* EMC_XM2QUSEPADCTRL */
4068 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4069 0x00000802, /* EMC_CTT_TERM_CTRL */
4070 0x00064000, /* EMC_ZCAL_INTERVAL */
4071 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
4072 0x00090009, /* EMC_MRS_WAIT_CNT */
4073 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4074 0x00000000, /* EMC_CTT */
4075 0x00000000, /* EMC_CTT_DURATION */
4076 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
4077 0x00000003, /* MC_EMEM_ARB_CFG */
4078 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4079 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4080 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4081 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
4082 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
4083 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
4084 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4085 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4086 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4087 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
4088 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4089 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
4090 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
4091 0x02030001, /* MC_EMEM_ARB_DA_TURNS */
4092 0x00070506, /* MC_EMEM_ARB_DA_COVERS */
4093 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
4094 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4095 0x50000000, /* EMC_FBIO_SPARE */
4096 0xff00ff00, /* EMC_CFG_RSV */
4097 },
4098 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
4099 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4100 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4101 0x00000000, /* Mode Register 0 */
4102 0x00010042, /* Mode Register 1 */
4103 0x00020001, /* Mode Register 2 */
4104 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4105 },
4106 {
4107 0x32, /* Rev 3.2 */
4108 533000, /* SDRAM frequency */
4109 {
4110 0x0000001f, /* EMC_RC */
4111 0x00000045, /* EMC_RFC */
4112 0x00000016, /* EMC_RAS */
4113 0x00000009, /* EMC_RP */
4114 0x00000008, /* EMC_R2W */
4115 0x00000009, /* EMC_W2R */
4116 0x00000003, /* EMC_R2P */
4117 0x0000000d, /* EMC_W2P */
4118 0x00000009, /* EMC_RD_RCD */
4119 0x00000009, /* EMC_WR_RCD */
4120 0x00000005, /* EMC_RRD */
4121 0x00000003, /* EMC_REXT */
4122 0x00000000, /* EMC_WEXT */
4123 0x00000004, /* EMC_WDV */
4124 0x00000009, /* EMC_QUSE */
4125 0x00000006, /* EMC_QRST */
4126 0x0000000c, /* EMC_QSAFE */
4127 0x00000010, /* EMC_RDV */
4128 0x000007df, /* EMC_REFRESH */
4129 0x00000000, /* EMC_BURST_REFRESH_NUM */
4130 0x000001f7, /* EMC_PRE_REFRESH_REQ_CNT */
4131 0x00000003, /* EMC_PDEX2WR */
4132 0x00000003, /* EMC_PDEX2RD */
4133 0x00000009, /* EMC_PCHG2PDEN */
4134 0x00000000, /* EMC_ACT2PDEN */
4135 0x00000001, /* EMC_AR2PDEN */
4136 0x0000000f, /* EMC_RW2PDEN */
4137 0x0000004b, /* EMC_TXSR */
4138 0x0000004b, /* EMC_TXSRDLL */
4139 0x00000008, /* EMC_TCKE */
4140 0x0000001b, /* EMC_TFAW */
4141 0x0000000c, /* EMC_TRPAB */
4142 0x00000004, /* EMC_TCLKSTABLE */
4143 0x00000002, /* EMC_TCLKSTOP */
4144 0x000008aa, /* EMC_TREFBW */
4145 0x00000000, /* EMC_QUSE_EXTRA */
4146 0x00000006, /* EMC_FBIO_CFG6 */
4147 0x00000000, /* EMC_ODT_WRITE */
4148 0x00000000, /* EMC_ODT_READ */
4149 0x00006282, /* EMC_FBIO_CFG5 */
4150 0xf0120091, /* EMC_CFG_DIG_DLL */
4151 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4152 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
4153 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
4154 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
4155 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
4156 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4157 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4158 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4159 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4160 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4161 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4162 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4163 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4164 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
4165 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
4166 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
4167 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
4168 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4169 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4170 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4171 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4172 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4173 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4174 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4175 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4176 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
4177 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
4178 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
4179 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
4180 0x000b0220, /* EMC_XM2CMDPADCTRL */
4181 0x0800003d, /* EMC_XM2DQSPADCTRL2 */
4182 0x00000000, /* EMC_XM2DQPADCTRL2 */
4183 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4184 0x01f1f408, /* EMC_XM2COMPPADCTRL */
4185 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4186 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4187 0x08000068, /* EMC_XM2QUSEPADCTRL */
4188 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4189 0x00000802, /* EMC_CTT_TERM_CTRL */
4190 0x00064000, /* EMC_ZCAL_INTERVAL */
4191 0x000000c0, /* EMC_ZCAL_WAIT_CNT */
4192 0x000e000e, /* EMC_MRS_WAIT_CNT */
4193 0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
4194 0x00000000, /* EMC_CTT */
4195 0x00000000, /* EMC_CTT_DURATION */
4196 0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
4197 0x00000008, /* MC_EMEM_ARB_CFG */
4198 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4199 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
4200 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
4201 0x00000010, /* MC_EMEM_ARB_TIMING_RC */
4202 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
4203 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
4204 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
4205 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4206 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4207 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
4208 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4209 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
4210 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
4211 0x05040002, /* MC_EMEM_ARB_DA_TURNS */
4212 0x00110b10, /* MC_EMEM_ARB_DA_COVERS */
4213 0x71c81811, /* MC_EMEM_ARB_MISC0 */
4214 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4215 0xe0000000, /* EMC_FBIO_SPARE */
4216 0xff00ff88, /* EMC_CFG_RSV */
4217 },
4218 0x00000030, /* EMC_ZCAL_WAIT_CNT after clock change */
4219 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4220 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4221 0x00000000, /* Mode Register 0 */
4222 0x000100c2, /* Mode Register 1 */
4223 0x00020006, /* Mode Register 2 */
4224 0x00000000, /* EMC_CFG.DYN_SELF_REF */
4225 },
4226};
4227
4228static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
4229 {
4230 0x32, /* Rev 3.2 */
4231 25500, /* SDRAM frequency */
4232 {
4233 0x00000001, /* EMC_RC */
4234 0x00000003, /* EMC_RFC */
4235 0x00000002, /* EMC_RAS */
4236 0x00000002, /* EMC_RP */
4237 0x00000004, /* EMC_R2W */
4238 0x00000004, /* EMC_W2R */
4239 0x00000001, /* EMC_R2P */
4240 0x00000005, /* EMC_W2P */
4241 0x00000002, /* EMC_RD_RCD */
4242 0x00000002, /* EMC_WR_RCD */
4243 0x00000001, /* EMC_RRD */
4244 0x00000001, /* EMC_REXT */
4245 0x00000000, /* EMC_WEXT */
4246 0x00000001, /* EMC_WDV */
4247 0x00000003, /* EMC_QUSE */
4248 0x00000001, /* EMC_QRST */
4249 0x00000009, /* EMC_QSAFE */
4250 0x0000000a, /* EMC_RDV */
4251 0x00000060, /* EMC_REFRESH */
4252 0x00000000, /* EMC_BURST_REFRESH_NUM */
4253 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
4254 0x00000001, /* EMC_PDEX2WR */
4255 0x00000001, /* EMC_PDEX2RD */
4256 0x00000002, /* EMC_PCHG2PDEN */
4257 0x00000000, /* EMC_ACT2PDEN */
4258 0x00000001, /* EMC_AR2PDEN */
4259 0x00000007, /* EMC_RW2PDEN */
4260 0x00000004, /* EMC_TXSR */
4261 0x00000004, /* EMC_TXSRDLL */
4262 0x00000003, /* EMC_TCKE */
4263 0x00000008, /* EMC_TFAW */
4264 0x00000004, /* EMC_TRPAB */
4265 0x00000004, /* EMC_TCLKSTABLE */
4266 0x00000002, /* EMC_TCLKSTOP */
4267 0x0000006b, /* EMC_TREFBW */
4268 0x00000004, /* EMC_QUSE_EXTRA */
4269 0x00000006, /* EMC_FBIO_CFG6 */
4270 0x00000000, /* EMC_ODT_WRITE */
4271 0x00000000, /* EMC_ODT_READ */
4272 0x00004282, /* EMC_FBIO_CFG5 */
4273 0x007800a4, /* EMC_CFG_DIG_DLL */
4274 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4275 0x000a0000, /* EMC_DLL_XFORM_DQS0 */
4276 0x000a0000, /* EMC_DLL_XFORM_DQS1 */
4277 0x000a0000, /* EMC_DLL_XFORM_DQS2 */
4278 0x000a0000, /* EMC_DLL_XFORM_DQS3 */
4279 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4280 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4281 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4282 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4283 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4284 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4285 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4286 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4287 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
4288 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
4289 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
4290 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
4291 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4292 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4293 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4294 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4295 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4296 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4297 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4298 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4299 0x00080000, /* EMC_DLL_XFORM_DQ0 */
4300 0x00080000, /* EMC_DLL_XFORM_DQ1 */
4301 0x00080000, /* EMC_DLL_XFORM_DQ2 */
4302 0x00080000, /* EMC_DLL_XFORM_DQ3 */
4303 0x00120220, /* EMC_XM2CMDPADCTRL */
4304 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
4305 0x00000000, /* EMC_XM2DQPADCTRL2 */
4306 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4307 0x01f1f008, /* EMC_XM2COMPPADCTRL */
4308 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4309 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4310 0x08000068, /* EMC_XM2QUSEPADCTRL */
4311 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4312 0x00000802, /* EMC_CTT_TERM_CTRL */
4313 0x00064000, /* EMC_ZCAL_INTERVAL */
4314 0x0000000a, /* EMC_ZCAL_WAIT_CNT */
4315 0x00090009, /* EMC_MRS_WAIT_CNT */
4316 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4317 0x00000000, /* EMC_CTT */
4318 0x00000000, /* EMC_CTT_DURATION */
4319 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
4320 0x00020001, /* MC_EMEM_ARB_CFG */
4321 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4322 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4323 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4324 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
4325 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
4326 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
4327 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4328 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4329 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4330 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
4331 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4332 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
4333 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
4334 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
4335 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
4336 0x73e30303, /* MC_EMEM_ARB_MISC0 */
4337 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4338 0x50000000, /* EMC_FBIO_SPARE */
4339 0xff00ff00, /* EMC_CFG_RSV */
4340 },
4341 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
4342 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4343 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4344 0x00000000, /* Mode Register 0 */
4345 0x00010022, /* Mode Register 1 */
4346 0x00020001, /* Mode Register 2 */
4347 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4348 },
4349 {
4350 0x32, /* Rev 3.2 */
4351 51000, /* SDRAM frequency */
4352 {
4353 0x00000003, /* EMC_RC */
4354 0x00000006, /* EMC_RFC */
4355 0x00000002, /* EMC_RAS */
4356 0x00000002, /* EMC_RP */
4357 0x00000004, /* EMC_R2W */
4358 0x00000004, /* EMC_W2R */
4359 0x00000001, /* EMC_R2P */
4360 0x00000005, /* EMC_W2P */
4361 0x00000002, /* EMC_RD_RCD */
4362 0x00000002, /* EMC_WR_RCD */
4363 0x00000001, /* EMC_RRD */
4364 0x00000001, /* EMC_REXT */
4365 0x00000000, /* EMC_WEXT */
4366 0x00000001, /* EMC_WDV */
4367 0x00000003, /* EMC_QUSE */
4368 0x00000001, /* EMC_QRST */
4369 0x00000009, /* EMC_QSAFE */
4370 0x0000000a, /* EMC_RDV */
4371 0x000000c0, /* EMC_REFRESH */
4372 0x00000000, /* EMC_BURST_REFRESH_NUM */
4373 0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
4374 0x00000001, /* EMC_PDEX2WR */
4375 0x00000001, /* EMC_PDEX2RD */
4376 0x00000002, /* EMC_PCHG2PDEN */
4377 0x00000000, /* EMC_ACT2PDEN */
4378 0x00000001, /* EMC_AR2PDEN */
4379 0x00000007, /* EMC_RW2PDEN */
4380 0x00000008, /* EMC_TXSR */
4381 0x00000008, /* EMC_TXSRDLL */
4382 0x00000003, /* EMC_TCKE */
4383 0x00000008, /* EMC_TFAW */
4384 0x00000004, /* EMC_TRPAB */
4385 0x00000004, /* EMC_TCLKSTABLE */
4386 0x00000002, /* EMC_TCLKSTOP */
4387 0x000000d5, /* EMC_TREFBW */
4388 0x00000004, /* EMC_QUSE_EXTRA */
4389 0x00000006, /* EMC_FBIO_CFG6 */
4390 0x00000000, /* EMC_ODT_WRITE */
4391 0x00000000, /* EMC_ODT_READ */
4392 0x00004282, /* EMC_FBIO_CFG5 */
4393 0x007800a4, /* EMC_CFG_DIG_DLL */
4394 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4395 0x000a0000, /* EMC_DLL_XFORM_DQS0 */
4396 0x000a0000, /* EMC_DLL_XFORM_DQS1 */
4397 0x000a0000, /* EMC_DLL_XFORM_DQS2 */
4398 0x000a0000, /* EMC_DLL_XFORM_DQS3 */
4399 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4400 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4401 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4402 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4403 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4404 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4405 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4406 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4407 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
4408 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
4409 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
4410 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
4411 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4412 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4413 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4414 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4415 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4416 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4417 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4418 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4419 0x00080000, /* EMC_DLL_XFORM_DQ0 */
4420 0x00080000, /* EMC_DLL_XFORM_DQ1 */
4421 0x00080000, /* EMC_DLL_XFORM_DQ2 */
4422 0x00080000, /* EMC_DLL_XFORM_DQ3 */
4423 0x00120220, /* EMC_XM2CMDPADCTRL */
4424 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
4425 0x00000000, /* EMC_XM2DQPADCTRL2 */
4426 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4427 0x01f1f008, /* EMC_XM2COMPPADCTRL */
4428 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4429 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4430 0x08000068, /* EMC_XM2QUSEPADCTRL */
4431 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4432 0x00000802, /* EMC_CTT_TERM_CTRL */
4433 0x00064000, /* EMC_ZCAL_INTERVAL */
4434 0x00000013, /* EMC_ZCAL_WAIT_CNT */
4435 0x00090009, /* EMC_MRS_WAIT_CNT */
4436 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4437 0x00000000, /* EMC_CTT */
4438 0x00000000, /* EMC_CTT_DURATION */
4439 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
4440 0x00010001, /* MC_EMEM_ARB_CFG */
4441 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4442 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4443 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4444 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
4445 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
4446 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
4447 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4448 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4449 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4450 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
4451 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4452 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
4453 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
4454 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
4455 0x00060402, /* MC_EMEM_ARB_DA_COVERS */
4456 0x72c30303, /* MC_EMEM_ARB_MISC0 */
4457 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4458 0x50000000, /* EMC_FBIO_SPARE */
4459 0xff00ff00, /* EMC_CFG_RSV */
4460 },
4461 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
4462 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4463 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4464 0x00000000, /* Mode Register 0 */
4465 0x00010022, /* Mode Register 1 */
4466 0x00020001, /* Mode Register 2 */
4467 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4468 },
4469 {
4470 0x32, /* Rev 3.2 */
4471 102000, /* SDRAM frequency */
4472 {
4473 0x00000006, /* EMC_RC */
4474 0x0000000d, /* EMC_RFC */
4475 0x00000004, /* EMC_RAS */
4476 0x00000002, /* EMC_RP */
4477 0x00000004, /* EMC_R2W */
4478 0x00000004, /* EMC_W2R */
4479 0x00000001, /* EMC_R2P */
4480 0x00000005, /* EMC_W2P */
4481 0x00000002, /* EMC_RD_RCD */
4482 0x00000002, /* EMC_WR_RCD */
4483 0x00000001, /* EMC_RRD */
4484 0x00000001, /* EMC_REXT */
4485 0x00000000, /* EMC_WEXT */
4486 0x00000001, /* EMC_WDV */
4487 0x00000003, /* EMC_QUSE */
4488 0x00000001, /* EMC_QRST */
4489 0x00000009, /* EMC_QSAFE */
4490 0x0000000a, /* EMC_RDV */
4491 0x00000181, /* EMC_REFRESH */
4492 0x00000000, /* EMC_BURST_REFRESH_NUM */
4493 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
4494 0x00000001, /* EMC_PDEX2WR */
4495 0x00000001, /* EMC_PDEX2RD */
4496 0x00000002, /* EMC_PCHG2PDEN */
4497 0x00000000, /* EMC_ACT2PDEN */
4498 0x00000001, /* EMC_AR2PDEN */
4499 0x00000007, /* EMC_RW2PDEN */
4500 0x0000000f, /* EMC_TXSR */
4501 0x0000000f, /* EMC_TXSRDLL */
4502 0x00000003, /* EMC_TCKE */
4503 0x00000008, /* EMC_TFAW */
4504 0x00000004, /* EMC_TRPAB */
4505 0x00000004, /* EMC_TCLKSTABLE */
4506 0x00000002, /* EMC_TCLKSTOP */
4507 0x000001a9, /* EMC_TREFBW */
4508 0x00000004, /* EMC_QUSE_EXTRA */
4509 0x00000006, /* EMC_FBIO_CFG6 */
4510 0x00000000, /* EMC_ODT_WRITE */
4511 0x00000000, /* EMC_ODT_READ */
4512 0x00004282, /* EMC_FBIO_CFG5 */
4513 0x007800a4, /* EMC_CFG_DIG_DLL */
4514 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4515 0x000a0000, /* EMC_DLL_XFORM_DQS0 */
4516 0x000a0000, /* EMC_DLL_XFORM_DQS1 */
4517 0x000a0000, /* EMC_DLL_XFORM_DQS2 */
4518 0x000a0000, /* EMC_DLL_XFORM_DQS3 */
4519 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4520 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4521 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4522 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4523 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4524 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4525 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4526 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4527 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
4528 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
4529 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
4530 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
4531 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4532 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4533 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4534 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4535 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4536 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4537 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4538 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4539 0x00080000, /* EMC_DLL_XFORM_DQ0 */
4540 0x00080000, /* EMC_DLL_XFORM_DQ1 */
4541 0x00080000, /* EMC_DLL_XFORM_DQ2 */
4542 0x00080000, /* EMC_DLL_XFORM_DQ3 */
4543 0x00120220, /* EMC_XM2CMDPADCTRL */
4544 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
4545 0x00000000, /* EMC_XM2DQPADCTRL2 */
4546 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4547 0x01f1f008, /* EMC_XM2COMPPADCTRL */
4548 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4549 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4550 0x08000068, /* EMC_XM2QUSEPADCTRL */
4551 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4552 0x00000802, /* EMC_CTT_TERM_CTRL */
4553 0x00064000, /* EMC_ZCAL_INTERVAL */
4554 0x00000025, /* EMC_ZCAL_WAIT_CNT */
4555 0x00090009, /* EMC_MRS_WAIT_CNT */
4556 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4557 0x00000000, /* EMC_CTT */
4558 0x00000000, /* EMC_CTT_DURATION */
4559 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
4560 0x00000001, /* MC_EMEM_ARB_CFG */
4561 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4562 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4563 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4564 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
4565 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
4566 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
4567 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4568 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4569 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4570 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
4571 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4572 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
4573 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
4574 0x02020001, /* MC_EMEM_ARB_DA_TURNS */
4575 0x00060403, /* MC_EMEM_ARB_DA_COVERS */
4576 0x72430504, /* MC_EMEM_ARB_MISC0 */
4577 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4578 0x50000000, /* EMC_FBIO_SPARE */
4579 0xff00ff00, /* EMC_CFG_RSV */
4580 },
4581 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
4582 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4583 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4584 0x00000000, /* Mode Register 0 */
4585 0x00010022, /* Mode Register 1 */
4586 0x00020001, /* Mode Register 2 */
4587 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4588 },
4589 {
4590 0x32, /* Rev 3.2 */
4591 204000, /* SDRAM frequency */
4592 {
4593 0x0000000c, /* EMC_RC */
4594 0x0000001a, /* EMC_RFC */
4595 0x00000008, /* EMC_RAS */
4596 0x00000003, /* EMC_RP */
4597 0x00000005, /* EMC_R2W */
4598 0x00000004, /* EMC_W2R */
4599 0x00000001, /* EMC_R2P */
4600 0x00000006, /* EMC_W2P */
4601 0x00000003, /* EMC_RD_RCD */
4602 0x00000003, /* EMC_WR_RCD */
4603 0x00000002, /* EMC_RRD */
4604 0x00000002, /* EMC_REXT */
4605 0x00000000, /* EMC_WEXT */
4606 0x00000001, /* EMC_WDV */
4607 0x00000004, /* EMC_QUSE */
4608 0x00000001, /* EMC_QRST */
4609 0x0000000b, /* EMC_QSAFE */
4610 0x0000000a, /* EMC_RDV */
4611 0x00000303, /* EMC_REFRESH */
4612 0x00000000, /* EMC_BURST_REFRESH_NUM */
4613 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
4614 0x00000001, /* EMC_PDEX2WR */
4615 0x00000001, /* EMC_PDEX2RD */
4616 0x00000003, /* EMC_PCHG2PDEN */
4617 0x00000000, /* EMC_ACT2PDEN */
4618 0x00000001, /* EMC_AR2PDEN */
4619 0x00000007, /* EMC_RW2PDEN */
4620 0x0000001d, /* EMC_TXSR */
4621 0x0000001d, /* EMC_TXSRDLL */
4622 0x00000004, /* EMC_TCKE */
4623 0x0000000b, /* EMC_TFAW */
4624 0x00000005, /* EMC_TRPAB */
4625 0x00000004, /* EMC_TCLKSTABLE */
4626 0x00000002, /* EMC_TCLKSTOP */
4627 0x00000351, /* EMC_TREFBW */
4628 0x00000005, /* EMC_QUSE_EXTRA */
4629 0x00000004, /* EMC_FBIO_CFG6 */
4630 0x00000000, /* EMC_ODT_WRITE */
4631 0x00000000, /* EMC_ODT_READ */
4632 0x00004282, /* EMC_FBIO_CFG5 */
4633 0x004400a4, /* EMC_CFG_DIG_DLL */
4634 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4635 0x00070000, /* EMC_DLL_XFORM_DQS0 */
4636 0x00070000, /* EMC_DLL_XFORM_DQS1 */
4637 0x00070000, /* EMC_DLL_XFORM_DQS2 */
4638 0x00070000, /* EMC_DLL_XFORM_DQS3 */
4639 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4640 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4641 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4642 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4643 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4644 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4645 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4646 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4647 0x00000018, /* EMC_DLL_XFORM_QUSE4 */
4648 0x00000018, /* EMC_DLL_XFORM_QUSE5 */
4649 0x00000018, /* EMC_DLL_XFORM_QUSE6 */
4650 0x00000018, /* EMC_DLL_XFORM_QUSE7 */
4651 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4652 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4653 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4654 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4655 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4656 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4657 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4658 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4659 0x00078000, /* EMC_DLL_XFORM_DQ0 */
4660 0x00078000, /* EMC_DLL_XFORM_DQ1 */
4661 0x00078000, /* EMC_DLL_XFORM_DQ2 */
4662 0x00078000, /* EMC_DLL_XFORM_DQ3 */
4663 0x000d0220, /* EMC_XM2CMDPADCTRL */
4664 0x0800201c, /* EMC_XM2DQSPADCTRL2 */
4665 0x00000000, /* EMC_XM2DQPADCTRL2 */
4666 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4667 0x01f1f008, /* EMC_XM2COMPPADCTRL */
4668 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4669 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4670 0x08000068, /* EMC_XM2QUSEPADCTRL */
4671 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4672 0x00000802, /* EMC_CTT_TERM_CTRL */
4673 0x00064000, /* EMC_ZCAL_INTERVAL */
4674 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
4675 0x00090009, /* EMC_MRS_WAIT_CNT */
4676 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4677 0x00000000, /* EMC_CTT */
4678 0x00000000, /* EMC_CTT_DURATION */
4679 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
4680 0x00000003, /* MC_EMEM_ARB_CFG */
4681 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4682 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4683 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4684 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
4685 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
4686 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
4687 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4688 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4689 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4690 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
4691 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4692 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
4693 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
4694 0x02030001, /* MC_EMEM_ARB_DA_TURNS */
4695 0x00070506, /* MC_EMEM_ARB_DA_COVERS */
4696 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
4697 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4698 0xd0000000, /* EMC_FBIO_SPARE */
4699 0xff00ff00, /* EMC_CFG_RSV */
4700 },
4701 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
4702 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4703 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4704 0x00000000, /* Mode Register 0 */
4705 0x00010042, /* Mode Register 1 */
4706 0x00020001, /* Mode Register 2 */
4707 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4708 },
4709 {
4710 0x32, /* Rev 3.2 */
4711 533000, /* SDRAM frequency */
4712 {
4713 0x0000001f, /* EMC_RC */
4714 0x00000045, /* EMC_RFC */
4715 0x00000016, /* EMC_RAS */
4716 0x00000009, /* EMC_RP */
4717 0x00000008, /* EMC_R2W */
4718 0x00000009, /* EMC_W2R */
4719 0x00000003, /* EMC_R2P */
4720 0x0000000d, /* EMC_W2P */
4721 0x00000009, /* EMC_RD_RCD */
4722 0x00000009, /* EMC_WR_RCD */
4723 0x00000005, /* EMC_RRD */
4724 0x00000003, /* EMC_REXT */
4725 0x00000000, /* EMC_WEXT */
4726 0x00000004, /* EMC_WDV */
4727 0x00000009, /* EMC_QUSE */
4728 0x00000006, /* EMC_QRST */
4729 0x0000000c, /* EMC_QSAFE */
4730 0x00000010, /* EMC_RDV */
4731 0x000007df, /* EMC_REFRESH */
4732 0x00000000, /* EMC_BURST_REFRESH_NUM */
4733 0x000001f7, /* EMC_PRE_REFRESH_REQ_CNT */
4734 0x00000003, /* EMC_PDEX2WR */
4735 0x00000003, /* EMC_PDEX2RD */
4736 0x00000009, /* EMC_PCHG2PDEN */
4737 0x00000000, /* EMC_ACT2PDEN */
4738 0x00000001, /* EMC_AR2PDEN */
4739 0x0000000f, /* EMC_RW2PDEN */
4740 0x0000004b, /* EMC_TXSR */
4741 0x0000004b, /* EMC_TXSRDLL */
4742 0x00000008, /* EMC_TCKE */
4743 0x0000001b, /* EMC_TFAW */
4744 0x0000000c, /* EMC_TRPAB */
4745 0x00000004, /* EMC_TCLKSTABLE */
4746 0x00000002, /* EMC_TCLKSTOP */
4747 0x000008aa, /* EMC_TREFBW */
4748 0x00000000, /* EMC_QUSE_EXTRA */
4749 0x00000006, /* EMC_FBIO_CFG6 */
4750 0x00000000, /* EMC_ODT_WRITE */
4751 0x00000000, /* EMC_ODT_READ */
4752 0x00006282, /* EMC_FBIO_CFG5 */
4753 0xf0120091, /* EMC_CFG_DIG_DLL */
4754 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4755 0x00000008, /* EMC_DLL_XFORM_DQS0 */
4756 0x00000008, /* EMC_DLL_XFORM_DQS1 */
4757 0x00000008, /* EMC_DLL_XFORM_DQS2 */
4758 0x00000008, /* EMC_DLL_XFORM_DQS3 */
4759 0x00000010, /* EMC_DLL_XFORM_DQS4 */
4760 0x00000010, /* EMC_DLL_XFORM_DQS5 */
4761 0x00000010, /* EMC_DLL_XFORM_DQS6 */
4762 0x00000010, /* EMC_DLL_XFORM_DQS7 */
4763 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4764 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4765 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4766 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4767 0x00000008, /* EMC_DLL_XFORM_QUSE4 */
4768 0x00000008, /* EMC_DLL_XFORM_QUSE5 */
4769 0x00000008, /* EMC_DLL_XFORM_QUSE6 */
4770 0x00000008, /* EMC_DLL_XFORM_QUSE7 */
4771 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4772 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4773 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4774 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4775 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4776 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4777 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4778 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4779 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
4780 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
4781 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
4782 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
4783 0x00070220, /* EMC_XM2CMDPADCTRL */
4784 0x0400003d, /* EMC_XM2DQSPADCTRL2 */
4785 0x00000000, /* EMC_XM2DQPADCTRL2 */
4786 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4787 0x01f1f408, /* EMC_XM2COMPPADCTRL */
4788 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4789 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
4790 0x08000068, /* EMC_XM2QUSEPADCTRL */
4791 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4792 0x00000802, /* EMC_CTT_TERM_CTRL */
4793 0x00064000, /* EMC_ZCAL_INTERVAL */
4794 0x000000c0, /* EMC_ZCAL_WAIT_CNT */
4795 0x000e000e, /* EMC_MRS_WAIT_CNT */
4796 0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
4797 0x00000000, /* EMC_CTT */
4798 0x00000000, /* EMC_CTT_DURATION */
4799 0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
4800 0x00000008, /* MC_EMEM_ARB_CFG */
4801 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4802 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
4803 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
4804 0x00000010, /* MC_EMEM_ARB_TIMING_RC */
4805 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
4806 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
4807 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
4808 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4809 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4810 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
4811 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
4812 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
4813 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
4814 0x05040002, /* MC_EMEM_ARB_DA_TURNS */
4815 0x00110b10, /* MC_EMEM_ARB_DA_COVERS */
4816 0x71c81811, /* MC_EMEM_ARB_MISC0 */
4817 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4818 0x60000000, /* EMC_FBIO_SPARE */
4819 0xff00ff88, /* EMC_CFG_RSV */
4820 },
4821 0x00000030, /* EMC_ZCAL_WAIT_CNT after clock change */
4822 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4823 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4824 0x00000000, /* Mode Register 0 */
4825 0x000100c2, /* Mode Register 1 */
4826 0x00020006, /* Mode Register 2 */
4827 0x00000000, /* EMC_CFG.DYN_SELF_REF */
4828 },
4829};
4830
4831static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
4832 {
4833 0x32, /* Rev 3.2 */
4834 51000, /* SDRAM frequency */
4835 {
4836 0x00000002, /* EMC_RC */
4837 0x00000008, /* EMC_RFC */
4838 0x00000001, /* EMC_RAS */
4839 0x00000000, /* EMC_RP */
4840 0x00000002, /* EMC_R2W */
4841 0x0000000a, /* EMC_W2R */
4842 0x00000003, /* EMC_R2P */
4843 0x0000000b, /* EMC_W2P */
4844 0x00000000, /* EMC_RD_RCD */
4845 0x00000000, /* EMC_WR_RCD */
4846 0x00000003, /* EMC_RRD */
4847 0x00000001, /* EMC_REXT */
4848 0x00000000, /* EMC_WEXT */
4849 0x00000005, /* EMC_WDV */
4850 0x00000005, /* EMC_QUSE */
4851 0x00000004, /* EMC_QRST */
4852 0x00000009, /* EMC_QSAFE */
4853 0x0000000b, /* EMC_RDV */
4854 0x00000181, /* EMC_REFRESH */
4855 0x00000000, /* EMC_BURST_REFRESH_NUM */
4856 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
4857 0x00000002, /* EMC_PDEX2WR */
4858 0x00000002, /* EMC_PDEX2RD */
4859 0x00000001, /* EMC_PCHG2PDEN */
4860 0x00000000, /* EMC_ACT2PDEN */
4861 0x00000007, /* EMC_AR2PDEN */
4862 0x0000000f, /* EMC_RW2PDEN */
4863 0x00000009, /* EMC_TXSR */
4864 0x00000009, /* EMC_TXSRDLL */
4865 0x00000004, /* EMC_TCKE */
4866 0x00000002, /* EMC_TFAW */
4867 0x00000000, /* EMC_TRPAB */
4868 0x00000004, /* EMC_TCLKSTABLE */
4869 0x00000005, /* EMC_TCLKSTOP */
4870 0x0000018e, /* EMC_TREFBW */
4871 0x00000006, /* EMC_QUSE_EXTRA */
4872 0x00000004, /* EMC_FBIO_CFG6 */
4873 0x00000000, /* EMC_ODT_WRITE */
4874 0x00000000, /* EMC_ODT_READ */
4875 0x00004288, /* EMC_FBIO_CFG5 */
4876 0x007800a4, /* EMC_CFG_DIG_DLL */
4877 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4878 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
4879 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
4880 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
4881 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
4882 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
4883 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
4884 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
4885 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
4886 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4887 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4888 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4889 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4890 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
4891 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
4892 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
4893 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
4894 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4895 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4896 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4897 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4898 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4899 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4900 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4901 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4902 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
4903 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
4904 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
4905 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
4906 0x000002a0, /* EMC_XM2CMDPADCTRL */
4907 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
4908 0x00000000, /* EMC_XM2DQPADCTRL2 */
4909 0x77ffc084, /* EMC_XM2CLKPADCTRL */
4910 0x01f1f108, /* EMC_XM2COMPPADCTRL */
4911 0x05057404, /* EMC_XM2VTTGENPADCTRL */
4912 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
4913 0x08000168, /* EMC_XM2QUSEPADCTRL */
4914 0x08000000, /* EMC_XM2DQSPADCTRL3 */
4915 0x00000802, /* EMC_CTT_TERM_CTRL */
4916 0x00000000, /* EMC_ZCAL_INTERVAL */
4917 0x00000040, /* EMC_ZCAL_WAIT_CNT */
4918 0x000c000c, /* EMC_MRS_WAIT_CNT */
4919 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4920 0x00000000, /* EMC_CTT */
4921 0x00000000, /* EMC_CTT_DURATION */
4922 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
4923 0x00010001, /* MC_EMEM_ARB_CFG */
4924 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4925 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4926 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4927 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
4928 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
4929 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
4930 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4931 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4932 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4933 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
4934 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
4935 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
4936 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
4937 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
4938 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
4939 0x73430303, /* MC_EMEM_ARB_MISC0 */
4940 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4941 0xe8000000, /* EMC_FBIO_SPARE */
4942 0xff00ff00, /* EMC_CFG_RSV */
4943 },
4944 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
4945 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4946 0x00000001, /* EMC_CFG.PERIODIC_QRST */
4947 0x80001221, /* Mode Register 0 */
4948 0x80100003, /* Mode Register 1 */
4949 0x80200008, /* Mode Register 2 */
4950 0x00000001, /* EMC_CFG.DYN_SELF_REF */
4951 },
4952 {
4953 0x32, /* Rev 3.2 */
4954 102000, /* SDRAM frequency */
4955 {
4956 0x00000005, /* EMC_RC */
4957 0x00000010, /* EMC_RFC */
4958 0x00000003, /* EMC_RAS */
4959 0x00000001, /* EMC_RP */
4960 0x00000002, /* EMC_R2W */
4961 0x0000000a, /* EMC_W2R */
4962 0x00000003, /* EMC_R2P */
4963 0x0000000b, /* EMC_W2P */
4964 0x00000001, /* EMC_RD_RCD */
4965 0x00000001, /* EMC_WR_RCD */
4966 0x00000003, /* EMC_RRD */
4967 0x00000001, /* EMC_REXT */
4968 0x00000000, /* EMC_WEXT */
4969 0x00000005, /* EMC_WDV */
4970 0x00000005, /* EMC_QUSE */
4971 0x00000004, /* EMC_QRST */
4972 0x00000009, /* EMC_QSAFE */
4973 0x0000000c, /* EMC_RDV */
4974 0x00000303, /* EMC_REFRESH */
4975 0x00000000, /* EMC_BURST_REFRESH_NUM */
4976 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
4977 0x00000002, /* EMC_PDEX2WR */
4978 0x00000002, /* EMC_PDEX2RD */
4979 0x00000001, /* EMC_PCHG2PDEN */
4980 0x00000000, /* EMC_ACT2PDEN */
4981 0x00000007, /* EMC_AR2PDEN */
4982 0x0000000f, /* EMC_RW2PDEN */
4983 0x00000012, /* EMC_TXSR */
4984 0x00000012, /* EMC_TXSRDLL */
4985 0x00000004, /* EMC_TCKE */
4986 0x00000004, /* EMC_TFAW */
4987 0x00000000, /* EMC_TRPAB */
4988 0x00000004, /* EMC_TCLKSTABLE */
4989 0x00000005, /* EMC_TCLKSTOP */
4990 0x0000031c, /* EMC_TREFBW */
4991 0x00000006, /* EMC_QUSE_EXTRA */
4992 0x00000004, /* EMC_FBIO_CFG6 */
4993 0x00000000, /* EMC_ODT_WRITE */
4994 0x00000000, /* EMC_ODT_READ */
4995 0x00004288, /* EMC_FBIO_CFG5 */
4996 0x007800a4, /* EMC_CFG_DIG_DLL */
4997 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4998 0x000fc000, /* EMC_DLL_XFORM_DQS0 */
4999 0x000fc000, /* EMC_DLL_XFORM_DQS1 */
5000 0x000fc000, /* EMC_DLL_XFORM_DQS2 */
5001 0x000fc000, /* EMC_DLL_XFORM_DQS3 */
5002 0x000fc000, /* EMC_DLL_XFORM_DQS4 */
5003 0x000fc000, /* EMC_DLL_XFORM_DQS5 */
5004 0x000fc000, /* EMC_DLL_XFORM_DQS6 */
5005 0x000fc000, /* EMC_DLL_XFORM_DQS7 */
5006 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
5007 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
5008 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
5009 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
5010 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
5011 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
5012 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
5013 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
5014 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
5015 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
5016 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
5017 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
5018 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
5019 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
5020 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
5021 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
5022 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
5023 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
5024 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
5025 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
5026 0x000002a0, /* EMC_XM2CMDPADCTRL */
5027 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
5028 0x00000000, /* EMC_XM2DQPADCTRL2 */
5029 0x77ffc084, /* EMC_XM2CLKPADCTRL */
5030 0x01f1f108, /* EMC_XM2COMPPADCTRL */
5031 0x03037404, /* EMC_XM2VTTGENPADCTRL */
5032 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
5033 0x08000168, /* EMC_XM2QUSEPADCTRL */
5034 0x08000000, /* EMC_XM2DQSPADCTRL3 */
5035 0x00000802, /* EMC_CTT_TERM_CTRL */
5036 0x00000000, /* EMC_ZCAL_INTERVAL */
5037 0x00000040, /* EMC_ZCAL_WAIT_CNT */
5038 0x000c000c, /* EMC_MRS_WAIT_CNT */
5039 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
5040 0x00000000, /* EMC_CTT */
5041 0x00000000, /* EMC_CTT_DURATION */
5042 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
5043 0x00000001, /* MC_EMEM_ARB_CFG */
5044 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
5045 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
5046 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
5047 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
5048 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
5049 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
5050 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
5051 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
5052 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
5053 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
5054 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
5055 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
5056 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
5057 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
5058 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
5059 0x72830504, /* MC_EMEM_ARB_MISC0 */
5060 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
5061 0xe8000000, /* EMC_FBIO_SPARE */
5062 0xff00ff00, /* EMC_CFG_RSV */
5063 },
5064 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
5065 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
5066 0x00000001, /* EMC_CFG.PERIODIC_QRST */
5067 0x80001221, /* Mode Register 0 */
5068 0x80100003, /* Mode Register 1 */
5069 0x80200008, /* Mode Register 2 */
5070 0x00000001, /* EMC_CFG.DYN_SELF_REF */
5071 },
5072 {
5073 0x32, /* Rev 3.2 */
5074 204000, /* SDRAM frequency */
5075 {
5076 0x0000000a, /* EMC_RC */
5077 0x00000020, /* EMC_RFC */
5078 0x00000007, /* EMC_RAS */
5079 0x00000002, /* EMC_RP */
5080 0x00000002, /* EMC_R2W */
5081 0x0000000a, /* EMC_W2R */
5082 0x00000003, /* EMC_R2P */
5083 0x0000000b, /* EMC_W2P */
5084 0x00000002, /* EMC_RD_RCD */
5085 0x00000002, /* EMC_WR_RCD */
5086 0x00000003, /* EMC_RRD */
5087 0x00000001, /* EMC_REXT */
5088 0x00000000, /* EMC_WEXT */
5089 0x00000005, /* EMC_WDV */
5090 0x00000006, /* EMC_QUSE */
5091 0x00000004, /* EMC_QRST */
5092 0x00000009, /* EMC_QSAFE */
5093 0x0000000b, /* EMC_RDV */
5094 0x00000607, /* EMC_REFRESH */
5095 0x00000000, /* EMC_BURST_REFRESH_NUM */
5096 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
5097 0x00000002, /* EMC_PDEX2WR */
5098 0x00000002, /* EMC_PDEX2RD */
5099 0x00000001, /* EMC_PCHG2PDEN */
5100 0x00000000, /* EMC_ACT2PDEN */
5101 0x00000007, /* EMC_AR2PDEN */
5102 0x0000000f, /* EMC_RW2PDEN */
5103 0x00000023, /* EMC_TXSR */
5104 0x00000023, /* EMC_TXSRDLL */
5105 0x00000004, /* EMC_TCKE */
5106 0x00000007, /* EMC_TFAW */
5107 0x00000000, /* EMC_TRPAB */
5108 0x00000004, /* EMC_TCLKSTABLE */
5109 0x00000005, /* EMC_TCLKSTOP */
5110 0x00000638, /* EMC_TREFBW */
5111 0x00000007, /* EMC_QUSE_EXTRA */
5112 0x00000004, /* EMC_FBIO_CFG6 */
5113 0x00000000, /* EMC_ODT_WRITE */
5114 0x00000000, /* EMC_ODT_READ */
5115 0x00004288, /* EMC_FBIO_CFG5 */
5116 0x004400a4, /* EMC_CFG_DIG_DLL */
5117 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
5118 0x00080000, /* EMC_DLL_XFORM_DQS0 */
5119 0x00080000, /* EMC_DLL_XFORM_DQS1 */
5120 0x00080000, /* EMC_DLL_XFORM_DQS2 */
5121 0x00080000, /* EMC_DLL_XFORM_DQS3 */
5122 0x00080000, /* EMC_DLL_XFORM_DQS4 */
5123 0x00080000, /* EMC_DLL_XFORM_DQS5 */
5124 0x00080000, /* EMC_DLL_XFORM_DQS6 */
5125 0x00080000, /* EMC_DLL_XFORM_DQS7 */
5126 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
5127 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
5128 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
5129 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
5130 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
5131 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
5132 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
5133 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
5134 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
5135 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
5136 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
5137 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
5138 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
5139 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
5140 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
5141 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
5142 0x00080000, /* EMC_DLL_XFORM_DQ0 */
5143 0x00080000, /* EMC_DLL_XFORM_DQ1 */
5144 0x00080000, /* EMC_DLL_XFORM_DQ2 */
5145 0x00080000, /* EMC_DLL_XFORM_DQ3 */
5146 0x000002a0, /* EMC_XM2CMDPADCTRL */
5147 0x0800211c, /* EMC_XM2DQSPADCTRL2 */
5148 0x00000000, /* EMC_XM2DQPADCTRL2 */
5149 0x77fff884, /* EMC_XM2CLKPADCTRL */
5150 0x01f1f108, /* EMC_XM2COMPPADCTRL */
5151 0x05057404, /* EMC_XM2VTTGENPADCTRL */
5152 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
5153 0x08000168, /* EMC_XM2QUSEPADCTRL */
5154 0x08000000, /* EMC_XM2DQSPADCTRL3 */
5155 0x00000802, /* EMC_CTT_TERM_CTRL */
5156 0x00020000, /* EMC_ZCAL_INTERVAL */
5157 0x00000100, /* EMC_ZCAL_WAIT_CNT */
5158 0x000c000c, /* EMC_MRS_WAIT_CNT */
5159 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
5160 0x00000000, /* EMC_CTT */
5161 0x00000000, /* EMC_CTT_DURATION */
5162 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
5163 0x00000003, /* MC_EMEM_ARB_CFG */
5164 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
5165 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
5166 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
5167 0x00000005, /* MC_EMEM_ARB_TIMING_RC */
5168 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
5169 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
5170 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
5171 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
5172 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
5173 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
5174 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
5175 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
5176 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
5177 0x06020102, /* MC_EMEM_ARB_DA_TURNS */
5178 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
5179 0x72440a06, /* MC_EMEM_ARB_MISC0 */
5180 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
5181 0xe8000000, /* EMC_FBIO_SPARE */
5182 0xff00ff00, /* EMC_CFG_RSV */
5183 },
5184 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
5185 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
5186 0x00000001, /* EMC_CFG.PERIODIC_QRST */
5187 0x80001221, /* Mode Register 0 */
5188 0x80100003, /* Mode Register 1 */
5189 0x80200008, /* Mode Register 2 */
5190 0x00000001, /* EMC_CFG.DYN_SELF_REF */
5191 },
5192 {
5193 0x32, /* Rev 3.2 */
5194 333500, /* SDRAM frequency */
5195 {
5196 0x0000000f, /* EMC_RC */
5197 0x00000034, /* EMC_RFC */
5198 0x0000000a, /* EMC_RAS */
5199 0x00000003, /* EMC_RP */
5200 0x00000003, /* EMC_R2W */
5201 0x00000008, /* EMC_W2R */
5202 0x00000002, /* EMC_R2P */
5203 0x00000009, /* EMC_W2P */
5204 0x00000003, /* EMC_RD_RCD */
5205 0x00000003, /* EMC_WR_RCD */
5206 0x00000002, /* EMC_RRD */
5207 0x00000001, /* EMC_REXT */
5208 0x00000000, /* EMC_WEXT */
5209 0x00000004, /* EMC_WDV */
5210 0x00000006, /* EMC_QUSE */
5211 0x00000004, /* EMC_QRST */
5212 0x0000000a, /* EMC_QSAFE */
5213 0x0000000c, /* EMC_RDV */
5214 0x000009e9, /* EMC_REFRESH */
5215 0x00000000, /* EMC_BURST_REFRESH_NUM */
5216 0x0000027a, /* EMC_PRE_REFRESH_REQ_CNT */
5217 0x00000001, /* EMC_PDEX2WR */
5218 0x00000008, /* EMC_PDEX2RD */
5219 0x00000001, /* EMC_PCHG2PDEN */
5220 0x00000000, /* EMC_ACT2PDEN */
5221 0x00000007, /* EMC_AR2PDEN */
5222 0x0000000e, /* EMC_RW2PDEN */
5223 0x00000039, /* EMC_TXSR */
5224 0x00000200, /* EMC_TXSRDLL */
5225 0x00000004, /* EMC_TCKE */
5226 0x0000000a, /* EMC_TFAW */
5227 0x00000000, /* EMC_TRPAB */
5228 0x00000004, /* EMC_TCLKSTABLE */
5229 0x00000005, /* EMC_TCLKSTOP */
5230 0x00000a2a, /* EMC_TREFBW */
5231 0x00000000, /* EMC_QUSE_EXTRA */
5232 0x00000006, /* EMC_FBIO_CFG6 */
5233 0x00000000, /* EMC_ODT_WRITE */
5234 0x00000000, /* EMC_ODT_READ */
5235 0x00007088, /* EMC_FBIO_CFG5 */
5236 0x002600a4, /* EMC_CFG_DIG_DLL */
5237 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
5238 0x00014000, /* EMC_DLL_XFORM_DQS0 */
5239 0x00014000, /* EMC_DLL_XFORM_DQS1 */
5240 0x00014000, /* EMC_DLL_XFORM_DQS2 */
5241 0x00014000, /* EMC_DLL_XFORM_DQS3 */
5242 0x00014000, /* EMC_DLL_XFORM_DQS4 */
5243 0x00014000, /* EMC_DLL_XFORM_DQS5 */
5244 0x00014000, /* EMC_DLL_XFORM_DQS6 */
5245 0x00014000, /* EMC_DLL_XFORM_DQS7 */
5246 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
5247 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
5248 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
5249 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
5250 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
5251 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
5252 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
5253 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
5254 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
5255 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
5256 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
5257 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
5258 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
5259 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
5260 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
5261 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
5262 0x00050000, /* EMC_DLL_XFORM_DQ0 */
5263 0x00050000, /* EMC_DLL_XFORM_DQ1 */
5264 0x00050000, /* EMC_DLL_XFORM_DQ2 */
5265 0x00050000, /* EMC_DLL_XFORM_DQ3 */
5266 0x000002a0, /* EMC_XM2CMDPADCTRL */
5267 0x0800013d, /* EMC_XM2DQSPADCTRL2 */
5268 0x00000000, /* EMC_XM2DQPADCTRL2 */
5269 0x77fff884, /* EMC_XM2CLKPADCTRL */
5270 0x01f1f508, /* EMC_XM2COMPPADCTRL */
5271 0x05057404, /* EMC_XM2VTTGENPADCTRL */
5272 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
5273 0x080001e8, /* EMC_XM2QUSEPADCTRL */
5274 0x08000021, /* EMC_XM2DQSPADCTRL3 */
5275 0x00000802, /* EMC_CTT_TERM_CTRL */
5276 0x00020000, /* EMC_ZCAL_INTERVAL */
5277 0x00000100, /* EMC_ZCAL_WAIT_CNT */
5278 0x018b000c, /* EMC_MRS_WAIT_CNT */
5279 0xa0f11c1c, /* EMC_AUTO_CAL_CONFIG */
5280 0x00000000, /* EMC_CTT */
5281 0x00000000, /* EMC_CTT_DURATION */
5282 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
5283 0x00000005, /* MC_EMEM_ARB_CFG */
5284 0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
5285 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
5286 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
5287 0x00000008, /* MC_EMEM_ARB_TIMING_RC */
5288 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
5289 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
5290 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
5291 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
5292 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
5293 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
5294 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
5295 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
5296 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
5297 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
5298 0x000b0608, /* MC_EMEM_ARB_DA_COVERS */
5299 0x76850f09, /* MC_EMEM_ARB_MISC0 */
5300 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
5301 0xe8000000, /* EMC_FBIO_SPARE */
5302 0xff00ff89, /* EMC_CFG_RSV */
5303 },
5304 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
5305 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
5306 0x00000000, /* EMC_CFG.PERIODIC_QRST */
5307 0x80000321, /* Mode Register 0 */
5308 0x80100002, /* Mode Register 1 */
5309 0x80200000, /* Mode Register 2 */
5310 0x00000000, /* EMC_CFG.DYN_SELF_REF */
5311 },
5312 {
5313 0x32, /* Rev 3.2 */
5314 667000, /* SDRAM frequency */
5315 {
5316 0x00000020, /* EMC_RC */
5317 0x00000069, /* EMC_RFC */
5318 0x00000017, /* EMC_RAS */
5319 0x00000007, /* EMC_RP */
5320 0x00000005, /* EMC_R2W */
5321 0x0000000c, /* EMC_W2R */
5322 0x00000003, /* EMC_R2P */
5323 0x00000011, /* EMC_W2P */
5324 0x00000007, /* EMC_RD_RCD */
5325 0x00000007, /* EMC_WR_RCD */
5326 0x00000002, /* EMC_RRD */
5327 0x00000001, /* EMC_REXT */
5328 0x00000000, /* EMC_WEXT */
5329 0x00000007, /* EMC_WDV */
5330 0x0000000b, /* EMC_QUSE */
5331 0x00000009, /* EMC_QRST */
5332 0x0000000c, /* EMC_QSAFE */
5333 0x00000011, /* EMC_RDV */
5334 0x00001412, /* EMC_REFRESH */
5335 0x00000000, /* EMC_BURST_REFRESH_NUM */
5336 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
5337 0x00000002, /* EMC_PDEX2WR */
5338 0x0000000e, /* EMC_PDEX2RD */
5339 0x00000001, /* EMC_PCHG2PDEN */
5340 0x00000000, /* EMC_ACT2PDEN */
5341 0x0000000c, /* EMC_AR2PDEN */
5342 0x00000016, /* EMC_RW2PDEN */
5343 0x00000072, /* EMC_TXSR */
5344 0x00000200, /* EMC_TXSRDLL */
5345 0x00000005, /* EMC_TCKE */
5346 0x00000015, /* EMC_TFAW */
5347 0x00000000, /* EMC_TRPAB */
5348 0x00000006, /* EMC_TCLKSTABLE */
5349 0x00000007, /* EMC_TCLKSTOP */
5350 0x00001453, /* EMC_TREFBW */
5351 0x0000000c, /* EMC_QUSE_EXTRA */
5352 0x00000004, /* EMC_FBIO_CFG6 */
5353 0x00000000, /* EMC_ODT_WRITE */
5354 0x00000000, /* EMC_ODT_READ */
5355 0x00005088, /* EMC_FBIO_CFG5 */
5356 0xf00b0191, /* EMC_CFG_DIG_DLL */
5357 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
5358 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
5359 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
5360 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
5361 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
5362 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
5363 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
5364 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
5365 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
5366 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
5367 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
5368 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
5369 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
5370 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
5371 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
5372 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
5373 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
5374 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
5375 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
5376 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
5377 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
5378 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
5379 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
5380 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
5381 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
5382 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
5383 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
5384 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
5385 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
5386 0x000002a0, /* EMC_XM2CMDPADCTRL */
5387 0x0700013d, /* EMC_XM2DQSPADCTRL2 */
5388 0x22220000, /* EMC_XM2DQPADCTRL2 */
5389 0x77fff884, /* EMC_XM2CLKPADCTRL */
5390 0x01f1f501, /* EMC_XM2COMPPADCTRL */
5391 0x07077404, /* EMC_XM2VTTGENPADCTRL */
5392 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
5393 0x080001e8, /* EMC_XM2QUSEPADCTRL */
5394 0x07000021, /* EMC_XM2DQSPADCTRL3 */
5395 0x00000802, /* EMC_CTT_TERM_CTRL */
5396 0x00020000, /* EMC_ZCAL_INTERVAL */
5397 0x00000100, /* EMC_ZCAL_WAIT_CNT */
5398 0x0156000c, /* EMC_MRS_WAIT_CNT */
5399 0xa0f11d1d, /* EMC_AUTO_CAL_CONFIG */
5400 0x00000000, /* EMC_CTT */
5401 0x00000000, /* EMC_CTT_DURATION */
5402 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
5403 0x0000000a, /* MC_EMEM_ARB_CFG */
5404 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
5405 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
5406 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
5407 0x00000010, /* MC_EMEM_ARB_TIMING_RC */
5408 0x0000000b, /* MC_EMEM_ARB_TIMING_RAS */
5409 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
5410 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
5411 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
5412 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
5413 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
5414 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
5415 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
5416 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
5417 0x08040202, /* MC_EMEM_ARB_DA_TURNS */
5418 0x00130b10, /* MC_EMEM_ARB_DA_COVERS */
5419 0x734a1f11, /* MC_EMEM_ARB_MISC0 */
5420 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
5421 0xe8000000, /* EMC_FBIO_SPARE */
5422 0xff00ff49, /* EMC_CFG_RSV */
5423 },
5424 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
5425 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
5426 0x00000001, /* EMC_CFG.PERIODIC_QRST */
5427 0x80000b71, /* Mode Register 0 */
5428 0x80100002, /* Mode Register 1 */
5429 0x80200018, /* Mode Register 2 */
5430 0x00000000, /* EMC_CFG.DYN_SELF_REF */
5431 },
5432};
5433
5434static const u32 pm269_bit_swap_map[32] = {
5435 /* DDR bit # SoC bit # */
5436 [0] = 0x1 << 1,
5437 [1] = 0x1 << 2,
5438 [2] = 0x1 << 3,
5439 [3] = 0x1 << 0,
5440 [4] = 0x1 << 7,
5441 [5] = 0x1 << 5,
5442 [6] = 0x1 << 6,
5443 [7] = 0x1 << 4,
5444
5445 [8] = 0x1 << 13,
5446 [9] = 0x1 << 9,
5447 [10] = 0x1 << 8,
5448 [11] = 0x1 << 12,
5449 [12] = 0x1 << 11,
5450 [13] = 0x1 << 10,
5451 [14] = 0x1 << 14,
5452 [15] = 0x1 << 15,
5453
5454 [16] = 0x1 << 20,
5455 [17] = 0x1 << 23,
5456 [18] = 0x1 << 16,
5457 [19] = 0x1 << 19,
5458 [20] = 0x1 << 18,
5459 [21] = 0x1 << 21,
5460 [22] = 0x1 << 22,
5461 [23] = 0x1 << 17,
5462
5463 [24] = 0x1 << 27,
5464 [25] = 0x1 << 30,
5465 [26] = 0x1 << 31,
5466 [27] = 0x1 << 28,
5467 [28] = 0x1 << 26,
5468 [29] = 0x1 << 25,
5469 [30] = 0x1 << 24,
5470 [31] = 0x1 << 29,
5471};
5472
5473int cardhu_emc_init(void)
5474{
5475 struct board_info board;
5476
5477 tegra_get_board_info(&board);
5478
5479 switch (board.board_id) {
5480 case BOARD_PM269:
5481 tegra_init_dram_bit_map(pm269_bit_swap_map,
5482 ARRAY_SIZE(pm269_bit_swap_map));
5483 /* fall through */
5484 case BOARD_E1257:
5485 if (MEMORY_TYPE(board.sku) == SKU_MEMORY_ELPIDA)
5486 tegra_init_emc(cardhu_emc_tables_edb8132b2ma,
5487 ARRAY_SIZE(cardhu_emc_tables_edb8132b2ma));
5488 else
5489 tegra_init_emc(cardhu_emc_tables_k4p8g304eb,
5490 ARRAY_SIZE(cardhu_emc_tables_k4p8g304eb));
5491 break;
5492
5493 case BOARD_PM305:
5494 break;
5495 case BOARD_PM311:
5496 tegra_init_emc(cardhu_emc_tables_h5tc2g_pm311,
5497 ARRAY_SIZE(cardhu_emc_tables_h5tc2g_pm311));
5498 break;
5499 default:
5500 if (tegra_get_revision() == TEGRA_REVISION_A01)
5501 tegra_init_emc(cardhu_emc_tables_h5tc2g,
5502 ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
5503 else if (MEMORY_TYPE(board.sku) == SKU_MEMORY_CARDHU_1GB_1R)
5504 tegra_init_emc(cardhu_emc_tables_h5tc2g_a2,
5505 ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2));
5506 else if (MEMORY_TYPE(board.sku) ==
5507 SKU_MEMORY_CARDHU_2GB_1R_HYK0)
5508 tegra_init_emc(cardhu_emc_tables_k4b4g0846b_hyk0,
5509 ARRAY_SIZE(cardhu_emc_tables_k4b4g0846b_hyk0));
5510 else if (MEMORY_TYPE(board.sku) ==
5511 SKU_MEMORY_CARDHU_2GB_1R_HYNIX)
5512 tegra_init_emc(cardhu_emc_tables_h5tc2g_a2_2GB1R,
5513 ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2GB1R));
5514 break;
5515 }
5516
5517 return 0;
5518}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 08:55:28 -0400