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1/*
2 * arch/arm/mach-tegra/board-aruba.c
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/ctype.h>
25#include <linux/platform_device.h>
26#include <linux/clk.h>
27#include <linux/serial_8250.h>
28#include <linux/i2c.h>
29#include <linux/i2c/panjit_ts.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/i2c-tegra.h>
33#include <linux/gpio.h>
34#include <linux/gpio_keys.h>
35#include <linux/input.h>
36#include <linux/platform_data/tegra_usb.h>
37#include <mach/clk.h>
38#include <mach/iomap.h>
39#include <mach/irqs.h>
40#include <mach/pinmux.h>
41#include <mach/iomap.h>
42#include <mach/io.h>
43#include <mach/i2s.h>
44#include <mach/audio.h>
45#include <mach/tegra_das.h>
46#include <asm/mach-types.h>
47#include <asm/mach/arch.h>
48#include <mach/usb_phy.h>
49#include <mach/nand.h>
50#include "board.h"
51#include "clock.h"
52#include "board-aruba.h"
53#include "devices.h"
54#include "gpio-names.h"
55#include "fuse.h"
56
57#define ENABLE_OTG 0
58
59static struct plat_serial8250_port debug_uart_platform_data[] = {
60 {
61 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
62 .mapbase = TEGRA_UARTA_BASE,
63 .irq = INT_UARTA,
64 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
65 .type = PORT_TEGRA,
66 .iotype = UPIO_MEM,
67 .regshift = 2,
68 .uartclk = 13000000,
69 }, {
70 .flags = 0,
71 }
72};
73
74static struct platform_device debug_uart = {
75 .name = "serial8250",
76 .id = PLAT8250_DEV_PLATFORM,
77 .dev = {
78 .platform_data = debug_uart_platform_data,
79 },
80};
81
82/* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
83static struct tegra_utmip_config utmi_phy_config[] = {
84 [0] = {
85 .hssync_start_delay = 0,
86 .idle_wait_delay = 17,
87 .elastic_limit = 16,
88 .term_range_adj = 6,
89 .xcvr_setup = 15,
90 .xcvr_lsfslew = 2,
91 .xcvr_lsrslew = 2,
92 },
93 [1] = {
94 .hssync_start_delay = 0,
95 .idle_wait_delay = 17,
96 .elastic_limit = 16,
97 .term_range_adj = 6,
98 .xcvr_setup = 8,
99 .xcvr_lsfslew = 2,
100 .xcvr_lsrslew = 2,
101 },
102};
103
104/* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
105static struct tegra_ulpi_config ulpi_phy_config = {
106 .clk = "cdev2",
107};
108
109#ifdef CONFIG_BCM4329_RFKILL
110
111static struct resource aruba_bcm4329_rfkill_resources[] = {
112 {
113 .name = "bcm4329_nreset_gpio",
114 .start = TEGRA_GPIO_PU0,
115 .end = TEGRA_GPIO_PU0,
116 .flags = IORESOURCE_IO,
117 },
118 {
119 .name = "bcm4329_nshutdown_gpio",
120 .start = TEGRA_GPIO_PK2,
121 .end = TEGRA_GPIO_PK2,
122 .flags = IORESOURCE_IO,
123 },
124};
125
126static struct platform_device aruba_bcm4329_rfkill_device = {
127 .name = "bcm4329_rfkill",
128 .id = -1,
129 .num_resources = ARRAY_SIZE(aruba_bcm4329_rfkill_resources),
130 .resource = aruba_bcm4329_rfkill_resources,
131};
132
133static noinline void __init aruba_bt_rfkill(void)
134{
135 /*Add Clock Resource*/
136 clk_add_alias("bcm4329_32k_clk", aruba_bcm4329_rfkill_device.name, \
137 "blink", NULL);
138
139 platform_device_register(&aruba_bcm4329_rfkill_device);
140
141 return;
142}
143#else
144static inline void aruba_bt_rfkill(void) { }
145#endif
146
147static __initdata struct tegra_clk_init_table aruba_clk_init_table[] = {
148 /* name parent rate enabled */
149 { "uarta", "clk_m", 13000000, true},
150 { "uartb", "clk_m", 13000000, true},
151 { "uartc", "clk_m", 13000000, true},
152 { "uartd", "clk_m", 13000000, true},
153 { "uarte", "clk_m", 13000000, true},
154 { "pll_m", NULL, 0, true},
155 { "blink", "clk_32k", 32768, false},
156 { "pll_p_out4", "pll_p", 24000000, true },
157 { "pwm", "clk_32k", 32768, false},
158 { "blink", "clk_32k", 32768, false},
159 { "pll_a", NULL, 56448000, true},
160 { "pll_a_out0", NULL, 11289600, true},
161 { "i2s1", "pll_a_out0", 11289600, true},
162 { "i2s2", "pll_a_out0", 11289600, true},
163 { "d_audio", "pll_a_out0", 11289600, false},
164 { "audio_2x", "audio", 22579200, true},
165 { NULL, NULL, 0, 0},
166};
167
168struct tegra_das_platform_data tegra_das_pdata = {
169 .tegra_dap_port_info_table = {
170 /* I2S0 <--> NULL */
171 [0] = {
172 .dac_port = tegra_das_port_none,
173 .codec_type = tegra_audio_codec_type_none,
174 .device_property = {
175 .num_channels = 0,
176 .bits_per_sample = 0,
177 .rate = 0,
178 .master = 0,
179 .lrck_high_left = false,
180 .dac_dap_data_comm_format = 0,
181 },
182 },
183 /* I2S1 <--> Hifi Codec */
184 [1] = {
185 .dac_port = tegra_das_port_i2s1,
186 .codec_type = tegra_audio_codec_type_hifi,
187 .device_property = {
188 .num_channels = 2,
189 .bits_per_sample = 16,
190 .rate = 48000,
191 .master = 0,
192 .lrck_high_left = false,
193 .dac_dap_data_comm_format =
194 dac_dap_data_format_i2s,
195 },
196 },
197 /* I2s2 <--> BB */
198 [2] = {
199 .dac_port = tegra_das_port_i2s2,
200 .codec_type = tegra_audio_codec_type_baseband,
201 .device_property = {
202 .num_channels = 1,
203 .bits_per_sample = 16,
204 .rate = 16000,
205 .master = 0,
206 .lrck_high_left = true,
207 .dac_dap_data_comm_format =
208 dac_dap_data_format_dsp,
209 },
210 },
211 /* I2s3 <--> BT */
212 [3] = {
213 .dac_port = tegra_das_port_i2s3,
214 .codec_type = tegra_audio_codec_type_bluetooth,
215 .device_property = {
216 .num_channels = 1,
217 .bits_per_sample = 16,
218 .rate = 8000,
219 .master = 0,
220 .lrck_high_left = false,
221 .dac_dap_data_comm_format =
222 dac_dap_data_format_dsp,
223 },
224 },
225 [4] = {
226 .dac_port = tegra_das_port_none,
227 .codec_type = tegra_audio_codec_type_none,
228 .device_property = {
229 .num_channels = 0,
230 .bits_per_sample = 0,
231 .rate = 0,
232 .master = 0,
233 .lrck_high_left = false,
234 .dac_dap_data_comm_format = 0,
235 },
236 },
237 },
238};
239
240static struct i2c_board_info __initdata aruba_i2c_bus1_board_info[] = {
241 {
242 I2C_BOARD_INFO("wm8903", 0x1a),
243 },
244};
245
246static struct tegra_i2c_platform_data aruba_i2c1_platform_data = {
247 .adapter_nr = 0,
248 .bus_count = 1,
249 .bus_clk_rate = { 100000, 0 },
250};
251
252#if 0 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
253static const struct tegra_pingroup_config i2c2_ddc = {
254 .pingroup = TEGRA_PINGROUP_DDC,
255 .func = TEGRA_MUX_I2C2,
256};
257
258static const struct tegra_pingroup_config i2c2_gen2 = {
259 .pingroup = TEGRA_PINGROUP_PTA,
260 .func = TEGRA_MUX_I2C2,
261};
262#endif
263
264static struct tegra_i2c_platform_data aruba_i2c2_platform_data = {
265 .adapter_nr = 1,
266 .bus_count = 2,
267 .bus_clk_rate = { 100000, 100000 },
268#if 0 /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
269 .bus_mux = { &i2c2_ddc, &i2c2_gen2 },
270 .bus_mux_len = { 1, 1 },
271#endif
272};
273
274static struct tegra_i2c_platform_data aruba_i2c3_platform_data = {
275 .adapter_nr = 3,
276 .bus_count = 1,
277 .bus_clk_rate = { 100000, 0 },
278};
279
280static struct tegra_i2c_platform_data aruba_i2c4_platform_data = {
281 .adapter_nr = 4,
282 .bus_count = 1,
283 .bus_clk_rate = { 100000, 0 },
284};
285
286static struct tegra_i2c_platform_data aruba_i2c5_platform_data = {
287 .adapter_nr = 5,
288 .bus_count = 1,
289 .bus_clk_rate = { 100000, 0 },
290};
291
292static void aruba_i2c_init(void)
293{
294 tegra_i2c_device1.dev.platform_data = &aruba_i2c1_platform_data;
295 tegra_i2c_device2.dev.platform_data = &aruba_i2c2_platform_data;
296 tegra_i2c_device3.dev.platform_data = &aruba_i2c3_platform_data;
297 tegra_i2c_device4.dev.platform_data = &aruba_i2c4_platform_data;
298 tegra_i2c_device5.dev.platform_data = &aruba_i2c5_platform_data;
299
300 i2c_register_board_info(0, aruba_i2c_bus1_board_info, 1);
301
302 platform_device_register(&tegra_i2c_device5);
303 platform_device_register(&tegra_i2c_device4);
304 platform_device_register(&tegra_i2c_device3);
305 platform_device_register(&tegra_i2c_device2);
306 platform_device_register(&tegra_i2c_device1);
307}
308
309#define GPIO_KEY(_id, _gpio, _iswake) \
310 { \
311 .code = _id, \
312 .gpio = TEGRA_GPIO_##_gpio, \
313 .active_low = 1, \
314 .desc = #_id, \
315 .type = EV_KEY, \
316 .wakeup = _iswake, \
317 .debounce_interval = 10, \
318 }
319
320// !!!FIXME!!! THESE ARE VENTANA DEFINITIONS
321static struct gpio_keys_button aruba_keys[] = {
322 [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
323 [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
324 [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
325 [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
326 [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
327 [5] = GPIO_KEY(KEY_POWER, PV2, 1),
328};
329
330static struct gpio_keys_platform_data aruba_keys_platform_data = {
331 .buttons = aruba_keys,
332 .nbuttons = ARRAY_SIZE(aruba_keys),
333};
334
335static struct platform_device aruba_keys_device = {
336 .name = "gpio-keys",
337 .id = 0,
338 .dev = {
339 .platform_data = &aruba_keys_platform_data,
340 },
341};
342
343static struct resource tegra_rtc_resources[] = {
344 [0] = {
345 .start = TEGRA_RTC_BASE,
346 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = INT_RTC,
351 .end = INT_RTC,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device tegra_rtc_device = {
357 .name = "tegra_rtc",
358 .id = -1,
359 .resource = tegra_rtc_resources,
360 .num_resources = ARRAY_SIZE(tegra_rtc_resources),
361};
362
363#if defined(CONFIG_MTD_NAND_TEGRA)
364static struct resource nand_resources[] = {
365 [0] = {
366 .start = INT_NANDFLASH,
367 .end = INT_NANDFLASH,
368 .flags = IORESOURCE_IRQ
369 },
370 [1] = {
371 .start = TEGRA_NAND_BASE,
372 .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
373 .flags = IORESOURCE_MEM
374 }
375};
376
377static struct tegra_nand_chip_parms nand_chip_parms[] = {
378 /* Samsung K5E2G1GACM */
379 [0] = {
380 .vendor_id = 0xEC,
381 .device_id = 0xAA,
382 .capacity = 256,
383 .timing = {
384 .trp = 21,
385 .trh = 15,
386 .twp = 21,
387 .twh = 15,
388 .tcs = 31,
389 .twhr = 60,
390 .tcr_tar_trr = 20,
391 .twb = 100,
392 .trp_resp = 30,
393 .tadl = 100,
394 },
395 },
396 /* Hynix H5PS1GB3EFR */
397 [1] = {
398 .vendor_id = 0xAD,
399 .device_id = 0xDC,
400 .capacity = 512,
401 .timing = {
402 .trp = 12,
403 .trh = 10,
404 .twp = 12,
405 .twh = 10,
406 .tcs = 20,
407 .twhr = 80,
408 .tcr_tar_trr = 20,
409 .twb = 100,
410 .trp_resp = 20,
411 .tadl = 70,
412 },
413 },
414};
415
416struct tegra_nand_platform nand_data = {
417 .max_chips = 8,
418 .chip_parms = nand_chip_parms,
419 .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
420};
421
422struct platform_device tegra_nand_device = {
423 .name = "tegra_nand",
424 .id = -1,
425 .resource = nand_resources,
426 .num_resources = ARRAY_SIZE(nand_resources),
427 .dev = {
428 .platform_data = &nand_data,
429 },
430};
431#endif
432
433static struct platform_device *aruba_devices[] __initdata = {
434#if ENABLE_OTG
435 &tegra_otg_device,
436#endif
437 &debug_uart,
438 &tegra_uartb_device,
439 &tegra_uartc_device,
440 &tegra_uartd_device,
441 &tegra_uarte_device,
442 &tegra_pmu_device,
443 &tegra_rtc_device,
444 &tegra_udc_device,
445#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
446 &tegra_smmu_device,
447#endif
448 &aruba_keys_device,
449 &tegra_wdt_device,
450#if defined(CONFIG_SND_HDA_TEGRA)
451 &tegra_hda_device,
452#endif
453 &tegra_avp_device,
454#if defined(CONFIG_MTD_NAND_TEGRA)
455 &tegra_nand_device,
456#endif
457};
458
459static void aruba_keys_init(void)
460{
461 int i;
462
463 for (i = 0; i < ARRAY_SIZE(aruba_keys); i++)
464 tegra_gpio_enable(aruba_keys[i].gpio);
465}
466
467static int __init aruba_touch_init(void)
468{
469 return 0;
470}
471
472
473static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
474 [0] = {
475 .phy_config = &utmi_phy_config[0],
476 .operating_mode = TEGRA_USB_HOST,
477 .power_down_on_bus_suspend = 0,
478 },
479 [1] = {
480 .phy_config = &ulpi_phy_config,
481 .operating_mode = TEGRA_USB_HOST,
482 .power_down_on_bus_suspend = 1,
483 },
484 [2] = {
485 .phy_config = &utmi_phy_config[1],
486 .operating_mode = TEGRA_USB_HOST,
487 .power_down_on_bus_suspend = 0,
488 },
489};
490
491
492static void aruba_usb_init(void)
493{
494 tegra_ehci2_device.dev.platform_data=&tegra_ehci_pdata[1];
495 platform_device_register(&tegra_ehci2_device);
496}
497
498#ifdef CONFIG_SATA_AHCI_TEGRA
499static void aruba_sata_init(void)
500{
501 platform_device_register(&tegra_sata_device);
502}
503#else
504static void aruba_sata_init(void) { }
505#endif
506
507static void __init tegra_aruba_init(void)
508{
509 tegra_clk_init_from_table(aruba_clk_init_table);
510 aruba_pinmux_init();
511
512 platform_add_devices(aruba_devices, ARRAY_SIZE(aruba_devices));
513
514 aruba_sdhci_init();
515 aruba_i2c_init();
516 aruba_regulator_init();
517 aruba_touch_init();
518 aruba_keys_init();
519 aruba_usb_init();
520 aruba_panel_init();
521 aruba_sensors_init();
522 aruba_bt_rfkill();
523 aruba_sata_init();
524 tegra_release_bootloader_fb();
525}
526
527static void __init tegra_aruba_reserve(void)
528{
529#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
530 tegra_reserve(0, SZ_4M, 0);
531#else
532 tegra_reserve(SZ_32M, SZ_4M, 0);
533#endif
534}
535
536MACHINE_START(ARUBA, "aruba")
537 .boot_params = 0x80000100,
538 .map_io = tegra_map_common_io,
539 .reserve = tegra_aruba_reserve,
540 .init_early = tegra_init_early,
541 .init_irq = tegra_init_irq,
542 .timer = &tegra_timer,
543 .init_machine = tegra_aruba_init,
544MACHINE_END
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