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Diffstat (limited to 'arch/arm/mach-tegra/ahb.c')
-rw-r--r-- | arch/arm/mach-tegra/ahb.c | 218 |
1 files changed, 218 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/ahb.c b/arch/arm/mach-tegra/ahb.c new file mode 100644 index 00000000000..b7f3fb5219b --- /dev/null +++ b/arch/arm/mach-tegra/ahb.c | |||
@@ -0,0 +1,218 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/ahb.c | ||
3 | * | ||
4 | * Copyright (C) 2011 Google, Inc. | ||
5 | * | ||
6 | * Author: | ||
7 | * Jay Cheng <jacheng@nvidia.com> | ||
8 | * James Wylder <james.wylder@motorola.com> | ||
9 | * Benoit Goby <benoit@android.com> | ||
10 | * Colin Cross <ccross@android.com> | ||
11 | * | ||
12 | * This software is licensed under the terms of the GNU General Public | ||
13 | * License version 2, as published by the Free Software Foundation, and | ||
14 | * may be copied, distributed, and modified under those terms. | ||
15 | * | ||
16 | * This program is distributed in the hope that it will be useful, | ||
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
19 | * GNU General Public License for more details. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/io.h> | ||
26 | #include <linux/syscore_ops.h> | ||
27 | |||
28 | #include <mach/iomap.h> | ||
29 | |||
30 | #define AHB_ARBITRATION_DISABLE 0x00 | ||
31 | #define AHB_ARBITRATION_PRIORITY_CTRL 0x04 | ||
32 | #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29) | ||
33 | #define PRIORITY_SELECT_USB BIT(6) | ||
34 | #define PRIORITY_SELECT_USB2 BIT(18) | ||
35 | #define PRIORITY_SELECT_USB3 BIT(17) | ||
36 | |||
37 | #define AHB_GIZMO_AHB_MEM 0x0c | ||
38 | #define ENB_FAST_REARBITRATE BIT(2) | ||
39 | #define DONT_SPLIT_AHB_WR BIT(7) | ||
40 | |||
41 | #define AHB_GIZMO_APB_DMA 0x10 | ||
42 | #define AHB_GIZMO_IDE 0x18 | ||
43 | #define AHB_GIZMO_USB 0x1c | ||
44 | #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x20 | ||
45 | #define AHB_GIZMO_CPU_AHB_BRIDGE 0x24 | ||
46 | #define AHB_GIZMO_COP_AHB_BRIDGE 0x28 | ||
47 | #define AHB_GIZMO_XBAR_APB_CTLR 0x2c | ||
48 | #define AHB_GIZMO_VCP_AHB_BRIDGE 0x30 | ||
49 | #define AHB_GIZMO_NAND 0x3c | ||
50 | #define AHB_GIZMO_SDMMC4 0x44 | ||
51 | #define AHB_GIZMO_XIO 0x48 | ||
52 | #define AHB_GIZMO_BSEV 0x60 | ||
53 | #define AHB_GIZMO_BSEA 0x70 | ||
54 | #define AHB_GIZMO_NOR 0x74 | ||
55 | #define AHB_GIZMO_USB2 0x78 | ||
56 | #define AHB_GIZMO_USB3 0x7c | ||
57 | #define IMMEDIATE BIT(18) | ||
58 | |||
59 | #define AHB_GIZMO_SDMMC1 0x80 | ||
60 | #define AHB_GIZMO_SDMMC2 0x84 | ||
61 | #define AHB_GIZMO_SDMMC3 0x88 | ||
62 | #define AHB_MEM_PREFETCH_CFG_X 0xd8 | ||
63 | #define AHB_ARBITRATION_XBAR_CTRL 0xdc | ||
64 | #define AHB_MEM_PREFETCH_CFG3 0xe0 | ||
65 | #define AHB_MEM_PREFETCH_CFG4 0xe4 | ||
66 | #define AHB_MEM_PREFETCH_CFG1 0xec | ||
67 | #define AHB_MEM_PREFETCH_CFG2 0xf0 | ||
68 | #define PREFETCH_ENB BIT(31) | ||
69 | #define MST_ID(x) (((x) & 0x1f) << 26) | ||
70 | #define AHBDMA_MST_ID MST_ID(5) | ||
71 | #define USB_MST_ID MST_ID(6) | ||
72 | #define USB2_MST_ID MST_ID(18) | ||
73 | #define USB3_MST_ID MST_ID(17) | ||
74 | #define ADDR_BNDRY(x) (((x) & 0xf) << 21) | ||
75 | #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0) | ||
76 | |||
77 | #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xf8 | ||
78 | |||
79 | |||
80 | static inline unsigned long gizmo_readl(unsigned long offset) | ||
81 | { | ||
82 | return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset)); | ||
83 | } | ||
84 | |||
85 | static inline void gizmo_writel(unsigned long value, unsigned long offset) | ||
86 | { | ||
87 | writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset)); | ||
88 | } | ||
89 | |||
90 | static u32 ahb_gizmo[29]; | ||
91 | |||
92 | #ifdef CONFIG_PM | ||
93 | int tegra_ahbgizmo_suspend(void) | ||
94 | { | ||
95 | ahb_gizmo[0] = gizmo_readl(AHB_ARBITRATION_DISABLE); | ||
96 | ahb_gizmo[1] = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL); | ||
97 | ahb_gizmo[2] = gizmo_readl(AHB_GIZMO_AHB_MEM); | ||
98 | ahb_gizmo[3] = gizmo_readl(AHB_GIZMO_APB_DMA); | ||
99 | ahb_gizmo[4] = gizmo_readl(AHB_GIZMO_IDE); | ||
100 | ahb_gizmo[5] = gizmo_readl(AHB_GIZMO_USB); | ||
101 | ahb_gizmo[6] = gizmo_readl(AHB_GIZMO_AHB_XBAR_BRIDGE); | ||
102 | ahb_gizmo[7] = gizmo_readl(AHB_GIZMO_CPU_AHB_BRIDGE); | ||
103 | ahb_gizmo[8] = gizmo_readl(AHB_GIZMO_COP_AHB_BRIDGE); | ||
104 | ahb_gizmo[9] = gizmo_readl(AHB_GIZMO_XBAR_APB_CTLR); | ||
105 | ahb_gizmo[10] = gizmo_readl(AHB_GIZMO_VCP_AHB_BRIDGE); | ||
106 | ahb_gizmo[11] = gizmo_readl(AHB_GIZMO_NAND); | ||
107 | ahb_gizmo[12] = gizmo_readl(AHB_GIZMO_SDMMC4); | ||
108 | ahb_gizmo[13] = gizmo_readl(AHB_GIZMO_XIO); | ||
109 | ahb_gizmo[14] = gizmo_readl(AHB_GIZMO_BSEV); | ||
110 | ahb_gizmo[15] = gizmo_readl(AHB_GIZMO_BSEA); | ||
111 | ahb_gizmo[16] = gizmo_readl(AHB_GIZMO_NOR); | ||
112 | ahb_gizmo[17] = gizmo_readl(AHB_GIZMO_USB2); | ||
113 | ahb_gizmo[18] = gizmo_readl(AHB_GIZMO_USB3); | ||
114 | ahb_gizmo[19] = gizmo_readl(AHB_GIZMO_SDMMC1); | ||
115 | ahb_gizmo[20] = gizmo_readl(AHB_GIZMO_SDMMC2); | ||
116 | ahb_gizmo[21] = gizmo_readl(AHB_GIZMO_SDMMC3); | ||
117 | ahb_gizmo[22] = gizmo_readl(AHB_MEM_PREFETCH_CFG_X); | ||
118 | ahb_gizmo[23] = gizmo_readl(AHB_ARBITRATION_XBAR_CTRL); | ||
119 | ahb_gizmo[24] = gizmo_readl(AHB_MEM_PREFETCH_CFG3); | ||
120 | ahb_gizmo[25] = gizmo_readl(AHB_MEM_PREFETCH_CFG4); | ||
121 | ahb_gizmo[26] = gizmo_readl(AHB_MEM_PREFETCH_CFG1); | ||
122 | ahb_gizmo[27] = gizmo_readl(AHB_MEM_PREFETCH_CFG2); | ||
123 | ahb_gizmo[28] = gizmo_readl(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID); | ||
124 | return 0; | ||
125 | } | ||
126 | |||
127 | void tegra_ahbgizmo_resume(void) | ||
128 | { | ||
129 | gizmo_writel(ahb_gizmo[0], AHB_ARBITRATION_DISABLE); | ||
130 | gizmo_writel(ahb_gizmo[1], AHB_ARBITRATION_PRIORITY_CTRL); | ||
131 | gizmo_writel(ahb_gizmo[2], AHB_GIZMO_AHB_MEM); | ||
132 | gizmo_writel(ahb_gizmo[3], AHB_GIZMO_APB_DMA); | ||
133 | gizmo_writel(ahb_gizmo[4], AHB_GIZMO_IDE); | ||
134 | gizmo_writel(ahb_gizmo[5], AHB_GIZMO_USB); | ||
135 | gizmo_writel(ahb_gizmo[6], AHB_GIZMO_AHB_XBAR_BRIDGE); | ||
136 | gizmo_writel(ahb_gizmo[7], AHB_GIZMO_CPU_AHB_BRIDGE); | ||
137 | gizmo_writel(ahb_gizmo[8], AHB_GIZMO_COP_AHB_BRIDGE); | ||
138 | gizmo_writel(ahb_gizmo[9], AHB_GIZMO_XBAR_APB_CTLR); | ||
139 | gizmo_writel(ahb_gizmo[10], AHB_GIZMO_VCP_AHB_BRIDGE); | ||
140 | gizmo_writel(ahb_gizmo[11], AHB_GIZMO_NAND); | ||
141 | gizmo_writel(ahb_gizmo[12], AHB_GIZMO_SDMMC4); | ||
142 | gizmo_writel(ahb_gizmo[13], AHB_GIZMO_XIO); | ||
143 | gizmo_writel(ahb_gizmo[14], AHB_GIZMO_BSEV); | ||
144 | gizmo_writel(ahb_gizmo[15], AHB_GIZMO_BSEA); | ||
145 | gizmo_writel(ahb_gizmo[16], AHB_GIZMO_NOR); | ||
146 | gizmo_writel(ahb_gizmo[17], AHB_GIZMO_USB2); | ||
147 | gizmo_writel(ahb_gizmo[18], AHB_GIZMO_USB3); | ||
148 | gizmo_writel(ahb_gizmo[19], AHB_GIZMO_SDMMC1); | ||
149 | gizmo_writel(ahb_gizmo[20], AHB_GIZMO_SDMMC2); | ||
150 | gizmo_writel(ahb_gizmo[21], AHB_GIZMO_SDMMC3); | ||
151 | gizmo_writel(ahb_gizmo[22], AHB_MEM_PREFETCH_CFG_X); | ||
152 | gizmo_writel(ahb_gizmo[23], AHB_ARBITRATION_XBAR_CTRL); | ||
153 | gizmo_writel(ahb_gizmo[24], AHB_MEM_PREFETCH_CFG3); | ||
154 | gizmo_writel(ahb_gizmo[25], AHB_MEM_PREFETCH_CFG4); | ||
155 | gizmo_writel(ahb_gizmo[26], AHB_MEM_PREFETCH_CFG1); | ||
156 | gizmo_writel(ahb_gizmo[27], AHB_MEM_PREFETCH_CFG2); | ||
157 | gizmo_writel(ahb_gizmo[28], AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID); | ||
158 | } | ||
159 | #else | ||
160 | #define tegra_ahbgizmo_suspend NULL | ||
161 | #define tegra_ahbgizmo_resume NULL | ||
162 | #endif | ||
163 | |||
164 | static struct syscore_ops tegra_ahbgizmo_syscore_ops = { | ||
165 | .suspend = tegra_ahbgizmo_suspend, | ||
166 | .resume = tegra_ahbgizmo_resume, | ||
167 | }; | ||
168 | |||
169 | static int __init tegra_init_ahb_gizmo_settings(void) | ||
170 | { | ||
171 | unsigned long val; | ||
172 | |||
173 | val = gizmo_readl(AHB_GIZMO_AHB_MEM); | ||
174 | val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; | ||
175 | gizmo_writel(val, AHB_GIZMO_AHB_MEM); | ||
176 | |||
177 | val = gizmo_readl(AHB_GIZMO_USB); | ||
178 | val |= IMMEDIATE; | ||
179 | gizmo_writel(val, AHB_GIZMO_USB); | ||
180 | |||
181 | val = gizmo_readl(AHB_GIZMO_USB2); | ||
182 | val |= IMMEDIATE; | ||
183 | gizmo_writel(val, AHB_GIZMO_USB2); | ||
184 | |||
185 | val = gizmo_readl(AHB_GIZMO_USB3); | ||
186 | val |= IMMEDIATE; | ||
187 | gizmo_writel(val, AHB_GIZMO_USB3); | ||
188 | |||
189 | val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL); | ||
190 | val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3 | ||
191 | | AHB_PRIORITY_WEIGHT(7); | ||
192 | gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL); | ||
193 | |||
194 | val = gizmo_readl(AHB_MEM_PREFETCH_CFG1); | ||
195 | val &= ~MST_ID(~0); | ||
196 | val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); | ||
197 | gizmo_writel(val, AHB_MEM_PREFETCH_CFG1); | ||
198 | |||
199 | val = gizmo_readl(AHB_MEM_PREFETCH_CFG2); | ||
200 | val &= ~MST_ID(~0); | ||
201 | val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); | ||
202 | gizmo_writel(val, AHB_MEM_PREFETCH_CFG2); | ||
203 | |||
204 | val = gizmo_readl(AHB_MEM_PREFETCH_CFG3); | ||
205 | val &= ~MST_ID(~0); | ||
206 | val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); | ||
207 | gizmo_writel(val, AHB_MEM_PREFETCH_CFG3); | ||
208 | |||
209 | val = gizmo_readl(AHB_MEM_PREFETCH_CFG4); | ||
210 | val &= ~MST_ID(~0); | ||
211 | val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); | ||
212 | gizmo_writel(val, AHB_MEM_PREFETCH_CFG4); | ||
213 | |||
214 | register_syscore_ops(&tegra_ahbgizmo_syscore_ops); | ||
215 | |||
216 | return 0; | ||
217 | } | ||
218 | postcore_initcall(tegra_init_ahb_gizmo_settings); | ||