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diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
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1/*
2 * arch/arm/mach-spear3xx/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <mach/hardware.h>
16
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE
28 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
29 teq \irqstat, #0
30 beq 1001f @ this will set/reset
31 @ zero register
32 /*
33 * Following code will find bit position of least significang
34 * bit set in irqstat, using following equation
35 * least significant bit set in n = (n & ~(n-1))
36 */
37 sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
38 mvn \tmp, \tmp @ tmp = ~tmp
39 and \irqstat, \irqstat, \tmp @ irqstat &= tmp
40 /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
41 clz \tmp, \irqstat @ tmp = leading zeros
42 rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1
43
441001: /* EQ will be set if no irqs pending */
45 .endm