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-rw-r--r--arch/arm/mach-spear3xx/include/mach/entry-macro.S45
-rw-r--r--arch/arm/mach-spear3xx/include/mach/gpio.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/io.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/memory.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/vmalloc.h19
9 files changed, 319 insertions, 0 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
new file mode 100644
index 00000000000..53da4224ba3
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -0,0 +1,45 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <mach/hardware.h>
16
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE
28 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
29 teq \irqstat, #0
30 beq 1001f @ this will set/reset
31 @ zero register
32 /*
33 * Following code will find bit position of least significang
34 * bit set in irqstat, using following equation
35 * least significant bit set in n = (n & ~(n-1))
36 */
37 sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
38 mvn \tmp, \tmp @ tmp = ~tmp
39 and \irqstat, \irqstat, \tmp @ irqstat &= tmp
40 /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
41 clz \tmp, \irqstat @ tmp = leading zeros
42 rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1
43
441001: /* EQ will be set if no irqs pending */
45 .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
new file mode 100644
index 00000000000..451b2081bfc
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/gpio.h
3 *
4 * GPIO macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GPIO_H
15#define __MACH_GPIO_H
16
17#include <plat/gpio.h>
18
19#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
new file mode 100644
index 00000000000..30cff8a1f6b
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/io.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/io.h
3 *
4 * IO definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_IO_H
15#define __MACH_IO_H
16
17#include <plat/io.h>
18
19#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h
new file mode 100644
index 00000000000..51735221ea1
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/memory.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/memory.h
3 *
4 * Memory map for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_MEMORY_H
15#define __MACH_MEMORY_H
16
17#include <plat/memory.h>
18
19#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
new file mode 100644
index 00000000000..3b6ea072904
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -0,0 +1,54 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
new file mode 100644
index 00000000000..1567d0da725
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -0,0 +1,58 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
new file mode 100644
index 00000000000..8cfa83fa129
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -0,0 +1,67 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
new file mode 100644
index 00000000000..92cee6335c9
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/system.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/system.h
3 *
4 * SPEAr3xx Machine family specific architecture functions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SYSTEM_H
15#define __MACH_SYSTEM_H
16
17#include <plat/system.h>
18
19#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
new file mode 100644
index 00000000000..df977b3c9a6
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/vmalloc.h
3 *
4 * Defining Vmalloc area for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_VMALLOC_H
15#define __MACH_VMALLOC_H
16
17#include <plat/vmalloc.h>
18
19#endif /* __MACH_VMALLOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 06:52:50 -0400