diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-sh7372.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-sh7372.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2e3e11ee7c4..ff0494f3d00 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
@@ -38,6 +38,8 @@ | |||
38 | static struct plat_sci_port scif0_platform_data = { | 38 | static struct plat_sci_port scif0_platform_data = { |
39 | .mapbase = 0xe6c40000, | 39 | .mapbase = 0xe6c40000, |
40 | .flags = UPF_BOOT_AUTOCONF, | 40 | .flags = UPF_BOOT_AUTOCONF, |
41 | .scscr = SCSCR_RE | SCSCR_TE, | ||
42 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
41 | .type = PORT_SCIFA, | 43 | .type = PORT_SCIFA, |
42 | .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), | 44 | .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), |
43 | evt2irq(0x0c00), evt2irq(0x0c00) }, | 45 | evt2irq(0x0c00), evt2irq(0x0c00) }, |
@@ -55,6 +57,8 @@ static struct platform_device scif0_device = { | |||
55 | static struct plat_sci_port scif1_platform_data = { | 57 | static struct plat_sci_port scif1_platform_data = { |
56 | .mapbase = 0xe6c50000, | 58 | .mapbase = 0xe6c50000, |
57 | .flags = UPF_BOOT_AUTOCONF, | 59 | .flags = UPF_BOOT_AUTOCONF, |
60 | .scscr = SCSCR_RE | SCSCR_TE, | ||
61 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
58 | .type = PORT_SCIFA, | 62 | .type = PORT_SCIFA, |
59 | .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), | 63 | .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), |
60 | evt2irq(0x0c20), evt2irq(0x0c20) }, | 64 | evt2irq(0x0c20), evt2irq(0x0c20) }, |
@@ -72,6 +76,8 @@ static struct platform_device scif1_device = { | |||
72 | static struct plat_sci_port scif2_platform_data = { | 76 | static struct plat_sci_port scif2_platform_data = { |
73 | .mapbase = 0xe6c60000, | 77 | .mapbase = 0xe6c60000, |
74 | .flags = UPF_BOOT_AUTOCONF, | 78 | .flags = UPF_BOOT_AUTOCONF, |
79 | .scscr = SCSCR_RE | SCSCR_TE, | ||
80 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
75 | .type = PORT_SCIFA, | 81 | .type = PORT_SCIFA, |
76 | .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), | 82 | .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), |
77 | evt2irq(0x0c40), evt2irq(0x0c40) }, | 83 | evt2irq(0x0c40), evt2irq(0x0c40) }, |
@@ -89,6 +95,8 @@ static struct platform_device scif2_device = { | |||
89 | static struct plat_sci_port scif3_platform_data = { | 95 | static struct plat_sci_port scif3_platform_data = { |
90 | .mapbase = 0xe6c70000, | 96 | .mapbase = 0xe6c70000, |
91 | .flags = UPF_BOOT_AUTOCONF, | 97 | .flags = UPF_BOOT_AUTOCONF, |
98 | .scscr = SCSCR_RE | SCSCR_TE, | ||
99 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
92 | .type = PORT_SCIFA, | 100 | .type = PORT_SCIFA, |
93 | .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), | 101 | .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), |
94 | evt2irq(0x0c60), evt2irq(0x0c60) }, | 102 | evt2irq(0x0c60), evt2irq(0x0c60) }, |
@@ -106,6 +114,8 @@ static struct platform_device scif3_device = { | |||
106 | static struct plat_sci_port scif4_platform_data = { | 114 | static struct plat_sci_port scif4_platform_data = { |
107 | .mapbase = 0xe6c80000, | 115 | .mapbase = 0xe6c80000, |
108 | .flags = UPF_BOOT_AUTOCONF, | 116 | .flags = UPF_BOOT_AUTOCONF, |
117 | .scscr = SCSCR_RE | SCSCR_TE, | ||
118 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
109 | .type = PORT_SCIFA, | 119 | .type = PORT_SCIFA, |
110 | .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), | 120 | .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), |
111 | evt2irq(0x0d20), evt2irq(0x0d20) }, | 121 | evt2irq(0x0d20), evt2irq(0x0d20) }, |
@@ -123,6 +133,8 @@ static struct platform_device scif4_device = { | |||
123 | static struct plat_sci_port scif5_platform_data = { | 133 | static struct plat_sci_port scif5_platform_data = { |
124 | .mapbase = 0xe6cb0000, | 134 | .mapbase = 0xe6cb0000, |
125 | .flags = UPF_BOOT_AUTOCONF, | 135 | .flags = UPF_BOOT_AUTOCONF, |
136 | .scscr = SCSCR_RE | SCSCR_TE, | ||
137 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
126 | .type = PORT_SCIFA, | 138 | .type = PORT_SCIFA, |
127 | .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), | 139 | .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), |
128 | evt2irq(0x0d40), evt2irq(0x0d40) }, | 140 | evt2irq(0x0d40), evt2irq(0x0d40) }, |
@@ -140,6 +152,8 @@ static struct platform_device scif5_device = { | |||
140 | static struct plat_sci_port scif6_platform_data = { | 152 | static struct plat_sci_port scif6_platform_data = { |
141 | .mapbase = 0xe6c30000, | 153 | .mapbase = 0xe6c30000, |
142 | .flags = UPF_BOOT_AUTOCONF, | 154 | .flags = UPF_BOOT_AUTOCONF, |
155 | .scscr = SCSCR_RE | SCSCR_TE, | ||
156 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
143 | .type = PORT_SCIFB, | 157 | .type = PORT_SCIFB, |
144 | .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), | 158 | .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), |
145 | evt2irq(0x0d60), evt2irq(0x0d60) }, | 159 | evt2irq(0x0d60), evt2irq(0x0d60) }, |