aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-shmobile
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/board-g3evm.c372
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c415
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c355
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c366
-rw-r--r--arch/arm/mach-shmobile/entry-gic.S18
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S34
-rw-r--r--arch/arm/mach-shmobile/include/mach/gpio.h48
-rw-r--r--arch/arm/mach-shmobile/include/mach/io.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7367.h332
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7377.h360
-rw-r--r--arch/arm/mach-shmobile/include/mach/vmalloc.h7
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c440
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c646
-rw-r--r--arch/arm/mach-shmobile/localtimer.c26
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7367.c1801
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7377.c1767
-rw-r--r--arch/arm/mach-shmobile/pm_runtime.c66
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c448
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c469
19 files changed, 7979 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
new file mode 100644
index 00000000000..ef4613b993a
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -0,0 +1,372 @@
1/*
2 * G3EVM board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h>
29#include <linux/mtd/sh_flctl.h>
30#include <linux/usb/r8a66597.h>
31#include <linux/io.h>
32#include <linux/gpio.h>
33#include <linux/input.h>
34#include <linux/input/sh_keysc.h>
35#include <mach/sh7367.h>
36#include <mach/common.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/time.h>
41
42/*
43 * IrDA
44 *
45 * S67: 5bit : ON power
46 * : 6bit : ON remote control
47 * OFF IrDA
48 */
49
50static struct mtd_partition nor_flash_partitions[] = {
51 {
52 .name = "loader",
53 .offset = 0x00000000,
54 .size = 512 * 1024,
55 },
56 {
57 .name = "bootenv",
58 .offset = MTDPART_OFS_APPEND,
59 .size = 512 * 1024,
60 },
61 {
62 .name = "kernel_ro",
63 .offset = MTDPART_OFS_APPEND,
64 .size = 8 * 1024 * 1024,
65 .mask_flags = MTD_WRITEABLE,
66 },
67 {
68 .name = "kernel",
69 .offset = MTDPART_OFS_APPEND,
70 .size = 8 * 1024 * 1024,
71 },
72 {
73 .name = "data",
74 .offset = MTDPART_OFS_APPEND,
75 .size = MTDPART_SIZ_FULL,
76 },
77};
78
79static struct physmap_flash_data nor_flash_data = {
80 .width = 2,
81 .parts = nor_flash_partitions,
82 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
83};
84
85static struct resource nor_flash_resources[] = {
86 [0] = {
87 .start = 0x00000000,
88 .end = 0x08000000 - 1,
89 .flags = IORESOURCE_MEM,
90 }
91};
92
93static struct platform_device nor_flash_device = {
94 .name = "physmap-flash",
95 .dev = {
96 .platform_data = &nor_flash_data,
97 },
98 .num_resources = ARRAY_SIZE(nor_flash_resources),
99 .resource = nor_flash_resources,
100};
101
102/* USBHS */
103static void usb_host_port_power(int port, int power)
104{
105 if (!power) /* only power-on supported for now */
106 return;
107
108 /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
109 __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
110}
111
112static struct r8a66597_platdata usb_host_data = {
113 .on_chip = 1,
114 .port_power = usb_host_port_power,
115};
116
117static struct resource usb_host_resources[] = {
118 [0] = {
119 .name = "USBHS",
120 .start = 0xe6890000,
121 .end = 0xe68900e5,
122 .flags = IORESOURCE_MEM,
123 },
124 [1] = {
125 .start = evt2irq(0xa20), /* USBHS_USHI0 */
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct platform_device usb_host_device = {
131 .name = "r8a66597_hcd",
132 .id = 0,
133 .dev = {
134 .platform_data = &usb_host_data,
135 .dma_mask = NULL,
136 .coherent_dma_mask = 0xffffffff,
137 },
138 .num_resources = ARRAY_SIZE(usb_host_resources),
139 .resource = usb_host_resources,
140};
141
142/* KEYSC */
143static struct sh_keysc_info keysc_info = {
144 .mode = SH_KEYSC_MODE_5,
145 .scan_timing = 3,
146 .delay = 100,
147 .keycodes = {
148 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
149 KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
150 KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
151 KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
152 KEY_WAKEUP, KEY_COFFEE, KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
153 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
154 },
155};
156
157static struct resource keysc_resources[] = {
158 [0] = {
159 .name = "KEYSC",
160 .start = 0xe61b0000,
161 .end = 0xe61b000f,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 .start = evt2irq(0xbe0), /* KEYSC_KEY */
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device keysc_device = {
171 .name = "sh_keysc",
172 .num_resources = ARRAY_SIZE(keysc_resources),
173 .resource = keysc_resources,
174 .dev = {
175 .platform_data = &keysc_info,
176 },
177};
178
179static struct mtd_partition nand_partition_info[] = {
180 {
181 .name = "system",
182 .offset = 0,
183 .size = 64 * 1024 * 1024,
184 },
185 {
186 .name = "userdata",
187 .offset = MTDPART_OFS_APPEND,
188 .size = 128 * 1024 * 1024,
189 },
190 {
191 .name = "cache",
192 .offset = MTDPART_OFS_APPEND,
193 .size = 64 * 1024 * 1024,
194 },
195};
196
197static struct resource nand_flash_resources[] = {
198 [0] = {
199 .start = 0xe6a30000,
200 .end = 0xe6a3009b,
201 .flags = IORESOURCE_MEM,
202 }
203};
204
205static struct sh_flctl_platform_data nand_flash_data = {
206 .parts = nand_partition_info,
207 .nr_parts = ARRAY_SIZE(nand_partition_info),
208 .flcmncr_val = QTSEL_E | FCKSEL_E | TYPESEL_SET | NANWF_E
209 | SHBUSSEL | SEL_16BIT,
210};
211
212static struct platform_device nand_flash_device = {
213 .name = "sh_flctl",
214 .resource = nand_flash_resources,
215 .num_resources = ARRAY_SIZE(nand_flash_resources),
216 .dev = {
217 .platform_data = &nand_flash_data,
218 },
219};
220
221static struct resource irda_resources[] = {
222 [0] = {
223 .start = 0xE6D00000,
224 .end = 0xE6D01FD4 - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = evt2irq(0x480), /* IRDA */
229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device irda_device = {
234 .name = "sh_irda",
235 .id = -1,
236 .resource = irda_resources,
237 .num_resources = ARRAY_SIZE(irda_resources),
238};
239
240static struct platform_device *g3evm_devices[] __initdata = {
241 &nor_flash_device,
242 &usb_host_device,
243 &keysc_device,
244 &nand_flash_device,
245 &irda_device,
246};
247
248static struct map_desc g3evm_io_desc[] __initdata = {
249 /* create a 1:1 entity map for 0xe6xxxxxx
250 * used by CPGA, INTC and PFC.
251 */
252 {
253 .virtual = 0xe6000000,
254 .pfn = __phys_to_pfn(0xe6000000),
255 .length = 256 << 20,
256 .type = MT_DEVICE_NONSHARED
257 },
258};
259
260static void __init g3evm_map_io(void)
261{
262 iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
263
264 /* setup early devices and console here as well */
265 sh7367_add_early_devices();
266 shmobile_setup_console();
267}
268
269static void __init g3evm_init(void)
270{
271 sh7367_pinmux_init();
272
273 /* Lit DS4 LED */
274 gpio_request(GPIO_PORT22, NULL);
275 gpio_direction_output(GPIO_PORT22, 1);
276 gpio_export(GPIO_PORT22, 0);
277
278 /* Lit DS8 LED */
279 gpio_request(GPIO_PORT23, NULL);
280 gpio_direction_output(GPIO_PORT23, 1);
281 gpio_export(GPIO_PORT23, 0);
282
283 /* Lit DS3 LED */
284 gpio_request(GPIO_PORT24, NULL);
285 gpio_direction_output(GPIO_PORT24, 1);
286 gpio_export(GPIO_PORT24, 0);
287
288 /* SCIFA1 */
289 gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
290 gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
291 gpio_request(GPIO_FN_SCIFA1_CTS, NULL);
292 gpio_request(GPIO_FN_SCIFA1_RTS, NULL);
293
294 /* USBHS */
295 gpio_request(GPIO_FN_VBUS0, NULL);
296 gpio_request(GPIO_FN_PWEN, NULL);
297 gpio_request(GPIO_FN_OVCN, NULL);
298 gpio_request(GPIO_FN_OVCN2, NULL);
299 gpio_request(GPIO_FN_EXTLP, NULL);
300 gpio_request(GPIO_FN_IDIN, NULL);
301
302 /* setup USB phy */
303 __raw_writew(0x0300, 0xe605810a); /* USBCR1 */
304 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
305 __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */
306 __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */
307
308 /* KEYSC @ CN7 */
309 gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
310 gpio_request(GPIO_FN_PORT43_KEYOUT1, NULL);
311 gpio_request(GPIO_FN_PORT44_KEYOUT2, NULL);
312 gpio_request(GPIO_FN_PORT45_KEYOUT3, NULL);
313 gpio_request(GPIO_FN_PORT46_KEYOUT4, NULL);
314 gpio_request(GPIO_FN_PORT47_KEYOUT5, NULL);
315 gpio_request(GPIO_FN_PORT48_KEYIN0_PU, NULL);
316 gpio_request(GPIO_FN_PORT49_KEYIN1_PU, NULL);
317 gpio_request(GPIO_FN_PORT50_KEYIN2_PU, NULL);
318 gpio_request(GPIO_FN_PORT55_KEYIN3_PU, NULL);
319 gpio_request(GPIO_FN_PORT56_KEYIN4_PU, NULL);
320 gpio_request(GPIO_FN_PORT57_KEYIN5_PU, NULL);
321 gpio_request(GPIO_FN_PORT58_KEYIN6_PU, NULL);
322
323 /* FLCTL */
324 gpio_request(GPIO_FN_FCE0, NULL);
325 gpio_request(GPIO_FN_D0_ED0_NAF0, NULL);
326 gpio_request(GPIO_FN_D1_ED1_NAF1, NULL);
327 gpio_request(GPIO_FN_D2_ED2_NAF2, NULL);
328 gpio_request(GPIO_FN_D3_ED3_NAF3, NULL);
329 gpio_request(GPIO_FN_D4_ED4_NAF4, NULL);
330 gpio_request(GPIO_FN_D5_ED5_NAF5, NULL);
331 gpio_request(GPIO_FN_D6_ED6_NAF6, NULL);
332 gpio_request(GPIO_FN_D7_ED7_NAF7, NULL);
333 gpio_request(GPIO_FN_D8_ED8_NAF8, NULL);
334 gpio_request(GPIO_FN_D9_ED9_NAF9, NULL);
335 gpio_request(GPIO_FN_D10_ED10_NAF10, NULL);
336 gpio_request(GPIO_FN_D11_ED11_NAF11, NULL);
337 gpio_request(GPIO_FN_D12_ED12_NAF12, NULL);
338 gpio_request(GPIO_FN_D13_ED13_NAF13, NULL);
339 gpio_request(GPIO_FN_D14_ED14_NAF14, NULL);
340 gpio_request(GPIO_FN_D15_ED15_NAF15, NULL);
341 gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
342 gpio_request(GPIO_FN_FRB, NULL);
343 /* FOE, FCDE, FSC on dedicated pins */
344 __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
345
346 /* IrDA */
347 gpio_request(GPIO_FN_IRDA_OUT, NULL);
348 gpio_request(GPIO_FN_IRDA_IN, NULL);
349 gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
350
351 sh7367_add_standard_devices();
352
353 platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
354}
355
356static void __init g3evm_timer_init(void)
357{
358 sh7367_clock_init();
359 shmobile_timer.init();
360}
361
362static struct sys_timer g3evm_timer = {
363 .init = g3evm_timer_init,
364};
365
366MACHINE_START(G3EVM, "g3evm")
367 .map_io = g3evm_map_io,
368 .init_irq = sh7367_init_irq,
369 .handle_irq = shmobile_handle_irq_intc,
370 .init_machine = g3evm_init,
371 .timer = &g3evm_timer,
372MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
new file mode 100644
index 00000000000..8e3c5559f27
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -0,0 +1,415 @@
1/*
2 * G4EVM board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h>
29#include <linux/usb/r8a66597.h>
30#include <linux/io.h>
31#include <linux/input.h>
32#include <linux/input/sh_keysc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/sh_mobile_sdhi.h>
35#include <linux/gpio.h>
36#include <mach/sh7377.h>
37#include <mach/common.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/map.h>
41#include <asm/mach/time.h>
42
43/*
44 * SDHI
45 *
46 * SDHI0 : card detection is possible
47 * SDHI1 : card detection is impossible
48 *
49 * [G4-MAIN-BOARD]
50 * JP74 : short # DBG_2V8A for SDHI0
51 * JP75 : NC # DBG_3V3A for SDHI0
52 * JP76 : NC # DBG_3V3A_SD for SDHI0
53 * JP77 : NC # 3V3A_SDIO for SDHI1
54 * JP78 : short # DBG_2V8A for SDHI1
55 * JP79 : NC # DBG_3V3A for SDHI1
56 * JP80 : NC # DBG_3V3A_SD for SDHI1
57 *
58 * [G4-CORE-BOARD]
59 * S32 : all off # to dissever from G3-CORE_DBG board
60 * S33 : all off # to dissever from G3-CORE_DBG board
61 *
62 * [G3-CORE_DBG-BOARD]
63 * S1 : all off # to dissever from G3-CORE_DBG board
64 * S3 : all off # to dissever from G3-CORE_DBG board
65 * S4 : all off # to dissever from G3-CORE_DBG board
66 */
67
68static struct mtd_partition nor_flash_partitions[] = {
69 {
70 .name = "loader",
71 .offset = 0x00000000,
72 .size = 512 * 1024,
73 },
74 {
75 .name = "bootenv",
76 .offset = MTDPART_OFS_APPEND,
77 .size = 512 * 1024,
78 },
79 {
80 .name = "kernel_ro",
81 .offset = MTDPART_OFS_APPEND,
82 .size = 8 * 1024 * 1024,
83 .mask_flags = MTD_WRITEABLE,
84 },
85 {
86 .name = "kernel",
87 .offset = MTDPART_OFS_APPEND,
88 .size = 8 * 1024 * 1024,
89 },
90 {
91 .name = "data",
92 .offset = MTDPART_OFS_APPEND,
93 .size = MTDPART_SIZ_FULL,
94 },
95};
96
97static struct physmap_flash_data nor_flash_data = {
98 .width = 2,
99 .parts = nor_flash_partitions,
100 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
101};
102
103static struct resource nor_flash_resources[] = {
104 [0] = {
105 .start = 0x00000000,
106 .end = 0x08000000 - 1,
107 .flags = IORESOURCE_MEM,
108 }
109};
110
111static struct platform_device nor_flash_device = {
112 .name = "physmap-flash",
113 .dev = {
114 .platform_data = &nor_flash_data,
115 },
116 .num_resources = ARRAY_SIZE(nor_flash_resources),
117 .resource = nor_flash_resources,
118};
119
120/* USBHS */
121static void usb_host_port_power(int port, int power)
122{
123 if (!power) /* only power-on supported for now */
124 return;
125
126 /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
127 __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
128}
129
130static struct r8a66597_platdata usb_host_data = {
131 .on_chip = 1,
132 .port_power = usb_host_port_power,
133};
134
135static struct resource usb_host_resources[] = {
136 [0] = {
137 .name = "USBHS",
138 .start = 0xe6890000,
139 .end = 0xe68900e5,
140 .flags = IORESOURCE_MEM,
141 },
142 [1] = {
143 .start = evt2irq(0x0a20), /* USBHS_USHI0 */
144 .flags = IORESOURCE_IRQ,
145 },
146};
147
148static struct platform_device usb_host_device = {
149 .name = "r8a66597_hcd",
150 .id = 0,
151 .dev = {
152 .platform_data = &usb_host_data,
153 .dma_mask = NULL,
154 .coherent_dma_mask = 0xffffffff,
155 },
156 .num_resources = ARRAY_SIZE(usb_host_resources),
157 .resource = usb_host_resources,
158};
159
160/* KEYSC */
161static struct sh_keysc_info keysc_info = {
162 .mode = SH_KEYSC_MODE_5,
163 .scan_timing = 3,
164 .delay = 100,
165 .keycodes = {
166 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
167 KEY_G, KEY_H, KEY_I, KEY_J, KEY_K, KEY_L,
168 KEY_M, KEY_N, KEY_U, KEY_P, KEY_Q, KEY_R,
169 KEY_S, KEY_T, KEY_U, KEY_V, KEY_W, KEY_X,
170 KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE,
171 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
172 KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
173 },
174};
175
176static struct resource keysc_resources[] = {
177 [0] = {
178 .name = "KEYSC",
179 .start = 0xe61b0000,
180 .end = 0xe61b000f,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = evt2irq(0x0be0), /* KEYSC_KEY */
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device keysc_device = {
190 .name = "sh_keysc",
191 .id = 0, /* keysc0 clock */
192 .num_resources = ARRAY_SIZE(keysc_resources),
193 .resource = keysc_resources,
194 .dev = {
195 .platform_data = &keysc_info,
196 },
197};
198
199/* SDHI */
200static struct sh_mobile_sdhi_info sdhi0_info = {
201 .tmio_caps = MMC_CAP_SDIO_IRQ,
202};
203
204static struct resource sdhi0_resources[] = {
205 [0] = {
206 .name = "SDHI0",
207 .start = 0xe6d50000,
208 .end = 0xe6d500ff,
209 .flags = IORESOURCE_MEM,
210 },
211 [1] = {
212 .start = evt2irq(0x0e00), /* SDHI0 */
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217static struct platform_device sdhi0_device = {
218 .name = "sh_mobile_sdhi",
219 .num_resources = ARRAY_SIZE(sdhi0_resources),
220 .resource = sdhi0_resources,
221 .id = 0,
222 .dev = {
223 .platform_data = &sdhi0_info,
224 },
225};
226
227static struct sh_mobile_sdhi_info sdhi1_info = {
228 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
229};
230
231static struct resource sdhi1_resources[] = {
232 [0] = {
233 .name = "SDHI1",
234 .start = 0xe6d60000,
235 .end = 0xe6d600ff,
236 .flags = IORESOURCE_MEM,
237 },
238 [1] = {
239 .start = evt2irq(0x0e80), /* SDHI1 */
240 .flags = IORESOURCE_IRQ,
241 },
242};
243
244static struct platform_device sdhi1_device = {
245 .name = "sh_mobile_sdhi",
246 .num_resources = ARRAY_SIZE(sdhi1_resources),
247 .resource = sdhi1_resources,
248 .id = 1,
249 .dev = {
250 .platform_data = &sdhi1_info,
251 },
252};
253
254static struct platform_device *g4evm_devices[] __initdata = {
255 &nor_flash_device,
256 &usb_host_device,
257 &keysc_device,
258 &sdhi0_device,
259 &sdhi1_device,
260};
261
262static struct map_desc g4evm_io_desc[] __initdata = {
263 /* create a 1:1 entity map for 0xe6xxxxxx
264 * used by CPGA, INTC and PFC.
265 */
266 {
267 .virtual = 0xe6000000,
268 .pfn = __phys_to_pfn(0xe6000000),
269 .length = 256 << 20,
270 .type = MT_DEVICE_NONSHARED
271 },
272};
273
274static void __init g4evm_map_io(void)
275{
276 iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
277
278 /* setup early devices and console here as well */
279 sh7377_add_early_devices();
280 shmobile_setup_console();
281}
282
283#define GPIO_SDHID0_D0 0xe60520fc
284#define GPIO_SDHID0_D1 0xe60520fd
285#define GPIO_SDHID0_D2 0xe60520fe
286#define GPIO_SDHID0_D3 0xe60520ff
287#define GPIO_SDHICMD0 0xe6052100
288
289#define GPIO_SDHID1_D0 0xe6052103
290#define GPIO_SDHID1_D1 0xe6052104
291#define GPIO_SDHID1_D2 0xe6052105
292#define GPIO_SDHID1_D3 0xe6052106
293#define GPIO_SDHICMD1 0xe6052107
294
295/*
296 * FIXME !!
297 *
298 * gpio_pull_up is quick_hack.
299 *
300 * current gpio frame work doesn't have
301 * the method to control only pull up/down/free.
302 * this function should be replaced by correct gpio function
303 */
304static void __init gpio_pull_up(u32 addr)
305{
306 u8 data = __raw_readb(addr);
307
308 data &= 0x0F;
309 data |= 0xC0;
310 __raw_writeb(data, addr);
311}
312
313static void __init g4evm_init(void)
314{
315 sh7377_pinmux_init();
316
317 /* Lit DS14 LED */
318 gpio_request(GPIO_PORT109, NULL);
319 gpio_direction_output(GPIO_PORT109, 1);
320 gpio_export(GPIO_PORT109, 1);
321
322 /* Lit DS15 LED */
323 gpio_request(GPIO_PORT110, NULL);
324 gpio_direction_output(GPIO_PORT110, 1);
325 gpio_export(GPIO_PORT110, 1);
326
327 /* Lit DS16 LED */
328 gpio_request(GPIO_PORT112, NULL);
329 gpio_direction_output(GPIO_PORT112, 1);
330 gpio_export(GPIO_PORT112, 1);
331
332 /* Lit DS17 LED */
333 gpio_request(GPIO_PORT113, NULL);
334 gpio_direction_output(GPIO_PORT113, 1);
335 gpio_export(GPIO_PORT113, 1);
336
337 /* USBHS */
338 gpio_request(GPIO_FN_VBUS_0, NULL);
339 gpio_request(GPIO_FN_PWEN, NULL);
340 gpio_request(GPIO_FN_OVCN, NULL);
341 gpio_request(GPIO_FN_OVCN2, NULL);
342 gpio_request(GPIO_FN_EXTLP, NULL);
343 gpio_request(GPIO_FN_IDIN, NULL);
344
345 /* setup USB phy */
346 __raw_writew(0x0200, 0xe605810a); /* USBCR1 */
347 __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */
348 __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */
349 __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */
350
351 /* KEYSC @ CN31 */
352 gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
353 gpio_request(GPIO_FN_PORT61_KEYOUT4, NULL);
354 gpio_request(GPIO_FN_PORT62_KEYOUT3, NULL);
355 gpio_request(GPIO_FN_PORT63_KEYOUT2, NULL);
356 gpio_request(GPIO_FN_PORT64_KEYOUT1, NULL);
357 gpio_request(GPIO_FN_PORT65_KEYOUT0, NULL);
358 gpio_request(GPIO_FN_PORT66_KEYIN0_PU, NULL);
359 gpio_request(GPIO_FN_PORT67_KEYIN1_PU, NULL);
360 gpio_request(GPIO_FN_PORT68_KEYIN2_PU, NULL);
361 gpio_request(GPIO_FN_PORT69_KEYIN3_PU, NULL);
362 gpio_request(GPIO_FN_PORT70_KEYIN4_PU, NULL);
363 gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
364 gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
365
366 /* SDHI0 */
367 gpio_request(GPIO_FN_SDHICLK0, NULL);
368 gpio_request(GPIO_FN_SDHICD0, NULL);
369 gpio_request(GPIO_FN_SDHID0_0, NULL);
370 gpio_request(GPIO_FN_SDHID0_1, NULL);
371 gpio_request(GPIO_FN_SDHID0_2, NULL);
372 gpio_request(GPIO_FN_SDHID0_3, NULL);
373 gpio_request(GPIO_FN_SDHICMD0, NULL);
374 gpio_request(GPIO_FN_SDHIWP0, NULL);
375 gpio_pull_up(GPIO_SDHID0_D0);
376 gpio_pull_up(GPIO_SDHID0_D1);
377 gpio_pull_up(GPIO_SDHID0_D2);
378 gpio_pull_up(GPIO_SDHID0_D3);
379 gpio_pull_up(GPIO_SDHICMD0);
380
381 /* SDHI1 */
382 gpio_request(GPIO_FN_SDHICLK1, NULL);
383 gpio_request(GPIO_FN_SDHID1_0, NULL);
384 gpio_request(GPIO_FN_SDHID1_1, NULL);
385 gpio_request(GPIO_FN_SDHID1_2, NULL);
386 gpio_request(GPIO_FN_SDHID1_3, NULL);
387 gpio_request(GPIO_FN_SDHICMD1, NULL);
388 gpio_pull_up(GPIO_SDHID1_D0);
389 gpio_pull_up(GPIO_SDHID1_D1);
390 gpio_pull_up(GPIO_SDHID1_D2);
391 gpio_pull_up(GPIO_SDHID1_D3);
392 gpio_pull_up(GPIO_SDHICMD1);
393
394 sh7377_add_standard_devices();
395
396 platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
397}
398
399static void __init g4evm_timer_init(void)
400{
401 sh7377_clock_init();
402 shmobile_timer.init();
403}
404
405static struct sys_timer g4evm_timer = {
406 .init = g4evm_timer_init,
407};
408
409MACHINE_START(G4EVM, "g4evm")
410 .map_io = g4evm_map_io,
411 .init_irq = sh7377_init_irq,
412 .handle_irq = shmobile_handle_irq_intc,
413 .init_machine = g4evm_init,
414 .timer = &g4evm_timer,
415MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
new file mode 100644
index 00000000000..5218c34a9cc
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -0,0 +1,355 @@
1/*
2 * SH7367 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <linux/clkdev.h>
24#include <mach/common.h>
25
26/* SH7367 registers */
27#define RTFRQCR 0xe6150000
28#define SYFRQCR 0xe6150004
29#define CMFRQCR 0xe61500E0
30#define VCLKCR1 0xe6150008
31#define VCLKCR2 0xe615000C
32#define VCLKCR3 0xe615001C
33#define SCLKACR 0xe6150010
34#define SCLKBCR 0xe6150014
35#define SUBUSBCKCR 0xe6158080
36#define SPUCKCR 0xe6150084
37#define MSUCKCR 0xe6150088
38#define MVI3CKCR 0xe6150090
39#define VOUCKCR 0xe6150094
40#define MFCK1CR 0xe6150098
41#define MFCK2CR 0xe615009C
42#define PLLC1CR 0xe6150028
43#define PLLC2CR 0xe615002C
44#define RTMSTPCR0 0xe6158030
45#define RTMSTPCR2 0xe6158038
46#define SYMSTPCR0 0xe6158040
47#define SYMSTPCR2 0xe6158048
48#define CMMSTPCR0 0xe615804c
49
50/* Fixed 32 KHz root clock from EXTALR pin */
51static struct clk r_clk = {
52 .rate = 32768,
53};
54
55/*
56 * 26MHz default rate for the EXTALB1 root input clock.
57 * If needed, reset this with clk_set_rate() from the platform code.
58 */
59struct clk sh7367_extalb1_clk = {
60 .rate = 26666666,
61};
62
63/*
64 * 48MHz default rate for the EXTAL2 root input clock.
65 * If needed, reset this with clk_set_rate() from the platform code.
66 */
67struct clk sh7367_extal2_clk = {
68 .rate = 48000000,
69};
70
71/* A fixed divide-by-2 block */
72static unsigned long div2_recalc(struct clk *clk)
73{
74 return clk->parent->rate / 2;
75}
76
77static struct clk_ops div2_clk_ops = {
78 .recalc = div2_recalc,
79};
80
81/* Divide extalb1 by two */
82static struct clk extalb1_div2_clk = {
83 .ops = &div2_clk_ops,
84 .parent = &sh7367_extalb1_clk,
85};
86
87/* Divide extal2 by two */
88static struct clk extal2_div2_clk = {
89 .ops = &div2_clk_ops,
90 .parent = &sh7367_extal2_clk,
91};
92
93/* PLLC1 */
94static unsigned long pllc1_recalc(struct clk *clk)
95{
96 unsigned long mult = 1;
97
98 if (__raw_readl(PLLC1CR) & (1 << 14))
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
100
101 return clk->parent->rate * mult;
102}
103
104static struct clk_ops pllc1_clk_ops = {
105 .recalc = pllc1_recalc,
106};
107
108static struct clk pllc1_clk = {
109 .ops = &pllc1_clk_ops,
110 .flags = CLK_ENABLE_ON_INIT,
111 .parent = &extalb1_div2_clk,
112};
113
114/* Divide PLLC1 by two */
115static struct clk pllc1_div2_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &pllc1_clk,
118};
119
120/* PLLC2 */
121static unsigned long pllc2_recalc(struct clk *clk)
122{
123 unsigned long mult = 1;
124
125 if (__raw_readl(PLLC2CR) & (1 << 31))
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
127
128 return clk->parent->rate * mult;
129}
130
131static struct clk_ops pllc2_clk_ops = {
132 .recalc = pllc2_recalc,
133};
134
135static struct clk pllc2_clk = {
136 .ops = &pllc2_clk_ops,
137 .flags = CLK_ENABLE_ON_INIT,
138 .parent = &extalb1_div2_clk,
139};
140
141static struct clk *main_clks[] = {
142 &r_clk,
143 &sh7367_extalb1_clk,
144 &sh7367_extal2_clk,
145 &extalb1_div2_clk,
146 &extal2_div2_clk,
147 &pllc1_clk,
148 &pllc1_div2_clk,
149 &pllc2_clk,
150};
151
152static void div4_kick(struct clk *clk)
153{
154 unsigned long value;
155
156 /* set KICK bit in SYFRQCR to update hardware setting */
157 value = __raw_readl(SYFRQCR);
158 value |= (1 << 31);
159 __raw_writel(value, SYFRQCR);
160}
161
162static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
163 24, 32, 36, 48, 0, 72, 0, 0 };
164
165static struct clk_div_mult_table div4_div_mult_table = {
166 .divisors = divisors,
167 .nr_divisors = ARRAY_SIZE(divisors),
168};
169
170static struct clk_div4_table div4_table = {
171 .div_mult_table = &div4_div_mult_table,
172 .kick = div4_kick,
173};
174
175enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
176 DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
178
179#define DIV4(_reg, _bit, _mask, _flags) \
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
181
182static struct clk div4_clks[DIV4_NR] = {
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
191 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
192 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
193 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
194 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
195 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
196};
197
198enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
199 DIV6_MVI3, DIV6_MF1, DIV6_MF2,
200 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
201 DIV6_NR };
202
203static struct clk div6_clks[DIV6_NR] = {
204 [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
205 [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
206 [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
207 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
208 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
209 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
210 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
211 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
212 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
213 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
214 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
215 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
216};
217
218enum { RTMSTP001,
219 RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
220 RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
221 SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
222 SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
223 SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
224 SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
225 CMMSTP003,
226 MSTP_NR };
227
228#define MSTP(_parent, _reg, _bit, _flags) \
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
230
231static struct clk mstp_clks[MSTP_NR] = {
232 [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
238 [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
240 [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
242 [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
243 [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
244 [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
245 [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
246 [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
247 [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
248 [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
249 [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
250 [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
251 [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
252 [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
253 [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
254 [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
255 [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
256 [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
257 [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
258 [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
260};
261
262static struct clk_lookup lookups[] = {
263 /* main clocks */
264 CLKDEV_CON_ID("r_clk", &r_clk),
265 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
266 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
267 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
268 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
269 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
270 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
271 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
272
273 /* DIV4 clocks */
274 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
275 CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
276 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
277 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
278 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
279 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
280 CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
281 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
282 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
283 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
284 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
285 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
286
287 /* DIV6 clocks */
288 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
289 CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
290 CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
291 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
292 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
293 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
294 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
295 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
296 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
297 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
298 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
299 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
300
301 /* MSTP32 clocks */
302 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
303 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
304 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
305 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
308 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
310 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
311 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
312 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
313 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
314 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
315 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
316 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
317 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
318 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
319 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
320 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
321 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
322 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
323 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
324 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
325 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
326 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
327 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
328 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
329 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
330 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
331};
332
333void __init sh7367_clock_init(void)
334{
335 int k, ret = 0;
336
337 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
338 ret = clk_register(main_clks[k]);
339
340 if (!ret)
341 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
342
343 if (!ret)
344 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
345
346 if (!ret)
347 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
348
349 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
350
351 if (!ret)
352 clk_init();
353 else
354 panic("failed to setup sh7367 clocks\n");
355}
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
new file mode 100644
index 00000000000..8cee7b151ae
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -0,0 +1,366 @@
1/*
2 * SH7377 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <linux/clkdev.h>
24#include <mach/common.h>
25
26/* SH7377 registers */
27#define RTFRQCR 0xe6150000
28#define SYFRQCR 0xe6150004
29#define CMFRQCR 0xe61500E0
30#define VCLKCR1 0xe6150008
31#define VCLKCR2 0xe615000C
32#define VCLKCR3 0xe615001C
33#define FMSICKCR 0xe6150010
34#define FMSOCKCR 0xe6150014
35#define FSICKCR 0xe6150018
36#define PLLC1CR 0xe6150028
37#define PLLC2CR 0xe615002C
38#define SUBUSBCKCR 0xe6150080
39#define SPUCKCR 0xe6150084
40#define MSUCKCR 0xe6150088
41#define MVI3CKCR 0xe6150090
42#define HDMICKCR 0xe6150094
43#define MFCK1CR 0xe6150098
44#define MFCK2CR 0xe615009C
45#define DSITCKCR 0xe6150060
46#define DSIPCKCR 0xe6150064
47#define SMSTPCR0 0xe6150130
48#define SMSTPCR1 0xe6150134
49#define SMSTPCR2 0xe6150138
50#define SMSTPCR3 0xe615013C
51#define SMSTPCR4 0xe6150140
52
53/* Fixed 32 KHz root clock from EXTALR pin */
54static struct clk r_clk = {
55 .rate = 32768,
56};
57
58/*
59 * 26MHz default rate for the EXTALC1 root input clock.
60 * If needed, reset this with clk_set_rate() from the platform code.
61 */
62struct clk sh7377_extalc1_clk = {
63 .rate = 26666666,
64};
65
66/*
67 * 48MHz default rate for the EXTAL2 root input clock.
68 * If needed, reset this with clk_set_rate() from the platform code.
69 */
70struct clk sh7377_extal2_clk = {
71 .rate = 48000000,
72};
73
74/* A fixed divide-by-2 block */
75static unsigned long div2_recalc(struct clk *clk)
76{
77 return clk->parent->rate / 2;
78}
79
80static struct clk_ops div2_clk_ops = {
81 .recalc = div2_recalc,
82};
83
84/* Divide extalc1 by two */
85static struct clk extalc1_div2_clk = {
86 .ops = &div2_clk_ops,
87 .parent = &sh7377_extalc1_clk,
88};
89
90/* Divide extal2 by two */
91static struct clk extal2_div2_clk = {
92 .ops = &div2_clk_ops,
93 .parent = &sh7377_extal2_clk,
94};
95
96/* Divide extal2 by four */
97static struct clk extal2_div4_clk = {
98 .ops = &div2_clk_ops,
99 .parent = &extal2_div2_clk,
100};
101
102/* PLLC1 */
103static unsigned long pllc1_recalc(struct clk *clk)
104{
105 unsigned long mult = 1;
106
107 if (__raw_readl(PLLC1CR) & (1 << 14))
108 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
109
110 return clk->parent->rate * mult;
111}
112
113static struct clk_ops pllc1_clk_ops = {
114 .recalc = pllc1_recalc,
115};
116
117static struct clk pllc1_clk = {
118 .ops = &pllc1_clk_ops,
119 .flags = CLK_ENABLE_ON_INIT,
120 .parent = &extalc1_div2_clk,
121};
122
123/* Divide PLLC1 by two */
124static struct clk pllc1_div2_clk = {
125 .ops = &div2_clk_ops,
126 .parent = &pllc1_clk,
127};
128
129/* PLLC2 */
130static unsigned long pllc2_recalc(struct clk *clk)
131{
132 unsigned long mult = 1;
133
134 if (__raw_readl(PLLC2CR) & (1 << 31))
135 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
136
137 return clk->parent->rate * mult;
138}
139
140static struct clk_ops pllc2_clk_ops = {
141 .recalc = pllc2_recalc,
142};
143
144static struct clk pllc2_clk = {
145 .ops = &pllc2_clk_ops,
146 .flags = CLK_ENABLE_ON_INIT,
147 .parent = &extalc1_div2_clk,
148};
149
150static struct clk *main_clks[] = {
151 &r_clk,
152 &sh7377_extalc1_clk,
153 &sh7377_extal2_clk,
154 &extalc1_div2_clk,
155 &extal2_div2_clk,
156 &extal2_div4_clk,
157 &pllc1_clk,
158 &pllc1_div2_clk,
159 &pllc2_clk,
160};
161
162static void div4_kick(struct clk *clk)
163{
164 unsigned long value;
165
166 /* set KICK bit in SYFRQCR to update hardware setting */
167 value = __raw_readl(SYFRQCR);
168 value |= (1 << 31);
169 __raw_writel(value, SYFRQCR);
170}
171
172static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
173 24, 32, 36, 48, 0, 72, 96, 0 };
174
175static struct clk_div_mult_table div4_div_mult_table = {
176 .divisors = divisors,
177 .nr_divisors = ARRAY_SIZE(divisors),
178};
179
180static struct clk_div4_table div4_table = {
181 .div_mult_table = &div4_div_mult_table,
182 .kick = div4_kick,
183};
184
185enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
186 DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
187 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
188
189#define DIV4(_reg, _bit, _mask, _flags) \
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
191
192static struct clk div4_clks[DIV4_NR] = {
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
197 [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
198 [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
199 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
200 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
201 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
202 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
203 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
204 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
205 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
206};
207
208enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
209 DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
210 DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
211 DIV6_NR };
212
213static struct clk div6_clks[] = {
214 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
215 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
216 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
217 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
218 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
219 [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
220 [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
221 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
222 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
223 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
224 [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
225 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
226 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
227 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
228 [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
229};
230
231enum { MSTP001,
232 MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
233 MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
234 MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
235 MSTP315, MSTP314, MSTP313,
236 MSTP403,
237 MSTP_NR };
238
239#define MSTP(_parent, _reg, _bit, _flags) \
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
241
242static struct clk mstp_clks[] = {
243 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
244 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
245 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
246 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
247 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
248 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
249 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
250 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
251 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
252 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
253 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
254 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
255 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
256 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
257 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
258 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
259 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
260 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
261 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
262 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
263 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
264 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
265 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
266 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
267 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
268};
269
270static struct clk_lookup lookups[] = {
271 /* main clocks */
272 CLKDEV_CON_ID("r_clk", &r_clk),
273 CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
274 CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
275 CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
276 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
277 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
278 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
279 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
280 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
281
282 /* DIV4 clocks */
283 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
284 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
285 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
286 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
287 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
288 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
289 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
290 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
291 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
292 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
293 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
294 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
295 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
296
297 /* DIV6 clocks */
298 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
299 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
300 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
301 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
302 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
303 CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
304 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
305 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
306 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
307 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
308 CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
309 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
310 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
311 CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
312 CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
313
314 /* MSTP32 clocks */
315 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
316 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
317 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
318 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
319 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
320 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
321 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
322 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
323 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
324 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
325 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
326 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
327 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
328 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
329 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
330 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
331 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
332 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
333 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
334 CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
335 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
336 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
337 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
338 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
339 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
340 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
341 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
342};
343
344void __init sh7377_clock_init(void)
345{
346 int k, ret = 0;
347
348 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
349 ret = clk_register(main_clks[k]);
350
351 if (!ret)
352 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
353
354 if (!ret)
355 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
356
357 if (!ret)
358 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
359
360 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
361
362 if (!ret)
363 clk_init();
364 else
365 panic("failed to setup sh7377 clocks\n");
366}
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
new file mode 100644
index 00000000000..e20239b08c8
--- /dev/null
+++ b/arch/arm/mach-shmobile/entry-gic.S
@@ -0,0 +1,18 @@
1/*
2 * ARM Interrupt demux handler using GIC
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2011 Paul Mundt
6 * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <asm/assembler.h>
14#include <asm/entry-macro-multi.S>
15#include <asm/hardware/gic.h>
16#include <asm/hardware/entry-macro-gic.S>
17
18 arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
new file mode 100644
index 00000000000..d791f10eeac
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2010 Paul Mundt
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */
17
18 .macro disable_fiq
19 .endm
20
21 .macro get_irqnr_preamble, base, tmp
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 .endm
26
27 .macro test_for_ipi, irqnr, irqstat, base, tmp
28 .endm
29
30 .macro test_for_ltirq, irqnr, irqstat, base, tmp
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
new file mode 100644
index 00000000000..2b1bb9e43dd
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -0,0 +1,48 @@
1/*
2 * Generic GPIO API and pinmux table support
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_ARCH_GPIO_H
11#define __ASM_ARCH_GPIO_H
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15
16#define ARCH_NR_GPIOS 1024
17#include <linux/sh_pfc.h>
18
19#ifdef CONFIG_GPIOLIB
20
21static inline int gpio_get_value(unsigned gpio)
22{
23 return __gpio_get_value(gpio);
24}
25
26static inline void gpio_set_value(unsigned gpio, int value)
27{
28 __gpio_set_value(gpio, value);
29}
30
31static inline int gpio_cansleep(unsigned gpio)
32{
33 return __gpio_cansleep(gpio);
34}
35
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return __gpio_to_irq(gpio);
39}
40
41static inline int irq_to_gpio(unsigned int irq)
42{
43 return -ENOSYS;
44}
45
46#endif /* CONFIG_GPIOLIB */
47
48#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
new file mode 100644
index 00000000000..7339fe46cb7
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_MACH_IO_H
2#define __ASM_MACH_IO_H
3
4#define IO_SPACE_LIMIT 0xffffffff
5
6#define __io(a) ((void __iomem *)(a))
7#define __mem_pci(a) (a)
8
9#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
new file mode 100644
index 00000000000..52d0de686f6
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh7367.h
@@ -0,0 +1,332 @@
1#ifndef __ASM_SH7367_H__
2#define __ASM_SH7367_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* 49-1 -> 49-6 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
45
46 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
47 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
48
49 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
50 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
51
52 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
53 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
54
55 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
56 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
57
58 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
59 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
60
61 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
62 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
63
64 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
65 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
66
67 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
68 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
69
70 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
71 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
72
73 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
74 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
75
76 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
77 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
78
79 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
80 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
81
82 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
83 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
84
85 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
86 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
87
88 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
89 GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
90
91 GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
92
93 /* Special Pull-up / Pull-down Functions */
94 GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
95 GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
96 GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
97 GPIO_FN_PORT58_KEYIN6_PU,
98
99 /* 49-1 (FN) */
100 GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
101 GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
102 GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
103 GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
104 GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
105 GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
106 GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
107 GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
108 GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
109 GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
110 GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
111 GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
112 GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
113 GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
114 GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
115
116 /* 49-2 (FN) */
117 GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
118 GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
119 GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
120 GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
121 GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
122 GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
123 GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
124 GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
125 GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
126 GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
127 GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
128 GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
129 GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
130 GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
131 GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
132 GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
133 GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
134 GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
135 GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
136 GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
137 GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
138 GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
139 GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
140 GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
141 GPIO_FN_XTALB1L,
142 GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
143 GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
144 GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
145 GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
146 GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
147 GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
148 GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
149 GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
150 GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
151 GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
152 GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
153 GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
154 GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
155 GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
156 GPIO_FN_NMI, GPIO_FN_TPU4TO0,
157 GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
158 GPIO_FN_IRQ_TMPB,
159 GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
160 GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
161 GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
162
163 /* 49-3 (FN) */
164 GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
165 GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
166 GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
167 GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
168 GPIO_FN_SCIFA5_RXD,
169 GPIO_FN_SCIFA5_TXD,
170 GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
171 GPIO_FN_A0_EA0, GPIO_FN_BS,
172 GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
173 GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
174 GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
175 GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
176 GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
177 GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
178 GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
179 GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
180 GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
181 GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
182 GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
183 GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
184 GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
185 GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
186 GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
187 GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
188 GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
189 GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
190 GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
191 GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
192 GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
193 GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
194 GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
195 GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
196 GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
197 GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
198 GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
199 GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
200 GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
201 GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
202 GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
203 GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
204 GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
205 GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
206 GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
207
208 /* 49-4 (FN) */
209 GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
210 GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
211 GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
212 GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
213 GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
214 GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
215 GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
216 GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
217 GPIO_FN_VIO_CKO,
218 GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
219 GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
220 GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
221 GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
222 GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
223 GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
224 GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
225 GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
226 GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
227 GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
228 GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
229 GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
230 GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
231 GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
232 GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
233 GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
234 GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
235 GPIO_FN_LCDD6, GPIO_FN_DV_D6,
236 GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
237 GPIO_FN_LCDD7, GPIO_FN_DV_D7,
238 GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
239 GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
240 GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
241 GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
242 GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
243 GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
244 GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
245 GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
246 GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
247 GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
248 GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
249 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
250 GPIO_FN_D26, GPIO_FN_ED26,
251 GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
252 GPIO_FN_D27, GPIO_FN_ED27,
253 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
254 GPIO_FN_D28, GPIO_FN_ED28,
255 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
256 GPIO_FN_D29, GPIO_FN_ED29,
257 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
258 GPIO_FN_D30, GPIO_FN_ED30,
259 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
260 GPIO_FN_D31, GPIO_FN_ED31,
261 GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
262 GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
263
264
265 /* 49-5 (FN) */
266 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
267 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
268 GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
269 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
270 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
271 GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
272 GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
273 GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
274 GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
275 GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
276 GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
277 GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
278 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
279 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
280 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
281 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
282 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
283 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
284 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
285 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
286 GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
287 GPIO_FN_MSIOF1_SS2,
288 GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
289 GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
290 GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
291 GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
292 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
293 GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
294 GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
295 GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
296 GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
297 GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
298 GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
299 GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
300 GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
301 GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
302 GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
303 GPIO_FN_SDHICD0,
304 GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
305 GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
306 GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
307 GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
308
309 /* 49-6 (FN) */
310 GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
311 GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
312 GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
313 GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
314 GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
315 GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
316 GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
317 GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
318 GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
319 GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
320 GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
321 GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
322 GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
323 GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
324 GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
325 GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
326 GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
327 GPIO_FN_SDHICMD2,
328 GPIO_FN_RESETOUTS,
329 GPIO_FN_DIVLOCK,
330};
331
332#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h
new file mode 100644
index 00000000000..f580e227dd1
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh7377.h
@@ -0,0 +1,360 @@
1#ifndef __ASM_SH7377_H__
2#define __ASM_SH7377_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* 55-1 -> 55-5 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
45
46 GPIO_PORT128, GPIO_PORT129,
47
48 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
49 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
50
51 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
52 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
53
54 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
55 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
56
57 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
58
59 GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
60 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
61
62 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
63 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
64
65 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
66 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
67
68 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
69 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
70
71 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
72 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
73
74 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
75 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
76
77 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
78 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
79
80 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
81
82 /* Special Pull-up / Pull-down Functions */
83 GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
84 GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
85 GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
86 GPIO_FN_PORT72_KEYIN6_PU,
87
88 /* 55-1 (FN) */
89 GPIO_FN_VBUS_0,
90 GPIO_FN_CPORT0,
91 GPIO_FN_CPORT1,
92 GPIO_FN_CPORT2,
93 GPIO_FN_CPORT3,
94 GPIO_FN_CPORT4,
95 GPIO_FN_CPORT5,
96 GPIO_FN_CPORT6,
97 GPIO_FN_CPORT7,
98 GPIO_FN_CPORT8,
99 GPIO_FN_CPORT9,
100 GPIO_FN_CPORT10,
101 GPIO_FN_CPORT11, GPIO_FN_SIN2,
102 GPIO_FN_CPORT12, GPIO_FN_XCTS2,
103 GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
104 GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
105 GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
106 GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
107 GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
108 GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
109 GPIO_FN_CPORT19_MPORT1,
110 GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
111 GPIO_FN_CPORT21, GPIO_FN_STATUS0,
112 GPIO_FN_CPORT22, GPIO_FN_STATUS1,
113 GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
114 GPIO_FN_B_SYNLD1,
115 GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
116 GPIO_FN_XMAINPS,
117 GPIO_FN_XDIVPS,
118 GPIO_FN_XIDRST,
119 GPIO_FN_IDCLK, GPIO_FN_IC_DP,
120 GPIO_FN_IDIO, GPIO_FN_IC_DM,
121 GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
122 GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
123 GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
124 GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
125 GPIO_FN_PCMCLKO,
126 GPIO_FN_SYNC8KO,
127
128 /* 55-2 (FN) */
129 GPIO_FN_DNPCM_A,
130 GPIO_FN_UPPCM_A,
131 GPIO_FN_VACK,
132 GPIO_FN_XTALB1L,
133 GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
134 GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
135 GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
136 GPIO_FN_GPS_IM,
137 GPIO_FN_GPS_IS,
138 GPIO_FN_GPS_QM,
139 GPIO_FN_GPS_QS,
140 GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
141 GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
142 GPIO_FN_FMSIOLR,
143 GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
144 GPIO_FN_FMSIOBT,
145 GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
146 GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
147 GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
148 GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
149 GPIO_FN_FMSIIBT,
150 GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
151 GPIO_FN_A0_EA0, GPIO_FN_BS,
152 GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
153 GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
154 GPIO_FN_TPU0TO1,
155 GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
156 GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
157 GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
158 GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
159 GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
160 GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
161 GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
162 GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
163 GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
164 GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
165 GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
166 GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
167 GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
168 GPIO_FN_D0_ED0_NAF0,
169 GPIO_FN_D1_ED1_NAF1,
170 GPIO_FN_D2_ED2_NAF2,
171 GPIO_FN_D3_ED3_NAF3,
172 GPIO_FN_D4_ED4_NAF4,
173 GPIO_FN_D5_ED5_NAF5,
174 GPIO_FN_D6_ED6_NAF6,
175 GPIO_FN_D7_ED7_NAF7,
176 GPIO_FN_D8_ED8_NAF8,
177 GPIO_FN_D9_ED9_NAF9,
178 GPIO_FN_D10_ED10_NAF10,
179 GPIO_FN_D11_ED11_NAF11,
180 GPIO_FN_D12_ED12_NAF12,
181 GPIO_FN_D13_ED13_NAF13,
182 GPIO_FN_D14_ED14_NAF14,
183 GPIO_FN_D15_ED15_NAF15,
184 GPIO_FN_CS4,
185 GPIO_FN_CS5A, GPIO_FN_FMSICK,
186 GPIO_FN_CS5B, GPIO_FN_FCE1,
187
188 /* 55-3 (FN) */
189 GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
190 GPIO_FN_FCE0,
191 GPIO_FN_WAIT, GPIO_FN_DREQ0,
192 GPIO_FN_RD_XRD,
193 GPIO_FN_WE0_XWR0_FWE,
194 GPIO_FN_WE1_XWR1,
195 GPIO_FN_FRB,
196 GPIO_FN_CKO,
197 GPIO_FN_NBRSTOUT,
198 GPIO_FN_NBRST,
199 GPIO_FN_GPS_EPPSIN,
200 GPIO_FN_LATCHPULSE,
201 GPIO_FN_LTESIGNAL,
202 GPIO_FN_LEGACYSTATE,
203 GPIO_FN_TCKON,
204 GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
205 GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
206 GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
207 GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
208 GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
209 GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
210 GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
211 GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
212 GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
213 GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
214 GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
215 GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
216 GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
217 GPIO_FN_PORT140_FSIAOBT,
218 GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
219 GPIO_FN_PORT141_FSIAOSLD,
220 GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
221 GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
222 GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
223 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
224 GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
225 GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
226 GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
227 GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
228 GPIO_FN_MFG0_IN2,
229 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
230 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
231 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
232 GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
233 GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
234 GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
235 GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
236
237 /* 55-4 (FN) */
238 GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
239 GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
240 GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
241 GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
242 GPIO_FN_MFG3_IN2,
243 GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
244 GPIO_FN_MFG3_IN1,
245 GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
246 GPIO_FN_MFG3_OUT1,
247 GPIO_FN_TPU3TO0,
248 GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
249 GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
250 GPIO_FN_BBIF2_TSYNC1,
251 GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
252 GPIO_FN_BBIF2_TSCK1,
253 GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
254 GPIO_FN_BBIF2_TXD1,
255 GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
256 GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
257 GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
258 GPIO_FN_LCDD6, GPIO_FN_XWR2,
259 GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
260 GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
261 GPIO_FN_ED16,
262 GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
263 GPIO_FN_ED17,
264 GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
265 GPIO_FN_ED18,
266 GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
267 GPIO_FN_ED19,
268 GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
269 GPIO_FN_ED20,
270 GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
271 GPIO_FN_ED21,
272 GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
273 GPIO_FN_ED22,
274 GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
275 GPIO_FN_VIO_DR7,
276 GPIO_FN_D23, GPIO_FN_ED23,
277 GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
278 GPIO_FN_VIO_VDR,
279 GPIO_FN_D24, GPIO_FN_ED24,
280 GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
281 GPIO_FN_ED25,
282 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
283 GPIO_FN_ED26,
284 GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
285 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
286 GPIO_FN_ED28,
287 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
288 GPIO_FN_ED29,
289 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
290 GPIO_FN_ED30,
291 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
292 GPIO_FN_ED31,
293 GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
294 GPIO_FN_VIO_CLKR,
295 GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
296 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
297 GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
298 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
299 GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
300 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
301 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
302 GPIO_FN_MSIOF0L_TXD,
303 GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
304 GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
305 GPIO_FN_PORT226_VIO_CKO2,
306 GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
307 GPIO_FN_SCIFA1_RXD,
308 GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
309 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
310 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
311 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
312 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
313 GPIO_FN_PORT233_FSIACK,
314 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
315 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
316 GPIO_FN_PORT235_FSIAILR,
317 GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
318 GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
319 GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
320
321 /* 55-5 (FN) */
322 GPIO_FN_MSIOF1_SS2,
323 GPIO_FN_SCIFA6_TXD,
324 GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
325 GPIO_FN_TPU4TO0,
326 GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
327 GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
328 GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
329 GPIO_FN_PORT244_MSIOF2_RXD,
330 GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
331 GPIO_FN_PORT245_MSIOF2_TXD,
332 GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
333 GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
334 GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
335 GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
336 GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
337 GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
338 GPIO_FN_PORT248_MSIOF2_TSCK,
339 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
340 GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
341 GPIO_FN_SDHICD0,
342 GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
343 GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
344 GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
345 GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
346 GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
347 GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
348 GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
349 GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
350 GPIO_FN_TMS3_SWDIO_MC1,
351 GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
352 GPIO_FN_TDO3_SWO0_MC1,
353 GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
354 GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
355 GPIO_FN_RTCK3_SWO1_MC1,
356 GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
357 GPIO_FN_RESETOUTS,
358};
359
360#endif /* __ASM_SH7377_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
new file mode 100644
index 00000000000..2b8fd8b942f
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_VMALLOC_H
2#define __ASM_MACH_VMALLOC_H
3
4/* Vmalloc at ... - 0xe5ffffff */
5#define VMALLOC_END 0xe6000000UL
6
7#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
new file mode 100644
index 00000000000..cc442d198cd
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -0,0 +1,440 @@
1/*
2 * sh7367 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28enum {
29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
32
33 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
36 DIRC,
37 CRYPT1_ERR, CRYPT2_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
40 ETM11_ACQCMP, ETM11_FULL,
41 MFI_MFIM, MFI_MFIS,
42 BBIF1, BBIF2,
43 USBDMAC_USHDMI,
44 USBHS_USHI0, USBHS_USHI1,
45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
46 KEYSC_KEY,
47 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
48 MSIOF2, MSIOF1,
49 SCIFA4, SCIFA5, SCIFB,
50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
51 SDHI0,
52 SDHI1,
53 MSU_MSU, MSU_MSU2,
54 IREM,
55 SIU,
56 SPU,
57 IRDA,
58 TPU0, TPU1, TPU2, TPU3, TPU4,
59 LCRC,
60 PINT1, PINT2,
61 TTI20,
62 MISTY,
63 DDM,
64 SDHI2,
65 RWDT0, RWDT1,
66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72
73 /* interrupt groups INTCA */
74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
75 ETM11, ARM11, USBHS, FLCTL, IIC1
76};
77
78static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
82 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
83 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
84 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
85 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
86 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
87 INTC_VECT(DIRC, 0x0560),
88 INTC_VECT(CRYPT1_ERR, 0x05e0),
89 INTC_VECT(CRYPT2_STD, 0x0700),
90 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
91 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
92 INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
93 INTC_VECT(ARM11_COMMRX, 0x0860),
94 INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
95 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
96 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
97 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
98 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
99 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
100 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
101 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
102 INTC_VECT(KEYSC_KEY, 0x0be0),
103 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
104 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
105 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
106 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
107 INTC_VECT(SCIFB, 0x0d60),
108 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
109 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
110 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
111 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
112 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
113 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
114 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
115 INTC_VECT(IREM, 0x0f60),
116 INTC_VECT(SIU, 0x0fa0),
117 INTC_VECT(SPU, 0x0fc0),
118 INTC_VECT(IRDA, 0x0480),
119 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
120 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
121 INTC_VECT(TPU4, 0x0520),
122 INTC_VECT(LCRC, 0x0540),
123 INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
124 INTC_VECT(TTI20, 0x1100),
125 INTC_VECT(MISTY, 0x1120),
126 INTC_VECT(DDM, 0x1140),
127 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
128 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
129 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
130 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
131 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
132 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
133 INTC_VECT(DMAC_2_DADERR, 0x20c0),
134 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
135 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
136 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
137 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
138 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
139 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
140 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
141 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
142};
143
144static struct intc_group intca_groups[] __initdata = {
145 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
146 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
147 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
148 DMAC_2_DEI5, DMAC_2_DADERR),
149 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
150 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
151 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
152 DMAC2_2_DEI5, DMAC2_2_DADERR),
153 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
154 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
155 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
156 DMAC3_2_DEI5, DMAC3_2_DADERR),
157 INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
158 INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
159 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
160 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
161 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
163};
164
165static struct intc_mask_reg intca_mask_registers[] __initdata = {
166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
169 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
170 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
171 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
172 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
173 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
174 { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
175 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
176 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
177 { PINT1, PINT2, 0, 0,
178 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
179 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
180 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
181 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
182 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
183 { DDM, 0, 0, 0,
184 0, 0, ETM11_FULL, ETM11_ACQCMP } },
185 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
186 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
187 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
188 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
189 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
190 0, 0, MSIOF2, 0 } },
191 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
192 { DISABLED, ENABLED, ENABLED, ENABLED,
193 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
194 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
195 { DISABLED, ENABLED, ENABLED, ENABLED,
196 TTI20, USBDMAC_USHDMI, SPU, SIU } },
197 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
198 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
199 CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
200 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
201 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
202 0, 0, 0, 0 } },
203 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
204 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
205 LCRC, MSU_MSU2, IREM, MSU_MSU } },
206 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
207 { 0, 0, TPU0, TPU1,
208 TPU2, TPU3, TPU4, 0 } },
209 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
210 { DISABLED, ENABLED, ENABLED, ENABLED,
211 MISTY, CMT3, RWDT1, RWDT0 } },
212};
213
214static struct intc_prio_reg intca_prio_registers[] __initdata = {
215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
218 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
219
220 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
221 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
222 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
223 CMT1_CMT11, ARM11 } },
224 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
225 CMT1_CMT12, TPU4 } },
226 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
227 MFI_MFIM, USBHS } },
228 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
229 0, CMT1_CMT10 } },
230 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
231 SCIFA2, SCIFA3 } },
232 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
233 FLCTL, SDHI0 } },
234 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
235 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
236 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
237 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
238 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
239 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
240 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
241};
242
243static struct intc_sense_reg intca_sense_registers[] __initdata = {
244 { 0xe6900000, 16, 2, /* ICR1A */
245 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
246 { 0xe6900004, 16, 2, /* ICR2A */
247 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
248};
249
250static struct intc_mask_reg intca_ack_registers[] __initdata = {
251 { 0xe6900020, 0, 8, /* INTREQ00A */
252 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
253 { 0xe6900024, 0, 8, /* INTREQ10A */
254 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
255};
256
257static struct intc_desc intca_desc __initdata = {
258 .name = "sh7367-intca",
259 .force_enable = ENABLED,
260 .force_disable = DISABLED,
261 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
262 intca_mask_registers, intca_prio_registers,
263 intca_sense_registers, intca_ack_registers),
264};
265
266enum {
267 UNUSED_INTCS = 0,
268
269 INTCS,
270
271 /* interrupt sources INTCS */
272 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
273 VIO3_VOU,
274 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
275 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
276 VPU,
277 SGX530,
278 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
279 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
280 IPMMU_IPMMUB, IPMMU_IPMMUS,
281 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
282 MSIOF,
283 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
284 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
285 CMT,
286 TSIF,
287 IPMMUI,
288 MVI3,
289 ICB,
290 PEP,
291 ASA,
292 BEM,
293 VE2HO,
294 HQE,
295 JPEG,
296 LCDC,
297
298 /* interrupt groups INTCS */
299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
300};
301
302static struct intc_vect intcs_vectors[] = {
303 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
304 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
305 INTCS_VECT(VIO3_VOU, 0x780),
306 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
307 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
308 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
309 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
310 INTCS_VECT(VPU, 0x980),
311 INTCS_VECT(SGX530, 0x9e0),
312 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
313 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
314 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
315 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
316 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
317 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
318 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
319 INTCS_VECT(MSIOF, 0xd20),
320 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
321 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
322 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
323 INTCS_VECT(TMU_TUNI2, 0xec0),
324 INTCS_VECT(CMT, 0xf00),
325 INTCS_VECT(TSIF, 0xf20),
326 INTCS_VECT(IPMMUI, 0xf60),
327 INTCS_VECT(MVI3, 0x420),
328 INTCS_VECT(ICB, 0x480),
329 INTCS_VECT(PEP, 0x4a0),
330 INTCS_VECT(ASA, 0x4c0),
331 INTCS_VECT(BEM, 0x4e0),
332 INTCS_VECT(VE2HO, 0x520),
333 INTCS_VECT(HQE, 0x540),
334 INTCS_VECT(JPEG, 0x560),
335 INTCS_VECT(LCDC, 0x580),
336
337 INTC_VECT(INTCS, 0xf80),
338};
339
340static struct intc_group intcs_groups[] __initdata = {
341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
342 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
343 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
344 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
345 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
346 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
347 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
348 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
349 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
350 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
351};
352
353static struct intc_mask_reg intcs_mask_registers[] = {
354 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
355 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
356 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
357 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
358 { VIO3_VOU, 0, VE2HO, VPU,
359 0, 0, 0, 0 } },
360 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
361 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
362 BEM, ASA, PEP, ICB } },
363 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
364 { 0, 0, MVI3, 0,
365 JPEG, HQE, 0, LCDC } },
366 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
367 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
368 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
369 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
370 { 0, 0, MSIOF, 0,
371 SGX530, 0, 0, 0 } },
372 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
373 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
374 0, 0, 0, 0 } },
375 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
376 { 0, 0, 0, CMT,
377 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
378 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
379 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
380 0, 0, 0, 0 } },
381 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
382 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
383 0, 0, IPMMUI, TSIF } },
384 { 0xffd20104, 0, 16, /* INTAMASK */
385 { 0, 0, 0, 0, 0, 0, 0, 0,
386 0, 0, 0, 0, 0, 0, 0, INTCS } },
387};
388
389/* Priority is needed for INTCA to receive the INTCS interrupt */
390static struct intc_prio_reg intcs_prio_registers[] = {
391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
392 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
393 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
394 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
395 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
396 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
397 TMU_TUNI2, 0 } },
398 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
399 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
400 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
401 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
402 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
403 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
404};
405
406static struct resource intcs_resources[] __initdata = {
407 [0] = {
408 .start = 0xffd20000,
409 .end = 0xffd2ffff,
410 .flags = IORESOURCE_MEM,
411 }
412};
413
414static struct intc_desc intcs_desc __initdata = {
415 .name = "sh7367-intcs",
416 .resource = intcs_resources,
417 .num_resources = ARRAY_SIZE(intcs_resources),
418 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
419 intcs_prio_registers, NULL, NULL),
420};
421
422static void intcs_demux(unsigned int irq, struct irq_desc *desc)
423{
424 void __iomem *reg = (void *)irq_get_handler_data(irq);
425 unsigned int evtcodeas = ioread32(reg);
426
427 generic_handle_irq(intcs_evt2irq(evtcodeas));
428}
429
430void __init sh7367_init_irq(void)
431{
432 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
433
434 register_intc_controller(&intca_desc);
435 register_intc_controller(&intcs_desc);
436
437 /* demux using INTEVTSA */
438 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
439 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
440}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
new file mode 100644
index 00000000000..fe45154ce66
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -0,0 +1,646 @@
1/*
2 * sh7377 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28enum {
29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
32
33 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
36 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
37 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
38 DIRC,
39 _2DG,
40 CRYPT_STD,
41 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
42 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI_MFIM, MFI_MFIS,
44 BBIF1, BBIF2,
45 USBDMAC_USHDMI,
46 USBHS_USHI0, USBHS_USHI1,
47 _3DG_SGX540,
48 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
49 KEYSC_KEY,
50 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
51 MSIOF2, MSIOF1,
52 SCIFA4, SCIFA5, SCIFB,
53 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
54 SDHI0,
55 SDHI1,
56 MSU_MSU, MSU_MSU2,
57 IRREM,
58 MSUG,
59 IRDA,
60 TPU0, TPU1, TPU2, TPU3, TPU4,
61 LCRC,
62 PINTCA_PINT1, PINTCA_PINT2,
63 TTI20,
64 MISTY,
65 DDM,
66 RWDT0, RWDT1,
67 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
68 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 ICUSB_ICUSB0, ICUSB_ICUSB1,
75 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
76 SPU2_SPU0, SPU2_SPU1,
77 FSI,
78 FMSI,
79 SCUV,
80 IPMMU_IPMMUB,
81 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 SCIFA6,
86
87 /* interrupt groups INTCA */
88 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
89 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
90 ICUSB, ICUDMC
91};
92
93static struct intc_vect intca_vectors[] __initdata = {
94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
97 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
98 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
99 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
100 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
101 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
102 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
103 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
104 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
105 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
106 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
107 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
108 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
109 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
110 INTC_VECT(DIRC, 0x0560),
111 INTC_VECT(_2DG, 0x05e0),
112 INTC_VECT(CRYPT_STD, 0x0700),
113 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
114 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
115 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
116 INTC_VECT(AP_ARM_COMMRX, 0x0860),
117 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
118 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
119 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
120 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
121 INTC_VECT(_3DG_SGX540, 0x0a60),
122 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
123 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
124 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
125 INTC_VECT(KEYSC_KEY, 0x0be0),
126 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
127 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
128 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
129 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
130 INTC_VECT(SCIFB, 0x0d60),
131 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
132 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
133 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
134 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
135 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
136 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
137 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
138 INTC_VECT(IRREM, 0x0f60),
139 INTC_VECT(MSUG, 0x0fa0),
140 INTC_VECT(IRDA, 0x0480),
141 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
142 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
143 INTC_VECT(TPU4, 0x0520),
144 INTC_VECT(LCRC, 0x0540),
145 INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
146 INTC_VECT(TTI20, 0x1100),
147 INTC_VECT(MISTY, 0x1120),
148 INTC_VECT(DDM, 0x1140),
149 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
150 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
151 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
152 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
153 INTC_VECT(DMAC_2_DADERR, 0x20c0),
154 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
155 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
156 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
157 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
158 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
159 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
160 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
161 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
162 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
163 INTC_VECT(SHWYSTAT_COM, 0x1340),
164 INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
165 INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
166 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
167 INTC_VECT(FSI, 0x1840),
168 INTC_VECT(FMSI, 0x1860),
169 INTC_VECT(SCUV, 0x1880),
170 INTC_VECT(IPMMU_IPMMUB, 0x1900),
171 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
172 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
173 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
174 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
175 INTC_VECT(MFIS2, 0x1a00),
176 INTC_VECT(CPORTR2S, 0x1a20),
177 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
178 INTC_VECT(SCIFA6, 0x1a80),
179};
180
181static struct intc_group intca_groups[] __initdata = {
182 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
183 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
184 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
185 DMAC_2_DEI5, DMAC_2_DADERR),
186 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
187 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
188 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
189 DMAC2_2_DEI5, DMAC2_2_DADERR),
190 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
191 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
192 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
193 DMAC3_2_DEI5, DMAC3_2_DADERR),
194 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
195 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
196 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
197 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
198 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
199 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
200 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
201 INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
203};
204
205static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
209 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
210 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
211 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
212 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
213 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
214
215 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
216 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
217 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
218 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
219 { _2DG, CRYPT_STD, DIRC, 0,
220 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
221 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
222 { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
223 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
224 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
225 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
226 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
227 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
228 { DDM, 0, 0, 0,
229 0, 0, 0, 0 } },
230 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
231 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
232 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
233 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
235 0, 0, MSIOF2, 0 } },
236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
237 { DISABLED, ENABLED, ENABLED, ENABLED,
238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
240 { DISABLED, ENABLED, ENABLED, ENABLED,
241 TTI20, USBDMAC_USHDMI, 0, MSUG } },
242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
244 CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
245 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
246 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
247 0, 0, 0, 0 } },
248 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
249 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
250 LCRC, MSU_MSU2, IRREM, MSU_MSU } },
251 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
252 { 0, 0, TPU0, TPU1,
253 TPU2, TPU3, TPU4, 0 } },
254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
255 { 0, 0, 0, 0,
256 MISTY, CMT3, RWDT1, RWDT0 } },
257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
259 0, 0, 0, 0 } },
260 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
261 { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
262 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
263 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
264 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
265 SCUV, 0, 0, 0 } },
266 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
267 { IPMMU_IPMMUB, 0, 0, 0,
268 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
269 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
270 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
271 { MFIS2, CPORTR2S, CMT14, CMT15,
272 SCIFA6, 0, 0, 0 } },
273};
274
275static struct intc_prio_reg intca_prio_registers[] __initdata = {
276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
279 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
280 { 0xe6900018, 0, 32, 4, /* INTPRI10A */
281 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
282 { 0xe690001c, 0, 32, 4, /* INTPRI30A */
283 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
284
285 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
286 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
287 { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
288 CMT1_CMT11, AP_ARM1 } },
289 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
290 CMT1_CMT12, TPU4 } },
291 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
292 MFI_MFIM, USBHS } },
293 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
294 _3DG_SGX540, CMT1_CMT10 } },
295 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
296 SCIFA2, SCIFA3 } },
297 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
298 FLCTL, SDHI0 } },
299 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
300 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
301 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
302 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
303 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
304 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
305 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
306 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
307 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
308 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
309 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
310 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
311 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
312 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
313 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
314 CMT14, CMT15 } },
315 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
316};
317
318static struct intc_sense_reg intca_sense_registers[] __initdata = {
319 { 0xe6900000, 16, 2, /* ICR1A */
320 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
321 { 0xe6900004, 16, 2, /* ICR2A */
322 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
323 { 0xe6900008, 16, 2, /* ICR3A */
324 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
325 { 0xe690000c, 16, 2, /* ICR4A */
326 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
327};
328
329static struct intc_mask_reg intca_ack_registers[] __initdata = {
330 { 0xe6900020, 0, 8, /* INTREQ00A */
331 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
332 { 0xe6900024, 0, 8, /* INTREQ10A */
333 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
334 { 0xe6900028, 0, 8, /* INTREQ20A */
335 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
336 { 0xe690002c, 0, 8, /* INTREQ30A */
337 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
338};
339
340static struct intc_desc intca_desc __initdata = {
341 .name = "sh7377-intca",
342 .force_enable = ENABLED,
343 .force_disable = DISABLED,
344 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
345 intca_mask_registers, intca_prio_registers,
346 intca_sense_registers, intca_ack_registers),
347};
348
349/* this macro ignore entry which is also in INTCA */
350#define __IGNORE(a...)
351#define __IGNORE0(a...) 0
352
353enum {
354 UNUSED_INTCS = 0,
355
356 INTCS,
357
358 /* interrupt sources INTCS */
359 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
360 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
361 CEU,
362 BEU_BEU0, BEU_BEU1, BEU_BEU2,
363 __IGNORE(MFI)
364 __IGNORE(BBIF2)
365 VPU,
366 TSIF1,
367 __IGNORE(SGX540)
368 _2DDMAC,
369 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
370 IPMMU_IPMMUR, IPMMU_IPMMUR2,
371 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
372 __IGNORE(KEYSC)
373 __IGNORE(TTI20)
374 __IGNORE(MSIOF)
375 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
376 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
377 CMT0,
378 TSIF0,
379 __IGNORE(CMT2)
380 LMB,
381 __IGNORE(MSUG)
382 __IGNORE(MSU_MSU, MSU_MSU2)
383 __IGNORE(CTI)
384 MVI3,
385 __IGNORE(RWDT0)
386 __IGNORE(RWDT1)
387 ICB,
388 PEP,
389 ASA,
390 __IGNORE(_2DG)
391 HQE,
392 JPU,
393 LCDC0,
394 __IGNORE(LCRC)
395 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
396 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
397 FRC,
398 LCDC1,
399 CSIRX,
400 DSITX_DSITX0, DSITX_DSITX1,
401 __IGNORE(SPU2_SPU0, SPU2_SPU1)
402 __IGNORE(FSI)
403 __IGNORE(FMSI)
404 __IGNORE(SCUV)
405 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
406 TSIF2,
407 CMT4,
408 __IGNORE(MFIS2)
409 CPORTS2R,
410
411 /* interrupt groups INTCS */
412 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
413 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
414};
415
416#define INTCS_INTVECT 0x0F80
417static struct intc_vect intcs_vectors[] __initdata = {
418 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
419 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
420 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
421 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
422 INTCS_VECT(CEU, 0x0880),
423 INTCS_VECT(BEU_BEU0, 0x08A0),
424 INTCS_VECT(BEU_BEU1, 0x08C0),
425 INTCS_VECT(BEU_BEU2, 0x08E0),
426 __IGNORE(INTCS_VECT(MFI, 0x0900))
427 __IGNORE(INTCS_VECT(BBIF2, 0x0960))
428 INTCS_VECT(VPU, 0x0980),
429 INTCS_VECT(TSIF1, 0x09A0),
430 __IGNORE(INTCS_VECT(SGX540, 0x09E0))
431 INTCS_VECT(_2DDMAC, 0x0A00),
432 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
433 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
434 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
435 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
436 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
437 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
438 __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
439 __IGNORE(INTCS_VECT(TTI20, 0x0C80))
440 __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
441 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
442 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
443 INTCS_VECT(TMU_TUNI0, 0x0E80),
444 INTCS_VECT(TMU_TUNI1, 0x0EA0),
445 INTCS_VECT(TMU_TUNI2, 0x0EC0),
446 INTCS_VECT(CMT0, 0x0F00),
447 INTCS_VECT(TSIF0, 0x0F20),
448 __IGNORE(INTCS_VECT(CMT2, 0x0F40))
449 INTCS_VECT(LMB, 0x0F60),
450 __IGNORE(INTCS_VECT(MSUG, 0x0F80))
451 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
452 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
453 __IGNORE(INTCS_VECT(CTI, 0x0400))
454 INTCS_VECT(MVI3, 0x0420),
455 __IGNORE(INTCS_VECT(RWDT0, 0x0440))
456 __IGNORE(INTCS_VECT(RWDT1, 0x0460))
457 INTCS_VECT(ICB, 0x0480),
458 INTCS_VECT(PEP, 0x04A0),
459 INTCS_VECT(ASA, 0x04C0),
460 __IGNORE(INTCS_VECT(_2DG, 0x04E0))
461 INTCS_VECT(HQE, 0x0540),
462 INTCS_VECT(JPU, 0x0560),
463 INTCS_VECT(LCDC0, 0x0580),
464 __IGNORE(INTCS_VECT(LCRC, 0x05A0))
465 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
466 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
467 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
468 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
469 INTCS_VECT(FRC, 0x1700),
470 INTCS_VECT(LCDC1, 0x1780),
471 INTCS_VECT(CSIRX, 0x17A0),
472 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
473 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
474 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
475 __IGNORE(INTCS_VECT(FSI, 0x1840))
476 __IGNORE(INTCS_VECT(FMSI, 0x1860))
477 __IGNORE(INTCS_VECT(SCUV, 0x1880))
478 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
479 INTCS_VECT(TMU1_TUNI12, 0x1940),
480 INTCS_VECT(TSIF2, 0x1960),
481 INTCS_VECT(CMT4, 0x1980),
482 __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
483 INTCS_VECT(CPORTS2R, 0x1A20),
484
485 INTC_VECT(INTCS, INTCS_INTVECT),
486};
487
488static struct intc_group intcs_groups[] __initdata = {
489 INTC_GROUP(RTDMAC1_1,
490 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
491 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
492 INTC_GROUP(RTDMAC1_2,
493 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
494 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
495 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
496 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
497 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
498 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
499 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
500 INTC_GROUP(RTDMAC2_1,
501 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
502 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
503 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
504 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
505 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
506 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
507};
508
509static struct intc_mask_reg intcs_mask_registers[] __initdata = {
510 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
511 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
512 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
513 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
514 { 0, 0, 0, VPU,
515 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
516 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
517 { 0, 0, 0, _2DDMAC,
518 __IGNORE0(_2DG), ASA, PEP, ICB } },
519 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
520 { 0, 0, MVI3, __IGNORE0(CTI),
521 JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
522 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
523 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
524 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
525 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
526 { 0, 0, MSIOF, 0,
527 SGX540, 0, TTI20, 0 } })
528 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
529 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
530 0, 0, 0, 0 } },
531 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
532 { 0, 0, 0, 0,
533 0, MSU_MSU, MSU_MSU2, MSUG } })
534 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
535 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
536 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
537 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
538 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
539 0, 0, 0, 0 } },
540 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
541 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
542 0, TSIF1, LMB, TSIF0 } },
543 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
544 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
545 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
546 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
547 { FRC, 0, 0, 0,
548 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
549 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
550 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
551 SCUV, 0, 0, 0 } })
552 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
553 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
554 CMT4, 0, 0, 0 } },
555 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
556 { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
557 0, 0, 0, 0 } },
558 { 0xFFD20104, 0, 16, /* INTAMASK */
559 { 0, 0, 0, 0, 0, 0, 0, 0,
560 0, 0, 0, 0, 0, 0, 0, INTCS } }
561};
562
563static struct intc_prio_reg intcs_prio_registers[] __initdata = {
564 /* IPRAS */
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
566 /* IPRBS */
567 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
568 /* IPRCS */
569 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
570 /* IPRES */
571 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
572 /* IPRFS */
573 { 0xFFD20014, 0, 16, 4,
574 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
575 /* IPRGS */
576 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
577 /* IPRHS */
578 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
579 /* IPRIS */
580 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
581 /* IPRJS */
582 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
583 /* IPRKS */
584 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
585 /* IPRLS */
586 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
587 /* IPRMS */
588 { 0xFFD20030, 0, 16, 4,
589 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
590 /* IPRAS3 */
591 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
592 /* IPRBS3 */
593 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
594 /* IPRIS3 */
595 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
596 /* IPRJS3 */
597 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
598 /* IPRKS3 */
599 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
600 /* IPRLS3 */
601 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
602 /* IPRMS3 */
603 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
604 /* IPRNS3 */
605 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
606 /* IPROS3 */
607 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
608};
609
610static struct resource intcs_resources[] __initdata = {
611 [0] = {
612 .start = 0xffd20000,
613 .end = 0xffd500ff,
614 .flags = IORESOURCE_MEM,
615 }
616};
617
618static struct intc_desc intcs_desc __initdata = {
619 .name = "sh7377-intcs",
620 .resource = intcs_resources,
621 .num_resources = ARRAY_SIZE(intcs_resources),
622 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
623 intcs_mask_registers, intcs_prio_registers,
624 NULL, NULL),
625};
626
627static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628{
629 void __iomem *reg = (void *)irq_get_handler_data(irq);
630 unsigned int evtcodeas = ioread32(reg);
631
632 generic_handle_irq(intcs_evt2irq(evtcodeas));
633}
634
635#define INTEVTSA 0xFFD20100
636void __init sh7377_init_irq(void)
637{
638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
639
640 register_intc_controller(&intca_desc);
641 register_intc_controller(&intcs_desc);
642
643 /* demux using INTEVTSA */
644 irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645 irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
646}
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
new file mode 100644
index 00000000000..ad9ccc9900c
--- /dev/null
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -0,0 +1,26 @@
1/*
2 * SMP support for R-Mobile / SH-Mobile - local timer portion
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/init.h>
13#include <linux/smp.h>
14#include <linux/clockchips.h>
15#include <asm/smp_twd.h>
16#include <asm/localtimer.h>
17
18/*
19 * Setup the local clock events for a CPU.
20 */
21int __cpuinit local_timer_setup(struct clock_event_device *evt)
22{
23 evt->irq = 29;
24 twd_timer_setup(evt);
25 return 0;
26}
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
new file mode 100644
index 00000000000..128555e76e4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -0,0 +1,1801 @@
1/*
2 * sh7367 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/gpio.h>
22#include <mach/sh7367.h>
23
24#define _1(fn, pfx, sfx) fn(pfx, sfx)
25
26#define _10(fn, pfx, sfx) \
27 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
28 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
29 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
30 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
31 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
32
33#define _90(fn, pfx, sfx) \
34 _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
35 _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
36 _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
37 _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
38 _10(fn, pfx##9, sfx)
39
40#define _273(fn, pfx, sfx) \
41 _10(fn, pfx, sfx), _90(fn, pfx, sfx), \
42 _10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \
43 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
44 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
45 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
46 _10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \
47 _1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx)
48
49#define _PORT(pfx, sfx) pfx##_##sfx
50#define PORT_273(str) _273(_PORT, PORT, str)
51
52enum {
53 PINMUX_RESERVED = 0,
54
55 PINMUX_DATA_BEGIN,
56 PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */
57 PINMUX_DATA_END,
58
59 PINMUX_INPUT_BEGIN,
60 PORT_273(IN), /* PORT0_IN -> PORT272_IN */
61 PINMUX_INPUT_END,
62
63 PINMUX_INPUT_PULLUP_BEGIN,
64 PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
65 PINMUX_INPUT_PULLUP_END,
66
67 PINMUX_INPUT_PULLDOWN_BEGIN,
68 PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
69 PINMUX_INPUT_PULLDOWN_END,
70
71 PINMUX_OUTPUT_BEGIN,
72 PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */
73 PINMUX_OUTPUT_END,
74
75 PINMUX_FUNCTION_BEGIN,
76 PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
77 PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
78 PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */
79 PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */
80 PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */
81 PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */
82 PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */
83 PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */
84 PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */
85 PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */
86
87 MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
88 PINMUX_FUNCTION_END,
89
90 PINMUX_MARK_BEGIN,
91 /* Special Pull-up / Pull-down Functions */
92 PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
93 PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
94 PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
95 PORT58_KEYIN6_PU_MARK,
96
97 /* 49-1 */
98 VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
99 CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
100 CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
101 CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
102 CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
103 CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
104 CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
105 RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
106 STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
107 MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
108 XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
109 IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
110 M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
111 XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
112 XCTS1_MARK, SCIFA4_CTS_MARK,
113
114 /* 49-2 */
115 HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
116 HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
117 HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
118 HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
119 HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
120 HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
121 HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
122 HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
123 HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
124 HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
125 HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
126 HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
127 HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
128 HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
129 HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
130 HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
131 B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
132 HSU_SDI_MARK, PORT55_KEYIN3_MARK,
133 HSU_SCO_MARK, PORT56_KEYIN4_MARK,
134 HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
135 HSU_DACK_MARK, PORT58_KEYIN6_MARK,
136 HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
137 HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
138 PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
139 XTALB1L_MARK,
140 GPS_AGC1_MARK, SCIFA0_RTS_MARK,
141 GPS_AGC2_MARK, SCIFA0_SCK_MARK,
142 GPS_AGC3_MARK, SCIFA0_TXD_MARK,
143 GPS_AGC4_MARK, SCIFA0_RXD_MARK,
144 GPS_PWRD_MARK, SCIFA0_CTS_MARK,
145 GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
146 SIUBOMC_MARK, TPU2TO0_MARK,
147 SIUCKB_MARK, TPU2TO1_MARK,
148 SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
149 SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
150 SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
151 SIUBILR_MARK, TPU3TO1_MARK,
152 SIUBIBT_MARK, TPU3TO2_MARK,
153 SIUBISLD_MARK, TPU3TO3_MARK,
154 NMI_MARK, TPU4TO0_MARK,
155 DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
156 IRQ_TMPB_MARK,
157 PWEN_MARK, MFG1_OUT1_MARK,
158 OVCN_MARK, MFG1_IN1_MARK,
159 OVCN2_MARK, MFG1_IN2_MARK,
160
161 /* 49-3 */
162 RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
163 USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
164 SCIFA5_CTS_MARK, MFG0_IN1_MARK,
165 SCIFA5_RTS_MARK, MFG0_IN2_MARK,
166 SCIFA5_RXD_MARK,
167 SCIFA5_TXD_MARK,
168 SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
169 A0_EA0_MARK, BS_MARK,
170 A14_EA14_MARK, PORT102_KEYOUT0_MARK,
171 A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
172 A16_EA16_MARK, PORT104_KEYOUT2_MARK,
173 DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
174 A17_EA17_MARK, PORT105_KEYOUT3_MARK,
175 DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
176 A18_EA18_MARK, PORT106_KEYOUT4_MARK,
177 DV_DL0_MARK, MSIOF0_TSCK_MARK,
178 A19_EA19_MARK, PORT107_KEYOUT5_MARK,
179 DV_DL1_MARK, MSIOF0_TXD_MARK,
180 A20_EA20_MARK, PORT108_KEYIN0_MARK,
181 DV_DL2_MARK, MSIOF0_RSCK_MARK,
182 A21_EA21_MARK, PORT109_KEYIN1_MARK,
183 DV_DL3_MARK, MSIOF0_RSYNC_MARK,
184 A22_EA22_MARK, PORT110_KEYIN2_MARK,
185 DV_DL4_MARK, MSIOF0_MCK0_MARK,
186 A23_EA23_MARK, PORT111_KEYIN3_MARK,
187 DV_DL5_MARK, MSIOF0_MCK1_MARK,
188 A24_EA24_MARK, PORT112_KEYIN4_MARK,
189 DV_DL6_MARK, MSIOF0_RXD_MARK,
190 A25_EA25_MARK, PORT113_KEYIN5_MARK,
191 DV_DL7_MARK, MSIOF0_SS2_MARK,
192 A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
193 D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
194 D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
195 D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
196 D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
197 D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
198 D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
199 CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
200 CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
201 DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
202 A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
203 WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
204 NBRSTOUT_MARK, NBRST_MARK,
205
206 /* 49-4 */
207 RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
208 VIO_VD_MARK, VIO_HD_MARK,
209 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
210 VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
211 VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
212 VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
213 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
214 VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
215 VIO_CKO_MARK,
216 MFG3_IN1_MARK, MFG3_IN2_MARK,
217 M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
218 M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
219 M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
220 M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
221 LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
222 SIUCKA_MARK, MFG0_OUT2_MARK,
223 LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
224 SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
225 LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
226 SIUAOBT_MARK, BBIF2_TSCK1_MARK,
227 LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
228 SIUAOSLD_MARK, BBIF2_TXD1_MARK,
229 LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
230 SIUAISPD_MARK, MFG1_OUT2_MARK,
231 LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
232 SIUAILR_MARK, MFG2_OUT2_MARK,
233 LCDD6_MARK, DV_D6_MARK,
234 SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
235 LCDD7_MARK, DV_D7_MARK,
236 SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
237 LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
238 LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
239 LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
240 LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
241 LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
242 LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
243 LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
244 LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
245 LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
246 LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
247 LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
248 D26_MARK, ED26_MARK,
249 LCDD19_MARK, MSIOF0L_TSYNC_MARK,
250 D27_MARK, ED27_MARK,
251 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
252 D28_MARK, ED28_MARK,
253 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
254 D29_MARK, ED29_MARK,
255 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
256 D30_MARK, ED30_MARK,
257 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
258 D31_MARK, ED31_MARK,
259 LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
260 LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
261
262 /* 49-5 */
263 LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
264 LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
265 LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
266 LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
267 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
268 VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
269 VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
270 VIO_VDR_MARK, VIO_HDR_MARK,
271 VIO_CLKR_MARK, VIO_CKOR_MARK,
272 SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
273 SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
274 SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
275 SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
276 MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
277 MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
278 MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
279 MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
280 MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
281 MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
282 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
283 MSIOF1_SS1_MARK, EDBGREQ3_MARK,
284 MSIOF1_SS2_MARK,
285 PORT236_IROUT_MARK, IRDA_OUT_MARK,
286 IRDA_IN_MARK, IRDA_FIRSEL_MARK,
287 TPU1TO0_MARK, TS_SPSYNC3_MARK,
288 TPU1TO1_MARK, TS_SDAT3_MARK,
289 TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
290 TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
291 M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
292 M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
293 PORT245_IROUT_MARK, M15_RSW_MARK,
294 SOUT3_MARK, SCIFA2_TXD1_MARK,
295 SIN3_MARK, SCIFA2_RXD1_MARK,
296 XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
297 XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
298 DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
299 SDHICLK0_MARK, TCK2_MARK,
300 SDHICD0_MARK,
301 SDHID0_0_MARK, TMS2_MARK,
302 SDHID0_1_MARK, TDO2_MARK,
303 SDHID0_2_MARK, TDI2_MARK,
304 SDHID0_3_MARK, RTCK2_MARK,
305
306 /* 49-6 */
307 SDHICMD0_MARK, TRST2_MARK,
308 SDHIWP0_MARK, EDBGREQ2_MARK,
309 SDHICLK1_MARK, TCK3_MARK,
310 SDHID1_0_MARK, M11_SLCD_SO2_MARK,
311 TS_SPSYNC2_MARK, TMS3_MARK,
312 SDHID1_1_MARK, M9_SLCD_AO2_MARK,
313 TS_SDAT2_MARK, TDO3_MARK,
314 SDHID1_2_MARK, M10_SLCD_CK2_MARK,
315 TS_SDEN2_MARK, TDI3_MARK,
316 SDHID1_3_MARK, M12_SLCD_CE2_MARK,
317 TS_SCK2_MARK, RTCK3_MARK,
318 SDHICMD1_MARK, TRST3_MARK,
319 SDHICLK2_MARK, SCIFB_SCK_MARK,
320 SDHID2_0_MARK, SCIFB_TXD_MARK,
321 SDHID2_1_MARK, SCIFB_CTS_MARK,
322 SDHID2_2_MARK, SCIFB_RXD_MARK,
323 SDHID2_3_MARK, SCIFB_RTS_MARK,
324 SDHICMD2_MARK,
325 RESETOUTS_MARK,
326 DIVLOCK_MARK,
327 PINMUX_MARK_END,
328};
329
330#define PORT_DATA_I(nr) \
331 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
332
333#define PORT_DATA_I_PD(nr) \
334 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
335 PORT##nr##_IN, PORT##nr##_IN_PD)
336
337#define PORT_DATA_I_PU(nr) \
338 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
339 PORT##nr##_IN, PORT##nr##_IN_PU)
340
341#define PORT_DATA_I_PU_PD(nr) \
342 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
343 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
344
345#define PORT_DATA_O(nr) \
346 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
347
348#define PORT_DATA_IO(nr) \
349 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
350 PORT##nr##_IN)
351
352#define PORT_DATA_IO_PD(nr) \
353 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
354 PORT##nr##_IN, PORT##nr##_IN_PD)
355
356#define PORT_DATA_IO_PU(nr) \
357 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
358 PORT##nr##_IN, PORT##nr##_IN_PU)
359
360#define PORT_DATA_IO_PU_PD(nr) \
361 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
362 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
363
364
365static pinmux_enum_t pinmux_data[] = {
366
367 /* specify valid pin states for each pin in GPIO mode */
368
369 /* 49-1 (GPIO) */
370 PORT_DATA_I_PD(0),
371 PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
372 PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
373 PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
374 PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
375 PORT_DATA_I_PU(13),
376 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
377 PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
378 PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
379 PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
380 PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
381 PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
382 PORT_DATA_IO_PU(33),
383 PORT_DATA_O(34),
384 PORT_DATA_I_PU(35),
385 PORT_DATA_O(36),
386 PORT_DATA_I_PU_PD(37),
387
388 /* 49-2 (GPIO) */
389 PORT_DATA_IO_PU_PD(38),
390 PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
391 PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
392 PORT_DATA_O(46), PORT_DATA_O(47),
393 PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
394 PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
395 PORT_DATA_O(53),
396 PORT_DATA_IO_PD(54),
397 PORT_DATA_I_PU_PD(55),
398 PORT_DATA_IO_PU_PD(56),
399 PORT_DATA_I_PU_PD(57),
400 PORT_DATA_IO_PU_PD(58),
401 PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
402 PORT_DATA_O(63),
403 PORT_DATA_I_PU(64),
404 PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
405 PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
406 PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
407 PORT_DATA_I_PD(74),
408 PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
409 PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
410 PORT_DATA_O(79),
411 PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
412 PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
413 PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
414 PORT_DATA_I_PD(87),
415 PORT_DATA_IO_PU_PD(88),
416 PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
417
418 /* 49-3 (GPIO) */
419 PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
420 PORT_DATA_I_PU_PD(95),
421 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
422 PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
423 PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
424 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
425 PORT_DATA_IO_PD(107),
426 PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
427 PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
428 PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
429 PORT_DATA_IO_PU_PD(114),
430 PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
431 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
432 PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
433 PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
434 PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
435 PORT_DATA_IO_PU(130),
436 PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
437 PORT_DATA_IO_PU(134),
438 PORT_DATA_O(135), PORT_DATA_O(136),
439 PORT_DATA_I_PU_PD(137),
440 PORT_DATA_IO(138),
441 PORT_DATA_IO_PU_PD(139),
442 PORT_DATA_IO(140), PORT_DATA_IO(141),
443 PORT_DATA_I_PU(142),
444 PORT_DATA_O(143), PORT_DATA_O(144),
445 PORT_DATA_I_PU(145),
446
447 /* 49-4 (GPIO) */
448 PORT_DATA_O(146),
449 PORT_DATA_I_PU_PD(147),
450 PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
451 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
452 PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
453 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
454 PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
455 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
456 PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
457 PORT_DATA_IO_PU_PD(167),
458 PORT_DATA_O(168),
459 PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
460 PORT_DATA_O(171),
461 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
462 PORT_DATA_O(174),
463 PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
464 PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
465 PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
466 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
467 PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
468 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
469 PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
470 PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
471 PORT_DATA_O(199),
472 PORT_DATA_IO_PD(200),
473
474 /* 49-5 (GPIO) */
475 PORT_DATA_O(201),
476 PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
477 PORT_DATA_I(204),
478 PORT_DATA_O(205),
479 PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
480 PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
481 PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
482 PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
483 PORT_DATA_O(217),
484 PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
485 PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
486 PORT_DATA_I_PD(223),
487 PORT_DATA_I_PU_PD(224),
488 PORT_DATA_O(225),
489 PORT_DATA_IO_PD(226),
490 PORT_DATA_IO_PU_PD(227),
491 PORT_DATA_I_PD(228),
492 PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
493 PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
494 PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
495 PORT_DATA_I_PU_PD(235),
496 PORT_DATA_O(236),
497 PORT_DATA_I_PD(237),
498 PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
499 PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
500 PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
501 PORT_DATA_O(244),
502 PORT_DATA_IO_PU_PD(245),
503 PORT_DATA_O(246),
504 PORT_DATA_I_PD(247),
505 PORT_DATA_IO_PU_PD(248),
506 PORT_DATA_I_PU_PD(249),
507 PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
508 PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
509 PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
510 PORT_DATA_IO_PU_PD(256),
511
512 /* 49-6 (GPIO) */
513 PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
514 PORT_DATA_IO_PD(259),
515 PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
516 PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
517 PORT_DATA_O(265),
518 PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
519 PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
520 PORT_DATA_O(271),
521 PORT_DATA_I_PD(272),
522
523 /* Special Pull-up / Pull-down Functions */
524 PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
525 PORT48_FN2, PORT48_IN_PU),
526 PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
527 PORT49_FN2, PORT49_IN_PU),
528 PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
529 PORT50_FN2, PORT50_IN_PU),
530 PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
531 PORT55_FN2, PORT55_IN_PU),
532 PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
533 PORT56_FN2, PORT56_IN_PU),
534 PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
535 PORT57_FN2, PORT57_IN_PU),
536 PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
537 PORT58_FN2, PORT58_IN_PU),
538
539 /* 49-1 (FN) */
540 PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
541 PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
542 PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
543 PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
544 PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
545 PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
546 PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
547 PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
548 PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
549 PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
550 PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
551 PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
552 PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
553 PINMUX_DATA(SIN2_MARK, PORT12_FN2),
554 PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
555 PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
556 PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
557 PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
558 PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
559 PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
560 PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
561 PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
562 PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
563 PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
564 PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
565 PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
566 PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
567 PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
568 PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
569 PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
570 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
571 PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
572 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
573 PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
574 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
575 PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
576 PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
577 PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
578 PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
579 PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
580 PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
581 PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
582 PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
583 PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
584 PINMUX_DATA(IDIO_MARK, PORT33_FN1),
585 PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
586 PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
587 PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
588 PINMUX_DATA(SIN1_MARK, PORT35_FN1),
589 PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
590 PINMUX_DATA(XWUP_MARK, PORT35_FN3),
591 PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
592 PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
593 PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
594 PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
595 PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
596
597 /* 49-2 (FN) */
598 PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
599 PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
600 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
601 PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
602 PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
603 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
604 PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
605 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
606 PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
607 PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
608 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
609 PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
610 PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
611 PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
612 PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
613 PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
614 PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
615 PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
616 PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
617 PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
618 PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
619 PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
620 PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
621 PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
622 PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
623 PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
624 PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
625 PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
626 PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
627 PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
628 PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
629 PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
630 PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
631 PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
632 PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
633 PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
634 PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
635 PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
636 PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
637 PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
638 PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
639 PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
640 PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
641 PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
642 PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
643 PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
644 PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
645 PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
646 PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
647 PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
648 PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
649 PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
650 PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
651 PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
652 PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
653 PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
654 PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
655 PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
656 PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
657 PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
658 PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
659 PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
660 PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
661 PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
662 PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
663 PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
664 PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
665 PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
666 PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
667 PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
668 PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
669 PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
670 PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
671 PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
672 PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
673 PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
674 PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
675 PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
676 PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
677 PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
678 PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
679 PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
680 PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
681 PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
682 PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
683 PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
684 PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
685 PINMUX_DATA(NMI_MARK, PORT83_FN1),
686 PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
687 PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
688 PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
689 PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
690 PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
691 PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
692 PINMUX_DATA(PWEN_MARK, PORT88_FN1),
693 PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
694 PINMUX_DATA(OVCN_MARK, PORT89_FN1),
695 PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
696 PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
697 PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
698
699 /* 49-3 (FN) */
700 PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
701 PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
702 PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
703 PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
704 PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
705 PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
706 PINMUX_DATA(IDIN_MARK, PORT95_FN1),
707 PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
708 PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
709 PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
710 PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
711 PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
712 PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
713 PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
714 PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
715 PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
716 PINMUX_DATA(BS_MARK, PORT101_FN2),
717 PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
718 PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
719 PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
720 PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
721 PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
722 PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
723 PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
724 PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
725 PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
726 PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
727 PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
728 PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
729 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
730 PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
731 PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
732 PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
733 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
734 PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
735 PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
736 PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
737 PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
738 PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
739 PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
740 PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
741 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
742 PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
743 PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
744 PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
745 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
746 PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
747 PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
748 PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
749 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
750 PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
751 PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
752 PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
753 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
754 PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
755 PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
756 PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
757 PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
758 PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
759 PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
760 PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
761 PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
762 PINMUX_DATA(A26_MARK, PORT114_FN1),
763 PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
764 PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
765 PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
766 PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
767 PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
768 PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
769 PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
770 PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
771 PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
772 PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
773 PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
774 PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
775 PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
776 PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
777 PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
778 PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
779 PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
780 PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
781 PINMUX_DATA(CS4_MARK, PORT131_FN1),
782 PINMUX_DATA(CS5A_MARK, PORT132_FN1),
783 PINMUX_DATA(CS5B_MARK, PORT133_FN1),
784 PINMUX_DATA(FCE1_MARK, PORT133_FN2),
785 PINMUX_DATA(CS6B_MARK, PORT134_FN1),
786 PINMUX_DATA(XCS2_MARK, PORT134_FN2),
787 PINMUX_DATA(FCE0_MARK, PORT135_FN1),
788 PINMUX_DATA(CS6A_MARK, PORT136_FN1),
789 PINMUX_DATA(DACK0_MARK, PORT136_FN2),
790 PINMUX_DATA(WAIT_MARK, PORT137_FN1),
791 PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
792 PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
793 PINMUX_DATA(A27_MARK, PORT139_FN1),
794 PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
795 PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
796 PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
797 PINMUX_DATA(FRB_MARK, PORT142_FN1),
798 PINMUX_DATA(CKO_MARK, PORT143_FN1),
799 PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
800 PINMUX_DATA(NBRST_MARK, PORT145_FN1),
801
802 /* 49-4 (FN) */
803 PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
804 PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
805 PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
806 PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
807 PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
808 PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
809 PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
810 PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
811 PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
812 PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
813 PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
814 PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
815 PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
816 PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
817 PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
818 PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
819 PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
820 PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
821 PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
822 PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
823 PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
824 PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
825 PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
826 PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
827 PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
828 PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
829 PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
830 PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
831 PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
832 PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
833 PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
834 PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
835 PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
836 PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
837 PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
838 PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
839 PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
840 PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
841 PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
842 PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
843 PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
844 PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
845 PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
846 PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
847 PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
848 PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
849 PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
850 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
851 PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
852 PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
853 PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
854 PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
855 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
856 PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
857 PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
858 PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
859 PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
860 PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
861 PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
862 PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
863 PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
864 PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
865 PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
866 PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
867 PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
868 PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
869 PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
870 PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
871 PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
872 PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
873 PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
874 PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
875 PINMUX_DATA(XWR2_MARK, PORT181_FN7),
876 PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
877 PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
878 PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
879 PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
880 PINMUX_DATA(XWR3_MARK, PORT182_FN7),
881 PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
882 PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
883 PINMUX_DATA(D16_MARK, PORT183_FN6),
884 PINMUX_DATA(ED16_MARK, PORT183_FN7),
885 PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
886 PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
887 PINMUX_DATA(D17_MARK, PORT184_FN6),
888 PINMUX_DATA(ED17_MARK, PORT184_FN7),
889 PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
890 PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
891 PINMUX_DATA(D18_MARK, PORT185_FN6),
892 PINMUX_DATA(ED18_MARK, PORT185_FN7),
893 PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
894 PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
895 PINMUX_DATA(D19_MARK, PORT186_FN6),
896 PINMUX_DATA(ED19_MARK, PORT186_FN7),
897 PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
898 PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
899 PINMUX_DATA(D20_MARK, PORT187_FN6),
900 PINMUX_DATA(ED20_MARK, PORT187_FN7),
901 PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
902 PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
903 PINMUX_DATA(D21_MARK, PORT188_FN6),
904 PINMUX_DATA(ED21_MARK, PORT188_FN7),
905 PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
906 PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
907 PINMUX_DATA(D22_MARK, PORT189_FN6),
908 PINMUX_DATA(ED22_MARK, PORT189_FN7),
909 PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
910 PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
911 PINMUX_DATA(D23_MARK, PORT190_FN6),
912 PINMUX_DATA(ED23_MARK, PORT190_FN7),
913 PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
914 PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
915 PINMUX_DATA(D24_MARK, PORT191_FN6),
916 PINMUX_DATA(ED24_MARK, PORT191_FN7),
917 PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
918 PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
919 PINMUX_DATA(D25_MARK, PORT192_FN6),
920 PINMUX_DATA(ED25_MARK, PORT192_FN7),
921 PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
922 PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
923 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
924 PINMUX_DATA(D26_MARK, PORT193_FN6),
925 PINMUX_DATA(ED26_MARK, PORT193_FN7),
926 PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
927 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
928 PINMUX_DATA(D27_MARK, PORT194_FN6),
929 PINMUX_DATA(ED27_MARK, PORT194_FN7),
930 PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
931 PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
932 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
933 PINMUX_DATA(D28_MARK, PORT195_FN6),
934 PINMUX_DATA(ED28_MARK, PORT195_FN7),
935 PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
936 PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
937 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
938 PINMUX_DATA(D29_MARK, PORT196_FN6),
939 PINMUX_DATA(ED29_MARK, PORT196_FN7),
940 PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
941 PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
942 PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
943 PINMUX_DATA(D30_MARK, PORT197_FN6),
944 PINMUX_DATA(ED30_MARK, PORT197_FN7),
945 PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
946 PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
947 PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
948 PINMUX_DATA(D31_MARK, PORT198_FN6),
949 PINMUX_DATA(ED31_MARK, PORT198_FN7),
950 PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
951 PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
952 PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
953 PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
954 PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
955 PINMUX_DATA(DACK2_MARK, PORT200_FN2),
956 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
957
958 /* 49-5 (FN) */
959 PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
960 PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
961 PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
962 PINMUX_DATA(DACK3_MARK, PORT201_FN4),
963 PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
964 PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
965 PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
966 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
967 PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
968 PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
969 PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
970 PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
971 PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
972 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
973 PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
974 PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
975 PINMUX_DATA(DACK1_MARK, PORT205_FN3),
976 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
977 PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
978 PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
979 PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
980 PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
981 PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
982 PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
983 PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
984 PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
985 PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
986 PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
987 PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
988 PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
989 PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
990 PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
991 PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
992 PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
993 PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
994 PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
995 PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
996 PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
997 PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
998 PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
999 PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
1000 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
1001 PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
1002 PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
1003 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
1004 PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
1005 PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
1006 PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
1007 PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
1008 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
1009 PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
1010 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
1011 PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
1012 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
1013 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
1014 PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
1015 PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
1016 PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
1017 PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
1018 PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
1019 PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
1020 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
1021 PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
1022 PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
1023 PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
1024 PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
1025 PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
1026 PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
1027 PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
1028 PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
1029 PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
1030 PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
1031 PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
1032 PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
1033 PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
1034 PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
1035 PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
1036 PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
1037 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
1038 PINMUX_DATA(SIN3_MARK, PORT247_FN1),
1039 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
1040 PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
1041 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
1042 PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
1043 PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
1044 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
1045 PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
1046 PINMUX_DATA(DINT_MARK, PORT250_FN1),
1047 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
1048 PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
1049 PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
1050 PINMUX_DATA(TCK2_MARK, PORT251_FN2),
1051 PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
1052 PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
1053 PINMUX_DATA(TMS2_MARK, PORT253_FN2),
1054 PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
1055 PINMUX_DATA(TDO2_MARK, PORT254_FN2),
1056 PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
1057 PINMUX_DATA(TDI2_MARK, PORT255_FN2),
1058 PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
1059 PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
1060
1061 /* 49-6 (FN) */
1062 PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
1063 PINMUX_DATA(TRST2_MARK, PORT257_FN2),
1064 PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
1065 PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
1066 PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
1067 PINMUX_DATA(TCK3_MARK, PORT259_FN4),
1068 PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
1069 PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
1070 PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
1071 PINMUX_DATA(TMS3_MARK, PORT260_FN4),
1072 PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
1073 PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
1074 PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
1075 PINMUX_DATA(TDO3_MARK, PORT261_FN4),
1076 PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
1077 PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
1078 PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
1079 PINMUX_DATA(TDI3_MARK, PORT262_FN4),
1080 PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
1081 PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
1082 PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
1083 PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
1084 PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
1085 PINMUX_DATA(TRST3_MARK, PORT264_FN4),
1086 PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
1087 PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
1088 PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
1089 PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
1090 PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
1091 PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
1092 PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
1093 PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
1094 PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
1095 PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
1096 PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
1097 PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
1098 PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
1099};
1100
1101#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1102#define GPIO_PORT_273() _273(_GPIO_PORT, , unused)
1103#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1104
1105static struct pinmux_gpio pinmux_gpios[] = {
1106 /* 49-1 -> 49-6 (GPIO) */
1107 GPIO_PORT_273(),
1108
1109 /* Special Pull-up / Pull-down Functions */
1110 GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
1111 GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
1112 GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
1113 GPIO_FN(PORT58_KEYIN6_PU),
1114
1115 /* 49-1 (FN) */
1116 GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
1117 GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
1118 GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
1119 GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
1120 GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
1121 GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
1122 GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
1123 GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
1124 GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
1125 GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
1126 GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
1127 GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
1128 GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
1129 GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
1130 GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
1131
1132 /* 49-2 (FN) */
1133 GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
1134 GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
1135 GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
1136 GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
1137 GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
1138 GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
1139 GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
1140 GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
1141 GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
1142 GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
1143 GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
1144 GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
1145 GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
1146 GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
1147 GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
1148 GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
1149 GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
1150 GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
1151 GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
1152 GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
1153 GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
1154 GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
1155 GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
1156 GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
1157 GPIO_FN(XTALB1L),
1158 GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
1159 GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
1160 GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
1161 GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
1162 GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
1163 GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
1164 GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
1165 GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
1166 GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
1167 GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
1168 GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
1169 GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
1170 GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
1171 GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
1172 GPIO_FN(NMI), GPIO_FN(TPU4TO0),
1173 GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
1174 GPIO_FN(IRQ_TMPB),
1175 GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
1176 GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
1177 GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
1178
1179 /* 49-3 (FN) */
1180 GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
1181 GPIO_FN(PORT93_VIO_CKO2),
1182 GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
1183 GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
1184 GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
1185 GPIO_FN(SCIFA5_RXD),
1186 GPIO_FN(SCIFA5_TXD),
1187 GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
1188 GPIO_FN(A0_EA0), GPIO_FN(BS),
1189 GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
1190 GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
1191 GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
1192 GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
1193 GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
1194 GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
1195 GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
1196 GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
1197 GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
1198 GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
1199 GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
1200 GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
1201 GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
1202 GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
1203 GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
1204 GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
1205 GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
1206 GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
1207 GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
1208 GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
1209 GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
1210 GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
1211 GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
1212 GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
1213 GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
1214 GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
1215 GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
1216 GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
1217 GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
1218 GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
1219 GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
1220 GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
1221 GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
1222 GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
1223 GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
1224
1225 /* 49-4 (FN) */
1226 GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
1227 GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
1228 GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
1229 GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
1230 GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
1231 GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
1232 GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
1233 GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
1234 GPIO_FN(VIO_CKO),
1235 GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
1236 GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
1237 GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
1238 GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
1239 GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
1240 GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
1241 GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
1242 GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
1243 GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
1244 GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
1245 GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
1246 GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
1247 GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
1248 GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
1249 GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
1250 GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
1251 GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
1252 GPIO_FN(LCDD6), GPIO_FN(DV_D6),
1253 GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
1254 GPIO_FN(LCDD7), GPIO_FN(DV_D7),
1255 GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
1256 GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
1257 GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
1258 GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
1259 GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
1260 GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
1261 GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
1262 GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
1263 GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
1264 GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
1265 GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
1266 GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
1267 GPIO_FN(D26), GPIO_FN(ED26),
1268 GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
1269 GPIO_FN(D27), GPIO_FN(ED27),
1270 GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
1271 GPIO_FN(D28), GPIO_FN(ED28),
1272 GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
1273 GPIO_FN(D29), GPIO_FN(ED29),
1274 GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
1275 GPIO_FN(D30), GPIO_FN(ED30),
1276 GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
1277 GPIO_FN(D31), GPIO_FN(ED31),
1278 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
1279 GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
1280
1281 /* 49-5 (FN) */
1282 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
1283 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
1284 GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
1285 GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
1286 GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
1287 GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
1288 GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
1289 GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
1290 GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
1291 GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
1292 GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
1293 GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
1294 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
1295 GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
1296 GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
1297 GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
1298 GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
1299 GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
1300 GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
1301 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1302 GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
1303 GPIO_FN(MSIOF1_SS2),
1304 GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
1305 GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
1306 GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
1307 GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
1308 GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
1309 GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
1310 GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
1311 GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
1312 GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
1313 GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
1314 GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
1315 GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
1316 GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
1317 GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
1318 GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
1319 GPIO_FN(SDHICD0),
1320 GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
1321 GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
1322 GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
1323 GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
1324
1325 /* 49-6 (FN) */
1326 GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
1327 GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
1328 GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
1329 GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
1330 GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
1331 GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
1332 GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
1333 GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
1334 GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
1335 GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
1336 GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
1337 GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1338 GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
1339 GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
1340 GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
1341 GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
1342 GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
1343 GPIO_FN(SDHICMD2),
1344 GPIO_FN(RESETOUTS),
1345 GPIO_FN(DIVLOCK),
1346};
1347
1348/* helper for top 4 bits in PORTnCR */
1349#define PCRH(in, in_pd, in_pu, out) \
1350 0, (out), (in), 0, \
1351 0, 0, 0, 0, \
1352 0, 0, (in_pd), 0, \
1353 0, 0, (in_pu), 0
1354
1355#define PORTCR(nr, reg) \
1356 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1357 PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1358 PORT##nr##_IN_PU, PORT##nr##_OUT), \
1359 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
1360 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
1361 PORT##nr##_FN6, PORT##nr##_FN7 } \
1362 }
1363
1364static struct pinmux_cfg_reg pinmux_config_regs[] = {
1365 PORTCR(0, 0xe6050000), /* PORT0CR */
1366 PORTCR(1, 0xe6050001), /* PORT1CR */
1367 PORTCR(2, 0xe6050002), /* PORT2CR */
1368 PORTCR(3, 0xe6050003), /* PORT3CR */
1369 PORTCR(4, 0xe6050004), /* PORT4CR */
1370 PORTCR(5, 0xe6050005), /* PORT5CR */
1371 PORTCR(6, 0xe6050006), /* PORT6CR */
1372 PORTCR(7, 0xe6050007), /* PORT7CR */
1373 PORTCR(8, 0xe6050008), /* PORT8CR */
1374 PORTCR(9, 0xe6050009), /* PORT9CR */
1375
1376 PORTCR(10, 0xe605000a), /* PORT10CR */
1377 PORTCR(11, 0xe605000b), /* PORT11CR */
1378 PORTCR(12, 0xe605000c), /* PORT12CR */
1379 PORTCR(13, 0xe605000d), /* PORT13CR */
1380 PORTCR(14, 0xe605000e), /* PORT14CR */
1381 PORTCR(15, 0xe605000f), /* PORT15CR */
1382 PORTCR(16, 0xe6050010), /* PORT16CR */
1383 PORTCR(17, 0xe6050011), /* PORT17CR */
1384 PORTCR(18, 0xe6050012), /* PORT18CR */
1385 PORTCR(19, 0xe6050013), /* PORT19CR */
1386
1387 PORTCR(20, 0xe6050014), /* PORT20CR */
1388 PORTCR(21, 0xe6050015), /* PORT21CR */
1389 PORTCR(22, 0xe6050016), /* PORT22CR */
1390 PORTCR(23, 0xe6050017), /* PORT23CR */
1391 PORTCR(24, 0xe6050018), /* PORT24CR */
1392 PORTCR(25, 0xe6050019), /* PORT25CR */
1393 PORTCR(26, 0xe605001a), /* PORT26CR */
1394 PORTCR(27, 0xe605001b), /* PORT27CR */
1395 PORTCR(28, 0xe605001c), /* PORT28CR */
1396 PORTCR(29, 0xe605001d), /* PORT29CR */
1397
1398 PORTCR(30, 0xe605001e), /* PORT30CR */
1399 PORTCR(31, 0xe605001f), /* PORT31CR */
1400 PORTCR(32, 0xe6050020), /* PORT32CR */
1401 PORTCR(33, 0xe6050021), /* PORT33CR */
1402 PORTCR(34, 0xe6050022), /* PORT34CR */
1403 PORTCR(35, 0xe6050023), /* PORT35CR */
1404 PORTCR(36, 0xe6050024), /* PORT36CR */
1405 PORTCR(37, 0xe6050025), /* PORT37CR */
1406 PORTCR(38, 0xe6050026), /* PORT38CR */
1407 PORTCR(39, 0xe6050027), /* PORT39CR */
1408
1409 PORTCR(40, 0xe6050028), /* PORT40CR */
1410 PORTCR(41, 0xe6050029), /* PORT41CR */
1411 PORTCR(42, 0xe605002a), /* PORT42CR */
1412 PORTCR(43, 0xe605002b), /* PORT43CR */
1413 PORTCR(44, 0xe605002c), /* PORT44CR */
1414 PORTCR(45, 0xe605002d), /* PORT45CR */
1415 PORTCR(46, 0xe605002e), /* PORT46CR */
1416 PORTCR(47, 0xe605002f), /* PORT47CR */
1417 PORTCR(48, 0xe6050030), /* PORT48CR */
1418 PORTCR(49, 0xe6050031), /* PORT49CR */
1419
1420 PORTCR(50, 0xe6050032), /* PORT50CR */
1421 PORTCR(51, 0xe6050033), /* PORT51CR */
1422 PORTCR(52, 0xe6050034), /* PORT52CR */
1423 PORTCR(53, 0xe6050035), /* PORT53CR */
1424 PORTCR(54, 0xe6050036), /* PORT54CR */
1425 PORTCR(55, 0xe6050037), /* PORT55CR */
1426 PORTCR(56, 0xe6050038), /* PORT56CR */
1427 PORTCR(57, 0xe6050039), /* PORT57CR */
1428 PORTCR(58, 0xe605003a), /* PORT58CR */
1429 PORTCR(59, 0xe605003b), /* PORT59CR */
1430
1431 PORTCR(60, 0xe605003c), /* PORT60CR */
1432 PORTCR(61, 0xe605003d), /* PORT61CR */
1433 PORTCR(62, 0xe605003e), /* PORT62CR */
1434 PORTCR(63, 0xe605003f), /* PORT63CR */
1435 PORTCR(64, 0xe6050040), /* PORT64CR */
1436 PORTCR(65, 0xe6050041), /* PORT65CR */
1437 PORTCR(66, 0xe6050042), /* PORT66CR */
1438 PORTCR(67, 0xe6050043), /* PORT67CR */
1439 PORTCR(68, 0xe6050044), /* PORT68CR */
1440 PORTCR(69, 0xe6050045), /* PORT69CR */
1441
1442 PORTCR(70, 0xe6050046), /* PORT70CR */
1443 PORTCR(71, 0xe6050047), /* PORT71CR */
1444 PORTCR(72, 0xe6050048), /* PORT72CR */
1445 PORTCR(73, 0xe6050049), /* PORT73CR */
1446 PORTCR(74, 0xe605004a), /* PORT74CR */
1447 PORTCR(75, 0xe605004b), /* PORT75CR */
1448 PORTCR(76, 0xe605004c), /* PORT76CR */
1449 PORTCR(77, 0xe605004d), /* PORT77CR */
1450 PORTCR(78, 0xe605004e), /* PORT78CR */
1451 PORTCR(79, 0xe605004f), /* PORT79CR */
1452
1453 PORTCR(80, 0xe6050050), /* PORT80CR */
1454 PORTCR(81, 0xe6050051), /* PORT81CR */
1455 PORTCR(82, 0xe6050052), /* PORT82CR */
1456 PORTCR(83, 0xe6050053), /* PORT83CR */
1457 PORTCR(84, 0xe6050054), /* PORT84CR */
1458 PORTCR(85, 0xe6050055), /* PORT85CR */
1459 PORTCR(86, 0xe6050056), /* PORT86CR */
1460 PORTCR(87, 0xe6050057), /* PORT87CR */
1461 PORTCR(88, 0xe6051058), /* PORT88CR */
1462 PORTCR(89, 0xe6051059), /* PORT89CR */
1463
1464 PORTCR(90, 0xe605105a), /* PORT90CR */
1465 PORTCR(91, 0xe605105b), /* PORT91CR */
1466 PORTCR(92, 0xe605105c), /* PORT92CR */
1467 PORTCR(93, 0xe605105d), /* PORT93CR */
1468 PORTCR(94, 0xe605105e), /* PORT94CR */
1469 PORTCR(95, 0xe605105f), /* PORT95CR */
1470 PORTCR(96, 0xe6051060), /* PORT96CR */
1471 PORTCR(97, 0xe6051061), /* PORT97CR */
1472 PORTCR(98, 0xe6051062), /* PORT98CR */
1473 PORTCR(99, 0xe6051063), /* PORT99CR */
1474
1475 PORTCR(100, 0xe6051064), /* PORT100CR */
1476 PORTCR(101, 0xe6051065), /* PORT101CR */
1477 PORTCR(102, 0xe6051066), /* PORT102CR */
1478 PORTCR(103, 0xe6051067), /* PORT103CR */
1479 PORTCR(104, 0xe6051068), /* PORT104CR */
1480 PORTCR(105, 0xe6051069), /* PORT105CR */
1481 PORTCR(106, 0xe605106a), /* PORT106CR */
1482 PORTCR(107, 0xe605106b), /* PORT107CR */
1483 PORTCR(108, 0xe605106c), /* PORT108CR */
1484 PORTCR(109, 0xe605106d), /* PORT109CR */
1485
1486 PORTCR(110, 0xe605106e), /* PORT110CR */
1487 PORTCR(111, 0xe605106f), /* PORT111CR */
1488 PORTCR(112, 0xe6051070), /* PORT112CR */
1489 PORTCR(113, 0xe6051071), /* PORT113CR */
1490 PORTCR(114, 0xe6051072), /* PORT114CR */
1491 PORTCR(115, 0xe6051073), /* PORT115CR */
1492 PORTCR(116, 0xe6051074), /* PORT116CR */
1493 PORTCR(117, 0xe6051075), /* PORT117CR */
1494 PORTCR(118, 0xe6051076), /* PORT118CR */
1495 PORTCR(119, 0xe6051077), /* PORT119CR */
1496
1497 PORTCR(120, 0xe6051078), /* PORT120CR */
1498 PORTCR(121, 0xe6051079), /* PORT121CR */
1499 PORTCR(122, 0xe605107a), /* PORT122CR */
1500 PORTCR(123, 0xe605107b), /* PORT123CR */
1501 PORTCR(124, 0xe605107c), /* PORT124CR */
1502 PORTCR(125, 0xe605107d), /* PORT125CR */
1503 PORTCR(126, 0xe605107e), /* PORT126CR */
1504 PORTCR(127, 0xe605107f), /* PORT127CR */
1505 PORTCR(128, 0xe6051080), /* PORT128CR */
1506 PORTCR(129, 0xe6051081), /* PORT129CR */
1507
1508 PORTCR(130, 0xe6051082), /* PORT130CR */
1509 PORTCR(131, 0xe6051083), /* PORT131CR */
1510 PORTCR(132, 0xe6051084), /* PORT132CR */
1511 PORTCR(133, 0xe6051085), /* PORT133CR */
1512 PORTCR(134, 0xe6051086), /* PORT134CR */
1513 PORTCR(135, 0xe6051087), /* PORT135CR */
1514 PORTCR(136, 0xe6051088), /* PORT136CR */
1515 PORTCR(137, 0xe6051089), /* PORT137CR */
1516 PORTCR(138, 0xe605108a), /* PORT138CR */
1517 PORTCR(139, 0xe605108b), /* PORT139CR */
1518
1519 PORTCR(140, 0xe605108c), /* PORT140CR */
1520 PORTCR(141, 0xe605108d), /* PORT141CR */
1521 PORTCR(142, 0xe605108e), /* PORT142CR */
1522 PORTCR(143, 0xe605108f), /* PORT143CR */
1523 PORTCR(144, 0xe6051090), /* PORT144CR */
1524 PORTCR(145, 0xe6051091), /* PORT145CR */
1525 PORTCR(146, 0xe6051092), /* PORT146CR */
1526 PORTCR(147, 0xe6051093), /* PORT147CR */
1527 PORTCR(148, 0xe6051094), /* PORT148CR */
1528 PORTCR(149, 0xe6051095), /* PORT149CR */
1529
1530 PORTCR(150, 0xe6051096), /* PORT150CR */
1531 PORTCR(151, 0xe6051097), /* PORT151CR */
1532 PORTCR(152, 0xe6051098), /* PORT152CR */
1533 PORTCR(153, 0xe6051099), /* PORT153CR */
1534 PORTCR(154, 0xe605109a), /* PORT154CR */
1535 PORTCR(155, 0xe605109b), /* PORT155CR */
1536 PORTCR(156, 0xe605109c), /* PORT156CR */
1537 PORTCR(157, 0xe605109d), /* PORT157CR */
1538 PORTCR(158, 0xe605109e), /* PORT158CR */
1539 PORTCR(159, 0xe605109f), /* PORT159CR */
1540
1541 PORTCR(160, 0xe60510a0), /* PORT160CR */
1542 PORTCR(161, 0xe60510a1), /* PORT161CR */
1543 PORTCR(162, 0xe60510a2), /* PORT162CR */
1544 PORTCR(163, 0xe60510a3), /* PORT163CR */
1545 PORTCR(164, 0xe60510a4), /* PORT164CR */
1546 PORTCR(165, 0xe60510a5), /* PORT165CR */
1547 PORTCR(166, 0xe60510a6), /* PORT166CR */
1548 PORTCR(167, 0xe60510a7), /* PORT167CR */
1549 PORTCR(168, 0xe60510a8), /* PORT168CR */
1550 PORTCR(169, 0xe60510a9), /* PORT169CR */
1551
1552 PORTCR(170, 0xe60510aa), /* PORT170CR */
1553 PORTCR(171, 0xe60510ab), /* PORT171CR */
1554 PORTCR(172, 0xe60510ac), /* PORT172CR */
1555 PORTCR(173, 0xe60510ad), /* PORT173CR */
1556 PORTCR(174, 0xe60510ae), /* PORT174CR */
1557 PORTCR(175, 0xe60520af), /* PORT175CR */
1558 PORTCR(176, 0xe60520b0), /* PORT176CR */
1559 PORTCR(177, 0xe60520b1), /* PORT177CR */
1560 PORTCR(178, 0xe60520b2), /* PORT178CR */
1561 PORTCR(179, 0xe60520b3), /* PORT179CR */
1562
1563 PORTCR(180, 0xe60520b4), /* PORT180CR */
1564 PORTCR(181, 0xe60520b5), /* PORT181CR */
1565 PORTCR(182, 0xe60520b6), /* PORT182CR */
1566 PORTCR(183, 0xe60520b7), /* PORT183CR */
1567 PORTCR(184, 0xe60520b8), /* PORT184CR */
1568 PORTCR(185, 0xe60520b9), /* PORT185CR */
1569 PORTCR(186, 0xe60520ba), /* PORT186CR */
1570 PORTCR(187, 0xe60520bb), /* PORT187CR */
1571 PORTCR(188, 0xe60520bc), /* PORT188CR */
1572 PORTCR(189, 0xe60520bd), /* PORT189CR */
1573
1574 PORTCR(190, 0xe60520be), /* PORT190CR */
1575 PORTCR(191, 0xe60520bf), /* PORT191CR */
1576 PORTCR(192, 0xe60520c0), /* PORT192CR */
1577 PORTCR(193, 0xe60520c1), /* PORT193CR */
1578 PORTCR(194, 0xe60520c2), /* PORT194CR */
1579 PORTCR(195, 0xe60520c3), /* PORT195CR */
1580 PORTCR(196, 0xe60520c4), /* PORT196CR */
1581 PORTCR(197, 0xe60520c5), /* PORT197CR */
1582 PORTCR(198, 0xe60520c6), /* PORT198CR */
1583 PORTCR(199, 0xe60520c7), /* PORT199CR */
1584
1585 PORTCR(200, 0xe60520c8), /* PORT200CR */
1586 PORTCR(201, 0xe60520c9), /* PORT201CR */
1587 PORTCR(202, 0xe60520ca), /* PORT202CR */
1588 PORTCR(203, 0xe60520cb), /* PORT203CR */
1589 PORTCR(204, 0xe60520cc), /* PORT204CR */
1590 PORTCR(205, 0xe60520cd), /* PORT205CR */
1591 PORTCR(206, 0xe60520ce), /* PORT206CR */
1592 PORTCR(207, 0xe60520cf), /* PORT207CR */
1593 PORTCR(208, 0xe60520d0), /* PORT208CR */
1594 PORTCR(209, 0xe60520d1), /* PORT209CR */
1595
1596 PORTCR(210, 0xe60520d2), /* PORT210CR */
1597 PORTCR(211, 0xe60520d3), /* PORT211CR */
1598 PORTCR(212, 0xe60520d4), /* PORT212CR */
1599 PORTCR(213, 0xe60520d5), /* PORT213CR */
1600 PORTCR(214, 0xe60520d6), /* PORT214CR */
1601 PORTCR(215, 0xe60520d7), /* PORT215CR */
1602 PORTCR(216, 0xe60520d8), /* PORT216CR */
1603 PORTCR(217, 0xe60520d9), /* PORT217CR */
1604 PORTCR(218, 0xe60520da), /* PORT218CR */
1605 PORTCR(219, 0xe60520db), /* PORT219CR */
1606
1607 PORTCR(220, 0xe60520dc), /* PORT220CR */
1608 PORTCR(221, 0xe60520dd), /* PORT221CR */
1609 PORTCR(222, 0xe60520de), /* PORT222CR */
1610 PORTCR(223, 0xe60520df), /* PORT223CR */
1611 PORTCR(224, 0xe60520e0), /* PORT224CR */
1612 PORTCR(225, 0xe60520e1), /* PORT225CR */
1613 PORTCR(226, 0xe60520e2), /* PORT226CR */
1614 PORTCR(227, 0xe60520e3), /* PORT227CR */
1615 PORTCR(228, 0xe60520e4), /* PORT228CR */
1616 PORTCR(229, 0xe60520e5), /* PORT229CR */
1617
1618 PORTCR(230, 0xe60520e6), /* PORT230CR */
1619 PORTCR(231, 0xe60520e7), /* PORT231CR */
1620 PORTCR(232, 0xe60520e8), /* PORT232CR */
1621 PORTCR(233, 0xe60520e9), /* PORT233CR */
1622 PORTCR(234, 0xe60520ea), /* PORT234CR */
1623 PORTCR(235, 0xe60520eb), /* PORT235CR */
1624 PORTCR(236, 0xe60530ec), /* PORT236CR */
1625 PORTCR(237, 0xe60530ed), /* PORT237CR */
1626 PORTCR(238, 0xe60530ee), /* PORT238CR */
1627 PORTCR(239, 0xe60530ef), /* PORT239CR */
1628
1629 PORTCR(240, 0xe60530f0), /* PORT240CR */
1630 PORTCR(241, 0xe60530f1), /* PORT241CR */
1631 PORTCR(242, 0xe60530f2), /* PORT242CR */
1632 PORTCR(243, 0xe60530f3), /* PORT243CR */
1633 PORTCR(244, 0xe60530f4), /* PORT244CR */
1634 PORTCR(245, 0xe60530f5), /* PORT245CR */
1635 PORTCR(246, 0xe60530f6), /* PORT246CR */
1636 PORTCR(247, 0xe60530f7), /* PORT247CR */
1637 PORTCR(248, 0xe60530f8), /* PORT248CR */
1638 PORTCR(249, 0xe60530f9), /* PORT249CR */
1639
1640 PORTCR(250, 0xe60530fa), /* PORT250CR */
1641 PORTCR(251, 0xe60530fb), /* PORT251CR */
1642 PORTCR(252, 0xe60530fc), /* PORT252CR */
1643 PORTCR(253, 0xe60530fd), /* PORT253CR */
1644 PORTCR(254, 0xe60530fe), /* PORT254CR */
1645 PORTCR(255, 0xe60530ff), /* PORT255CR */
1646 PORTCR(256, 0xe6053100), /* PORT256CR */
1647 PORTCR(257, 0xe6053101), /* PORT257CR */
1648 PORTCR(258, 0xe6053102), /* PORT258CR */
1649 PORTCR(259, 0xe6053103), /* PORT259CR */
1650
1651 PORTCR(260, 0xe6053104), /* PORT260CR */
1652 PORTCR(261, 0xe6053105), /* PORT261CR */
1653 PORTCR(262, 0xe6053106), /* PORT262CR */
1654 PORTCR(263, 0xe6053107), /* PORT263CR */
1655 PORTCR(264, 0xe6053108), /* PORT264CR */
1656 PORTCR(265, 0xe6053109), /* PORT265CR */
1657 PORTCR(266, 0xe605310a), /* PORT266CR */
1658 PORTCR(267, 0xe605310b), /* PORT267CR */
1659 PORTCR(268, 0xe605310c), /* PORT268CR */
1660 PORTCR(269, 0xe605310d), /* PORT269CR */
1661
1662 PORTCR(270, 0xe605310e), /* PORT270CR */
1663 PORTCR(271, 0xe605310f), /* PORT271CR */
1664 PORTCR(272, 0xe6053110), /* PORT272CR */
1665
1666 { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
1667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1670 0, 0,
1671 0, 0,
1672 0, 0,
1673 0, 0,
1674 0, 0,
1675 MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
1676 0, 0,
1677 0, 0 }
1678 },
1679 { },
1680};
1681
1682static struct pinmux_data_reg pinmux_data_regs[] = {
1683 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
1684 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
1685 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
1686 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
1687 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
1688 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
1689 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
1690 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
1691 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
1692 },
1693 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
1694 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
1695 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
1696 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
1697 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
1698 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
1699 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
1700 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
1701 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
1702 },
1703 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
1704 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1705 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
1706 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
1707 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
1708 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
1709 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
1710 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
1711 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
1712 },
1713 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
1714 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
1715 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
1716 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
1717 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
1718 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
1719 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
1720 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
1721 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
1722 },
1723 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
1724 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
1725 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
1726 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
1727 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
1728 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
1729 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
1730 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
1731 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
1732 },
1733 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
1734 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
1735 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
1736 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
1737 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
1738 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
1739 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
1740 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
1741 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
1742 },
1743 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
1744 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
1745 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
1746 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
1747 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
1748 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
1749 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
1750 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
1751 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
1752 },
1753 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
1754 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
1755 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
1756 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
1757 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
1758 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
1759 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
1760 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
1761 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
1762 },
1763 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
1764 0, 0, 0, 0,
1765 0, 0, 0, 0,
1766 0, 0, 0, 0,
1767 0, 0, 0, PORT272_DATA,
1768 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
1769 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
1770 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
1771 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
1772 },
1773 { },
1774};
1775
1776static struct pinmux_info sh7367_pinmux_info = {
1777 .name = "sh7367_pfc",
1778 .reserved_id = PINMUX_RESERVED,
1779 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1780 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1781 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1782 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1783 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1784 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1785 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1786
1787 .first_gpio = GPIO_PORT0,
1788 .last_gpio = GPIO_FN_DIVLOCK,
1789
1790 .gpios = pinmux_gpios,
1791 .cfg_regs = pinmux_config_regs,
1792 .data_regs = pinmux_data_regs,
1793
1794 .gpio_data = pinmux_data,
1795 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1796};
1797
1798void sh7367_pinmux_init(void)
1799{
1800 register_pinmux(&sh7367_pinmux_info);
1801}
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
new file mode 100644
index 00000000000..613e6842ad0
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -0,0 +1,1767 @@
1/*
2 * sh7377 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 NISHIMOTO Hiroki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/gpio.h>
23#include <mach/sh7377.h>
24
25#define _1(fn, pfx, sfx) fn(pfx, sfx)
26
27#define _10(fn, pfx, sfx) \
28 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
29 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
30 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
31 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
32 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
33
34#define _90(fn, pfx, sfx) \
35 _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
36 _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
37 _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
38 _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
39 _10(fn, pfx##9, sfx)
40
41#define _265(fn, pfx, sfx) \
42 _10(fn, pfx, sfx), _90(fn, pfx, sfx), \
43 _10(fn, pfx##10, sfx), \
44 _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
45 _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
46 _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
47 _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
48 _1(fn, pfx##118, sfx), \
49 _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
50 _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
51 _10(fn, pfx##15, sfx), \
52 _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
53 _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
54 _1(fn, pfx##164, sfx), \
55 _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
56 _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
57 _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
58 _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
59 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
60 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
61 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
62 _1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \
63 _1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \
64 _1(fn, pfx##264, sfx)
65
66#define _PORT(pfx, sfx) pfx##_##sfx
67#define PORT_265(str) _265(_PORT, PORT, str)
68
69enum {
70 PINMUX_RESERVED = 0,
71
72 PINMUX_DATA_BEGIN,
73 PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */
74 PINMUX_DATA_END,
75
76 PINMUX_INPUT_BEGIN,
77 PORT_265(IN), /* PORT0_IN -> PORT264_IN */
78 PINMUX_INPUT_END,
79
80 PINMUX_INPUT_PULLUP_BEGIN,
81 PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
82 PINMUX_INPUT_PULLUP_END,
83
84 PINMUX_INPUT_PULLDOWN_BEGIN,
85 PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
86 PINMUX_INPUT_PULLDOWN_END,
87
88 PINMUX_OUTPUT_BEGIN,
89 PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */
90 PINMUX_OUTPUT_END,
91
92 PINMUX_FUNCTION_BEGIN,
93 PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
94 PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
95 PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */
96 PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */
97 PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */
98 PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */
99 PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */
100 PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */
101 PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */
102 PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */
103
104 MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
105 MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
106 PINMUX_FUNCTION_END,
107
108 PINMUX_MARK_BEGIN,
109 /* Special Pull-up / Pull-down Functions */
110 PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
111 PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
112 PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
113 PORT72_KEYIN6_PU_MARK,
114
115 /* 55-1 */
116 VBUS_0_MARK,
117 CPORT0_MARK,
118 CPORT1_MARK,
119 CPORT2_MARK,
120 CPORT3_MARK,
121 CPORT4_MARK,
122 CPORT5_MARK,
123 CPORT6_MARK,
124 CPORT7_MARK,
125 CPORT8_MARK,
126 CPORT9_MARK,
127 CPORT10_MARK,
128 CPORT11_MARK, SIN2_MARK,
129 CPORT12_MARK, XCTS2_MARK,
130 CPORT13_MARK, RFSPO4_MARK,
131 CPORT14_MARK, RFSPO5_MARK,
132 CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
133 CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
134 CPORT17_IC_OE_MARK, SOUT2_MARK,
135 CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
136 CPORT19_MPORT1_MARK,
137 CPORT20_MARK, RFSPO6_MARK,
138 CPORT21_MARK, STATUS0_MARK,
139 CPORT22_MARK, STATUS1_MARK,
140 CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
141 B_SYNLD1_MARK,
142 B_SYNLD2_MARK, SYSENMSK_MARK,
143 XMAINPS_MARK,
144 XDIVPS_MARK,
145 XIDRST_MARK,
146 IDCLK_MARK, IC_DP_MARK,
147 IDIO_MARK, IC_DM_MARK,
148 SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
149 SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
150 XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
151 XCTS1_MARK, SCIFA4_CTS_MARK,
152 PCMCLKO_MARK,
153 SYNC8KO_MARK,
154
155 /* 55-2 */
156 DNPCM_A_MARK,
157 UPPCM_A_MARK,
158 VACK_MARK,
159 XTALB1L_MARK,
160 GPS_AGC1_MARK, SCIFA0_RTS_MARK,
161 GPS_AGC4_MARK, SCIFA0_RXD_MARK,
162 GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
163 GPS_IM_MARK,
164 GPS_IS_MARK,
165 GPS_QM_MARK,
166 GPS_QS_MARK,
167 FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
168 FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
169 FMSIOLR_MARK,
170 FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
171 FMSIOBT_MARK,
172 FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
173 FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
174 FMSIILR_MARK,
175 FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
176 FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
177 A0_EA0_MARK, BS_MARK,
178 A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
179 A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
180 A14_EA14_MARK, PORT60_KEYOUT5_MARK,
181 A15_EA15_MARK, PORT61_KEYOUT4_MARK,
182 A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
183 A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
184 A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
185 A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
186 A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
187 A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
188 A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
189 A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
190 A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
191 A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
192 A26_MARK, PORT72_KEYIN6_MARK,
193 D0_ED0_NAF0_MARK,
194 D1_ED1_NAF1_MARK,
195 D2_ED2_NAF2_MARK,
196 D3_ED3_NAF3_MARK,
197 D4_ED4_NAF4_MARK,
198 D5_ED5_NAF5_MARK,
199 D6_ED6_NAF6_MARK,
200 D7_ED7_NAF7_MARK,
201 D8_ED8_NAF8_MARK,
202 D9_ED9_NAF9_MARK,
203 D10_ED10_NAF10_MARK,
204 D11_ED11_NAF11_MARK,
205 D12_ED12_NAF12_MARK,
206 D13_ED13_NAF13_MARK,
207 D14_ED14_NAF14_MARK,
208 D15_ED15_NAF15_MARK,
209 CS4_MARK,
210 CS5A_MARK, FMSICK_MARK,
211 CS5B_MARK, FCE1_MARK,
212
213 /* 55-3 */
214 CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
215 FCE0_MARK,
216 WAIT_MARK, DREQ0_MARK,
217 RD_XRD_MARK,
218 WE0_XWR0_FWE_MARK,
219 WE1_XWR1_MARK,
220 FRB_MARK,
221 CKO_MARK,
222 NBRSTOUT_MARK,
223 NBRST_MARK,
224 GPS_EPPSIN_MARK,
225 LATCHPULSE_MARK,
226 LTESIGNAL_MARK,
227 LEGACYSTATE_MARK,
228 TCKON_MARK,
229 VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
230 VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
231 VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
232 VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
233 VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
234 VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
235 VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
236 VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
237 VIO_D6_MARK, PORT136_KEYIN2_MARK,
238 VIO_D7_MARK, PORT137_KEYIN3_MARK,
239 VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
240 VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
241 VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
242 VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
243 VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
244 VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
245 VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
246 VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
247 VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
248 VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
249 VIO_CKO_MARK, PORT148_KEYIN6_MARK,
250 A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
251 MFG0_IN2_MARK,
252 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
253 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
254 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
255 SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
256 SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
257 XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
258 XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
259
260 /* 55-4 */
261 DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
262 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
263 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
264 PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
265 MFG3_IN2_MARK,
266 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
267 MFG3_IN1_MARK,
268 PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
269 MFG3_OUT1_MARK, TPU3TO0_MARK,
270 LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
271 LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
272 BBIF2_TSYNC1_MARK,
273 LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
274 BBIF2_TSCK1_MARK,
275 LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
276 BBIF2_TXD1_MARK,
277 LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
278 LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
279 MFG2_OUT2_MARK,
280 TPU2TO1_MARK,
281 LCDD6_MARK, XWR2_MARK,
282 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
283 LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
284 LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
285 LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
286 LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
287 LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
288 LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
289 LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
290 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
291 VIO_DR7_MARK, D23_MARK, ED23_MARK,
292 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
293 VIO_VDR_MARK, D24_MARK, ED24_MARK,
294 LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
295 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
296 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
297 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
298 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
299 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
300 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
301 LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
302 LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
303 LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
304 PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
305 LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
306 LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
307 LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
308 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
309 SCIFA1_TXD_MARK, OVCN2_MARK,
310 EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
311 SCIFA1_RTS_MARK, IDIN_MARK,
312 SCIFA1_RXD_MARK,
313 SCIFA1_CTS_MARK, MFG1_IN1_MARK,
314 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
315 MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
316 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
317 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
318 PORT233_FSIACK_MARK,
319 MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
320 MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
321 MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
322 MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
323 MSIOF1_SS1_MARK, EDBGREQ3_MARK,
324
325 /* 55-5 */
326 MSIOF1_SS2_MARK,
327 SCIFA6_TXD_MARK,
328 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
329 TPU4TO0_MARK,
330 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
331 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
332 PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
333 PORT244_MSIOF2_RXD_MARK,
334 PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
335 PORT245_MSIOF2_TXD_MARK,
336 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
337 TPU1TO0_MARK,
338 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
339 TPU3TO1_MARK,
340 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
341 TPU2TO0_MARK,
342 PORT248_MSIOF2_TSCK_MARK,
343 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
344 SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
345 SDHICD0_MARK,
346 SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
347 SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
348 SDHID0_2_MARK, TDI2_MARK,
349 SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
350 SDHICMD0_MARK, TRST2_MARK,
351 SDHIWP0_MARK, EDBGREQ2_MARK,
352 SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
353 SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
354 TMS3_SWDIO_MC1_MARK,
355 SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
356 SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
357 SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
358 SDHICMD1_MARK, TRST3_MARK,
359 RESETOUTS_MARK,
360 PINMUX_MARK_END,
361};
362
363#define PORT_DATA_I(nr) \
364 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
365
366#define PORT_DATA_I_PD(nr) \
367 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
368 PORT##nr##_IN, PORT##nr##_IN_PD)
369
370#define PORT_DATA_I_PU(nr) \
371 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
372 PORT##nr##_IN, PORT##nr##_IN_PU)
373
374#define PORT_DATA_I_PU_PD(nr) \
375 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
376 PORT##nr##_IN, PORT##nr##_IN_PD, \
377 PORT##nr##_IN_PU)
378
379#define PORT_DATA_O(nr) \
380 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
381 PORT##nr##_OUT)
382
383#define PORT_DATA_IO(nr) \
384 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
385 PORT##nr##_OUT, PORT##nr##_IN)
386
387#define PORT_DATA_IO_PD(nr) \
388 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
389 PORT##nr##_OUT, PORT##nr##_IN, \
390 PORT##nr##_IN_PD)
391
392#define PORT_DATA_IO_PU(nr) \
393 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
394 PORT##nr##_OUT, PORT##nr##_IN, \
395 PORT##nr##_IN_PU)
396
397#define PORT_DATA_IO_PU_PD(nr) \
398 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
399 PORT##nr##_OUT, PORT##nr##_IN, \
400 PORT##nr##_IN_PD, PORT##nr##_IN_PU)
401
402static pinmux_enum_t pinmux_data[] = {
403 /* specify valid pin states for each pin in GPIO mode */
404 /* 55-1 (GPIO) */
405 PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
406 PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
407 PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
408 PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
409 PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
410 PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
411 PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
412 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
413 PORT_DATA_O(16), PORT_DATA_IO(17),
414 PORT_DATA_O(18), PORT_DATA_O(19),
415 PORT_DATA_O(20), PORT_DATA_O(21),
416 PORT_DATA_O(22), PORT_DATA_O(23),
417 PORT_DATA_O(24), PORT_DATA_I_PD(25),
418 PORT_DATA_I_PD(26), PORT_DATA_O(27),
419 PORT_DATA_O(28), PORT_DATA_O(29),
420 PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
421 PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
422 PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
423 PORT_DATA_O(36), PORT_DATA_IO(37),
424
425 /* 55-2 (GPIO) */
426 PORT_DATA_O(38), PORT_DATA_I_PU(39),
427 PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
428 PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
429 PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
430 PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
431 PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
432 PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
433 PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
434 PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
435 PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
436 PORT_DATA_IO(58), PORT_DATA_IO(59),
437 PORT_DATA_IO(60), PORT_DATA_IO(61),
438 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
439 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
440 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
441 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
442 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
443 PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
444 PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
445 PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
446 PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
447 PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
448 PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
449 PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
450 PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
451 PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
452 PORT_DATA_O(90), PORT_DATA_IO_PU(91),
453 PORT_DATA_O(92),
454
455 /* 55-3 (GPIO) */
456 PORT_DATA_IO_PU(93),
457 PORT_DATA_O(94),
458 PORT_DATA_I_PU_PD(95),
459 PORT_DATA_IO(96), PORT_DATA_IO(97),
460 PORT_DATA_IO(98), PORT_DATA_I_PU(99),
461 PORT_DATA_O(100), PORT_DATA_O(101),
462 PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
463 PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
464 PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
465 PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
466 PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
467 PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
468 PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
469 PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
470 PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
471 PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
472 PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
473 PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
474 PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
475 PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
476 PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
477 PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
478 PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
479 PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
480 PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
481 PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
482 PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
483 PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
484 PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
485 PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
486
487 /* 55-4 (GPIO) */
488 PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
489 PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
490 PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
491 PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
492 PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
493 PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
494 PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
495 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
496 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
497 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
498 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
499 PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
500 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
501 PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
502 PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
503 PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
504 PORT_DATA_O(218), PORT_DATA_IO_PD(219),
505 PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
506 PORT_DATA_IO_PU_PD(222),
507 PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
508 PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
509 PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
510 PORT_DATA_I_PD(229), PORT_DATA_IO(230),
511 PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
512 PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
513 PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
514 PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
515
516 /* 55-5 (GPIO) */
517 PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
518 PORT_DATA_O(241), PORT_DATA_I_PD(242),
519 PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
520 PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
521 PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
522 PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
523 PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
524 PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
525 PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
526 PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
527 PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
528 PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
529 PORT_DATA_IO_PU_PD(263),
530
531 /* Special Pull-up / Pull-down Functions */
532 PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
533 PORT66_FN2, PORT66_IN_PU),
534 PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
535 PORT67_FN2, PORT67_IN_PU),
536 PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
537 PORT68_FN2, PORT68_IN_PU),
538 PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
539 PORT69_FN2, PORT69_IN_PU),
540 PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
541 PORT70_FN2, PORT70_IN_PU),
542 PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
543 PORT71_FN2, PORT71_IN_PU),
544 PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
545 PORT72_FN2, PORT72_IN_PU),
546
547
548 /* 55-1 (FN) */
549 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
550 PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
551 PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
552 PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
553 PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
554 PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
555 PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
556 PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
557 PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
558 PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
559 PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
560 PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
561 PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
562 PINMUX_DATA(SIN2_MARK, PORT12_FN2),
563 PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
564 PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
565 PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
566 PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
567 PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
568 PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
569 PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
570 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
571 PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
572 PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
573 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
574 PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
575 PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
576 PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
577 PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
578 PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
579 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
580 PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
581 PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
582 PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
583 PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
584 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
585 PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
586 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
587 PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
588 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
589 PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
590 PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
591 PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
592 PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
593 PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
594 PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
595 PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
596 PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
597 PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
598 PINMUX_DATA(IDIO_MARK, PORT31_FN1),
599 PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
600 PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
601 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
602 PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
603 PINMUX_DATA(SIN1_MARK, PORT33_FN1),
604 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
605 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
606 PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
607 PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
608 PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
609 PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
610 PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
611 PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
612 PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
613
614 /* 55-2 (FN) */
615 PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
616 PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
617 PINMUX_DATA(VACK_MARK, PORT40_FN1),
618 PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
619 PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
620 PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
621 PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
622 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
623 PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
624 PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
625 PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
626 PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
627 PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
628 PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
629 PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
630 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
631 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
632 PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
633 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
634 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
635 PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
636 PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
637 PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
638 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
639 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
640 PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
641 PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
642 PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
643 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
644 PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
645 PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
646 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
647 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
648 PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
649 PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
650 PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
651 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
652 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
653 PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
654 PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
655 PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
656 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
657 PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
658 PINMUX_DATA(BS_MARK, PORT57_FN2),
659 PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
660 PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
661 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
662 PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
663 PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
664 PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
665 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
666 PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
667 PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
668 PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
669 PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
670 PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
671 PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
672 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
673 PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
674 PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
675 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
676 PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
677 PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
678 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
679 PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
680 PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
681 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
682 PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
683 PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
684 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
685 PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
686 PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
687 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
688 PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
689 PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
690 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
691 PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
692 PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
693 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
694 PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
695 PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
696 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
697 PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
698 PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
699 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
700 PINMUX_DATA(A26_MARK, PORT72_FN1),
701 PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
702 PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
703 PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
704 PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
705 PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
706 PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
707 PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
708 PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
709 PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
710 PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
711 PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
712 PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
713 PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
714 PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
715 PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
716 PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
717 PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
718 PINMUX_DATA(CS4_MARK, PORT90_FN1),
719 PINMUX_DATA(CS5A_MARK, PORT91_FN1),
720 PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
721 PINMUX_DATA(CS5B_MARK, PORT92_FN1),
722 PINMUX_DATA(FCE1_MARK, PORT92_FN2),
723
724 /* 55-3 (FN) */
725 PINMUX_DATA(CS6B_MARK, PORT93_FN1),
726 PINMUX_DATA(XCS2_MARK, PORT93_FN2),
727 PINMUX_DATA(CS6A_MARK, PORT93_FN3),
728 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
729 PINMUX_DATA(FCE0_MARK, PORT94_FN1),
730 PINMUX_DATA(WAIT_MARK, PORT95_FN1),
731 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
732 PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
733 PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
734 PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
735 PINMUX_DATA(FRB_MARK, PORT99_FN1),
736 PINMUX_DATA(CKO_MARK, PORT100_FN1),
737 PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
738 PINMUX_DATA(NBRST_MARK, PORT102_FN1),
739 PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
740 PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
741 PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
742 PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
743 PINMUX_DATA(TCKON_MARK, PORT118_FN1),
744 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
745 PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
746 PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
747 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
748 PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
749 PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
750 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
751 PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
752 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
753 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
754 PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
755 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
756 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
757 PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
758 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
759 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
760 PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
761 PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
762 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
763 PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
764 PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
765 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
766 PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
767 PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
768 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
769 PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
770 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
771 PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
772 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
773 PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
774 PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
775 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
776 PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
777 PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
778 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
779 PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
780 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
781 PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
782 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
783 PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
784 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
785 PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
786 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
787 PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
788 PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
789 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
790 PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
791 PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
792 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
793 PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
794 PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
795 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
796 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
797 PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
798 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
799 PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
800 PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
801 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
802 PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
803 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
804 PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
805 PINMUX_DATA(A27_MARK, PORT149_FN1),
806 PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
807 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
808 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
809 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
810 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
811 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
812 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
813 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
814 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
815 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
816 PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
817 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
818 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
819 PINMUX_DATA(SIN3_MARK, PORT155_FN1),
820 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
821 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
822 PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
823 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
824 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
825 PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
826 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
827 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
828
829 /* 55-4 (FN) */
830 PINMUX_DATA(DINT_MARK, PORT158_FN1),
831 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
832 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
833 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
834 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
835 PINMUX_DATA(NMI_MARK, PORT159_FN3),
836 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
837 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
838 PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
839 PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
840 PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
841 PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
842 PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
843 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
844 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
845 PINMUX_DATA(SIN0_MARK, PORT162_FN3),
846 PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
847 PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
848 PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
849 PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
850 PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
851 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
852 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
853 PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
854 PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
855 PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
856 PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
857 PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
858 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
859 PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
860 PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
861 PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
862 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
863 PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
864 PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
865 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
866 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
867 PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
868 PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
869 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
870 PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
871 PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
872 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
873 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
874 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
875 PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
876 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
877 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
878 PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
879 PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
880 PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
881 PINMUX_DATA(D16_MARK, PORT200_FN4),
882 PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
883 PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
884 PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
885 PINMUX_DATA(D17_MARK, PORT201_FN4),
886 PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
887 PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
888 PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
889 PINMUX_DATA(D18_MARK, PORT202_FN4),
890 PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
891 PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
892 PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
893 PINMUX_DATA(D19_MARK, PORT203_FN4),
894 PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
895 PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
896 PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
897 PINMUX_DATA(D20_MARK, PORT204_FN4),
898 PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
899 PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
900 PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
901 PINMUX_DATA(D21_MARK, PORT205_FN4),
902 PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
903 PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
904 PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
905 PINMUX_DATA(D22_MARK, PORT206_FN4),
906 PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
907 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
908 PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
909 PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
910 PINMUX_DATA(D23_MARK, PORT207_FN5),
911 PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
912 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
913 PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
914 PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
915 PINMUX_DATA(D24_MARK, PORT208_FN5),
916 PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
917 PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
918 PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
919 PINMUX_DATA(D25_MARK, PORT209_FN4),
920 PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
921 PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
922 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
923 PINMUX_DATA(D26_MARK, PORT210_FN4),
924 PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
925 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
926 PINMUX_DATA(D27_MARK, PORT211_FN3),
927 PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
928 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
929 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
930 PINMUX_DATA(D28_MARK, PORT212_FN4),
931 PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
932 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
933 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
934 PINMUX_DATA(D29_MARK, PORT213_FN4),
935 PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
936 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
937 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
938 PINMUX_DATA(D30_MARK, PORT214_FN4),
939 PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
940 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
941 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
942 PINMUX_DATA(D31_MARK, PORT215_FN4),
943 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
944 PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
945 PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
946 PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
947 PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
948 PINMUX_DATA(DACK2_MARK, PORT217_FN2),
949 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
950 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
951 PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
952 PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
953 PINMUX_DATA(DACK3_MARK, PORT218_FN4),
954 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
955 PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
956 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
957 PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
958 PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
959 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
960 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
961 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
962 PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
963 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
964 PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
965 PINMUX_DATA(PWEN_MARK, PORT221_FN3),
966 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
967 PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
968 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
969 PINMUX_DATA(DACK1_MARK, PORT222_FN3),
970 PINMUX_DATA(OVCN_MARK, PORT222_FN4),
971 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
972 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
973 PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
974 PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
975 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
976 PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
977 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
978 PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
979 PINMUX_DATA(IDIN_MARK, PORT227_FN2),
980 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
981 PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
982 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
983 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
984 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
985 PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
986 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
987 PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
988 PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
989 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
990 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
991 PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
992 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
993 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
994 PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
995 PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
996 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
997 PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
998 PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
999 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
1000 PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
1001 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
1002 PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
1003 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
1004 PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
1005 PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
1006 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
1007 PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
1008 PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
1009 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
1010 PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
1011
1012 /* 55-5 (FN) */
1013 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
1014 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
1015 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
1016 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
1017 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
1018 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
1019 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
1020 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
1021 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
1022 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
1023 PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
1024 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
1025 PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
1026 PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
1027 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
1028 PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
1029 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
1030 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
1031 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
1032 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
1033 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
1034 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
1035 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
1036 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1037 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
1038 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
1039 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
1040 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
1041 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
1042 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
1043 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1044 PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
1045 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1046 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1047 PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
1048 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1049 PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
1050 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1051 PINMUX_DATA(TDI2_MARK, PORT254_FN2),
1052 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1053 PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
1054 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1055 PINMUX_DATA(TRST2_MARK, PORT256_FN2),
1056 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1057 PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
1058 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1059 PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
1060 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
1061 PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
1062 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1063 PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
1064 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
1065 PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
1066 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1067 PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
1068 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
1069 PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
1070 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1071 PINMUX_DATA(TDI3_MARK, PORT261_FN4),
1072 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
1073 PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
1074 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1075 PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
1076 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1077 PINMUX_DATA(TRST3_MARK, PORT263_FN2),
1078 PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
1079};
1080
1081#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1082#define GPIO_PORT_265() _265(_GPIO_PORT, , unused)
1083#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1084
1085static struct pinmux_gpio pinmux_gpios[] = {
1086 /* 55-1 -> 55-5 (GPIO) */
1087 GPIO_PORT_265(),
1088
1089 /* Special Pull-up / Pull-down Functions */
1090 GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
1091 GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
1092 GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
1093 GPIO_FN(PORT72_KEYIN6_PU),
1094
1095 /* 55-1 (FN) */
1096 GPIO_FN(VBUS_0),
1097 GPIO_FN(CPORT0),
1098 GPIO_FN(CPORT1),
1099 GPIO_FN(CPORT2),
1100 GPIO_FN(CPORT3),
1101 GPIO_FN(CPORT4),
1102 GPIO_FN(CPORT5),
1103 GPIO_FN(CPORT6),
1104 GPIO_FN(CPORT7),
1105 GPIO_FN(CPORT8),
1106 GPIO_FN(CPORT9),
1107 GPIO_FN(CPORT10),
1108 GPIO_FN(CPORT11), GPIO_FN(SIN2),
1109 GPIO_FN(CPORT12), GPIO_FN(XCTS2),
1110 GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
1111 GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
1112 GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
1113 GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
1114 GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
1115 GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
1116 GPIO_FN(CPORT19_MPORT1),
1117 GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
1118 GPIO_FN(CPORT21), GPIO_FN(STATUS0),
1119 GPIO_FN(CPORT22), GPIO_FN(STATUS1),
1120 GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
1121 GPIO_FN(B_SYNLD1),
1122 GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
1123 GPIO_FN(XMAINPS),
1124 GPIO_FN(XDIVPS),
1125 GPIO_FN(XIDRST),
1126 GPIO_FN(IDCLK), GPIO_FN(IC_DP),
1127 GPIO_FN(IDIO), GPIO_FN(IC_DM),
1128 GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
1129 GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
1130 GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
1131 GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
1132 GPIO_FN(PCMCLKO),
1133 GPIO_FN(SYNC8KO),
1134
1135 /* 55-2 (FN) */
1136 GPIO_FN(DNPCM_A),
1137 GPIO_FN(UPPCM_A),
1138 GPIO_FN(VACK),
1139 GPIO_FN(XTALB1L),
1140 GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
1141 GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
1142 GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
1143 GPIO_FN(GPS_IM),
1144 GPIO_FN(GPS_IS),
1145 GPIO_FN(GPS_QM),
1146 GPIO_FN(GPS_QS),
1147 GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
1148 GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
1149 GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
1150 GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
1151 GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
1152 GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
1153 GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
1154 GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
1155 GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
1156 GPIO_FN(FMSIIBT),
1157 GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
1158 GPIO_FN(A0_EA0), GPIO_FN(BS),
1159 GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
1160 GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
1161 GPIO_FN(TPU0TO1),
1162 GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
1163 GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
1164 GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
1165 GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
1166 GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
1167 GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
1168 GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
1169 GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
1170 GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
1171 GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
1172 GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
1173 GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
1174 GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
1175 GPIO_FN(D0_ED0_NAF0),
1176 GPIO_FN(D1_ED1_NAF1),
1177 GPIO_FN(D2_ED2_NAF2),
1178 GPIO_FN(D3_ED3_NAF3),
1179 GPIO_FN(D4_ED4_NAF4),
1180 GPIO_FN(D5_ED5_NAF5),
1181 GPIO_FN(D6_ED6_NAF6),
1182 GPIO_FN(D7_ED7_NAF7),
1183 GPIO_FN(D8_ED8_NAF8),
1184 GPIO_FN(D9_ED9_NAF9),
1185 GPIO_FN(D10_ED10_NAF10),
1186 GPIO_FN(D11_ED11_NAF11),
1187 GPIO_FN(D12_ED12_NAF12),
1188 GPIO_FN(D13_ED13_NAF13),
1189 GPIO_FN(D14_ED14_NAF14),
1190 GPIO_FN(D15_ED15_NAF15),
1191 GPIO_FN(CS4),
1192 GPIO_FN(CS5A), GPIO_FN(FMSICK),
1193
1194 /* 55-3 (FN) */
1195 GPIO_FN(CS5B), GPIO_FN(FCE1),
1196 GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
1197 GPIO_FN(FCE0),
1198 GPIO_FN(WAIT), GPIO_FN(DREQ0),
1199 GPIO_FN(RD_XRD),
1200 GPIO_FN(WE0_XWR0_FWE),
1201 GPIO_FN(WE1_XWR1),
1202 GPIO_FN(FRB),
1203 GPIO_FN(CKO),
1204 GPIO_FN(NBRSTOUT),
1205 GPIO_FN(NBRST),
1206 GPIO_FN(GPS_EPPSIN),
1207 GPIO_FN(LATCHPULSE),
1208 GPIO_FN(LTESIGNAL),
1209 GPIO_FN(LEGACYSTATE),
1210 GPIO_FN(TCKON),
1211 GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
1212 GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
1213 GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
1214 GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
1215 GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
1216 GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
1217 GPIO_FN(PORT133_MSIOF2_TSYNC),
1218 GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
1219 GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
1220 GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
1221 GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
1222 GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
1223 GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
1224 GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
1225 GPIO_FN(PORT140_FSIAOBT),
1226 GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
1227 GPIO_FN(PORT141_FSIAOSLD),
1228 GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
1229 GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
1230 GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
1231 GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
1232 GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
1233 GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
1234 GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
1235 GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
1236 GPIO_FN(MFG0_IN2),
1237 GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
1238 GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
1239 GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
1240 GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
1241 GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
1242 GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
1243 GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
1244
1245 /* 55-4 (FN) */
1246 GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
1247 GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
1248 GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
1249 GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
1250 GPIO_FN(MFG3_IN2),
1251 GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
1252 GPIO_FN(MFG3_IN1),
1253 GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
1254 GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
1255 GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
1256 GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
1257 GPIO_FN(BBIF2_TSYNC1),
1258 GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
1259 GPIO_FN(BBIF2_TSCK1),
1260 GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
1261 GPIO_FN(BBIF2_TXD1),
1262 GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
1263 GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
1264 GPIO_FN(MFG2_OUT2),
1265 GPIO_FN(LCDD6),
1266 GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
1267 GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
1268 GPIO_FN(D16),
1269 GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
1270 GPIO_FN(D17),
1271 GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
1272 GPIO_FN(D18),
1273 GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
1274 GPIO_FN(D19),
1275 GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
1276 GPIO_FN(D20),
1277 GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
1278 GPIO_FN(D21),
1279 GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
1280 GPIO_FN(D22),
1281 GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
1282 GPIO_FN(VIO_DR7), GPIO_FN(D23),
1283 GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
1284 GPIO_FN(VIO_VDR), GPIO_FN(D24),
1285 GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
1286 GPIO_FN(D25),
1287 GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
1288 GPIO_FN(D26),
1289 GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
1290 GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
1291 GPIO_FN(D28),
1292 GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
1293 GPIO_FN(D29),
1294 GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
1295 GPIO_FN(D30),
1296 GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
1297 GPIO_FN(D31),
1298 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
1299 GPIO_FN(VIO_CLKR),
1300 GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
1301 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
1302 GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
1303 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
1304 GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
1305 GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
1306 GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
1307 GPIO_FN(MSIOF0L_TXD),
1308 GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
1309 GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
1310 GPIO_FN(PORT226_VIO_CKO2),
1311 GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
1312 GPIO_FN(SCIFA1_RXD),
1313 GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
1314 GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
1315 GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
1316 GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
1317 GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
1318 GPIO_FN(PORT233_FSIACK),
1319 GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
1320 GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
1321 GPIO_FN(PORT235_FSIAILR),
1322 GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
1323 GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
1324 GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
1325
1326 /* 55-5 (FN) */
1327 GPIO_FN(MSIOF1_SS2),
1328 GPIO_FN(SCIFA6_TXD),
1329 GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
1330 GPIO_FN(TPU4TO0),
1331 GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
1332 GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
1333 GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
1334 GPIO_FN(PORT244_SCIFB_CTS),
1335 GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
1336 GPIO_FN(PORT245_SCIFB_RTS),
1337 GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
1338 GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
1339 GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
1340 GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
1341 GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
1342 GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
1343 GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
1344 GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
1345 GPIO_FN(SDHICD0),
1346 GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
1347 GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
1348 GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
1349 GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
1350 GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
1351 GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
1352 GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
1353 GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
1354 GPIO_FN(TMS3_SWDIO_MC1),
1355 GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
1356 GPIO_FN(TDO3_SWO0_MC1),
1357 GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
1358 GPIO_FN(TDI3),
1359 GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
1360 GPIO_FN(RTCK3_SWO1_MC1),
1361 GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1362 GPIO_FN(RESETOUTS),
1363};
1364
1365/* helper for top 4 bits in PORTnCR */
1366#define PCRH(in, in_pd, in_pu, out) \
1367 0, (out), (in), 0, \
1368 0, 0, 0, 0, \
1369 0, 0, (in_pd), 0, \
1370 0, 0, (in_pu), 0
1371
1372#define PORTCR(nr, reg) \
1373 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1374 PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1375 PORT##nr##_IN_PU, PORT##nr##_OUT), \
1376 PORT##nr##_FN0, PORT##nr##_FN1, \
1377 PORT##nr##_FN2, PORT##nr##_FN3, \
1378 PORT##nr##_FN4, PORT##nr##_FN5, \
1379 PORT##nr##_FN6, PORT##nr##_FN7 } \
1380 }
1381
1382static struct pinmux_cfg_reg pinmux_config_regs[] = {
1383 PORTCR(0, 0xe6050000), /* PORT0CR */
1384 PORTCR(1, 0xe6050001), /* PORT1CR */
1385 PORTCR(2, 0xe6050002), /* PORT2CR */
1386 PORTCR(3, 0xe6050003), /* PORT3CR */
1387 PORTCR(4, 0xe6050004), /* PORT4CR */
1388 PORTCR(5, 0xe6050005), /* PORT5CR */
1389 PORTCR(6, 0xe6050006), /* PORT6CR */
1390 PORTCR(7, 0xe6050007), /* PORT7CR */
1391 PORTCR(8, 0xe6050008), /* PORT8CR */
1392 PORTCR(9, 0xe6050009), /* PORT9CR */
1393
1394 PORTCR(10, 0xe605000a), /* PORT10CR */
1395 PORTCR(11, 0xe605000b), /* PORT11CR */
1396 PORTCR(12, 0xe605000c), /* PORT12CR */
1397 PORTCR(13, 0xe605000d), /* PORT13CR */
1398 PORTCR(14, 0xe605000e), /* PORT14CR */
1399 PORTCR(15, 0xe605000f), /* PORT15CR */
1400 PORTCR(16, 0xe6050010), /* PORT16CR */
1401 PORTCR(17, 0xe6050011), /* PORT17CR */
1402 PORTCR(18, 0xe6050012), /* PORT18CR */
1403 PORTCR(19, 0xe6050013), /* PORT19CR */
1404
1405 PORTCR(20, 0xe6050014), /* PORT20CR */
1406 PORTCR(21, 0xe6050015), /* PORT21CR */
1407 PORTCR(22, 0xe6050016), /* PORT22CR */
1408 PORTCR(23, 0xe6050017), /* PORT23CR */
1409 PORTCR(24, 0xe6050018), /* PORT24CR */
1410 PORTCR(25, 0xe6050019), /* PORT25CR */
1411 PORTCR(26, 0xe605001a), /* PORT26CR */
1412 PORTCR(27, 0xe605001b), /* PORT27CR */
1413 PORTCR(28, 0xe605001c), /* PORT28CR */
1414 PORTCR(29, 0xe605001d), /* PORT29CR */
1415
1416 PORTCR(30, 0xe605001e), /* PORT30CR */
1417 PORTCR(31, 0xe605001f), /* PORT31CR */
1418 PORTCR(32, 0xe6050020), /* PORT32CR */
1419 PORTCR(33, 0xe6050021), /* PORT33CR */
1420 PORTCR(34, 0xe6050022), /* PORT34CR */
1421 PORTCR(35, 0xe6050023), /* PORT35CR */
1422 PORTCR(36, 0xe6050024), /* PORT36CR */
1423 PORTCR(37, 0xe6050025), /* PORT37CR */
1424 PORTCR(38, 0xe6050026), /* PORT38CR */
1425 PORTCR(39, 0xe6050027), /* PORT39CR */
1426
1427 PORTCR(40, 0xe6050028), /* PORT40CR */
1428 PORTCR(41, 0xe6050029), /* PORT41CR */
1429 PORTCR(42, 0xe605002a), /* PORT42CR */
1430 PORTCR(43, 0xe605002b), /* PORT43CR */
1431 PORTCR(44, 0xe605002c), /* PORT44CR */
1432 PORTCR(45, 0xe605002d), /* PORT45CR */
1433 PORTCR(46, 0xe605002e), /* PORT46CR */
1434 PORTCR(47, 0xe605002f), /* PORT47CR */
1435 PORTCR(48, 0xe6050030), /* PORT48CR */
1436 PORTCR(49, 0xe6050031), /* PORT49CR */
1437
1438 PORTCR(50, 0xe6050032), /* PORT50CR */
1439 PORTCR(51, 0xe6050033), /* PORT51CR */
1440 PORTCR(52, 0xe6050034), /* PORT52CR */
1441 PORTCR(53, 0xe6050035), /* PORT53CR */
1442 PORTCR(54, 0xe6050036), /* PORT54CR */
1443 PORTCR(55, 0xe6050037), /* PORT55CR */
1444 PORTCR(56, 0xe6050038), /* PORT56CR */
1445 PORTCR(57, 0xe6050039), /* PORT57CR */
1446 PORTCR(58, 0xe605003a), /* PORT58CR */
1447 PORTCR(59, 0xe605003b), /* PORT59CR */
1448
1449 PORTCR(60, 0xe605003c), /* PORT60CR */
1450 PORTCR(61, 0xe605003d), /* PORT61CR */
1451 PORTCR(62, 0xe605003e), /* PORT62CR */
1452 PORTCR(63, 0xe605003f), /* PORT63CR */
1453 PORTCR(64, 0xe6050040), /* PORT64CR */
1454 PORTCR(65, 0xe6050041), /* PORT65CR */
1455 PORTCR(66, 0xe6050042), /* PORT66CR */
1456 PORTCR(67, 0xe6050043), /* PORT67CR */
1457 PORTCR(68, 0xe6050044), /* PORT68CR */
1458 PORTCR(69, 0xe6050045), /* PORT69CR */
1459
1460 PORTCR(70, 0xe6050046), /* PORT70CR */
1461 PORTCR(71, 0xe6050047), /* PORT71CR */
1462 PORTCR(72, 0xe6050048), /* PORT72CR */
1463 PORTCR(73, 0xe6050049), /* PORT73CR */
1464 PORTCR(74, 0xe605004a), /* PORT74CR */
1465 PORTCR(75, 0xe605004b), /* PORT75CR */
1466 PORTCR(76, 0xe605004c), /* PORT76CR */
1467 PORTCR(77, 0xe605004d), /* PORT77CR */
1468 PORTCR(78, 0xe605004e), /* PORT78CR */
1469 PORTCR(79, 0xe605004f), /* PORT79CR */
1470
1471 PORTCR(80, 0xe6050050), /* PORT80CR */
1472 PORTCR(81, 0xe6050051), /* PORT81CR */
1473 PORTCR(82, 0xe6050052), /* PORT82CR */
1474 PORTCR(83, 0xe6050053), /* PORT83CR */
1475 PORTCR(84, 0xe6050054), /* PORT84CR */
1476 PORTCR(85, 0xe6050055), /* PORT85CR */
1477 PORTCR(86, 0xe6050056), /* PORT86CR */
1478 PORTCR(87, 0xe6050057), /* PORT87CR */
1479 PORTCR(88, 0xe6050058), /* PORT88CR */
1480 PORTCR(89, 0xe6050059), /* PORT89CR */
1481
1482 PORTCR(90, 0xe605005a), /* PORT90CR */
1483 PORTCR(91, 0xe605005b), /* PORT91CR */
1484 PORTCR(92, 0xe605005c), /* PORT92CR */
1485 PORTCR(93, 0xe605005d), /* PORT93CR */
1486 PORTCR(94, 0xe605005e), /* PORT94CR */
1487 PORTCR(95, 0xe605005f), /* PORT95CR */
1488 PORTCR(96, 0xe6050060), /* PORT96CR */
1489 PORTCR(97, 0xe6050061), /* PORT97CR */
1490 PORTCR(98, 0xe6050062), /* PORT98CR */
1491 PORTCR(99, 0xe6050063), /* PORT99CR */
1492
1493 PORTCR(100, 0xe6050064), /* PORT100CR */
1494 PORTCR(101, 0xe6050065), /* PORT101CR */
1495 PORTCR(102, 0xe6050066), /* PORT102CR */
1496 PORTCR(103, 0xe6050067), /* PORT103CR */
1497 PORTCR(104, 0xe6050068), /* PORT104CR */
1498 PORTCR(105, 0xe6050069), /* PORT105CR */
1499 PORTCR(106, 0xe605006a), /* PORT106CR */
1500 PORTCR(107, 0xe605006b), /* PORT107CR */
1501 PORTCR(108, 0xe605006c), /* PORT108CR */
1502 PORTCR(109, 0xe605006d), /* PORT109CR */
1503
1504 PORTCR(110, 0xe605006e), /* PORT110CR */
1505 PORTCR(111, 0xe605006f), /* PORT111CR */
1506 PORTCR(112, 0xe6050070), /* PORT112CR */
1507 PORTCR(113, 0xe6050071), /* PORT113CR */
1508 PORTCR(114, 0xe6050072), /* PORT114CR */
1509 PORTCR(115, 0xe6050073), /* PORT115CR */
1510 PORTCR(116, 0xe6050074), /* PORT116CR */
1511 PORTCR(117, 0xe6050075), /* PORT117CR */
1512 PORTCR(118, 0xe6050076), /* PORT118CR */
1513
1514 PORTCR(128, 0xe6051080), /* PORT128CR */
1515 PORTCR(129, 0xe6051081), /* PORT129CR */
1516
1517 PORTCR(130, 0xe6051082), /* PORT130CR */
1518 PORTCR(131, 0xe6051083), /* PORT131CR */
1519 PORTCR(132, 0xe6051084), /* PORT132CR */
1520 PORTCR(133, 0xe6051085), /* PORT133CR */
1521 PORTCR(134, 0xe6051086), /* PORT134CR */
1522 PORTCR(135, 0xe6051087), /* PORT135CR */
1523 PORTCR(136, 0xe6051088), /* PORT136CR */
1524 PORTCR(137, 0xe6051089), /* PORT137CR */
1525 PORTCR(138, 0xe605108a), /* PORT138CR */
1526 PORTCR(139, 0xe605108b), /* PORT139CR */
1527
1528 PORTCR(140, 0xe605108c), /* PORT140CR */
1529 PORTCR(141, 0xe605108d), /* PORT141CR */
1530 PORTCR(142, 0xe605108e), /* PORT142CR */
1531 PORTCR(143, 0xe605108f), /* PORT143CR */
1532 PORTCR(144, 0xe6051090), /* PORT144CR */
1533 PORTCR(145, 0xe6051091), /* PORT145CR */
1534 PORTCR(146, 0xe6051092), /* PORT146CR */
1535 PORTCR(147, 0xe6051093), /* PORT147CR */
1536 PORTCR(148, 0xe6051094), /* PORT148CR */
1537 PORTCR(149, 0xe6051095), /* PORT149CR */
1538
1539 PORTCR(150, 0xe6051096), /* PORT150CR */
1540 PORTCR(151, 0xe6051097), /* PORT151CR */
1541 PORTCR(152, 0xe6051098), /* PORT152CR */
1542 PORTCR(153, 0xe6051099), /* PORT153CR */
1543 PORTCR(154, 0xe605109a), /* PORT154CR */
1544 PORTCR(155, 0xe605109b), /* PORT155CR */
1545 PORTCR(156, 0xe605109c), /* PORT156CR */
1546 PORTCR(157, 0xe605109d), /* PORT157CR */
1547 PORTCR(158, 0xe605109e), /* PORT158CR */
1548 PORTCR(159, 0xe605109f), /* PORT159CR */
1549
1550 PORTCR(160, 0xe60510a0), /* PORT160CR */
1551 PORTCR(161, 0xe60510a1), /* PORT161CR */
1552 PORTCR(162, 0xe60510a2), /* PORT162CR */
1553 PORTCR(163, 0xe60510a3), /* PORT163CR */
1554 PORTCR(164, 0xe60510a4), /* PORT164CR */
1555
1556 PORTCR(192, 0xe60520c0), /* PORT192CR */
1557 PORTCR(193, 0xe60520c1), /* PORT193CR */
1558 PORTCR(194, 0xe60520c2), /* PORT194CR */
1559 PORTCR(195, 0xe60520c3), /* PORT195CR */
1560 PORTCR(196, 0xe60520c4), /* PORT196CR */
1561 PORTCR(197, 0xe60520c5), /* PORT197CR */
1562 PORTCR(198, 0xe60520c6), /* PORT198CR */
1563 PORTCR(199, 0xe60520c7), /* PORT199CR */
1564
1565 PORTCR(200, 0xe60520c8), /* PORT200CR */
1566 PORTCR(201, 0xe60520c9), /* PORT201CR */
1567 PORTCR(202, 0xe60520ca), /* PORT202CR */
1568 PORTCR(203, 0xe60520cb), /* PORT203CR */
1569 PORTCR(204, 0xe60520cc), /* PORT204CR */
1570 PORTCR(205, 0xe60520cd), /* PORT205CR */
1571 PORTCR(206, 0xe60520ce), /* PORT206CR */
1572 PORTCR(207, 0xe60520cf), /* PORT207CR */
1573 PORTCR(208, 0xe60520d0), /* PORT208CR */
1574 PORTCR(209, 0xe60520d1), /* PORT209CR */
1575
1576 PORTCR(210, 0xe60520d2), /* PORT210CR */
1577 PORTCR(211, 0xe60520d3), /* PORT211CR */
1578 PORTCR(212, 0xe60520d4), /* PORT212CR */
1579 PORTCR(213, 0xe60520d5), /* PORT213CR */
1580 PORTCR(214, 0xe60520d6), /* PORT214CR */
1581 PORTCR(215, 0xe60520d7), /* PORT215CR */
1582 PORTCR(216, 0xe60520d8), /* PORT216CR */
1583 PORTCR(217, 0xe60520d9), /* PORT217CR */
1584 PORTCR(218, 0xe60520da), /* PORT218CR */
1585 PORTCR(219, 0xe60520db), /* PORT219CR */
1586
1587 PORTCR(220, 0xe60520dc), /* PORT220CR */
1588 PORTCR(221, 0xe60520dd), /* PORT221CR */
1589 PORTCR(222, 0xe60520de), /* PORT222CR */
1590 PORTCR(223, 0xe60520df), /* PORT223CR */
1591 PORTCR(224, 0xe60520e0), /* PORT224CR */
1592 PORTCR(225, 0xe60520e1), /* PORT225CR */
1593 PORTCR(226, 0xe60520e2), /* PORT226CR */
1594 PORTCR(227, 0xe60520e3), /* PORT227CR */
1595 PORTCR(228, 0xe60520e4), /* PORT228CR */
1596 PORTCR(229, 0xe60520e5), /* PORT229CR */
1597
1598 PORTCR(230, 0xe60520e6), /* PORT230CR */
1599 PORTCR(231, 0xe60520e7), /* PORT231CR */
1600 PORTCR(232, 0xe60520e8), /* PORT232CR */
1601 PORTCR(233, 0xe60520e9), /* PORT233CR */
1602 PORTCR(234, 0xe60520ea), /* PORT234CR */
1603 PORTCR(235, 0xe60520eb), /* PORT235CR */
1604 PORTCR(236, 0xe60520ec), /* PORT236CR */
1605 PORTCR(237, 0xe60520ed), /* PORT237CR */
1606 PORTCR(238, 0xe60520ee), /* PORT238CR */
1607 PORTCR(239, 0xe60520ef), /* PORT239CR */
1608
1609 PORTCR(240, 0xe60520f0), /* PORT240CR */
1610 PORTCR(241, 0xe60520f1), /* PORT241CR */
1611 PORTCR(242, 0xe60520f2), /* PORT242CR */
1612 PORTCR(243, 0xe60520f3), /* PORT243CR */
1613 PORTCR(244, 0xe60520f4), /* PORT244CR */
1614 PORTCR(245, 0xe60520f5), /* PORT245CR */
1615 PORTCR(246, 0xe60520f6), /* PORT246CR */
1616 PORTCR(247, 0xe60520f7), /* PORT247CR */
1617 PORTCR(248, 0xe60520f8), /* PORT248CR */
1618 PORTCR(249, 0xe60520f9), /* PORT249CR */
1619
1620 PORTCR(250, 0xe60520fa), /* PORT250CR */
1621 PORTCR(251, 0xe60520fb), /* PORT251CR */
1622 PORTCR(252, 0xe60520fc), /* PORT252CR */
1623 PORTCR(253, 0xe60520fd), /* PORT253CR */
1624 PORTCR(254, 0xe60520fe), /* PORT254CR */
1625 PORTCR(255, 0xe60520ff), /* PORT255CR */
1626 PORTCR(256, 0xe6052100), /* PORT256CR */
1627 PORTCR(257, 0xe6052101), /* PORT257CR */
1628 PORTCR(258, 0xe6052102), /* PORT258CR */
1629 PORTCR(259, 0xe6052103), /* PORT259CR */
1630
1631 PORTCR(260, 0xe6052104), /* PORT260CR */
1632 PORTCR(261, 0xe6052105), /* PORT261CR */
1633 PORTCR(262, 0xe6052106), /* PORT262CR */
1634 PORTCR(263, 0xe6052107), /* PORT263CR */
1635 PORTCR(264, 0xe6052108), /* PORT264CR */
1636
1637 { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
1638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1640 MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
1641 MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
1642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1644 },
1645 { },
1646};
1647
1648static struct pinmux_data_reg pinmux_data_regs[] = {
1649 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
1650 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
1651 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
1652 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
1653 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
1654 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
1655 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
1656 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
1657 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
1658 },
1659 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
1660 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
1661 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
1662 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
1663 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
1664 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
1665 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
1666 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
1667 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
1668 },
1669 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
1670 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1671 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
1672 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
1673 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
1674 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
1675 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
1676 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
1677 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
1678 },
1679 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
1680 0, 0, 0, 0,
1681 0, 0, 0, 0,
1682 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
1683 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
1684 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
1685 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
1686 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
1687 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
1688 },
1689 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
1690 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
1691 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
1692 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
1693 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
1694 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
1695 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
1696 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
1697 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
1698 },
1699 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
1700 0, 0, 0, 0,
1701 0, 0, 0, 0,
1702 0, 0, 0, 0,
1703 0, 0, 0, 0,
1704 0, 0, 0, 0,
1705 0, 0, 0, 0,
1706 0, 0, 0, PORT164_DATA,
1707 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
1708 },
1709 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
1710 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
1711 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
1712 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
1713 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
1714 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
1715 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
1716 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
1717 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
1718 },
1719 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
1720 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
1721 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
1722 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
1723 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
1724 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
1725 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
1726 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
1727 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
1728 },
1729 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
1730 0, 0, 0, 0,
1731 0, 0, 0, 0,
1732 0, 0, 0, 0,
1733 0, 0, 0, 0,
1734 0, 0, 0, 0,
1735 0, 0, 0, PORT264_DATA,
1736 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
1737 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
1738 },
1739 { },
1740};
1741
1742static struct pinmux_info sh7377_pinmux_info = {
1743 .name = "sh7377_pfc",
1744 .reserved_id = PINMUX_RESERVED,
1745 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1746 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1747 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1748 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1749 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1750 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1751 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1752
1753 .first_gpio = GPIO_PORT0,
1754 .last_gpio = GPIO_FN_RESETOUTS,
1755
1756 .gpios = pinmux_gpios,
1757 .cfg_regs = pinmux_config_regs,
1758 .data_regs = pinmux_data_regs,
1759
1760 .gpio_data = pinmux_data,
1761 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1762};
1763
1764void sh7377_pinmux_init(void)
1765{
1766 register_pinmux(&sh7377_pinmux_info);
1767}
diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c
new file mode 100644
index 00000000000..6ec454e1e06
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm_runtime.c
@@ -0,0 +1,66 @@
1/*
2 * arch/arm/mach-shmobile/pm_runtime.c
3 *
4 * Runtime PM support code for SuperH Mobile ARM
5 *
6 * Copyright (C) 2009-2010 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/pm_runtime.h>
17#include <linux/pm_domain.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
20#include <linux/sh_clk.h>
21#include <linux/bitmap.h>
22#include <linux/slab.h>
23
24#ifdef CONFIG_PM_RUNTIME
25
26static int default_platform_runtime_idle(struct device *dev)
27{
28 /* suspend synchronously to disable clocks immediately */
29 return pm_runtime_suspend(dev);
30}
31
32static struct dev_pm_domain default_pm_domain = {
33 .ops = {
34 .runtime_suspend = pm_clk_suspend,
35 .runtime_resume = pm_clk_resume,
36 .runtime_idle = default_platform_runtime_idle,
37 USE_PLATFORM_PM_SLEEP_OPS
38 },
39};
40
41#define DEFAULT_PM_DOMAIN_PTR (&default_pm_domain)
42
43#else
44
45#define DEFAULT_PM_DOMAIN_PTR NULL
46
47#endif /* CONFIG_PM_RUNTIME */
48
49static struct pm_clk_notifier_block platform_bus_notifier = {
50 .pm_domain = DEFAULT_PM_DOMAIN_PTR,
51 .con_ids = { NULL, },
52};
53
54static int __init sh_pm_runtime_init(void)
55{
56 pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
57 return 0;
58}
59core_initcall(sh_pm_runtime_init);
60
61static int __init sh_pm_runtime_late_init(void)
62{
63 pm_genpd_poweroff_unused();
64 return 0;
65}
66late_initcall(sh_pm_runtime_late_init);
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
new file mode 100644
index 00000000000..e546017f15d
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -0,0 +1,448 @@
1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34
35/* SCIFA0 */
36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
41 .type = PORT_SCIFA,
42 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
43 evt2irq(0xc00), evt2irq(0xc00) },
44};
45
46static struct platform_device scif0_device = {
47 .name = "sh-sci",
48 .id = 0,
49 .dev = {
50 .platform_data = &scif0_platform_data,
51 },
52};
53
54/* SCIFA1 */
55static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4,
60 .type = PORT_SCIFA,
61 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
62 evt2irq(0xc20), evt2irq(0xc20) },
63};
64
65static struct platform_device scif1_device = {
66 .name = "sh-sci",
67 .id = 1,
68 .dev = {
69 .platform_data = &scif1_platform_data,
70 },
71};
72
73/* SCIFA2 */
74static struct plat_sci_port scif2_platform_data = {
75 .mapbase = 0xe6c60000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
79 .type = PORT_SCIFA,
80 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
81 evt2irq(0xc40), evt2irq(0xc40) },
82};
83
84static struct platform_device scif2_device = {
85 .name = "sh-sci",
86 .id = 2,
87 .dev = {
88 .platform_data = &scif2_platform_data,
89 },
90};
91
92/* SCIFA3 */
93static struct plat_sci_port scif3_platform_data = {
94 .mapbase = 0xe6c70000,
95 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4,
98 .type = PORT_SCIFA,
99 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
100 evt2irq(0xc60), evt2irq(0xc60) },
101};
102
103static struct platform_device scif3_device = {
104 .name = "sh-sci",
105 .id = 3,
106 .dev = {
107 .platform_data = &scif3_platform_data,
108 },
109};
110
111/* SCIFA4 */
112static struct plat_sci_port scif4_platform_data = {
113 .mapbase = 0xe6c80000,
114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4,
117 .type = PORT_SCIFA,
118 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
119 evt2irq(0xd20), evt2irq(0xd20) },
120};
121
122static struct platform_device scif4_device = {
123 .name = "sh-sci",
124 .id = 4,
125 .dev = {
126 .platform_data = &scif4_platform_data,
127 },
128};
129
130/* SCIFA5 */
131static struct plat_sci_port scif5_platform_data = {
132 .mapbase = 0xe6cb0000,
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
136 .type = PORT_SCIFA,
137 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
138 evt2irq(0xd40), evt2irq(0xd40) },
139};
140
141static struct platform_device scif5_device = {
142 .name = "sh-sci",
143 .id = 5,
144 .dev = {
145 .platform_data = &scif5_platform_data,
146 },
147};
148
149/* SCIFB */
150static struct plat_sci_port scif6_platform_data = {
151 .mapbase = 0xe6c30000,
152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
155 .type = PORT_SCIFB,
156 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
157 evt2irq(0xd60), evt2irq(0xd60) },
158};
159
160static struct platform_device scif6_device = {
161 .name = "sh-sci",
162 .id = 6,
163 .dev = {
164 .platform_data = &scif6_platform_data,
165 },
166};
167
168static struct sh_timer_config cmt10_platform_data = {
169 .name = "CMT10",
170 .channel_offset = 0x10,
171 .timer_bit = 0,
172 .clockevent_rating = 125,
173 .clocksource_rating = 125,
174};
175
176static struct resource cmt10_resources[] = {
177 [0] = {
178 .name = "CMT10",
179 .start = 0xe6138010,
180 .end = 0xe613801b,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = evt2irq(0xb00), /* CMT1_CMT10 */
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device cmt10_device = {
190 .name = "sh_cmt",
191 .id = 10,
192 .dev = {
193 .platform_data = &cmt10_platform_data,
194 },
195 .resource = cmt10_resources,
196 .num_resources = ARRAY_SIZE(cmt10_resources),
197};
198
199/* VPU */
200static struct uio_info vpu_platform_data = {
201 .name = "VPU5",
202 .version = "0",
203 .irq = intcs_evt2irq(0x980),
204};
205
206static struct resource vpu_resources[] = {
207 [0] = {
208 .name = "VPU",
209 .start = 0xfe900000,
210 .end = 0xfe902807,
211 .flags = IORESOURCE_MEM,
212 },
213};
214
215static struct platform_device vpu_device = {
216 .name = "uio_pdrv_genirq",
217 .id = 0,
218 .dev = {
219 .platform_data = &vpu_platform_data,
220 },
221 .resource = vpu_resources,
222 .num_resources = ARRAY_SIZE(vpu_resources),
223};
224
225/* VEU0 */
226static struct uio_info veu0_platform_data = {
227 .name = "VEU0",
228 .version = "0",
229 .irq = intcs_evt2irq(0x700),
230};
231
232static struct resource veu0_resources[] = {
233 [0] = {
234 .name = "VEU0",
235 .start = 0xfe920000,
236 .end = 0xfe9200b7,
237 .flags = IORESOURCE_MEM,
238 },
239};
240
241static struct platform_device veu0_device = {
242 .name = "uio_pdrv_genirq",
243 .id = 1,
244 .dev = {
245 .platform_data = &veu0_platform_data,
246 },
247 .resource = veu0_resources,
248 .num_resources = ARRAY_SIZE(veu0_resources),
249};
250
251/* VEU1 */
252static struct uio_info veu1_platform_data = {
253 .name = "VEU1",
254 .version = "0",
255 .irq = intcs_evt2irq(0x720),
256};
257
258static struct resource veu1_resources[] = {
259 [0] = {
260 .name = "VEU1",
261 .start = 0xfe924000,
262 .end = 0xfe9240b7,
263 .flags = IORESOURCE_MEM,
264 },
265};
266
267static struct platform_device veu1_device = {
268 .name = "uio_pdrv_genirq",
269 .id = 2,
270 .dev = {
271 .platform_data = &veu1_platform_data,
272 },
273 .resource = veu1_resources,
274 .num_resources = ARRAY_SIZE(veu1_resources),
275};
276
277/* VEU2 */
278static struct uio_info veu2_platform_data = {
279 .name = "VEU2",
280 .version = "0",
281 .irq = intcs_evt2irq(0x740),
282};
283
284static struct resource veu2_resources[] = {
285 [0] = {
286 .name = "VEU2",
287 .start = 0xfe928000,
288 .end = 0xfe9280b7,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device veu2_device = {
294 .name = "uio_pdrv_genirq",
295 .id = 3,
296 .dev = {
297 .platform_data = &veu2_platform_data,
298 },
299 .resource = veu2_resources,
300 .num_resources = ARRAY_SIZE(veu2_resources),
301};
302
303/* VEU3 */
304static struct uio_info veu3_platform_data = {
305 .name = "VEU3",
306 .version = "0",
307 .irq = intcs_evt2irq(0x760),
308};
309
310static struct resource veu3_resources[] = {
311 [0] = {
312 .name = "VEU3",
313 .start = 0xfe92c000,
314 .end = 0xfe92c0b7,
315 .flags = IORESOURCE_MEM,
316 },
317};
318
319static struct platform_device veu3_device = {
320 .name = "uio_pdrv_genirq",
321 .id = 4,
322 .dev = {
323 .platform_data = &veu3_platform_data,
324 },
325 .resource = veu3_resources,
326 .num_resources = ARRAY_SIZE(veu3_resources),
327};
328
329/* VEU2H */
330static struct uio_info veu2h_platform_data = {
331 .name = "VEU2H",
332 .version = "0",
333 .irq = intcs_evt2irq(0x520),
334};
335
336static struct resource veu2h_resources[] = {
337 [0] = {
338 .name = "VEU2H",
339 .start = 0xfe93c000,
340 .end = 0xfe93c27b,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device veu2h_device = {
346 .name = "uio_pdrv_genirq",
347 .id = 5,
348 .dev = {
349 .platform_data = &veu2h_platform_data,
350 },
351 .resource = veu2h_resources,
352 .num_resources = ARRAY_SIZE(veu2h_resources),
353};
354
355/* JPU */
356static struct uio_info jpu_platform_data = {
357 .name = "JPU",
358 .version = "0",
359 .irq = intcs_evt2irq(0x560),
360};
361
362static struct resource jpu_resources[] = {
363 [0] = {
364 .name = "JPU",
365 .start = 0xfe980000,
366 .end = 0xfe9902d3,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371static struct platform_device jpu_device = {
372 .name = "uio_pdrv_genirq",
373 .id = 6,
374 .dev = {
375 .platform_data = &jpu_platform_data,
376 },
377 .resource = jpu_resources,
378 .num_resources = ARRAY_SIZE(jpu_resources),
379};
380
381/* SPU1 */
382static struct uio_info spu1_platform_data = {
383 .name = "SPU1",
384 .version = "0",
385 .irq = evt2irq(0xfc0),
386};
387
388static struct resource spu1_resources[] = {
389 [0] = {
390 .name = "SPU1",
391 .start = 0xfe300000,
392 .end = 0xfe3fffff,
393 .flags = IORESOURCE_MEM,
394 },
395};
396
397static struct platform_device spu1_device = {
398 .name = "uio_pdrv_genirq",
399 .id = 7,
400 .dev = {
401 .platform_data = &spu1_platform_data,
402 },
403 .resource = spu1_resources,
404 .num_resources = ARRAY_SIZE(spu1_resources),
405};
406
407static struct platform_device *sh7367_early_devices[] __initdata = {
408 &scif0_device,
409 &scif1_device,
410 &scif2_device,
411 &scif3_device,
412 &scif4_device,
413 &scif5_device,
414 &scif6_device,
415 &cmt10_device,
416};
417
418static struct platform_device *sh7367_devices[] __initdata = {
419 &vpu_device,
420 &veu0_device,
421 &veu1_device,
422 &veu2_device,
423 &veu3_device,
424 &veu2h_device,
425 &jpu_device,
426 &spu1_device,
427};
428
429void __init sh7367_add_standard_devices(void)
430{
431 platform_add_devices(sh7367_early_devices,
432 ARRAY_SIZE(sh7367_early_devices));
433
434 platform_add_devices(sh7367_devices,
435 ARRAY_SIZE(sh7367_devices));
436}
437
438#define SYMSTPCR2 0xe6158048
439#define SYMSTPCR2_CMT1 (1 << 29)
440
441void __init sh7367_add_early_devices(void)
442{
443 /* enable clock to CMT1 */
444 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
445
446 early_platform_add_devices(sh7367_early_devices,
447 ARRAY_SIZE(sh7367_early_devices));
448}
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
new file mode 100644
index 00000000000..bb405b8e459
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -0,0 +1,469 @@
1/*
2 * sh7377 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_intc.h>
31#include <linux/sh_timer.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35
36/* SCIFA0 */
37static struct plat_sci_port scif0_platform_data = {
38 .mapbase = 0xe6c40000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE,
41 .scbrr_algo_id = SCBRR_ALGO_4,
42 .type = PORT_SCIFA,
43 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
44 evt2irq(0xc00), evt2irq(0xc00) },
45};
46
47static struct platform_device scif0_device = {
48 .name = "sh-sci",
49 .id = 0,
50 .dev = {
51 .platform_data = &scif0_platform_data,
52 },
53};
54
55/* SCIFA1 */
56static struct plat_sci_port scif1_platform_data = {
57 .mapbase = 0xe6c50000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_RE | SCSCR_TE,
60 .scbrr_algo_id = SCBRR_ALGO_4,
61 .type = PORT_SCIFA,
62 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
63 evt2irq(0xc20), evt2irq(0xc20) },
64};
65
66static struct platform_device scif1_device = {
67 .name = "sh-sci",
68 .id = 1,
69 .dev = {
70 .platform_data = &scif1_platform_data,
71 },
72};
73
74/* SCIFA2 */
75static struct plat_sci_port scif2_platform_data = {
76 .mapbase = 0xe6c60000,
77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE,
79 .scbrr_algo_id = SCBRR_ALGO_4,
80 .type = PORT_SCIFA,
81 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
82 evt2irq(0xc40), evt2irq(0xc40) },
83};
84
85static struct platform_device scif2_device = {
86 .name = "sh-sci",
87 .id = 2,
88 .dev = {
89 .platform_data = &scif2_platform_data,
90 },
91};
92
93/* SCIFA3 */
94static struct plat_sci_port scif3_platform_data = {
95 .mapbase = 0xe6c70000,
96 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE,
98 .scbrr_algo_id = SCBRR_ALGO_4,
99 .type = PORT_SCIFA,
100 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
101 evt2irq(0xc60), evt2irq(0xc60) },
102};
103
104static struct platform_device scif3_device = {
105 .name = "sh-sci",
106 .id = 3,
107 .dev = {
108 .platform_data = &scif3_platform_data,
109 },
110};
111
112/* SCIFA4 */
113static struct plat_sci_port scif4_platform_data = {
114 .mapbase = 0xe6c80000,
115 .flags = UPF_BOOT_AUTOCONF,
116 .scscr = SCSCR_RE | SCSCR_TE,
117 .scbrr_algo_id = SCBRR_ALGO_4,
118 .type = PORT_SCIFA,
119 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
120 evt2irq(0xd20), evt2irq(0xd20) },
121};
122
123static struct platform_device scif4_device = {
124 .name = "sh-sci",
125 .id = 4,
126 .dev = {
127 .platform_data = &scif4_platform_data,
128 },
129};
130
131/* SCIFA5 */
132static struct plat_sci_port scif5_platform_data = {
133 .mapbase = 0xe6cb0000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE,
136 .scbrr_algo_id = SCBRR_ALGO_4,
137 .type = PORT_SCIFA,
138 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
139 evt2irq(0xd40), evt2irq(0xd40) },
140};
141
142static struct platform_device scif5_device = {
143 .name = "sh-sci",
144 .id = 5,
145 .dev = {
146 .platform_data = &scif5_platform_data,
147 },
148};
149
150/* SCIFA6 */
151static struct plat_sci_port scif6_platform_data = {
152 .mapbase = 0xe6cc0000,
153 .flags = UPF_BOOT_AUTOCONF,
154 .scscr = SCSCR_RE | SCSCR_TE,
155 .scbrr_algo_id = SCBRR_ALGO_4,
156 .type = PORT_SCIFA,
157 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
158 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
159};
160
161static struct platform_device scif6_device = {
162 .name = "sh-sci",
163 .id = 6,
164 .dev = {
165 .platform_data = &scif6_platform_data,
166 },
167};
168
169/* SCIFB */
170static struct plat_sci_port scif7_platform_data = {
171 .mapbase = 0xe6c30000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFB,
176 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
177 evt2irq(0xd60), evt2irq(0xd60) },
178};
179
180static struct platform_device scif7_device = {
181 .name = "sh-sci",
182 .id = 7,
183 .dev = {
184 .platform_data = &scif7_platform_data,
185 },
186};
187
188static struct sh_timer_config cmt10_platform_data = {
189 .name = "CMT10",
190 .channel_offset = 0x10,
191 .timer_bit = 0,
192 .clockevent_rating = 125,
193 .clocksource_rating = 125,
194};
195
196static struct resource cmt10_resources[] = {
197 [0] = {
198 .name = "CMT10",
199 .start = 0xe6138010,
200 .end = 0xe613801b,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = evt2irq(0xb00), /* CMT1_CMT10 */
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
209static struct platform_device cmt10_device = {
210 .name = "sh_cmt",
211 .id = 10,
212 .dev = {
213 .platform_data = &cmt10_platform_data,
214 },
215 .resource = cmt10_resources,
216 .num_resources = ARRAY_SIZE(cmt10_resources),
217};
218
219/* VPU */
220static struct uio_info vpu_platform_data = {
221 .name = "VPU5HG",
222 .version = "0",
223 .irq = intcs_evt2irq(0x980),
224};
225
226static struct resource vpu_resources[] = {
227 [0] = {
228 .name = "VPU",
229 .start = 0xfe900000,
230 .end = 0xfe900157,
231 .flags = IORESOURCE_MEM,
232 },
233};
234
235static struct platform_device vpu_device = {
236 .name = "uio_pdrv_genirq",
237 .id = 0,
238 .dev = {
239 .platform_data = &vpu_platform_data,
240 },
241 .resource = vpu_resources,
242 .num_resources = ARRAY_SIZE(vpu_resources),
243};
244
245/* VEU0 */
246static struct uio_info veu0_platform_data = {
247 .name = "VEU0",
248 .version = "0",
249 .irq = intcs_evt2irq(0x700),
250};
251
252static struct resource veu0_resources[] = {
253 [0] = {
254 .name = "VEU0",
255 .start = 0xfe920000,
256 .end = 0xfe9200cb,
257 .flags = IORESOURCE_MEM,
258 },
259};
260
261static struct platform_device veu0_device = {
262 .name = "uio_pdrv_genirq",
263 .id = 1,
264 .dev = {
265 .platform_data = &veu0_platform_data,
266 },
267 .resource = veu0_resources,
268 .num_resources = ARRAY_SIZE(veu0_resources),
269};
270
271/* VEU1 */
272static struct uio_info veu1_platform_data = {
273 .name = "VEU1",
274 .version = "0",
275 .irq = intcs_evt2irq(0x720),
276};
277
278static struct resource veu1_resources[] = {
279 [0] = {
280 .name = "VEU1",
281 .start = 0xfe924000,
282 .end = 0xfe9240cb,
283 .flags = IORESOURCE_MEM,
284 },
285};
286
287static struct platform_device veu1_device = {
288 .name = "uio_pdrv_genirq",
289 .id = 2,
290 .dev = {
291 .platform_data = &veu1_platform_data,
292 },
293 .resource = veu1_resources,
294 .num_resources = ARRAY_SIZE(veu1_resources),
295};
296
297/* VEU2 */
298static struct uio_info veu2_platform_data = {
299 .name = "VEU2",
300 .version = "0",
301 .irq = intcs_evt2irq(0x740),
302};
303
304static struct resource veu2_resources[] = {
305 [0] = {
306 .name = "VEU2",
307 .start = 0xfe928000,
308 .end = 0xfe928307,
309 .flags = IORESOURCE_MEM,
310 },
311};
312
313static struct platform_device veu2_device = {
314 .name = "uio_pdrv_genirq",
315 .id = 3,
316 .dev = {
317 .platform_data = &veu2_platform_data,
318 },
319 .resource = veu2_resources,
320 .num_resources = ARRAY_SIZE(veu2_resources),
321};
322
323/* VEU3 */
324static struct uio_info veu3_platform_data = {
325 .name = "VEU3",
326 .version = "0",
327 .irq = intcs_evt2irq(0x760),
328};
329
330static struct resource veu3_resources[] = {
331 [0] = {
332 .name = "VEU3",
333 .start = 0xfe92c000,
334 .end = 0xfe92c307,
335 .flags = IORESOURCE_MEM,
336 },
337};
338
339static struct platform_device veu3_device = {
340 .name = "uio_pdrv_genirq",
341 .id = 4,
342 .dev = {
343 .platform_data = &veu3_platform_data,
344 },
345 .resource = veu3_resources,
346 .num_resources = ARRAY_SIZE(veu3_resources),
347};
348
349/* JPU */
350static struct uio_info jpu_platform_data = {
351 .name = "JPU",
352 .version = "0",
353 .irq = intcs_evt2irq(0x560),
354};
355
356static struct resource jpu_resources[] = {
357 [0] = {
358 .name = "JPU",
359 .start = 0xfe980000,
360 .end = 0xfe9902d3,
361 .flags = IORESOURCE_MEM,
362 },
363};
364
365static struct platform_device jpu_device = {
366 .name = "uio_pdrv_genirq",
367 .id = 5,
368 .dev = {
369 .platform_data = &jpu_platform_data,
370 },
371 .resource = jpu_resources,
372 .num_resources = ARRAY_SIZE(jpu_resources),
373};
374
375/* SPU2DSP0 */
376static struct uio_info spu0_platform_data = {
377 .name = "SPU2DSP0",
378 .version = "0",
379 .irq = evt2irq(0x1800),
380};
381
382static struct resource spu0_resources[] = {
383 [0] = {
384 .name = "SPU2DSP0",
385 .start = 0xfe200000,
386 .end = 0xfe2fffff,
387 .flags = IORESOURCE_MEM,
388 },
389};
390
391static struct platform_device spu0_device = {
392 .name = "uio_pdrv_genirq",
393 .id = 6,
394 .dev = {
395 .platform_data = &spu0_platform_data,
396 },
397 .resource = spu0_resources,
398 .num_resources = ARRAY_SIZE(spu0_resources),
399};
400
401/* SPU2DSP1 */
402static struct uio_info spu1_platform_data = {
403 .name = "SPU2DSP1",
404 .version = "0",
405 .irq = evt2irq(0x1820),
406};
407
408static struct resource spu1_resources[] = {
409 [0] = {
410 .name = "SPU2DSP1",
411 .start = 0xfe300000,
412 .end = 0xfe3fffff,
413 .flags = IORESOURCE_MEM,
414 },
415};
416
417static struct platform_device spu1_device = {
418 .name = "uio_pdrv_genirq",
419 .id = 7,
420 .dev = {
421 .platform_data = &spu1_platform_data,
422 },
423 .resource = spu1_resources,
424 .num_resources = ARRAY_SIZE(spu1_resources),
425};
426
427static struct platform_device *sh7377_early_devices[] __initdata = {
428 &scif0_device,
429 &scif1_device,
430 &scif2_device,
431 &scif3_device,
432 &scif4_device,
433 &scif5_device,
434 &scif6_device,
435 &scif7_device,
436 &cmt10_device,
437};
438
439static struct platform_device *sh7377_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &jpu_device,
446 &spu0_device,
447 &spu1_device,
448};
449
450void __init sh7377_add_standard_devices(void)
451{
452 platform_add_devices(sh7377_early_devices,
453 ARRAY_SIZE(sh7377_early_devices));
454
455 platform_add_devices(sh7377_devices,
456 ARRAY_SIZE(sh7377_devices));
457}
458
459#define SMSTPCR3 0xe615013c
460#define SMSTPCR3_CMT1 (1 << 29)
461
462void __init sh7377_add_early_devices(void)
463{
464 /* enable clock to CMT1 */
465 __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
466
467 early_platform_add_devices(sh7377_early_devices,
468 ARRAY_SIZE(sh7377_early_devices));
469}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 11:16:40 -0400