diff options
Diffstat (limited to 'arch/arm/mach-s5pv310/mach-smdkv310.c')
-rw-r--r-- | arch/arm/mach-s5pv310/mach-smdkv310.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index d5eb607763f..e4a826ac3c1 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
21 | 21 | ||
22 | #include <plat/regs-serial.h> | 22 | #include <plat/regs-serial.h> |
23 | #include <plat/regs-srom.h> | ||
23 | #include <plat/s5pv310.h> | 24 | #include <plat/s5pv310.h> |
24 | #include <plat/cpu.h> | 25 | #include <plat/cpu.h> |
25 | #include <plat/devs.h> | 26 | #include <plat/devs.h> |
@@ -27,7 +28,6 @@ | |||
27 | #include <plat/iic.h> | 28 | #include <plat/iic.h> |
28 | 29 | ||
29 | #include <mach/map.h> | 30 | #include <mach/map.h> |
30 | #include <mach/regs-srom.h> | ||
31 | 31 | ||
32 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 32 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
33 | #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 33 | #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
@@ -163,23 +163,22 @@ static void __init smdkv310_smsc911x_init(void) | |||
163 | u32 cs1; | 163 | u32 cs1; |
164 | 164 | ||
165 | /* configure nCS1 width to 16 bits */ | 165 | /* configure nCS1 width to 16 bits */ |
166 | cs1 = __raw_readl(S5PV310_SROM_BW) & | 166 | cs1 = __raw_readl(S5P_SROM_BW) & |
167 | ~(S5PV310_SROM_BW__CS_MASK << | 167 | ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); |
168 | S5PV310_SROM_BW__NCS1__SHIFT); | 168 | cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | |
169 | cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | | 169 | (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | |
170 | (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | | 170 | (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << |
171 | (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << | 171 | S5P_SROM_BW__NCS1__SHIFT; |
172 | S5PV310_SROM_BW__NCS1__SHIFT; | 172 | __raw_writel(cs1, S5P_SROM_BW); |
173 | __raw_writel(cs1, S5PV310_SROM_BW); | ||
174 | 173 | ||
175 | /* set timing for nCS1 suitable for ethernet chip */ | 174 | /* set timing for nCS1 suitable for ethernet chip */ |
176 | __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | | 175 | __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | |
177 | (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | | 176 | (0x9 << S5P_SROM_BCX__TACP__SHIFT) | |
178 | (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | | 177 | (0xc << S5P_SROM_BCX__TCAH__SHIFT) | |
179 | (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | | 178 | (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | |
180 | (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | | 179 | (0x6 << S5P_SROM_BCX__TACC__SHIFT) | |
181 | (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | | 180 | (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | |
182 | (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); | 181 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); |
183 | } | 182 | } |
184 | 183 | ||
185 | static void __init smdkv310_map_io(void) | 184 | static void __init smdkv310_map_io(void) |