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-rw-r--r--arch/arm/mach-s5pv210/clock.c327
1 files changed, 202 insertions, 125 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a69e9..11db6c0fb66 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -29,7 +29,8 @@
29#include <plat/pll.h> 29#include <plat/pll.h>
30#include <plat/s5p-clock.h> 30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h> 31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h> 32
33#include "common.h"
33 34
34static unsigned long xtal; 35static unsigned long xtal;
35 36
@@ -399,30 +400,6 @@ static struct clk init_clocks_off[] = {
399 .enable = s5pv210_clk_ip1_ctrl, 400 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25), 401 .ctrlbit = (1<<25),
401 }, { 402 }, {
402 .name = "hsmmc",
403 .devname = "s3c-sdhci.0",
404 .parent = &clk_hclk_psys.clk,
405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
409 .devname = "s3c-sdhci.1",
410 .parent = &clk_hclk_psys.clk,
411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.2",
416 .parent = &clk_hclk_psys.clk,
417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
421 .devname = "s3c-sdhci.3",
422 .parent = &clk_hclk_psys.clk,
423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer", 403 .name = "systimer",
427 .parent = &clk_pclk_psys.clk, 404 .parent = &clk_pclk_psys.clk,
428 .enable = s5pv210_clk_ip3_ctrl, 405 .enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +536,38 @@ static struct clk init_clocks[] = {
559 }, 536 },
560}; 537};
561 538
539static struct clk clk_hsmmc0 = {
540 .name = "hsmmc",
541 .devname = "s3c-sdhci.0",
542 .parent = &clk_hclk_psys.clk,
543 .enable = s5pv210_clk_ip2_ctrl,
544 .ctrlbit = (1<<16),
545};
546
547static struct clk clk_hsmmc1 = {
548 .name = "hsmmc",
549 .devname = "s3c-sdhci.1",
550 .parent = &clk_hclk_psys.clk,
551 .enable = s5pv210_clk_ip2_ctrl,
552 .ctrlbit = (1<<17),
553};
554
555static struct clk clk_hsmmc2 = {
556 .name = "hsmmc",
557 .devname = "s3c-sdhci.2",
558 .parent = &clk_hclk_psys.clk,
559 .enable = s5pv210_clk_ip2_ctrl,
560 .ctrlbit = (1<<18),
561};
562
563static struct clk clk_hsmmc3 = {
564 .name = "hsmmc",
565 .devname = "s3c-sdhci.3",
566 .parent = &clk_hclk_psys.clk,
567 .enable = s5pv210_clk_ip2_ctrl,
568 .ctrlbit = (1<<19),
569};
570
562static struct clk *clkset_uart_list[] = { 571static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk, 572 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk, 573 [7] = &clk_mout_epll.clk,
@@ -809,46 +818,6 @@ static struct clksrc_clk clksrcs[] = {
809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, 818 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
810 }, { 819 }, {
811 .clk = { 820 .clk = {
812 .name = "uclk1",
813 .devname = "s5pv210-uart.0",
814 .enable = s5pv210_clk_mask0_ctrl,
815 .ctrlbit = (1 << 12),
816 },
817 .sources = &clkset_uart,
818 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
820 }, {
821 .clk = {
822 .name = "uclk1",
823 .devname = "s5pv210-uart.1",
824 .enable = s5pv210_clk_mask0_ctrl,
825 .ctrlbit = (1 << 13),
826 },
827 .sources = &clkset_uart,
828 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
830 }, {
831 .clk = {
832 .name = "uclk1",
833 .devname = "s5pv210-uart.2",
834 .enable = s5pv210_clk_mask0_ctrl,
835 .ctrlbit = (1 << 14),
836 },
837 .sources = &clkset_uart,
838 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
839 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
840 }, {
841 .clk = {
842 .name = "uclk1",
843 .devname = "s5pv210-uart.3",
844 .enable = s5pv210_clk_mask0_ctrl,
845 .ctrlbit = (1 << 15),
846 },
847 .sources = &clkset_uart,
848 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
850 }, {
851 .clk = {
852 .name = "sclk_fimc", 821 .name = "sclk_fimc",
853 .devname = "s5pv210-fimc.0", 822 .devname = "s5pv210-fimc.0",
854 .enable = s5pv210_clk_mask1_ctrl, 823 .enable = s5pv210_clk_mask1_ctrl,
@@ -906,46 +875,6 @@ static struct clksrc_clk clksrcs[] = {
906 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 875 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
907 }, { 876 }, {
908 .clk = { 877 .clk = {
909 .name = "sclk_mmc",
910 .devname = "s3c-sdhci.0",
911 .enable = s5pv210_clk_mask0_ctrl,
912 .ctrlbit = (1 << 8),
913 },
914 .sources = &clkset_group2,
915 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
916 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
917 }, {
918 .clk = {
919 .name = "sclk_mmc",
920 .devname = "s3c-sdhci.1",
921 .enable = s5pv210_clk_mask0_ctrl,
922 .ctrlbit = (1 << 9),
923 },
924 .sources = &clkset_group2,
925 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
926 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
927 }, {
928 .clk = {
929 .name = "sclk_mmc",
930 .devname = "s3c-sdhci.2",
931 .enable = s5pv210_clk_mask0_ctrl,
932 .ctrlbit = (1 << 10),
933 },
934 .sources = &clkset_group2,
935 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
936 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
937 }, {
938 .clk = {
939 .name = "sclk_mmc",
940 .devname = "s3c-sdhci.3",
941 .enable = s5pv210_clk_mask0_ctrl,
942 .ctrlbit = (1 << 11),
943 },
944 .sources = &clkset_group2,
945 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
946 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_mfc", 878 .name = "sclk_mfc",
950 .devname = "s5p-mfc", 879 .devname = "s5p-mfc",
951 .enable = s5pv210_clk_ip0_ctrl, 880 .enable = s5pv210_clk_ip0_ctrl,
@@ -983,26 +912,6 @@ static struct clksrc_clk clksrcs[] = {
983 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 912 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
984 }, { 913 }, {
985 .clk = { 914 .clk = {
986 .name = "sclk_spi",
987 .devname = "s3c64xx-spi.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 16),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
994 }, {
995 .clk = {
996 .name = "sclk_spi",
997 .devname = "s3c64xx-spi.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 17),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1004 }, {
1005 .clk = {
1006 .name = "sclk_pwi", 915 .name = "sclk_pwi",
1007 .enable = s5pv210_clk_mask0_ctrl, 916 .enable = s5pv210_clk_mask0_ctrl,
1008 .ctrlbit = (1 << 29), 917 .ctrlbit = (1 << 29),
@@ -1022,6 +931,147 @@ static struct clksrc_clk clksrcs[] = {
1022 }, 931 },
1023}; 932};
1024 933
934static struct clksrc_clk clk_sclk_uart0 = {
935 .clk = {
936 .name = "uclk1",
937 .devname = "s5pv210-uart.0",
938 .enable = s5pv210_clk_mask0_ctrl,
939 .ctrlbit = (1 << 12),
940 },
941 .sources = &clkset_uart,
942 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
943 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
944};
945
946static struct clksrc_clk clk_sclk_uart1 = {
947 .clk = {
948 .name = "uclk1",
949 .devname = "s5pv210-uart.1",
950 .enable = s5pv210_clk_mask0_ctrl,
951 .ctrlbit = (1 << 13),
952 },
953 .sources = &clkset_uart,
954 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
955 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
956};
957
958static struct clksrc_clk clk_sclk_uart2 = {
959 .clk = {
960 .name = "uclk1",
961 .devname = "s5pv210-uart.2",
962 .enable = s5pv210_clk_mask0_ctrl,
963 .ctrlbit = (1 << 14),
964 },
965 .sources = &clkset_uart,
966 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
967 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
968};
969
970static struct clksrc_clk clk_sclk_uart3 = {
971 .clk = {
972 .name = "uclk1",
973 .devname = "s5pv210-uart.3",
974 .enable = s5pv210_clk_mask0_ctrl,
975 .ctrlbit = (1 << 15),
976 },
977 .sources = &clkset_uart,
978 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
979 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
980};
981
982static struct clksrc_clk clk_sclk_mmc0 = {
983 .clk = {
984 .name = "sclk_mmc",
985 .devname = "s3c-sdhci.0",
986 .enable = s5pv210_clk_mask0_ctrl,
987 .ctrlbit = (1 << 8),
988 },
989 .sources = &clkset_group2,
990 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
991 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
992};
993
994static struct clksrc_clk clk_sclk_mmc1 = {
995 .clk = {
996 .name = "sclk_mmc",
997 .devname = "s3c-sdhci.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 9),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1004};
1005
1006static struct clksrc_clk clk_sclk_mmc2 = {
1007 .clk = {
1008 .name = "sclk_mmc",
1009 .devname = "s3c-sdhci.2",
1010 .enable = s5pv210_clk_mask0_ctrl,
1011 .ctrlbit = (1 << 10),
1012 },
1013 .sources = &clkset_group2,
1014 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1015 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1016};
1017
1018static struct clksrc_clk clk_sclk_mmc3 = {
1019 .clk = {
1020 .name = "sclk_mmc",
1021 .devname = "s3c-sdhci.3",
1022 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 11),
1024 },
1025 .sources = &clkset_group2,
1026 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1027 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1028};
1029
1030static struct clksrc_clk clk_sclk_spi0 = {
1031 .clk = {
1032 .name = "sclk_spi",
1033 .devname = "s3c64xx-spi.0",
1034 .enable = s5pv210_clk_mask0_ctrl,
1035 .ctrlbit = (1 << 16),
1036 },
1037 .sources = &clkset_group2,
1038 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1039 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1040 };
1041
1042static struct clksrc_clk clk_sclk_spi1 = {
1043 .clk = {
1044 .name = "sclk_spi",
1045 .devname = "s3c64xx-spi.1",
1046 .enable = s5pv210_clk_mask0_ctrl,
1047 .ctrlbit = (1 << 17),
1048 },
1049 .sources = &clkset_group2,
1050 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1051 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1052 };
1053
1054
1055static struct clksrc_clk *clksrc_cdev[] = {
1056 &clk_sclk_uart0,
1057 &clk_sclk_uart1,
1058 &clk_sclk_uart2,
1059 &clk_sclk_uart3,
1060 &clk_sclk_mmc0,
1061 &clk_sclk_mmc1,
1062 &clk_sclk_mmc2,
1063 &clk_sclk_mmc3,
1064 &clk_sclk_spi0,
1065 &clk_sclk_spi1,
1066};
1067
1068static struct clk *clk_cdev[] = {
1069 &clk_hsmmc0,
1070 &clk_hsmmc1,
1071 &clk_hsmmc2,
1072 &clk_hsmmc3,
1073};
1074
1025/* Clock initialisation code */ 1075/* Clock initialisation code */
1026static struct clksrc_clk *sysclks[] = { 1076static struct clksrc_clk *sysclks[] = {
1027 &clk_mout_apll, 1077 &clk_mout_apll,
@@ -1261,6 +1311,25 @@ static struct clk *clks[] __initdata = {
1261 &clk_pcmcdclk2, 1311 &clk_pcmcdclk2,
1262}; 1312};
1263 1313
1314static struct clk_lookup s5pv210_clk_lookup[] = {
1315 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1316 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1317 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1318 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1319 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1328 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1329 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1330 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1331};
1332
1264void __init s5pv210_register_clocks(void) 1333void __init s5pv210_register_clocks(void)
1265{ 1334{
1266 int ptr; 1335 int ptr;
@@ -1273,11 +1342,19 @@ void __init s5pv210_register_clocks(void)
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1342 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1); 1343 s3c_register_clksrc(sclk_tv[ptr], 1);
1275 1344
1345 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1346 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1347
1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1348 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1349 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1278 1350
1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1351 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1352 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1353 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1354
1355 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1356 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1357 s3c_disable_clocks(clk_cdev[ptr], 1);
1281 1358
1282 s3c24xx_register_clock(&dummy_apb_pclk); 1359 s3c24xx_register_clock(&dummy_apb_pclk);
1283 s3c_pwmclk_init(); 1360 s3c_pwmclk_init();
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 04:54:17 -0500