diff options
Diffstat (limited to 'arch/arm/mach-s5pc100/mach-smdkc100.c')
| -rw-r--r-- | arch/arm/mach-s5pc100/mach-smdkc100.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 83a5d648a98..a63c8a46571 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
| @@ -49,16 +49,16 @@ | |||
| 49 | #include <plat/ts.h> | 49 | #include <plat/ts.h> |
| 50 | 50 | ||
| 51 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 51 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 52 | #define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 52 | #define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 53 | S3C2410_UCON_RXILEVEL | \ | 53 | S3C2410_UCON_RXILEVEL | \ |
| 54 | S3C2410_UCON_TXIRQMODE | \ | 54 | S3C2410_UCON_TXIRQMODE | \ |
| 55 | S3C2410_UCON_RXIRQMODE | \ | 55 | S3C2410_UCON_RXIRQMODE | \ |
| 56 | S3C2410_UCON_RXFIFO_TOI | \ | 56 | S3C2410_UCON_RXFIFO_TOI | \ |
| 57 | S3C2443_UCON_RXERR_IRQEN) | 57 | S3C2443_UCON_RXERR_IRQEN) |
| 58 | 58 | ||
| 59 | #define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 | 59 | #define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8 |
| 60 | 60 | ||
| 61 | #define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | 61 | #define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
| 62 | S3C2440_UFCON_RXTRIG8 | \ | 62 | S3C2440_UFCON_RXTRIG8 | \ |
| 63 | S3C2440_UFCON_TXTRIG16) | 63 | S3C2440_UFCON_TXTRIG16) |
| 64 | 64 | ||
| @@ -66,30 +66,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | |||
| 66 | [0] = { | 66 | [0] = { |
| 67 | .hwport = 0, | 67 | .hwport = 0, |
| 68 | .flags = 0, | 68 | .flags = 0, |
| 69 | .ucon = S5PC100_UCON_DEFAULT, | 69 | .ucon = SMDKC100_UCON_DEFAULT, |
| 70 | .ulcon = S5PC100_ULCON_DEFAULT, | 70 | .ulcon = SMDKC100_ULCON_DEFAULT, |
| 71 | .ufcon = S5PC100_UFCON_DEFAULT, | 71 | .ufcon = SMDKC100_UFCON_DEFAULT, |
| 72 | }, | 72 | }, |
| 73 | [1] = { | 73 | [1] = { |
| 74 | .hwport = 1, | 74 | .hwport = 1, |
| 75 | .flags = 0, | 75 | .flags = 0, |
| 76 | .ucon = S5PC100_UCON_DEFAULT, | 76 | .ucon = SMDKC100_UCON_DEFAULT, |
| 77 | .ulcon = S5PC100_ULCON_DEFAULT, | 77 | .ulcon = SMDKC100_ULCON_DEFAULT, |
| 78 | .ufcon = S5PC100_UFCON_DEFAULT, | 78 | .ufcon = SMDKC100_UFCON_DEFAULT, |
| 79 | }, | 79 | }, |
| 80 | [2] = { | 80 | [2] = { |
| 81 | .hwport = 2, | 81 | .hwport = 2, |
| 82 | .flags = 0, | 82 | .flags = 0, |
| 83 | .ucon = S5PC100_UCON_DEFAULT, | 83 | .ucon = SMDKC100_UCON_DEFAULT, |
| 84 | .ulcon = S5PC100_ULCON_DEFAULT, | 84 | .ulcon = SMDKC100_ULCON_DEFAULT, |
| 85 | .ufcon = S5PC100_UFCON_DEFAULT, | 85 | .ufcon = SMDKC100_UFCON_DEFAULT, |
| 86 | }, | 86 | }, |
| 87 | [3] = { | 87 | [3] = { |
| 88 | .hwport = 3, | 88 | .hwport = 3, |
| 89 | .flags = 0, | 89 | .flags = 0, |
| 90 | .ucon = S5PC100_UCON_DEFAULT, | 90 | .ucon = SMDKC100_UCON_DEFAULT, |
| 91 | .ulcon = S5PC100_ULCON_DEFAULT, | 91 | .ulcon = SMDKC100_ULCON_DEFAULT, |
| 92 | .ufcon = S5PC100_UFCON_DEFAULT, | 92 | .ufcon = SMDKC100_UFCON_DEFAULT, |
| 93 | }, | 93 | }, |
| 94 | }; | 94 | }; |
| 95 | 95 | ||