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-rw-r--r--arch/arm/mach-s5p64x0/cpu.c215
1 files changed, 0 insertions, 215 deletions
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
deleted file mode 100644
index ecab40cf19a..00000000000
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/cpu.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23#include <linux/dma-mapping.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28#include <asm/proc-fns.h>
29#include <asm/irq.h>
30
31#include <mach/hardware.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34
35#include <plat/regs-serial.h>
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/s5p6440.h>
40#include <plat/s5p6450.h>
41#include <plat/adc-core.h>
42#include <plat/fb-core.h>
43
44/* Initial IO mappings */
45
46static struct map_desc s5p64x0_iodesc[] __initdata = {
47 {
48 .virtual = (unsigned long)S5P_VA_GPIO,
49 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
50 .length = SZ_4K,
51 .type = MT_DEVICE,
52 }, {
53 .virtual = (unsigned long)VA_VIC0,
54 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
55 .length = SZ_16K,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = (unsigned long)VA_VIC1,
59 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
60 .length = SZ_16K,
61 .type = MT_DEVICE,
62 },
63};
64
65static struct map_desc s5p6440_iodesc[] __initdata = {
66 {
67 .virtual = (unsigned long)S3C_VA_UART,
68 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
69 .length = SZ_4K,
70 .type = MT_DEVICE,
71 },
72};
73
74static struct map_desc s5p6450_iodesc[] __initdata = {
75 {
76 .virtual = (unsigned long)S3C_VA_UART,
77 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
78 .length = SZ_512K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
82 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
83 .length = SZ_4K,
84 .type = MT_DEVICE,
85 },
86};
87
88static void s5p64x0_idle(void)
89{
90 unsigned long val;
91
92 if (!need_resched()) {
93 val = __raw_readl(S5P64X0_PWR_CFG);
94 val &= ~(0x3 << 5);
95 val |= (0x1 << 5);
96 __raw_writel(val, S5P64X0_PWR_CFG);
97
98 cpu_do_idle();
99 }
100 local_irq_enable();
101}
102
103/*
104 * s5p64x0_map_io
105 *
106 * register the standard CPU IO areas
107 */
108
109void __init s5p6440_map_io(void)
110{
111 /* initialize any device information early */
112 s3c_adc_setname("s3c64xx-adc");
113 s3c_fb_setname("s5p64x0-fb");
114
115 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
116 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
117 init_consistent_dma_size(SZ_8M);
118}
119
120void __init s5p6450_map_io(void)
121{
122 /* initialize any device information early */
123 s3c_adc_setname("s3c64xx-adc");
124 s3c_fb_setname("s5p64x0-fb");
125
126 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
127 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
128 init_consistent_dma_size(SZ_8M);
129}
130
131/*
132 * s5p64x0_init_clocks
133 *
134 * register and setup the CPU clocks
135 */
136
137void __init s5p6440_init_clocks(int xtal)
138{
139 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
140
141 s3c24xx_register_baseclocks(xtal);
142 s5p_register_clocks(xtal);
143 s5p6440_register_clocks();
144 s5p6440_setup_clocks();
145}
146
147void __init s5p6450_init_clocks(int xtal)
148{
149 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
150
151 s3c24xx_register_baseclocks(xtal);
152 s5p_register_clocks(xtal);
153 s5p6450_register_clocks();
154 s5p6450_setup_clocks();
155}
156
157/*
158 * s5p64x0_init_irq
159 *
160 * register the CPU interrupts
161 */
162
163void __init s5p6440_init_irq(void)
164{
165 /* S5P6440 supports 2 VIC */
166 u32 vic[2];
167
168 /*
169 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
170 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
171 */
172 vic[0] = 0xff800ae7;
173 vic[1] = 0xffbf23e5;
174
175 s5p_init_irq(vic, ARRAY_SIZE(vic));
176}
177
178void __init s5p6450_init_irq(void)
179{
180 /* S5P6450 supports only 2 VIC */
181 u32 vic[2];
182
183 /*
184 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
185 * VIC1 is missing IRQ VIC1[12, 14, 23]
186 */
187 vic[0] = 0xff9f1fff;
188 vic[1] = 0xff7fafff;
189
190 s5p_init_irq(vic, ARRAY_SIZE(vic));
191}
192
193struct sysdev_class s5p64x0_sysclass = {
194 .name = "s5p64x0-core",
195};
196
197static struct sys_device s5p64x0_sysdev = {
198 .cls = &s5p64x0_sysclass,
199};
200
201static int __init s5p64x0_core_init(void)
202{
203 return sysdev_class_register(&s5p64x0_sysclass);
204}
205core_initcall(s5p64x0_core_init);
206
207int __init s5p64x0_init(void)
208{
209 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
210
211 /* set idle function */
212 pm_idle = s5p64x0_idle;
213
214 return sysdev_register(&s5p64x0_sysdev);
215}
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