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Diffstat (limited to 'arch/arm/mach-s5p6442/dev-audio.c')
-rw-r--r--arch/arm/mach-s5p6442/dev-audio.c30
1 files changed, 10 insertions, 20 deletions
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
index 7a4e34720b7..3462197ff35 100644
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ b/arch/arm/mach-s5p6442/dev-audio.c
@@ -21,22 +21,16 @@
21 21
22static int s5p6442_cfg_i2s(struct platform_device *pdev) 22static int s5p6442_cfg_i2s(struct platform_device *pdev)
23{ 23{
24 unsigned int base;
25
24 /* configure GPIO for i2s port */ 26 /* configure GPIO for i2s port */
25 switch (pdev->id) { 27 switch (pdev->id) {
26 case 1: 28 case 1:
27 s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2)); 29 base = S5P6442_GPC1(0);
28 s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
29 s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
30 s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
31 s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
32 break; 30 break;
33 31
34 case -1: 32 case -1:
35 s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2)); 33 base = S5P6442_GPC0(0);
36 s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
37 s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
38 s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
39 s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
40 break; 34 break;
41 35
42 default: 36 default:
@@ -44,6 +38,7 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
44 return -EINVAL; 38 return -EINVAL;
45 } 39 }
46 40
41 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
47 return 0; 42 return 0;
48} 43}
49 44
@@ -111,21 +106,15 @@ struct platform_device s5p6442_device_iis1 = {
111 106
112static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev) 107static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
113{ 108{
109 unsigned int base;
110
114 switch (pdev->id) { 111 switch (pdev->id) {
115 case 0: 112 case 0:
116 s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3)); 113 base = S5P6442_GPC0(0);
117 s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
118 s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
119 s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
120 s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
121 break; 114 break;
122 115
123 case 1: 116 case 1:
124 s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3)); 117 base = S5P6442_GPC1(0);
125 s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
126 s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
127 s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
128 s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
129 break; 118 break;
130 119
131 default: 120 default:
@@ -133,6 +122,7 @@ static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
133 return -EINVAL; 122 return -EINVAL;
134 } 123 }
135 124
125 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
136 return 0; 126 return 0;
137} 127}
138 128