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-rw-r--r--arch/arm/mach-s3c2440/clock.c149
-rw-r--r--arch/arm/mach-s3c2440/dma.c211
-rw-r--r--arch/arm/mach-s3c2440/include/mach/gta02.h84
-rw-r--r--arch/arm/mach-s3c2440/irq.c126
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c506
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c241
-rw-r--r--arch/arm/mach-s3c2440/mach-gta02.c603
-rw-r--r--arch/arm/mach-s3c2440/mach-mini2440.c684
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c159
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris-dvs.c194
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c455
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c834
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c227
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c184
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c75
-rw-r--r--arch/arm/mach-s3c2440/s3c2442.c187
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-clock.c138
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c138
-rw-r--r--arch/arm/mach-s3c2440/s3c244x.c196
19 files changed, 5391 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
new file mode 100644
index 00000000000..f9e6bdaf41d
--- /dev/null
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -0,0 +1,149 @@
1/* linux/arch/arm/mach-s3c2440/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36#include <linux/io.h>
37
38#include <mach/hardware.h>
39#include <linux/atomic.h>
40#include <asm/irq.h>
41
42#include <mach/regs-clock.h>
43
44#include <plat/clock.h>
45#include <plat/cpu.h>
46
47/* S3C2440 extended clock support */
48
49static unsigned long s3c2440_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 /* note, we remove the +/- 1 calculations for the divisor */
59
60 div = (parent_rate / rate) / 2;
61
62 if (div < 1)
63 div = 1;
64 else if (div > 16)
65 div = 16;
66
67 return parent_rate / (div * 2);
68}
69
70static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
71{
72 unsigned long parent_rate = clk_get_rate(clk->parent);
73 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
74
75 rate = s3c2440_camif_upll_round(clk, rate);
76
77 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
78
79 if (rate != parent_rate) {
80 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
81 camdivn |= (((parent_rate / rate) / 2) - 1);
82 }
83
84 __raw_writel(camdivn, S3C2440_CAMDIVN);
85
86 return 0;
87}
88
89/* Extra S3C2440 clocks */
90
91static struct clk s3c2440_clk_cam = {
92 .name = "camif",
93 .enable = s3c2410_clkcon_enable,
94 .ctrlbit = S3C2440_CLKCON_CAMERA,
95};
96
97static struct clk s3c2440_clk_cam_upll = {
98 .name = "camif-upll",
99 .ops = &(struct clk_ops) {
100 .set_rate = s3c2440_camif_upll_setrate,
101 .round_rate = s3c2440_camif_upll_round,
102 },
103};
104
105static struct clk s3c2440_clk_ac97 = {
106 .name = "ac97",
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2440_CLKCON_CAMERA,
109};
110
111static int s3c2440_clk_add(struct sys_device *sysdev)
112{
113 struct clk *clock_upll;
114 struct clk *clock_h;
115 struct clk *clock_p;
116
117 clock_p = clk_get(NULL, "pclk");
118 clock_h = clk_get(NULL, "hclk");
119 clock_upll = clk_get(NULL, "upll");
120
121 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
122 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
123 return -EINVAL;
124 }
125
126 s3c2440_clk_cam.parent = clock_h;
127 s3c2440_clk_ac97.parent = clock_p;
128 s3c2440_clk_cam_upll.parent = clock_upll;
129
130 s3c24xx_register_clock(&s3c2440_clk_ac97);
131 s3c24xx_register_clock(&s3c2440_clk_cam);
132 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
133
134 clk_disable(&s3c2440_clk_ac97);
135 clk_disable(&s3c2440_clk_cam);
136
137 return 0;
138}
139
140static struct sysdev_driver s3c2440_clk_driver = {
141 .add = s3c2440_clk_add,
142};
143
144static __init int s3c24xx_clk_driver(void)
145{
146 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
147}
148
149arch_initcall(s3c24xx_clk_driver);
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
new file mode 100644
index 00000000000..3b0529f54e9
--- /dev/null
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -0,0 +1,211 @@
1/* linux/arch/arm/mach-s3c2440/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <mach/map.h>
21#include <mach/dma.h>
22
23#include <plat/dma-s3c24xx.h>
24#include <plat/cpu.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
37 [DMACH_XD0] = {
38 .name = "xdreq0",
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 },
41 [DMACH_XD1] = {
42 .name = "xdreq1",
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 },
45 [DMACH_SDI] = {
46 .name = "sdi",
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
51 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
53 },
54 [DMACH_SPI0] = {
55 .name = "spi0",
56 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
57 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
58 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
59 },
60 [DMACH_SPI1] = {
61 .name = "spi1",
62 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
63 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
65 },
66 [DMACH_UART0] = {
67 .name = "uart0",
68 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
69 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
70 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
71 },
72 [DMACH_UART1] = {
73 .name = "uart1",
74 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
75 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
77 },
78 [DMACH_UART2] = {
79 .name = "uart2",
80 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
81 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
83 },
84 [DMACH_TIMER] = {
85 .name = "timer",
86 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
87 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
88 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
89 },
90 [DMACH_I2S_IN] = {
91 .name = "i2s-sdi",
92 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
94 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
95 },
96 [DMACH_I2S_OUT] = {
97 .name = "i2s-sdo",
98 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
99 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
100 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
101 },
102 [DMACH_PCM_IN] = {
103 .name = "pcm-in",
104 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
105 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
106 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
107 },
108 [DMACH_PCM_OUT] = {
109 .name = "pcm-out",
110 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
111 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
112 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
113 },
114 [DMACH_MIC_IN] = {
115 .name = "mic-in",
116 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
117 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
118 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
119 },
120 [DMACH_USB_EP1] = {
121 .name = "usb-ep1",
122 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
123 },
124 [DMACH_USB_EP2] = {
125 .name = "usb-ep2",
126 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
127 },
128 [DMACH_USB_EP3] = {
129 .name = "usb-ep3",
130 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
131 },
132 [DMACH_USB_EP4] = {
133 .name = "usb-ep4",
134 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
135 },
136};
137
138static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
139 struct s3c24xx_dma_map *map)
140{
141 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
142}
143
144static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
145 .select = s3c2440_dma_select,
146 .dcon_mask = 7 << 24,
147 .map = s3c2440_dma_mappings,
148 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
149};
150
151static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
152 .channels = {
153 [DMACH_SDI] = {
154 .list = {
155 [0] = 3 | DMA_CH_VALID,
156 [1] = 2 | DMA_CH_VALID,
157 [2] = 1 | DMA_CH_VALID,
158 [3] = 0 | DMA_CH_VALID,
159 },
160 },
161 [DMACH_I2S_IN] = {
162 .list = {
163 [0] = 1 | DMA_CH_VALID,
164 [1] = 2 | DMA_CH_VALID,
165 },
166 },
167 [DMACH_I2S_OUT] = {
168 .list = {
169 [0] = 2 | DMA_CH_VALID,
170 [1] = 1 | DMA_CH_VALID,
171 },
172 },
173 [DMACH_PCM_IN] = {
174 .list = {
175 [0] = 2 | DMA_CH_VALID,
176 [1] = 1 | DMA_CH_VALID,
177 },
178 },
179 [DMACH_PCM_OUT] = {
180 .list = {
181 [0] = 1 | DMA_CH_VALID,
182 [1] = 3 | DMA_CH_VALID,
183 },
184 },
185 [DMACH_MIC_IN] = {
186 .list = {
187 [0] = 3 | DMA_CH_VALID,
188 [1] = 2 | DMA_CH_VALID,
189 },
190 },
191 },
192};
193
194static int __init s3c2440_dma_add(struct sys_device *sysdev)
195{
196 s3c2410_dma_init();
197 s3c24xx_dma_order_set(&s3c2440_dma_order);
198 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
199}
200
201static struct sysdev_driver s3c2440_dma_driver = {
202 .add = s3c2440_dma_add,
203};
204
205static int __init s3c2440_dma_init(void)
206{
207 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
208}
209
210arch_initcall(s3c2440_dma_init);
211
diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c2440/include/mach/gta02.h
new file mode 100644
index 00000000000..3a56a229cac
--- /dev/null
+++ b/arch/arm/mach-s3c2440/include/mach/gta02.h
@@ -0,0 +1,84 @@
1#ifndef _GTA02_H
2#define _GTA02_H
3
4#include <mach/regs-gpio.h>
5
6/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7#define GTA02v1_SYSTEM_REV 0x00000310
8#define GTA02v2_SYSTEM_REV 0x00000320
9#define GTA02v3_SYSTEM_REV 0x00000330
10#define GTA02v4_SYSTEM_REV 0x00000340
11#define GTA02v5_SYSTEM_REV 0x00000350
12/* since A7 is basically same as A6, we use A6 PCB ID */
13#define GTA02v6_SYSTEM_REV 0x00000360
14
15#define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */
16
17#define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0)
18#define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1)
19#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
20#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3)
21#define GTA02_GPIO_MODEM_RST S3C2410_GPB(5)
22#define GTA02_GPIO_BT_EN S3C2410_GPB(6)
23#define GTA02_GPIO_MODEM_ON S3C2410_GPB(7)
24#define GTA02_GPIO_EXTINT8 S3C2410_GPB(8)
25#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
26
27#define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */
28
29#define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */
30#define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */
31#define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */
32
33#define GTA02_GPIO_nG1_INT S3C2410_GPF(0)
34#define GTA02_GPIO_IO1 S3C2410_GPF(1)
35#define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */
36#define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4)
37#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */
38#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6)
39#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7)
40
41#define GTA02_GPIO_3D_IRQ S3C2410_GPG(4)
42#define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */
43#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */
44#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
45#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
46
47#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
48#define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2)
49#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
50#define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */
51#define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4)
52#define GTA02_GPIO_3D_RESET S3C2410_GPJ(5)
53#define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */
54#define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7)
55#define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8)
56#define GTA02_GPIO_KEEPACT S3C2410_GPJ(8)
57#define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10)
58#define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */
59#define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */
60
61#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
62#define GTA02_IRQ_MODEM IRQ_EINT1
63#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */
64#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
65#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5
66#define GTA02_IRQ_AUX IRQ_EINT6
67#define GTA02_IRQ_nHOLD IRQ_EINT7
68#define GTA02_IRQ_PCF50633 IRQ_EINT9
69#define GTA02_IRQ_3D IRQ_EINT12
70#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */
71#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */
72#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */
73#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */
74
75/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
76#define GTA02_PCB_ID1_0 S3C2410_GPC(13)
77#define GTA02_PCB_ID1_1 S3C2410_GPC(15)
78#define GTA02_PCB_ID1_2 S3C2410_GPD(0)
79#define GTA02_PCB_ID2_0 S3C2410_GPD(3)
80#define GTA02_PCB_ID2_1 S3C2410_GPD(4)
81
82int gta02_get_pcb_revision(void);
83
84#endif /* _GTA02_H */
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
new file mode 100644
index 00000000000..eb1cc0f0705
--- /dev/null
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -0,0 +1,126 @@
1/* linux/arch/arm/mach-s3c2440/irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/sysdev.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* WDT/AC97 */
42
43static void s3c_irq_demux_wdtac97(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 13;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_WDT);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_AC97);
64 }
65 }
66}
67
68
69#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
70
71static void
72s3c_irq_wdtac97_mask(struct irq_data *data)
73{
74 s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
75}
76
77static void
78s3c_irq_wdtac97_unmask(struct irq_data *data)
79{
80 s3c_irqsub_unmask(data->irq, INTMSK_WDT);
81}
82
83static void
84s3c_irq_wdtac97_ack(struct irq_data *data)
85{
86 s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
87}
88
89static struct irq_chip s3c_irq_wdtac97 = {
90 .irq_mask = s3c_irq_wdtac97_mask,
91 .irq_unmask = s3c_irq_wdtac97_unmask,
92 .irq_ack = s3c_irq_wdtac97_ack,
93};
94
95static int s3c2440_irq_add(struct sys_device *sysdev)
96{
97 unsigned int irqno;
98
99 printk("S3C2440: IRQ Support\n");
100
101 /* add new chained handler for wdt, ac7 */
102
103 irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104 handle_level_irq);
105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106
107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108 irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109 handle_level_irq);
110 set_irq_flags(irqno, IRQF_VALID);
111 }
112
113 return 0;
114}
115
116static struct sysdev_driver s3c2440_irq_driver = {
117 .add = s3c2440_irq_add,
118};
119
120static int s3c2440_irq_init(void)
121{
122 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
123}
124
125arch_initcall(s3c2440_irq_init);
126
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
new file mode 100644
index 00000000000..d7086788b1f
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -0,0 +1,506 @@
1/* linux/arch/arm/mach-s3c2440/mach-anubis.c
2 *
3 * Copyright 2003-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/ata_platform.h>
22#include <linux/i2c.h>
23#include <linux/io.h>
24#include <linux/sm501.h>
25#include <linux/sm501-regs.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/anubis-map.h>
32#include <mach/anubis-irq.h>
33#include <mach/anubis-cpld.h>
34
35#include <mach/hardware.h>
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <mach/regs-gpio.h>
41#include <mach/regs-mem.h>
42#include <mach/regs-lcd.h>
43#include <plat/nand.h>
44#include <plat/iic.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h>
50
51#include <net/ax88796.h>
52
53#include <plat/clock.h>
54#include <plat/devs.h>
55#include <plat/cpu.h>
56#include <plat/audio-simtec.h>
57
58#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
59
60static struct map_desc anubis_iodesc[] __initdata = {
61 /* ISA IO areas */
62
63 {
64 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
65 .pfn = __phys_to_pfn(0x0),
66 .length = SZ_4M,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (u32)S3C24XX_VA_ISA_WORD,
70 .pfn = __phys_to_pfn(0x0),
71 .length = SZ_4M,
72 .type = MT_DEVICE,
73 },
74
75 /* we could possibly compress the next set down into a set of smaller tables
76 * pagetables, but that would mean using an L2 section, and it still means
77 * we cannot actually feed the same register to an LDR due to 16K spacing
78 */
79
80 /* CPLD control registers */
81
82 {
83 .virtual = (u32)ANUBIS_VA_CTRL1,
84 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
85 .length = SZ_4K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = (u32)ANUBIS_VA_IDREG,
89 .pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
90 .length = SZ_4K,
91 .type = MT_DEVICE,
92 },
93};
94
95#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
96#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
97#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
98
99static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
100 [0] = {
101 .name = "uclk",
102 .divisor = 1,
103 .min_baud = 0,
104 .max_baud = 0,
105 },
106 [1] = {
107 .name = "pclk",
108 .divisor = 1,
109 .min_baud = 0,
110 .max_baud = 0,
111 }
112};
113
114
115static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
116 [0] = {
117 .hwport = 0,
118 .flags = 0,
119 .ucon = UCON,
120 .ulcon = ULCON,
121 .ufcon = UFCON,
122 .clocks = anubis_serial_clocks,
123 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
124 },
125 [1] = {
126 .hwport = 2,
127 .flags = 0,
128 .ucon = UCON,
129 .ulcon = ULCON,
130 .ufcon = UFCON,
131 .clocks = anubis_serial_clocks,
132 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
133 },
134};
135
136/* NAND Flash on Anubis board */
137
138static int external_map[] = { 2 };
139static int chip0_map[] = { 0 };
140static int chip1_map[] = { 1 };
141
142static struct mtd_partition __initdata anubis_default_nand_part[] = {
143 [0] = {
144 .name = "Boot Agent",
145 .size = SZ_16K,
146 .offset = 0,
147 },
148 [1] = {
149 .name = "/boot",
150 .size = SZ_4M - SZ_16K,
151 .offset = SZ_16K,
152 },
153 [2] = {
154 .name = "user1",
155 .offset = SZ_4M,
156 .size = SZ_32M - SZ_4M,
157 },
158 [3] = {
159 .name = "user2",
160 .offset = SZ_32M,
161 .size = MTDPART_SIZ_FULL,
162 }
163};
164
165static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
166 [0] = {
167 .name = "Boot Agent",
168 .size = SZ_128K,
169 .offset = 0,
170 },
171 [1] = {
172 .name = "/boot",
173 .size = SZ_4M - SZ_128K,
174 .offset = SZ_128K,
175 },
176 [2] = {
177 .name = "user1",
178 .offset = SZ_4M,
179 .size = SZ_32M - SZ_4M,
180 },
181 [3] = {
182 .name = "user2",
183 .offset = SZ_32M,
184 .size = MTDPART_SIZ_FULL,
185 }
186};
187
188/* the Anubis has 3 selectable slots for nand-flash, the two
189 * on-board chip areas, as well as the external slot.
190 *
191 * Note, there is no current hot-plug support for the External
192 * socket.
193*/
194
195static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
196 [1] = {
197 .name = "External",
198 .nr_chips = 1,
199 .nr_map = external_map,
200 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
201 .partitions = anubis_default_nand_part,
202 },
203 [0] = {
204 .name = "chip0",
205 .nr_chips = 1,
206 .nr_map = chip0_map,
207 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
208 .partitions = anubis_default_nand_part,
209 },
210 [2] = {
211 .name = "chip1",
212 .nr_chips = 1,
213 .nr_map = chip1_map,
214 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
215 .partitions = anubis_default_nand_part,
216 },
217};
218
219static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
220{
221 unsigned int tmp;
222
223 slot = set->nr_map[slot] & 3;
224
225 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
226 slot, set, set->nr_map);
227
228 tmp = __raw_readb(ANUBIS_VA_CTRL1);
229 tmp &= ~ANUBIS_CTRL1_NANDSEL;
230 tmp |= slot;
231
232 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
233
234 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
235}
236
237static struct s3c2410_platform_nand __initdata anubis_nand_info = {
238 .tacls = 25,
239 .twrph0 = 55,
240 .twrph1 = 40,
241 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
242 .sets = anubis_nand_sets,
243 .select_chip = anubis_nand_select,
244};
245
246/* IDE channels */
247
248static struct pata_platform_info anubis_ide_platdata = {
249 .ioport_shift = 5,
250};
251
252static struct resource anubis_ide0_resource[] = {
253 {
254 .start = S3C2410_CS3,
255 .end = S3C2410_CS3 + (8*32) - 1,
256 .flags = IORESOURCE_MEM,
257 }, {
258 .start = S3C2410_CS3 + (1<<26) + (6*32),
259 .end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
260 .flags = IORESOURCE_MEM,
261 }, {
262 .start = IRQ_IDE0,
263 .end = IRQ_IDE0,
264 .flags = IORESOURCE_IRQ,
265 },
266};
267
268static struct platform_device anubis_device_ide0 = {
269 .name = "pata_platform",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
272 .resource = anubis_ide0_resource,
273 .dev = {
274 .platform_data = &anubis_ide_platdata,
275 .coherent_dma_mask = ~0,
276 },
277};
278
279static struct resource anubis_ide1_resource[] = {
280 {
281 .start = S3C2410_CS4,
282 .end = S3C2410_CS4 + (8*32) - 1,
283 .flags = IORESOURCE_MEM,
284 }, {
285 .start = S3C2410_CS4 + (1<<26) + (6*32),
286 .end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
287 .flags = IORESOURCE_MEM,
288 }, {
289 .start = IRQ_IDE0,
290 .end = IRQ_IDE0,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device anubis_device_ide1 = {
296 .name = "pata_platform",
297 .id = 1,
298 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
299 .resource = anubis_ide1_resource,
300 .dev = {
301 .platform_data = &anubis_ide_platdata,
302 .coherent_dma_mask = ~0,
303 },
304};
305
306/* Asix AX88796 10/100 ethernet controller */
307
308static struct ax_plat_data anubis_asix_platdata = {
309 .flags = AXFLG_MAC_FROMDEV,
310 .wordlength = 2,
311 .dcr_val = 0x48,
312 .rcr_val = 0x40,
313};
314
315static struct resource anubis_asix_resource[] = {
316 [0] = {
317 .start = S3C2410_CS5,
318 .end = S3C2410_CS5 + (0x20 * 0x20) -1,
319 .flags = IORESOURCE_MEM
320 },
321 [1] = {
322 .start = IRQ_ASIX,
323 .end = IRQ_ASIX,
324 .flags = IORESOURCE_IRQ
325 }
326};
327
328static struct platform_device anubis_device_asix = {
329 .name = "ax88796",
330 .id = 0,
331 .num_resources = ARRAY_SIZE(anubis_asix_resource),
332 .resource = anubis_asix_resource,
333 .dev = {
334 .platform_data = &anubis_asix_platdata,
335 }
336};
337
338/* SM501 */
339
340static struct resource anubis_sm501_resource[] = {
341 [0] = {
342 .start = S3C2410_CS2,
343 .end = S3C2410_CS2 + SZ_8M,
344 .flags = IORESOURCE_MEM,
345 },
346 [1] = {
347 .start = S3C2410_CS2 + SZ_64M - SZ_2M,
348 .end = S3C2410_CS2 + SZ_64M - 1,
349 .flags = IORESOURCE_MEM,
350 },
351 [2] = {
352 .start = IRQ_EINT0,
353 .end = IRQ_EINT0,
354 .flags = IORESOURCE_IRQ,
355 },
356};
357
358static struct sm501_initdata anubis_sm501_initdata = {
359 .gpio_high = {
360 .set = 0x3F000000, /* 24bit panel */
361 .mask = 0x0,
362 },
363 .misc_timing = {
364 .set = 0x010100, /* SDRAM timing */
365 .mask = 0x1F1F00,
366 },
367 .misc_control = {
368 .set = SM501_MISC_PNL_24BIT,
369 .mask = 0,
370 },
371
372 .devices = SM501_USE_GPIO,
373
374 /* set the SDRAM and bus clocks */
375 .mclk = 72 * MHZ,
376 .m1xclk = 144 * MHZ,
377};
378
379static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
380 [0] = {
381 .bus_num = 1,
382 .pin_scl = 44,
383 .pin_sda = 45,
384 },
385 [1] = {
386 .bus_num = 2,
387 .pin_scl = 40,
388 .pin_sda = 41,
389 },
390};
391
392static struct sm501_platdata anubis_sm501_platdata = {
393 .init = &anubis_sm501_initdata,
394 .gpio_base = -1,
395 .gpio_i2c = anubis_sm501_gpio_i2c,
396 .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
397};
398
399static struct platform_device anubis_device_sm501 = {
400 .name = "sm501",
401 .id = 0,
402 .num_resources = ARRAY_SIZE(anubis_sm501_resource),
403 .resource = anubis_sm501_resource,
404 .dev = {
405 .platform_data = &anubis_sm501_platdata,
406 },
407};
408
409/* Standard Anubis devices */
410
411static struct platform_device *anubis_devices[] __initdata = {
412 &s3c_device_ohci,
413 &s3c_device_wdt,
414 &s3c_device_adc,
415 &s3c_device_i2c0,
416 &s3c_device_rtc,
417 &s3c_device_nand,
418 &anubis_device_ide0,
419 &anubis_device_ide1,
420 &anubis_device_asix,
421 &anubis_device_sm501,
422};
423
424static struct clk *anubis_clocks[] __initdata = {
425 &s3c24xx_dclk0,
426 &s3c24xx_dclk1,
427 &s3c24xx_clkout0,
428 &s3c24xx_clkout1,
429 &s3c24xx_uclk,
430};
431
432/* I2C devices. */
433
434static struct i2c_board_info anubis_i2c_devs[] __initdata = {
435 {
436 I2C_BOARD_INFO("tps65011", 0x48),
437 .irq = IRQ_EINT20,
438 }
439};
440
441/* Audio setup */
442static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
443 .have_mic = 1,
444 .have_lout = 1,
445 .output_cdclk = 1,
446 .use_mpllin = 1,
447 .amp_gpio = S3C2410_GPB(2),
448 .amp_gain[0] = S3C2410_GPD(10),
449 .amp_gain[1] = S3C2410_GPD(11),
450};
451
452static void __init anubis_map_io(void)
453{
454 /* initialise the clocks */
455
456 s3c24xx_dclk0.parent = &clk_upll;
457 s3c24xx_dclk0.rate = 12*1000*1000;
458
459 s3c24xx_dclk1.parent = &clk_upll;
460 s3c24xx_dclk1.rate = 24*1000*1000;
461
462 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
463 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
464
465 s3c24xx_uclk.parent = &s3c24xx_clkout1;
466
467 s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
468
469 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
470 s3c24xx_init_clocks(0);
471 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
472
473 /* check for the newer revision boards with large page nand */
474
475 if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
476 printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
477 __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
478 anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
479 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
480 } else {
481 /* ensure that the GPIO is setup */
482 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
483 }
484}
485
486static void __init anubis_init(void)
487{
488 s3c_i2c0_set_platdata(NULL);
489 s3c_nand_set_platdata(&anubis_nand_info);
490 simtec_audio_add(NULL, false, &anubis_audio);
491
492 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
493
494 i2c_register_board_info(0, anubis_i2c_devs,
495 ARRAY_SIZE(anubis_i2c_devs));
496}
497
498
499MACHINE_START(ANUBIS, "Simtec-Anubis")
500 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
501 .boot_params = S3C2410_SDRAM_PA + 0x100,
502 .map_io = anubis_map_io,
503 .init_machine = anubis_init,
504 .init_irq = s3c24xx_init_irq,
505 .timer = &s3c24xx_timer,
506MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
new file mode 100644
index 00000000000..6c98b789b8c
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -0,0 +1,241 @@
1/* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
2 *
3 * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
4 * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
5 * and modifications by SBZ <sbz@spgui.org> and
6 * Weibing <http://weibing.blogbus.com>
7 *
8 * For product information, visit http://www.arm.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/serial_core.h>
23#include <linux/dm9000.h>
24#include <linux/platform_device.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <mach/fb.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h>
37#include <mach/regs-mem.h>
38#include <mach/regs-lcd.h>
39#include <plat/nand.h>
40#include <plat/iic.h>
41
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/partitions.h>
46
47#include <plat/clock.h>
48#include <plat/devs.h>
49#include <plat/cpu.h>
50#include <plat/mci.h>
51
52static struct map_desc at2440evb_iodesc[] __initdata = {
53 /* Nothing here */
54};
55
56#define UCON S3C2410_UCON_DEFAULT
57#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
58#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
59
60static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
61 [0] = {
62 .name = "uclk",
63 .divisor = 1,
64 .min_baud = 0,
65 .max_baud = 0,
66 },
67 [1] = {
68 .name = "pclk",
69 .divisor = 1,
70 .min_baud = 0,
71 .max_baud = 0,
72 }
73};
74
75
76static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
77 [0] = {
78 .hwport = 0,
79 .flags = 0,
80 .ucon = UCON,
81 .ulcon = ULCON,
82 .ufcon = UFCON,
83 .clocks = at2440evb_serial_clocks,
84 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
85 },
86 [1] = {
87 .hwport = 1,
88 .flags = 0,
89 .ucon = UCON,
90 .ulcon = ULCON,
91 .ufcon = UFCON,
92 .clocks = at2440evb_serial_clocks,
93 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
94 },
95};
96
97/* NAND Flash on AT2440EVB board */
98
99static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
100 [0] = {
101 .name = "Boot Agent",
102 .size = SZ_256K,
103 .offset = 0,
104 },
105 [1] = {
106 .name = "Kernel",
107 .size = SZ_2M,
108 .offset = SZ_256K,
109 },
110 [2] = {
111 .name = "Root",
112 .offset = SZ_256K + SZ_2M,
113 .size = MTDPART_SIZ_FULL,
114 },
115};
116
117static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
118 [0] = {
119 .name = "nand",
120 .nr_chips = 1,
121 .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
122 .partitions = at2440evb_default_nand_part,
123 },
124};
125
126static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
127 .tacls = 25,
128 .twrph0 = 55,
129 .twrph1 = 40,
130 .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
131 .sets = at2440evb_nand_sets,
132};
133
134/* DM9000AEP 10/100 ethernet controller */
135
136static struct resource at2440evb_dm9k_resource[] = {
137 [0] = {
138 .start = S3C2410_CS3,
139 .end = S3C2410_CS3 + 3,
140 .flags = IORESOURCE_MEM
141 },
142 [1] = {
143 .start = S3C2410_CS3 + 4,
144 .end = S3C2410_CS3 + 7,
145 .flags = IORESOURCE_MEM
146 },
147 [2] = {
148 .start = IRQ_EINT7,
149 .end = IRQ_EINT7,
150 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
151 }
152};
153
154static struct dm9000_plat_data at2440evb_dm9k_pdata = {
155 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
156};
157
158static struct platform_device at2440evb_device_eth = {
159 .name = "dm9000",
160 .id = -1,
161 .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
162 .resource = at2440evb_dm9k_resource,
163 .dev = {
164 .platform_data = &at2440evb_dm9k_pdata,
165 },
166};
167
168static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
169 .gpio_detect = S3C2410_GPG(10),
170};
171
172/* 7" LCD panel */
173
174static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
175
176 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
177 S3C2410_LCDCON5_INVVLINE |
178 S3C2410_LCDCON5_INVVFRAME |
179 S3C2410_LCDCON5_PWREN |
180 S3C2410_LCDCON5_HWSWP,
181
182 .type = S3C2410_LCDCON1_TFT,
183
184 .width = 800,
185 .height = 480,
186
187 .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
188 .xres = 800,
189 .yres = 480,
190 .bpp = 16,
191 .left_margin = 88,
192 .right_margin = 40,
193 .hsync_len = 128,
194 .upper_margin = 32,
195 .lower_margin = 11,
196 .vsync_len = 2,
197};
198
199static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
200 .displays = &at2440evb_lcd_cfg,
201 .num_displays = 1,
202 .default_display = 0,
203};
204
205static struct platform_device *at2440evb_devices[] __initdata = {
206 &s3c_device_ohci,
207 &s3c_device_wdt,
208 &s3c_device_adc,
209 &s3c_device_i2c0,
210 &s3c_device_rtc,
211 &s3c_device_nand,
212 &s3c_device_sdi,
213 &s3c_device_lcd,
214 &at2440evb_device_eth,
215};
216
217static void __init at2440evb_map_io(void)
218{
219 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
220 s3c24xx_init_clocks(16934400);
221 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
222}
223
224static void __init at2440evb_init(void)
225{
226 s3c24xx_fb_set_platdata(&at2440evb_fb_info);
227 s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
228 s3c_nand_set_platdata(&at2440evb_nand_info);
229 s3c_i2c0_set_platdata(NULL);
230
231 platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
232}
233
234
235MACHINE_START(AT2440EVB, "AT2440EVB")
236 .boot_params = S3C2410_SDRAM_PA + 0x100,
237 .map_io = at2440evb_map_io,
238 .init_machine = at2440evb_init,
239 .init_irq = s3c24xx_init_irq,
240 .timer = &s3c24xx_timer,
241MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
new file mode 100644
index 00000000000..c10ddf4ed7f
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -0,0 +1,603 @@
1/*
2 * linux/arch/arm/mach-s3c2442/mach-gta02.c
3 *
4 * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
5 *
6 * Copyright (C) 2006-2009 by Openmoko, Inc.
7 * Authors: Harald Welte <laforge@openmoko.org>
8 * Andy Green <andy@openmoko.org>
9 * Werner Almesberger <werner@openmoko.org>
10 * All rights reserved.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/interrupt.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/timer.h>
35#include <linux/init.h>
36#include <linux/gpio.h>
37#include <linux/workqueue.h>
38#include <linux/platform_device.h>
39#include <linux/serial_core.h>
40#include <linux/spi/spi.h>
41
42#include <linux/mmc/host.h>
43
44#include <linux/mtd/mtd.h>
45#include <linux/mtd/nand.h>
46#include <linux/mtd/nand_ecc.h>
47#include <linux/mtd/partitions.h>
48#include <linux/mtd/physmap.h>
49#include <linux/io.h>
50
51#include <linux/i2c.h>
52#include <linux/regulator/machine.h>
53
54#include <linux/mfd/pcf50633/core.h>
55#include <linux/mfd/pcf50633/mbc.h>
56#include <linux/mfd/pcf50633/adc.h>
57#include <linux/mfd/pcf50633/gpio.h>
58#include <linux/mfd/pcf50633/pmic.h>
59#include <linux/mfd/pcf50633/backlight.h>
60
61#include <linux/input.h>
62#include <linux/gpio_keys.h>
63
64#include <asm/mach/arch.h>
65#include <asm/mach/map.h>
66#include <asm/mach/irq.h>
67
68#include <asm/irq.h>
69#include <asm/mach-types.h>
70
71#include <mach/regs-irq.h>
72#include <mach/regs-gpio.h>
73#include <mach/regs-gpioj.h>
74#include <mach/fb.h>
75
76#include <mach/spi.h>
77#include <plat/usb-control.h>
78#include <mach/regs-mem.h>
79#include <mach/hardware.h>
80
81#include <mach/gta02.h>
82
83#include <plat/regs-serial.h>
84#include <plat/nand.h>
85#include <plat/devs.h>
86#include <plat/cpu.h>
87#include <plat/pm.h>
88#include <plat/udc.h>
89#include <plat/gpio-cfg.h>
90#include <plat/iic.h>
91#include <plat/ts.h>
92
93
94static struct pcf50633 *gta02_pcf;
95
96/*
97 * This gets called frequently when we paniced.
98 */
99
100static long gta02_panic_blink(int state)
101{
102 long delay = 0;
103 char led;
104
105 led = (state) ? 1 : 0;
106 gpio_direction_output(GTA02_GPIO_AUX_LED, led);
107
108 return delay;
109}
110
111
112static struct map_desc gta02_iodesc[] __initdata = {
113 {
114 .virtual = 0xe0000000,
115 .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000),
116 .length = SZ_1M,
117 .type = MT_DEVICE
118 },
119};
120
121#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN)
122#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
123#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
124
125static struct s3c2410_uartcfg gta02_uartcfgs[] = {
126 [0] = {
127 .hwport = 0,
128 .flags = 0,
129 .ucon = UCON,
130 .ulcon = ULCON,
131 .ufcon = UFCON,
132 },
133 [1] = {
134 .hwport = 1,
135 .flags = 0,
136 .ucon = UCON,
137 .ulcon = ULCON,
138 .ufcon = UFCON,
139 },
140 [2] = {
141 .hwport = 2,
142 .flags = 0,
143 .ucon = UCON,
144 .ulcon = ULCON,
145 .ufcon = UFCON,
146 },
147};
148
149#ifdef CONFIG_CHARGER_PCF50633
150/*
151 * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin.
152 * We use this to recognize that we can pull 1A from the USB socket.
153 *
154 * These constants are the measured pcf50633 ADC levels with the 1A
155 * charger / 48K resistor, and with no pulldown resistor.
156 */
157
158#define ADC_NOM_CHG_DETECT_1A 6
159#define ADC_NOM_CHG_DETECT_USB 43
160
161static void
162gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
163{
164 int ma;
165
166 /* Interpret charger type */
167 if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
168
169 /*
170 * Sanity - stop GPO driving out now that we have a 1A charger
171 * GPO controls USB Host power generation on GTA02
172 */
173 pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
174
175 ma = 1000;
176 } else
177 ma = 100;
178
179 pcf50633_mbc_usb_curlim_set(pcf, ma);
180}
181
182static struct delayed_work gta02_charger_work;
183static int gta02_usb_vbus_draw;
184
185static void gta02_charger_worker(struct work_struct *work)
186{
187 if (gta02_usb_vbus_draw) {
188 pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw);
189 return;
190 }
191
192#ifdef CONFIG_PCF50633_ADC
193 pcf50633_adc_async_read(gta02_pcf,
194 PCF50633_ADCC1_MUX_ADCIN1,
195 PCF50633_ADCC1_AVERAGE_16,
196 gta02_configure_pmu_for_charger,
197 NULL);
198#else
199 /*
200 * If the PCF50633 ADC is disabled we fallback to a
201 * 100mA limit for safety.
202 */
203 pcf50633_mbc_usb_curlim_set(pcf, 100);
204#endif
205}
206
207#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
208
209static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
210{
211 if (irq == PCF50633_IRQ_USBINS) {
212 schedule_delayed_work(&gta02_charger_work,
213 GTA02_CHARGER_CONFIGURE_TIMEOUT);
214
215 return;
216 }
217
218 if (irq == PCF50633_IRQ_USBREM) {
219 cancel_delayed_work_sync(&gta02_charger_work);
220 gta02_usb_vbus_draw = 0;
221 }
222}
223
224static void gta02_udc_vbus_draw(unsigned int ma)
225{
226 if (!gta02_pcf)
227 return;
228
229 gta02_usb_vbus_draw = ma;
230
231 schedule_delayed_work(&gta02_charger_work,
232 GTA02_CHARGER_CONFIGURE_TIMEOUT);
233}
234#else /* !CONFIG_CHARGER_PCF50633 */
235#define gta02_pmu_event_callback NULL
236#define gta02_udc_vbus_draw NULL
237#endif
238
239/*
240 * This is called when pc50633 is probed, unfortunately quite late in the
241 * day since it is an I2C bus device. Here we can belatedly define some
242 * platform devices with the advantage that we can mark the pcf50633 as the
243 * parent. This makes them get suspended and resumed with their parent
244 * the pcf50633 still around.
245 */
246
247static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
248
249
250static char *gta02_batteries[] = {
251 "battery",
252};
253
254static struct pcf50633_bl_platform_data gta02_backlight_data = {
255 .default_brightness = 0x3f,
256 .default_brightness_limit = 0,
257 .ramp_time = 5,
258};
259
260struct pcf50633_platform_data gta02_pcf_pdata = {
261 .resumers = {
262 [0] = PCF50633_INT1_USBINS |
263 PCF50633_INT1_USBREM |
264 PCF50633_INT1_ALARM,
265 [1] = PCF50633_INT2_ONKEYF,
266 [2] = PCF50633_INT3_ONKEY1S,
267 [3] = PCF50633_INT4_LOWSYS |
268 PCF50633_INT4_LOWBAT |
269 PCF50633_INT4_HIGHTMP,
270 },
271
272 .batteries = gta02_batteries,
273 .num_batteries = ARRAY_SIZE(gta02_batteries),
274
275 .charger_reference_current_ma = 1000,
276
277 .backlight_data = &gta02_backlight_data,
278
279 .reg_init_data = {
280 [PCF50633_REGULATOR_AUTO] = {
281 .constraints = {
282 .min_uV = 3300000,
283 .max_uV = 3300000,
284 .valid_modes_mask = REGULATOR_MODE_NORMAL,
285 .always_on = 1,
286 .apply_uV = 1,
287 },
288 },
289 [PCF50633_REGULATOR_DOWN1] = {
290 .constraints = {
291 .min_uV = 1300000,
292 .max_uV = 1600000,
293 .valid_modes_mask = REGULATOR_MODE_NORMAL,
294 .always_on = 1,
295 .apply_uV = 1,
296 },
297 },
298 [PCF50633_REGULATOR_DOWN2] = {
299 .constraints = {
300 .min_uV = 1800000,
301 .max_uV = 1800000,
302 .valid_modes_mask = REGULATOR_MODE_NORMAL,
303 .apply_uV = 1,
304 .always_on = 1,
305 },
306 },
307 [PCF50633_REGULATOR_HCLDO] = {
308 .constraints = {
309 .min_uV = 2000000,
310 .max_uV = 3300000,
311 .valid_modes_mask = REGULATOR_MODE_NORMAL,
312 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
313 REGULATOR_CHANGE_STATUS,
314 },
315 },
316 [PCF50633_REGULATOR_LDO1] = {
317 .constraints = {
318 .min_uV = 3300000,
319 .max_uV = 3300000,
320 .valid_modes_mask = REGULATOR_MODE_NORMAL,
321 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
322 .apply_uV = 1,
323 },
324 },
325 [PCF50633_REGULATOR_LDO2] = {
326 .constraints = {
327 .min_uV = 3300000,
328 .max_uV = 3300000,
329 .valid_modes_mask = REGULATOR_MODE_NORMAL,
330 .apply_uV = 1,
331 },
332 },
333 [PCF50633_REGULATOR_LDO3] = {
334 .constraints = {
335 .min_uV = 3000000,
336 .max_uV = 3000000,
337 .valid_modes_mask = REGULATOR_MODE_NORMAL,
338 .apply_uV = 1,
339 },
340 },
341 [PCF50633_REGULATOR_LDO4] = {
342 .constraints = {
343 .min_uV = 3200000,
344 .max_uV = 3200000,
345 .valid_modes_mask = REGULATOR_MODE_NORMAL,
346 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
347 .apply_uV = 1,
348 },
349 },
350 [PCF50633_REGULATOR_LDO5] = {
351 .constraints = {
352 .min_uV = 3000000,
353 .max_uV = 3000000,
354 .valid_modes_mask = REGULATOR_MODE_NORMAL,
355 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
356 .apply_uV = 1,
357 },
358 },
359 [PCF50633_REGULATOR_LDO6] = {
360 .constraints = {
361 .min_uV = 3000000,
362 .max_uV = 3000000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL,
364 },
365 },
366 [PCF50633_REGULATOR_MEMLDO] = {
367 .constraints = {
368 .min_uV = 1800000,
369 .max_uV = 1800000,
370 .valid_modes_mask = REGULATOR_MODE_NORMAL,
371 },
372 },
373
374 },
375 .probe_done = gta02_pmu_attach_child_devices,
376 .mbc_event_callback = gta02_pmu_event_callback,
377};
378
379
380/* NOR Flash. */
381
382#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */
383#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */
384
385static struct physmap_flash_data gta02_nor_flash_data = {
386 .width = 2,
387};
388
389static struct resource gta02_nor_flash_resource = {
390 .start = GTA02_FLASH_BASE,
391 .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
392 .flags = IORESOURCE_MEM,
393};
394
395static struct platform_device gta02_nor_flash = {
396 .name = "physmap-flash",
397 .id = 0,
398 .dev = {
399 .platform_data = &gta02_nor_flash_data,
400 },
401 .resource = &gta02_nor_flash_resource,
402 .num_resources = 1,
403};
404
405
406struct platform_device s3c24xx_pwm_device = {
407 .name = "s3c24xx_pwm",
408 .num_resources = 0,
409};
410
411static struct platform_device gta02_dfbmcs320_device = {
412 .name = "dfbmcs320",
413};
414
415static struct i2c_board_info gta02_i2c_devs[] __initdata = {
416 {
417 I2C_BOARD_INFO("pcf50633", 0x73),
418 .irq = GTA02_IRQ_PCF50633,
419 .platform_data = &gta02_pcf_pdata,
420 },
421 {
422 I2C_BOARD_INFO("wm8753", 0x1a),
423 },
424};
425
426static struct s3c2410_nand_set __initdata gta02_nand_sets[] = {
427 [0] = {
428 /*
429 * This name is also hard-coded in the boot loaders, so
430 * changing it would would require all users to upgrade
431 * their boot loaders, some of which are stored in a NOR
432 * that is considered to be immutable.
433 */
434 .name = "neo1973-nand",
435 .nr_chips = 1,
436 .flash_bbt = 1,
437 },
438};
439
440/*
441 * Choose a set of timings derived from S3C@2442B MCP54
442 * data sheet (K5D2G13ACM-D075 MCP Memory).
443 */
444
445static struct s3c2410_platform_nand __initdata gta02_nand_info = {
446 .tacls = 0,
447 .twrph0 = 25,
448 .twrph1 = 15,
449 .nr_sets = ARRAY_SIZE(gta02_nand_sets),
450 .sets = gta02_nand_sets,
451};
452
453
454/* Get PMU to set USB current limit accordingly. */
455static struct s3c2410_udc_mach_info gta02_udc_cfg __initdata = {
456 .vbus_draw = gta02_udc_vbus_draw,
457 .pullup_pin = GTA02_GPIO_USB_PULLUP,
458};
459
460/* USB */
461static struct s3c2410_hcd_info gta02_usb_info __initdata = {
462 .port[0] = {
463 .flags = S3C_HCDFLG_USED,
464 },
465 .port[1] = {
466 .flags = 0,
467 },
468};
469
470/* Touchscreen */
471static struct s3c2410_ts_mach_info gta02_ts_info = {
472 .delay = 10000,
473 .presc = 0xff, /* slow as we can go */
474 .oversampling_shift = 2,
475};
476
477/* Buttons */
478static struct gpio_keys_button gta02_buttons[] = {
479 {
480 .gpio = GTA02_GPIO_AUX_KEY,
481 .code = KEY_PHONE,
482 .desc = "Aux",
483 .type = EV_KEY,
484 .debounce_interval = 100,
485 },
486 {
487 .gpio = GTA02_GPIO_HOLD_KEY,
488 .code = KEY_PAUSE,
489 .desc = "Hold",
490 .type = EV_KEY,
491 .debounce_interval = 100,
492 },
493};
494
495static struct gpio_keys_platform_data gta02_buttons_pdata = {
496 .buttons = gta02_buttons,
497 .nbuttons = ARRAY_SIZE(gta02_buttons),
498};
499
500static struct platform_device gta02_buttons_device = {
501 .name = "gpio-keys",
502 .id = -1,
503 .dev = {
504 .platform_data = &gta02_buttons_pdata,
505 },
506};
507
508static void __init gta02_map_io(void)
509{
510 s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
511 s3c24xx_init_clocks(12000000);
512 s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
513}
514
515
516/* These are the guys that don't need to be children of PMU. */
517
518static struct platform_device *gta02_devices[] __initdata = {
519 &s3c_device_ohci,
520 &s3c_device_wdt,
521 &s3c_device_sdi,
522 &s3c_device_usbgadget,
523 &s3c_device_nand,
524 &gta02_nor_flash,
525 &s3c24xx_pwm_device,
526 &s3c_device_iis,
527 &samsung_asoc_dma,
528 &s3c_device_i2c0,
529 &gta02_dfbmcs320_device,
530 &gta02_buttons_device,
531 &s3c_device_adc,
532 &s3c_device_ts,
533};
534
535/* These guys DO need to be children of PMU. */
536
537static struct platform_device *gta02_devices_pmu_children[] = {
538};
539
540
541/*
542 * This is called when pc50633 is probed, quite late in the day since it is an
543 * I2C bus device. Here we can define platform devices with the advantage that
544 * we can mark the pcf50633 as the parent. This makes them get suspended and
545 * resumed with their parent the pcf50633 still around. All devices whose
546 * operation depends on something from pcf50633 must have this relationship
547 * made explicit like this, or suspend and resume will become an unreliable
548 * hellworld.
549 */
550
551static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
552{
553 int n;
554
555 /* Grab a copy of the now probed PMU pointer. */
556 gta02_pcf = pcf;
557
558 for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
559 gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
560
561 platform_add_devices(gta02_devices_pmu_children,
562 ARRAY_SIZE(gta02_devices_pmu_children));
563}
564
565static void gta02_poweroff(void)
566{
567 pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);
568}
569
570static void __init gta02_machine_init(void)
571{
572 /* Set the panic callback to turn AUX LED on or off. */
573 panic_blink = gta02_panic_blink;
574
575 s3c_pm_init();
576
577#ifdef CONFIG_CHARGER_PCF50633
578 INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
579#endif
580
581 s3c24xx_udc_set_platdata(&gta02_udc_cfg);
582 s3c24xx_ts_set_platdata(&gta02_ts_info);
583 s3c_ohci_set_platdata(&gta02_usb_info);
584 s3c_nand_set_platdata(&gta02_nand_info);
585 s3c_i2c0_set_platdata(NULL);
586
587 i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
588
589 platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
590 pm_power_off = gta02_poweroff;
591
592 regulator_has_full_constraints();
593}
594
595
596MACHINE_START(NEO1973_GTA02, "GTA02")
597 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
598 .boot_params = S3C2410_SDRAM_PA + 0x100,
599 .map_io = gta02_map_io,
600 .init_irq = s3c24xx_init_irq,
601 .init_machine = gta02_machine_init,
602 .timer = &s3c24xx_timer,
603MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
new file mode 100644
index 00000000000..fc2dc0b3d4f
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -0,0 +1,684 @@
1/* linux/arch/arm/mach-s3c2440/mach-mini2440.c
2 *
3 * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
4 * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
5 * and modifications by SBZ <sbz@spgui.org> and
6 * Weibing <http://weibing.blogbus.com> and
7 * Michel Pollet <buserror@gmail.com>
8 *
9 * For product information, visit http://code.google.com/p/mini2440/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/gpio.h>
23#include <linux/input.h>
24#include <linux/io.h>
25#include <linux/serial_core.h>
26#include <linux/dm9000.h>
27#include <linux/i2c/at24.h>
28#include <linux/platform_device.h>
29#include <linux/gpio_keys.h>
30#include <linux/i2c.h>
31#include <linux/mmc/host.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include <mach/hardware.h>
37#include <mach/fb.h>
38#include <asm/mach-types.h>
39
40#include <plat/regs-serial.h>
41#include <mach/regs-gpio.h>
42#include <mach/leds-gpio.h>
43#include <mach/regs-mem.h>
44#include <mach/regs-lcd.h>
45#include <mach/irqs.h>
46#include <plat/nand.h>
47#include <plat/iic.h>
48#include <plat/mci.h>
49#include <plat/udc.h>
50
51#include <linux/mtd/mtd.h>
52#include <linux/mtd/nand.h>
53#include <linux/mtd/nand_ecc.h>
54#include <linux/mtd/partitions.h>
55
56#include <plat/gpio-cfg.h>
57#include <plat/clock.h>
58#include <plat/devs.h>
59#include <plat/cpu.h>
60
61#include <sound/s3c24xx_uda134x.h>
62
63#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300)
64
65static struct map_desc mini2440_iodesc[] __initdata = {
66 /* nothing to declare, move along */
67};
68
69#define UCON S3C2410_UCON_DEFAULT
70#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
71#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
72
73
74static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = {
75 [0] = {
76 .hwport = 0,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
81 },
82 [1] = {
83 .hwport = 1,
84 .flags = 0,
85 .ucon = UCON,
86 .ulcon = ULCON,
87 .ufcon = UFCON,
88 },
89 [2] = {
90 .hwport = 2,
91 .flags = 0,
92 .ucon = UCON,
93 .ulcon = ULCON,
94 .ufcon = UFCON,
95 },
96};
97
98/* USB device UDC support */
99
100static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = {
101 .pullup_pin = S3C2410_GPC(5),
102};
103
104
105/* LCD timing and setup */
106
107/*
108 * This macro simplifies the table bellow
109 */
110#define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \
111 _yres,margin_top,margin_bottom,vsync, refresh) \
112 .width = _xres, \
113 .xres = _xres, \
114 .height = _yres, \
115 .yres = _yres, \
116 .left_margin = margin_left, \
117 .right_margin = margin_right, \
118 .upper_margin = margin_top, \
119 .lower_margin = margin_bottom, \
120 .hsync_len = hsync, \
121 .vsync_len = vsync, \
122 .pixclock = ((_clock*100000000000LL) / \
123 ((refresh) * \
124 (hsync + margin_left + _xres + margin_right) * \
125 (vsync + margin_top + _yres + margin_bottom))), \
126 .bpp = 16,\
127 .type = (S3C2410_LCDCON1_TFT16BPP |\
128 S3C2410_LCDCON1_TFT)
129
130static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
131 [0] = { /* mini2440 + 3.5" TFT + touchscreen */
132 _LCD_DECLARE(
133 7, /* The 3.5 is quite fast */
134 240, 21, 38, 6, /* x timing */
135 320, 4, 4, 2, /* y timing */
136 60), /* refresh rate */
137 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
138 S3C2410_LCDCON5_INVVLINE |
139 S3C2410_LCDCON5_INVVFRAME |
140 S3C2410_LCDCON5_INVVDEN |
141 S3C2410_LCDCON5_PWREN),
142 },
143 [1] = { /* mini2440 + 7" TFT + touchscreen */
144 _LCD_DECLARE(
145 10, /* the 7" runs slower */
146 800, 40, 40, 48, /* x timing */
147 480, 29, 3, 3, /* y timing */
148 50), /* refresh rate */
149 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
150 S3C2410_LCDCON5_INVVLINE |
151 S3C2410_LCDCON5_INVVFRAME |
152 S3C2410_LCDCON5_PWREN),
153 },
154 /* The VGA shield can outout at several resolutions. All share
155 * the same timings, however, anything smaller than 1024x768
156 * will only be displayed in the top left corner of a 1024x768
157 * XGA output unless you add optional dip switches to the shield.
158 * Therefore timings for other resolutions have been omitted here.
159 */
160 [2] = {
161 _LCD_DECLARE(
162 10,
163 1024, 1, 2, 2, /* y timing */
164 768, 200, 16, 16, /* x timing */
165 24), /* refresh rate, maximum stable,
166 tested with the FPGA shield */
167 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
168 S3C2410_LCDCON5_HWSWP),
169 },
170};
171
172/* todo - put into gpio header */
173
174#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
175#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
176
177static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
178 .displays = &mini2440_lcd_cfg[0], /* not constant! see init */
179 .num_displays = 1,
180 .default_display = 0,
181
182 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
183 * and disable the pull down resistors on pins we are using for LCD
184 * data. */
185
186 .gpcup = (0xf << 1) | (0x3f << 10),
187
188 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
189 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
190 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
191 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
192 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
193
194 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
195 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
196 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
197 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
198 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
199
200 .gpdup = (0x3f << 2) | (0x3f << 10),
201
202 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
203 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
204 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
205 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
206 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
207 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
208
209 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
210 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
211 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
212 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
213 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
214 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
215};
216
217/* MMC/SD */
218
219static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = {
220 .gpio_detect = S3C2410_GPG(8),
221 .gpio_wprotect = S3C2410_GPH(8),
222 .set_power = NULL,
223 .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34,
224};
225
226/* NAND Flash on MINI2440 board */
227
228static struct mtd_partition mini2440_default_nand_part[] __initdata = {
229 [0] = {
230 .name = "u-boot",
231 .size = SZ_256K,
232 .offset = 0,
233 },
234 [1] = {
235 .name = "u-boot-env",
236 .size = SZ_128K,
237 .offset = SZ_256K,
238 },
239 [2] = {
240 .name = "kernel",
241 /* 5 megabytes, for a kernel with no modules
242 * or a uImage with a ramdisk attached */
243 .size = 0x00500000,
244 .offset = SZ_256K + SZ_128K,
245 },
246 [3] = {
247 .name = "root",
248 .offset = SZ_256K + SZ_128K + 0x00500000,
249 .size = MTDPART_SIZ_FULL,
250 },
251};
252
253static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = {
254 [0] = {
255 .name = "nand",
256 .nr_chips = 1,
257 .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part),
258 .partitions = mini2440_default_nand_part,
259 .flash_bbt = 1, /* we use u-boot to create a BBT */
260 },
261};
262
263static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
264 .tacls = 0,
265 .twrph0 = 25,
266 .twrph1 = 15,
267 .nr_sets = ARRAY_SIZE(mini2440_nand_sets),
268 .sets = mini2440_nand_sets,
269 .ignore_unset_ecc = 1,
270};
271
272/* DM9000AEP 10/100 ethernet controller */
273
274static struct resource mini2440_dm9k_resource[] = {
275 [0] = {
276 .start = MACH_MINI2440_DM9K_BASE,
277 .end = MACH_MINI2440_DM9K_BASE + 3,
278 .flags = IORESOURCE_MEM
279 },
280 [1] = {
281 .start = MACH_MINI2440_DM9K_BASE + 4,
282 .end = MACH_MINI2440_DM9K_BASE + 7,
283 .flags = IORESOURCE_MEM
284 },
285 [2] = {
286 .start = IRQ_EINT7,
287 .end = IRQ_EINT7,
288 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
289 }
290};
291
292/*
293 * The DM9000 has no eeprom, and it's MAC address is set by
294 * the bootloader before starting the kernel.
295 */
296static struct dm9000_plat_data mini2440_dm9k_pdata = {
297 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
298};
299
300static struct platform_device mini2440_device_eth = {
301 .name = "dm9000",
302 .id = -1,
303 .num_resources = ARRAY_SIZE(mini2440_dm9k_resource),
304 .resource = mini2440_dm9k_resource,
305 .dev = {
306 .platform_data = &mini2440_dm9k_pdata,
307 },
308};
309
310/* CON5
311 * +--+ /-----\
312 * | | | |
313 * | | | BAT |
314 * | | \_____/
315 * | |
316 * | | +----+ +----+
317 * | | | K5 | | K1 |
318 * | | +----+ +----+
319 * | | +----+ +----+
320 * | | | K4 | | K2 |
321 * | | +----+ +----+
322 * | | +----+ +----+
323 * | | | K6 | | K3 |
324 * | | +----+ +----+
325 * .....
326 */
327static struct gpio_keys_button mini2440_buttons[] = {
328 {
329 .gpio = S3C2410_GPG(0), /* K1 */
330 .code = KEY_F1,
331 .desc = "Button 1",
332 .active_low = 1,
333 },
334 {
335 .gpio = S3C2410_GPG(3), /* K2 */
336 .code = KEY_F2,
337 .desc = "Button 2",
338 .active_low = 1,
339 },
340 {
341 .gpio = S3C2410_GPG(5), /* K3 */
342 .code = KEY_F3,
343 .desc = "Button 3",
344 .active_low = 1,
345 },
346 {
347 .gpio = S3C2410_GPG(6), /* K4 */
348 .code = KEY_POWER,
349 .desc = "Power",
350 .active_low = 1,
351 },
352 {
353 .gpio = S3C2410_GPG(7), /* K5 */
354 .code = KEY_F5,
355 .desc = "Button 5",
356 .active_low = 1,
357 },
358#if 0
359 /* this pin is also known as TCLK1 and seems to already
360 * marked as "in use" somehow in the kernel -- possibly wrongly */
361 {
362 .gpio = S3C2410_GPG(11), /* K6 */
363 .code = KEY_F6,
364 .desc = "Button 6",
365 .active_low = 1,
366 },
367#endif
368};
369
370static struct gpio_keys_platform_data mini2440_button_data = {
371 .buttons = mini2440_buttons,
372 .nbuttons = ARRAY_SIZE(mini2440_buttons),
373};
374
375static struct platform_device mini2440_button_device = {
376 .name = "gpio-keys",
377 .id = -1,
378 .dev = {
379 .platform_data = &mini2440_button_data,
380 }
381};
382
383/* LEDS */
384
385static struct s3c24xx_led_platdata mini2440_led1_pdata = {
386 .name = "led1",
387 .gpio = S3C2410_GPB(5),
388 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
389 .def_trigger = "heartbeat",
390};
391
392static struct s3c24xx_led_platdata mini2440_led2_pdata = {
393 .name = "led2",
394 .gpio = S3C2410_GPB(6),
395 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
396 .def_trigger = "nand-disk",
397};
398
399static struct s3c24xx_led_platdata mini2440_led3_pdata = {
400 .name = "led3",
401 .gpio = S3C2410_GPB(7),
402 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
403 .def_trigger = "mmc0",
404};
405
406static struct s3c24xx_led_platdata mini2440_led4_pdata = {
407 .name = "led4",
408 .gpio = S3C2410_GPB(8),
409 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
410 .def_trigger = "",
411};
412
413static struct s3c24xx_led_platdata mini2440_led_backlight_pdata = {
414 .name = "backlight",
415 .gpio = S3C2410_GPG(4),
416 .def_trigger = "backlight",
417};
418
419static struct platform_device mini2440_led1 = {
420 .name = "s3c24xx_led",
421 .id = 1,
422 .dev = {
423 .platform_data = &mini2440_led1_pdata,
424 },
425};
426
427static struct platform_device mini2440_led2 = {
428 .name = "s3c24xx_led",
429 .id = 2,
430 .dev = {
431 .platform_data = &mini2440_led2_pdata,
432 },
433};
434
435static struct platform_device mini2440_led3 = {
436 .name = "s3c24xx_led",
437 .id = 3,
438 .dev = {
439 .platform_data = &mini2440_led3_pdata,
440 },
441};
442
443static struct platform_device mini2440_led4 = {
444 .name = "s3c24xx_led",
445 .id = 4,
446 .dev = {
447 .platform_data = &mini2440_led4_pdata,
448 },
449};
450
451static struct platform_device mini2440_led_backlight = {
452 .name = "s3c24xx_led",
453 .id = 5,
454 .dev = {
455 .platform_data = &mini2440_led_backlight_pdata,
456 },
457};
458
459/* AUDIO */
460
461static struct s3c24xx_uda134x_platform_data mini2440_audio_pins = {
462 .l3_clk = S3C2410_GPB(4),
463 .l3_mode = S3C2410_GPB(2),
464 .l3_data = S3C2410_GPB(3),
465 .model = UDA134X_UDA1341
466};
467
468static struct platform_device mini2440_audio = {
469 .name = "s3c24xx_uda134x",
470 .id = 0,
471 .dev = {
472 .platform_data = &mini2440_audio_pins,
473 },
474};
475
476/*
477 * I2C devices
478 */
479static struct at24_platform_data at24c08 = {
480 .byte_len = SZ_8K / 8,
481 .page_size = 16,
482};
483
484static struct i2c_board_info mini2440_i2c_devs[] __initdata = {
485 {
486 I2C_BOARD_INFO("24c08", 0x50),
487 .platform_data = &at24c08,
488 },
489};
490
491static struct platform_device uda1340_codec = {
492 .name = "uda134x-codec",
493 .id = -1,
494};
495
496static struct platform_device *mini2440_devices[] __initdata = {
497 &s3c_device_ohci,
498 &s3c_device_wdt,
499 &s3c_device_i2c0,
500 &s3c_device_rtc,
501 &s3c_device_usbgadget,
502 &mini2440_device_eth,
503 &mini2440_led1,
504 &mini2440_led2,
505 &mini2440_led3,
506 &mini2440_led4,
507 &mini2440_button_device,
508 &s3c_device_nand,
509 &s3c_device_sdi,
510 &s3c_device_iis,
511 &uda1340_codec,
512 &mini2440_audio,
513 &samsung_asoc_dma,
514};
515
516static void __init mini2440_map_io(void)
517{
518 s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
519 s3c24xx_init_clocks(12000000);
520 s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
521}
522
523/*
524 * mini2440_features string
525 *
526 * t = Touchscreen present
527 * b = backlight control
528 * c = camera [TODO]
529 * 0-9 LCD configuration
530 *
531 */
532static char mini2440_features_str[12] __initdata = "0tb";
533
534static int __init mini2440_features_setup(char *str)
535{
536 if (str)
537 strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str));
538 return 1;
539}
540
541__setup("mini2440=", mini2440_features_setup);
542
543#define FEATURE_SCREEN (1 << 0)
544#define FEATURE_BACKLIGHT (1 << 1)
545#define FEATURE_TOUCH (1 << 2)
546#define FEATURE_CAMERA (1 << 3)
547
548struct mini2440_features_t {
549 int count;
550 int done;
551 int lcd_index;
552 struct platform_device *optional[8];
553};
554
555static void __init mini2440_parse_features(
556 struct mini2440_features_t * features,
557 const char * features_str )
558{
559 const char * fp = features_str;
560
561 features->count = 0;
562 features->done = 0;
563 features->lcd_index = -1;
564
565 while (*fp) {
566 char f = *fp++;
567
568 switch (f) {
569 case '0'...'9': /* tft screen */
570 if (features->done & FEATURE_SCREEN) {
571 printk(KERN_INFO "MINI2440: '%c' ignored, "
572 "screen type already set\n", f);
573 } else {
574 int li = f - '0';
575 if (li >= ARRAY_SIZE(mini2440_lcd_cfg))
576 printk(KERN_INFO "MINI2440: "
577 "'%c' out of range LCD mode\n", f);
578 else {
579 features->optional[features->count++] =
580 &s3c_device_lcd;
581 features->lcd_index = li;
582 }
583 }
584 features->done |= FEATURE_SCREEN;
585 break;
586 case 'b':
587 if (features->done & FEATURE_BACKLIGHT)
588 printk(KERN_INFO "MINI2440: '%c' ignored, "
589 "backlight already set\n", f);
590 else {
591 features->optional[features->count++] =
592 &mini2440_led_backlight;
593 }
594 features->done |= FEATURE_BACKLIGHT;
595 break;
596 case 't':
597 printk(KERN_INFO "MINI2440: '%c' ignored, "
598 "touchscreen not compiled in\n", f);
599 break;
600 case 'c':
601 if (features->done & FEATURE_CAMERA)
602 printk(KERN_INFO "MINI2440: '%c' ignored, "
603 "camera already registered\n", f);
604 else
605 features->optional[features->count++] =
606 &s3c_device_camif;
607 features->done |= FEATURE_CAMERA;
608 break;
609 }
610 }
611}
612
613static void __init mini2440_init(void)
614{
615 struct mini2440_features_t features = { 0 };
616 int i;
617
618 printk(KERN_INFO "MINI2440: Option string mini2440=%s\n",
619 mini2440_features_str);
620
621 /* Parse the feature string */
622 mini2440_parse_features(&features, mini2440_features_str);
623
624 /* turn LCD on */
625 s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
626
627 /* Turn the backlight early on */
628 WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
629 gpio_direction_output(S3C2410_GPG(4), 1);
630
631 /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
632 s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
633 s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
634 s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
635
636 /* mark the key as input, without pullups (there is one on the board) */
637 for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
638 s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
639 s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
640 }
641 if (features.lcd_index != -1) {
642 int li;
643
644 mini2440_fb_info.displays =
645 &mini2440_lcd_cfg[features.lcd_index];
646
647 printk(KERN_INFO "MINI2440: LCD");
648 for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++)
649 if (li == features.lcd_index)
650 printk(" [%d:%dx%d]", li,
651 mini2440_lcd_cfg[li].width,
652 mini2440_lcd_cfg[li].height);
653 else
654 printk(" %d:%dx%d", li,
655 mini2440_lcd_cfg[li].width,
656 mini2440_lcd_cfg[li].height);
657 printk("\n");
658 s3c24xx_fb_set_platdata(&mini2440_fb_info);
659 }
660
661 s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
662 s3c24xx_mci_set_platdata(&mini2440_mmc_cfg);
663 s3c_nand_set_platdata(&mini2440_nand_info);
664 s3c_i2c0_set_platdata(NULL);
665
666 i2c_register_board_info(0, mini2440_i2c_devs,
667 ARRAY_SIZE(mini2440_i2c_devs));
668
669 platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices));
670
671 if (features.count) /* the optional features */
672 platform_add_devices(features.optional, features.count);
673
674}
675
676
677MACHINE_START(MINI2440, "MINI2440")
678 /* Maintainer: Michel Pollet <buserror@gmail.com> */
679 .boot_params = S3C2410_SDRAM_PA + 0x100,
680 .map_io = mini2440_map_io,
681 .init_machine = mini2440_init,
682 .init_irq = s3c24xx_init_irq,
683 .timer = &s3c24xx_timer,
684MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
new file mode 100644
index 00000000000..37dd306fb7d
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -0,0 +1,159 @@
1/* linux/arch/arm/mach-s3c2440/mach-nexcoder.c
2 *
3 * Copyright (c) 2004 Nex Vision
4 * Guillaume GOURAT <guillaume.gourat@nexvision.tv>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 15-10-2004 GG Created initial version
12 * 12-03-2005 BJD Updated for release
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
22#include <linux/string.h>
23#include <linux/serial_core.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26
27#include <linux/mtd/map.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include <asm/setup.h>
34#include <mach/hardware.h>
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37
38//#include <asm/debug-ll.h>
39#include <mach/regs-gpio.h>
40#include <plat/regs-serial.h>
41#include <plat/iic.h>
42
43#include <plat/gpio-cfg.h>
44#include <plat/s3c2410.h>
45#include <plat/s3c244x.h>
46#include <plat/clock.h>
47#include <plat/devs.h>
48#include <plat/cpu.h>
49
50static struct map_desc nexcoder_iodesc[] __initdata = {
51 /* nothing here yet */
52};
53
54#define UCON S3C2410_UCON_DEFAULT
55#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
56#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
57
58static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
59 [0] = {
60 .hwport = 0,
61 .flags = 0,
62 .ucon = UCON,
63 .ulcon = ULCON,
64 .ufcon = UFCON,
65 },
66 [1] = {
67 .hwport = 1,
68 .flags = 0,
69 .ucon = UCON,
70 .ulcon = ULCON,
71 .ufcon = UFCON,
72 },
73 [2] = {
74 .hwport = 2,
75 .flags = 0,
76 .ucon = UCON,
77 .ulcon = ULCON,
78 .ufcon = UFCON,
79 }
80};
81
82/* NOR Flash on NexVision NexCoder 2440 board */
83
84static struct resource nexcoder_nor_resource[] = {
85 [0] = {
86 .start = S3C2410_CS0,
87 .end = S3C2410_CS0 + (8*1024*1024) - 1,
88 .flags = IORESOURCE_MEM,
89 }
90};
91
92static struct map_info nexcoder_nor_map = {
93 .bankwidth = 2,
94};
95
96static struct platform_device nexcoder_device_nor = {
97 .name = "mtd-flash",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(nexcoder_nor_resource),
100 .resource = nexcoder_nor_resource,
101 .dev =
102 {
103 .platform_data = &nexcoder_nor_map,
104 }
105};
106
107/* Standard Nexcoder devices */
108
109static struct platform_device *nexcoder_devices[] __initdata = {
110 &s3c_device_ohci,
111 &s3c_device_lcd,
112 &s3c_device_wdt,
113 &s3c_device_i2c0,
114 &s3c_device_iis,
115 &s3c_device_rtc,
116 &s3c_device_camif,
117 &s3c_device_spi0,
118 &s3c_device_spi1,
119 &nexcoder_device_nor,
120};
121
122static void __init nexcoder_sensorboard_init(void)
123{
124 // Initialize SCCB bus
125 s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
126 s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
127 s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
128 s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
129
130 // Power up the sensor board
131 s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
132 s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
133 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
134 s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
135}
136
137static void __init nexcoder_map_io(void)
138{
139 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
140 s3c24xx_init_clocks(0);
141 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
142
143 nexcoder_sensorboard_init();
144}
145
146static void __init nexcoder_init(void)
147{
148 s3c_i2c0_set_platdata(NULL);
149 platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
150};
151
152MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
153 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
154 .boot_params = S3C2410_SDRAM_PA + 0x100,
155 .map_io = nexcoder_map_io,
156 .init_machine = nexcoder_init,
157 .init_irq = s3c24xx_init_irq,
158 .timer = &s3c24xx_timer,
159MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
new file mode 100644
index 00000000000..ad2792dfbee
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
@@ -0,0 +1,194 @@
1/* linux/arch/arm/mach-s3c2440/mach-osiris-dvs.c
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Simtec Osiris Dynamic Voltage Scaling support.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/cpufreq.h>
18#include <linux/gpio.h>
19
20#include <linux/i2c/tps65010.h>
21
22#include <plat/cpu-freq.h>
23
24#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
25
26static bool dvs_en;
27
28static void osiris_dvs_tps_setdvs(bool on)
29{
30 unsigned vregs1 = 0, vdcdc2 = 0;
31
32 if (!on) {
33 vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF;
34 vregs1 = TPS_LDO1_OFF; /* turn off in low-power mode */
35 }
36
37 dvs_en = on;
38 vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V;
39 vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE;
40
41 tps65010_config_vregs1(vregs1);
42 tps65010_config_vdcdc2(vdcdc2);
43}
44
45static bool is_dvs(struct s3c_freq *f)
46{
47 /* at the moment, we assume ARMCLK = HCLK => DVS */
48 return f->armclk == f->hclk;
49}
50
51/* keep track of current state */
52static bool cur_dvs = false;
53
54static int osiris_dvs_notify(struct notifier_block *nb,
55 unsigned long val, void *data)
56{
57 struct cpufreq_freqs *cf = data;
58 struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf);
59 bool old_dvs = is_dvs(&freqs->old);
60 bool new_dvs = is_dvs(&freqs->new);
61 int ret = 0;
62
63 if (!dvs_en)
64 return 0;
65
66 printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__,
67 freqs->old.armclk, freqs->old.hclk,
68 freqs->new.armclk, freqs->new.hclk);
69
70 switch (val) {
71 case CPUFREQ_PRECHANGE:
72 if (old_dvs & !new_dvs ||
73 cur_dvs & !new_dvs) {
74 pr_debug("%s: exiting dvs\n", __func__);
75 cur_dvs = false;
76 gpio_set_value(OSIRIS_GPIO_DVS, 1);
77 }
78 break;
79 case CPUFREQ_POSTCHANGE:
80 if (!old_dvs & new_dvs ||
81 !cur_dvs & new_dvs) {
82 pr_debug("entering dvs\n");
83 cur_dvs = true;
84 gpio_set_value(OSIRIS_GPIO_DVS, 0);
85 }
86 break;
87 }
88
89 return ret;
90}
91
92static struct notifier_block osiris_dvs_nb = {
93 .notifier_call = osiris_dvs_notify,
94};
95
96static int __devinit osiris_dvs_probe(struct platform_device *pdev)
97{
98 int ret;
99
100 dev_info(&pdev->dev, "initialising\n");
101
102 ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs");
103 if (ret) {
104 dev_err(&pdev->dev, "cannot claim gpio\n");
105 goto err_nogpio;
106 }
107
108 /* start with dvs disabled */
109 gpio_direction_output(OSIRIS_GPIO_DVS, 1);
110
111 ret = cpufreq_register_notifier(&osiris_dvs_nb,
112 CPUFREQ_TRANSITION_NOTIFIER);
113 if (ret) {
114 dev_err(&pdev->dev, "failed to register with cpufreq\n");
115 goto err_nofreq;
116 }
117
118 osiris_dvs_tps_setdvs(true);
119
120 return 0;
121
122err_nofreq:
123 gpio_free(OSIRIS_GPIO_DVS);
124
125err_nogpio:
126 return ret;
127}
128
129static int __devexit osiris_dvs_remove(struct platform_device *pdev)
130{
131 dev_info(&pdev->dev, "exiting\n");
132
133 /* disable any current dvs */
134 gpio_set_value(OSIRIS_GPIO_DVS, 1);
135 osiris_dvs_tps_setdvs(false);
136
137 cpufreq_unregister_notifier(&osiris_dvs_nb,
138 CPUFREQ_TRANSITION_NOTIFIER);
139
140 gpio_free(OSIRIS_GPIO_DVS);
141
142 return 0;
143}
144
145/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
146 * out if the configuration isn't set. */
147
148static int osiris_dvs_suspend(struct device *dev)
149{
150 gpio_set_value(OSIRIS_GPIO_DVS, 1);
151 osiris_dvs_tps_setdvs(false);
152 cur_dvs = false;
153
154 return 0;
155}
156
157static int osiris_dvs_resume(struct device *dev)
158{
159 osiris_dvs_tps_setdvs(true);
160 return 0;
161}
162
163static const struct dev_pm_ops osiris_dvs_pm = {
164 .suspend = osiris_dvs_suspend,
165 .resume = osiris_dvs_resume,
166};
167
168static struct platform_driver osiris_dvs_driver = {
169 .probe = osiris_dvs_probe,
170 .remove = __devexit_p(osiris_dvs_remove),
171 .driver = {
172 .name = "osiris-dvs",
173 .owner = THIS_MODULE,
174 .pm = &osiris_dvs_pm,
175 },
176};
177
178static int __init osiris_dvs_init(void)
179{
180 return platform_driver_register(&osiris_dvs_driver);
181}
182
183static void __exit osiris_dvs_exit(void)
184{
185 platform_driver_unregister(&osiris_dvs_driver);
186}
187
188module_init(osiris_dvs_init);
189module_exit(osiris_dvs_exit);
190
191MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
192MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
193MODULE_LICENSE("GPL");
194MODULE_ALIAS("platform:osiris-dvs");
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
new file mode 100644
index 00000000000..d8853639331
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -0,0 +1,455 @@
1/* linux/arch/arm/mach-s3c2440/mach-osiris.c
2 *
3 * Copyright (c) 2005-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/clk.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25
26#include <linux/i2c/tps65010.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/osiris-map.h>
33#include <mach/osiris-cpld.h>
34
35#include <mach/hardware.h>
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/cpu-freq.h>
40#include <plat/regs-serial.h>
41#include <mach/regs-gpio.h>
42#include <mach/regs-mem.h>
43#include <mach/regs-lcd.h>
44#include <plat/nand.h>
45#include <plat/iic.h>
46
47#include <linux/mtd/mtd.h>
48#include <linux/mtd/nand.h>
49#include <linux/mtd/nand_ecc.h>
50#include <linux/mtd/partitions.h>
51
52#include <plat/gpio-cfg.h>
53#include <plat/clock.h>
54#include <plat/devs.h>
55#include <plat/cpu.h>
56
57/* onboard perihperal map */
58
59static struct map_desc osiris_iodesc[] __initdata = {
60 /* ISA IO areas (may be over-written later) */
61
62 {
63 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
64 .pfn = __phys_to_pfn(S3C2410_CS5),
65 .length = SZ_16M,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (u32)S3C24XX_VA_ISA_WORD,
69 .pfn = __phys_to_pfn(S3C2410_CS5),
70 .length = SZ_16M,
71 .type = MT_DEVICE,
72 },
73
74 /* CPLD control registers */
75
76 {
77 .virtual = (u32)OSIRIS_VA_CTRL0,
78 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
79 .length = SZ_16K,
80 .type = MT_DEVICE,
81 }, {
82 .virtual = (u32)OSIRIS_VA_CTRL1,
83 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
84 .length = SZ_16K,
85 .type = MT_DEVICE,
86 }, {
87 .virtual = (u32)OSIRIS_VA_CTRL2,
88 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
89 .length = SZ_16K,
90 .type = MT_DEVICE,
91 }, {
92 .virtual = (u32)OSIRIS_VA_IDREG,
93 .pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
94 .length = SZ_16K,
95 .type = MT_DEVICE,
96 },
97};
98
99#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
100#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
101#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
102
103static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
104 [0] = {
105 .name = "uclk",
106 .divisor = 1,
107 .min_baud = 0,
108 .max_baud = 0,
109 },
110 [1] = {
111 .name = "pclk",
112 .divisor = 1,
113 .min_baud = 0,
114 .max_baud = 0,
115 }
116};
117
118static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
119 [0] = {
120 .hwport = 0,
121 .flags = 0,
122 .ucon = UCON,
123 .ulcon = ULCON,
124 .ufcon = UFCON,
125 .clocks = osiris_serial_clocks,
126 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
127 },
128 [1] = {
129 .hwport = 1,
130 .flags = 0,
131 .ucon = UCON,
132 .ulcon = ULCON,
133 .ufcon = UFCON,
134 .clocks = osiris_serial_clocks,
135 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
136 },
137 [2] = {
138 .hwport = 2,
139 .flags = 0,
140 .ucon = UCON,
141 .ulcon = ULCON,
142 .ufcon = UFCON,
143 .clocks = osiris_serial_clocks,
144 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
145 }
146};
147
148/* NAND Flash on Osiris board */
149
150static int external_map[] = { 2 };
151static int chip0_map[] = { 0 };
152static int chip1_map[] = { 1 };
153
154static struct mtd_partition __initdata osiris_default_nand_part[] = {
155 [0] = {
156 .name = "Boot Agent",
157 .size = SZ_16K,
158 .offset = 0,
159 },
160 [1] = {
161 .name = "/boot",
162 .size = SZ_4M - SZ_16K,
163 .offset = SZ_16K,
164 },
165 [2] = {
166 .name = "user1",
167 .offset = SZ_4M,
168 .size = SZ_32M - SZ_4M,
169 },
170 [3] = {
171 .name = "user2",
172 .offset = SZ_32M,
173 .size = MTDPART_SIZ_FULL,
174 }
175};
176
177static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
178 [0] = {
179 .name = "Boot Agent",
180 .size = SZ_128K,
181 .offset = 0,
182 },
183 [1] = {
184 .name = "/boot",
185 .size = SZ_4M - SZ_128K,
186 .offset = SZ_128K,
187 },
188 [2] = {
189 .name = "user1",
190 .offset = SZ_4M,
191 .size = SZ_32M - SZ_4M,
192 },
193 [3] = {
194 .name = "user2",
195 .offset = SZ_32M,
196 .size = MTDPART_SIZ_FULL,
197 }
198};
199
200/* the Osiris has 3 selectable slots for nand-flash, the two
201 * on-board chip areas, as well as the external slot.
202 *
203 * Note, there is no current hot-plug support for the External
204 * socket.
205*/
206
207static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
208 [1] = {
209 .name = "External",
210 .nr_chips = 1,
211 .nr_map = external_map,
212 .options = NAND_SCAN_SILENT_NODEV,
213 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
214 .partitions = osiris_default_nand_part,
215 },
216 [0] = {
217 .name = "chip0",
218 .nr_chips = 1,
219 .nr_map = chip0_map,
220 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
221 .partitions = osiris_default_nand_part,
222 },
223 [2] = {
224 .name = "chip1",
225 .nr_chips = 1,
226 .nr_map = chip1_map,
227 .options = NAND_SCAN_SILENT_NODEV,
228 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
229 .partitions = osiris_default_nand_part,
230 },
231};
232
233static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
234{
235 unsigned int tmp;
236
237 slot = set->nr_map[slot] & 3;
238
239 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
240 slot, set, set->nr_map);
241
242 tmp = __raw_readb(OSIRIS_VA_CTRL0);
243 tmp &= ~OSIRIS_CTRL0_NANDSEL;
244 tmp |= slot;
245
246 pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
247
248 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
249}
250
251static struct s3c2410_platform_nand __initdata osiris_nand_info = {
252 .tacls = 25,
253 .twrph0 = 60,
254 .twrph1 = 60,
255 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
256 .sets = osiris_nand_sets,
257 .select_chip = osiris_nand_select,
258};
259
260/* PCMCIA control and configuration */
261
262static struct resource osiris_pcmcia_resource[] = {
263 [0] = {
264 .start = 0x0f000000,
265 .end = 0x0f100000,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = 0x0c000000,
270 .end = 0x0c100000,
271 .flags = IORESOURCE_MEM,
272 }
273};
274
275static struct platform_device osiris_pcmcia = {
276 .name = "osiris-pcmcia",
277 .id = -1,
278 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
279 .resource = osiris_pcmcia_resource,
280};
281
282/* Osiris power management device */
283
284#ifdef CONFIG_PM
285static unsigned char pm_osiris_ctrl0;
286
287static int osiris_pm_suspend(void)
288{
289 unsigned int tmp;
290
291 pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
292 tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
293
294 /* ensure correct NAND slot is selected on resume */
295 if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
296 tmp |= 2;
297
298 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
299
300 /* ensure that an nRESET is not generated on resume. */
301 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
302 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
303
304 return 0;
305}
306
307static void osiris_pm_resume(void)
308{
309 if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
310 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
311
312 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
313
314 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
315}
316
317#else
318#define osiris_pm_suspend NULL
319#define osiris_pm_resume NULL
320#endif
321
322static struct syscore_ops osiris_pm_syscore_ops = {
323 .suspend = osiris_pm_suspend,
324 .resume = osiris_pm_resume,
325};
326
327/* Link for DVS driver to TPS65011 */
328
329static void osiris_tps_release(struct device *dev)
330{
331 /* static device, do not need to release anything */
332}
333
334static struct platform_device osiris_tps_device = {
335 .name = "osiris-dvs",
336 .id = -1,
337 .dev.release = osiris_tps_release,
338};
339
340static int osiris_tps_setup(struct i2c_client *client, void *context)
341{
342 osiris_tps_device.dev.parent = &client->dev;
343 return platform_device_register(&osiris_tps_device);
344}
345
346static int osiris_tps_remove(struct i2c_client *client, void *context)
347{
348 platform_device_unregister(&osiris_tps_device);
349 return 0;
350}
351
352static struct tps65010_board osiris_tps_board = {
353 .base = -1, /* GPIO can go anywhere at the moment */
354 .setup = osiris_tps_setup,
355 .teardown = osiris_tps_remove,
356};
357
358/* I2C devices fitted. */
359
360static struct i2c_board_info osiris_i2c_devs[] __initdata = {
361 {
362 I2C_BOARD_INFO("tps65011", 0x48),
363 .irq = IRQ_EINT20,
364 .platform_data = &osiris_tps_board,
365 },
366};
367
368/* Standard Osiris devices */
369
370static struct platform_device *osiris_devices[] __initdata = {
371 &s3c_device_i2c0,
372 &s3c_device_wdt,
373 &s3c_device_nand,
374 &osiris_pcmcia,
375};
376
377static struct clk *osiris_clocks[] __initdata = {
378 &s3c24xx_dclk0,
379 &s3c24xx_dclk1,
380 &s3c24xx_clkout0,
381 &s3c24xx_clkout1,
382 &s3c24xx_uclk,
383};
384
385static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
386 .refresh = 7800, /* refresh period is 7.8usec */
387 .auto_io = 1,
388 .need_io = 1,
389};
390
391static void __init osiris_map_io(void)
392{
393 unsigned long flags;
394
395 /* initialise the clocks */
396
397 s3c24xx_dclk0.parent = &clk_upll;
398 s3c24xx_dclk0.rate = 12*1000*1000;
399
400 s3c24xx_dclk1.parent = &clk_upll;
401 s3c24xx_dclk1.rate = 24*1000*1000;
402
403 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
404 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
405
406 s3c24xx_uclk.parent = &s3c24xx_clkout1;
407
408 s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
409
410 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
411 s3c24xx_init_clocks(0);
412 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
413
414 /* check for the newer revision boards with large page nand */
415
416 if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
417 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
418 __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
419 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
420 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
421 } else {
422 /* write-protect line to the NAND */
423 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
424 }
425
426 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
427
428 local_irq_save(flags);
429 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
430 local_irq_restore(flags);
431}
432
433static void __init osiris_init(void)
434{
435 register_syscore_ops(&osiris_pm_syscore_ops);
436
437 s3c_i2c0_set_platdata(NULL);
438 s3c_nand_set_platdata(&osiris_nand_info);
439
440 s3c_cpufreq_setboard(&osiris_cpufreq);
441
442 i2c_register_board_info(0, osiris_i2c_devs,
443 ARRAY_SIZE(osiris_i2c_devs));
444
445 platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
446};
447
448MACHINE_START(OSIRIS, "Simtec-OSIRIS")
449 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
450 .boot_params = S3C2410_SDRAM_PA + 0x100,
451 .map_io = osiris_map_io,
452 .init_irq = s3c24xx_init_irq,
453 .init_machine = osiris_init,
454 .timer = &s3c24xx_timer,
455MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
new file mode 100644
index 00000000000..27ea95096fe
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -0,0 +1,834 @@
1/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
2 *
3 * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
4 * Copyright (c) 2007-2010 Vasily Khoruzhick
5 *
6 * based on smdk2440 written by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/memblock.h>
19#include <linux/delay.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/gpio.h>
23#include <linux/platform_device.h>
24#include <linux/serial_core.h>
25#include <linux/input.h>
26#include <linux/gpio_keys.h>
27#include <linux/sysdev.h>
28#include <linux/pda_power.h>
29#include <linux/pwm_backlight.h>
30#include <linux/pwm.h>
31#include <linux/s3c_adc_battery.h>
32#include <linux/leds.h>
33#include <linux/i2c.h>
34
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/partitions.h>
37
38#include <linux/mmc/host.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach-types.h>
43
44#include <mach/regs-gpio.h>
45#include <mach/regs-gpioj.h>
46#include <mach/h1940.h>
47#include <mach/fb.h>
48
49#include <plat/clock.h>
50#include <plat/regs-serial.h>
51#include <plat/regs-iic.h>
52#include <plat/mci.h>
53#include <plat/udc.h>
54#include <plat/nand.h>
55#include <plat/iic.h>
56#include <plat/devs.h>
57#include <plat/cpu.h>
58#include <plat/pm.h>
59#include <plat/irq.h>
60#include <plat/ts.h>
61
62#include <sound/uda1380.h>
63
64#define LCD_PWM_PERIOD 192960
65#define LCD_PWM_DUTY 127353
66
67static struct map_desc rx1950_iodesc[] __initdata = {
68};
69
70static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
71 [0] = {
72 .name = "fclk",
73 .divisor = 0x0a,
74 .min_baud = 0,
75 .max_baud = 0,
76 },
77};
78
79static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
80 [0] = {
81 .hwport = 0,
82 .flags = 0,
83 .ucon = 0x3c5,
84 .ulcon = 0x03,
85 .ufcon = 0x51,
86 .clocks = rx1950_serial_clocks,
87 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
88 },
89 [1] = {
90 .hwport = 1,
91 .flags = 0,
92 .ucon = 0x3c5,
93 .ulcon = 0x03,
94 .ufcon = 0x51,
95 .clocks = rx1950_serial_clocks,
96 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
97 },
98 /* IR port */
99 [2] = {
100 .hwport = 2,
101 .flags = 0,
102 .ucon = 0x3c5,
103 .ulcon = 0x43,
104 .ufcon = 0xf1,
105 .clocks = rx1950_serial_clocks,
106 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
107 },
108};
109
110static struct s3c2410fb_display rx1950_display = {
111 .type = S3C2410_LCDCON1_TFT,
112 .width = 240,
113 .height = 320,
114 .xres = 240,
115 .yres = 320,
116 .bpp = 16,
117
118 .pixclock = 260000,
119 .left_margin = 10,
120 .right_margin = 20,
121 .hsync_len = 10,
122 .upper_margin = 2,
123 .lower_margin = 2,
124 .vsync_len = 2,
125
126 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
127 S3C2410_LCDCON5_INVVCLK |
128 S3C2410_LCDCON5_INVVLINE |
129 S3C2410_LCDCON5_INVVFRAME |
130 S3C2410_LCDCON5_HWSWP |
131 (0x02 << 13) |
132 (0x02 << 15),
133
134};
135
136static int power_supply_init(struct device *dev)
137{
138 return gpio_request(S3C2410_GPF(2), "cable plugged");
139}
140
141static int rx1950_is_ac_online(void)
142{
143 return !gpio_get_value(S3C2410_GPF(2));
144}
145
146static void power_supply_exit(struct device *dev)
147{
148 gpio_free(S3C2410_GPF(2));
149}
150
151static char *rx1950_supplicants[] = {
152 "main-battery"
153};
154
155static struct pda_power_pdata power_supply_info = {
156 .init = power_supply_init,
157 .is_ac_online = rx1950_is_ac_online,
158 .exit = power_supply_exit,
159 .supplied_to = rx1950_supplicants,
160 .num_supplicants = ARRAY_SIZE(rx1950_supplicants),
161};
162
163static struct resource power_supply_resources[] = {
164 [0] = {
165 .name = "ac",
166 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
167 IORESOURCE_IRQ_HIGHEDGE,
168 .start = IRQ_EINT2,
169 .end = IRQ_EINT2,
170 },
171};
172
173static struct platform_device power_supply = {
174 .name = "pda-power",
175 .id = -1,
176 .dev = {
177 .platform_data =
178 &power_supply_info,
179 },
180 .resource = power_supply_resources,
181 .num_resources = ARRAY_SIZE(power_supply_resources),
182};
183
184static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
185 { .volt = 4100, .cur = 156, .level = 100},
186 { .volt = 4050, .cur = 156, .level = 95},
187 { .volt = 4025, .cur = 141, .level = 90},
188 { .volt = 3995, .cur = 144, .level = 85},
189 { .volt = 3957, .cur = 162, .level = 80},
190 { .volt = 3931, .cur = 147, .level = 75},
191 { .volt = 3902, .cur = 147, .level = 70},
192 { .volt = 3863, .cur = 153, .level = 65},
193 { .volt = 3838, .cur = 150, .level = 60},
194 { .volt = 3800, .cur = 153, .level = 55},
195 { .volt = 3765, .cur = 153, .level = 50},
196 { .volt = 3748, .cur = 172, .level = 45},
197 { .volt = 3740, .cur = 153, .level = 40},
198 { .volt = 3714, .cur = 175, .level = 35},
199 { .volt = 3710, .cur = 156, .level = 30},
200 { .volt = 3963, .cur = 156, .level = 25},
201 { .volt = 3672, .cur = 178, .level = 20},
202 { .volt = 3651, .cur = 178, .level = 15},
203 { .volt = 3629, .cur = 178, .level = 10},
204 { .volt = 3612, .cur = 162, .level = 5},
205 { .volt = 3605, .cur = 162, .level = 0},
206};
207
208static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
209 { .volt = 4200, .cur = 0, .level = 100},
210 { .volt = 4190, .cur = 0, .level = 99},
211 { .volt = 4178, .cur = 0, .level = 95},
212 { .volt = 4110, .cur = 0, .level = 70},
213 { .volt = 4076, .cur = 0, .level = 65},
214 { .volt = 4046, .cur = 0, .level = 60},
215 { .volt = 4021, .cur = 0, .level = 55},
216 { .volt = 3999, .cur = 0, .level = 50},
217 { .volt = 3982, .cur = 0, .level = 45},
218 { .volt = 3965, .cur = 0, .level = 40},
219 { .volt = 3957, .cur = 0, .level = 35},
220 { .volt = 3948, .cur = 0, .level = 30},
221 { .volt = 3936, .cur = 0, .level = 25},
222 { .volt = 3927, .cur = 0, .level = 20},
223 { .volt = 3906, .cur = 0, .level = 15},
224 { .volt = 3880, .cur = 0, .level = 10},
225 { .volt = 3829, .cur = 0, .level = 5},
226 { .volt = 3820, .cur = 0, .level = 0},
227};
228
229int rx1950_bat_init(void)
230{
231 int ret;
232
233 ret = gpio_request(S3C2410_GPJ(2), "rx1950-charger-enable-1");
234 if (ret)
235 goto err_gpio1;
236 ret = gpio_request(S3C2410_GPJ(3), "rx1950-charger-enable-2");
237 if (ret)
238 goto err_gpio2;
239
240 return 0;
241
242err_gpio2:
243 gpio_free(S3C2410_GPJ(2));
244err_gpio1:
245 return ret;
246}
247
248void rx1950_bat_exit(void)
249{
250 gpio_free(S3C2410_GPJ(2));
251 gpio_free(S3C2410_GPJ(3));
252}
253
254void rx1950_enable_charger(void)
255{
256 gpio_direction_output(S3C2410_GPJ(2), 1);
257 gpio_direction_output(S3C2410_GPJ(3), 1);
258}
259
260void rx1950_disable_charger(void)
261{
262 gpio_direction_output(S3C2410_GPJ(2), 0);
263 gpio_direction_output(S3C2410_GPJ(3), 0);
264}
265
266DEFINE_SPINLOCK(rx1950_blink_spin);
267
268static int rx1950_led_blink_set(unsigned gpio, int state,
269 unsigned long *delay_on, unsigned long *delay_off)
270{
271 int blink_gpio, check_gpio;
272
273 switch (gpio) {
274 case S3C2410_GPA(6):
275 blink_gpio = S3C2410_GPA(4);
276 check_gpio = S3C2410_GPA(3);
277 break;
278 case S3C2410_GPA(7):
279 blink_gpio = S3C2410_GPA(3);
280 check_gpio = S3C2410_GPA(4);
281 break;
282 default:
283 return -EINVAL;
284 break;
285 }
286
287 if (delay_on && delay_off && !*delay_on && !*delay_off)
288 *delay_on = *delay_off = 500;
289
290 spin_lock(&rx1950_blink_spin);
291
292 switch (state) {
293 case GPIO_LED_NO_BLINK_LOW:
294 case GPIO_LED_NO_BLINK_HIGH:
295 if (!gpio_get_value(check_gpio))
296 gpio_set_value(S3C2410_GPJ(6), 0);
297 gpio_set_value(blink_gpio, 0);
298 gpio_set_value(gpio, state);
299 break;
300 case GPIO_LED_BLINK:
301 gpio_set_value(gpio, 0);
302 gpio_set_value(S3C2410_GPJ(6), 1);
303 gpio_set_value(blink_gpio, 1);
304 break;
305 }
306
307 spin_unlock(&rx1950_blink_spin);
308
309 return 0;
310}
311
312static struct gpio_led rx1950_leds_desc[] = {
313 {
314 .name = "Green",
315 .default_trigger = "main-battery-full",
316 .gpio = S3C2410_GPA(6),
317 .retain_state_suspended = 1,
318 },
319 {
320 .name = "Red",
321 .default_trigger
322 = "main-battery-charging-blink-full-solid",
323 .gpio = S3C2410_GPA(7),
324 .retain_state_suspended = 1,
325 },
326 {
327 .name = "Blue",
328 .default_trigger = "rx1950-acx-mem",
329 .gpio = S3C2410_GPA(11),
330 .retain_state_suspended = 1,
331 },
332};
333
334static struct gpio_led_platform_data rx1950_leds_pdata = {
335 .num_leds = ARRAY_SIZE(rx1950_leds_desc),
336 .leds = rx1950_leds_desc,
337 .gpio_blink_set = rx1950_led_blink_set,
338};
339
340static struct platform_device rx1950_leds = {
341 .name = "leds-gpio",
342 .id = -1,
343 .dev = {
344 .platform_data = &rx1950_leds_pdata,
345 },
346};
347
348static struct s3c_adc_bat_pdata rx1950_bat_cfg = {
349 .init = rx1950_bat_init,
350 .exit = rx1950_bat_exit,
351 .enable_charger = rx1950_enable_charger,
352 .disable_charger = rx1950_disable_charger,
353 .gpio_charge_finished = S3C2410_GPF(3),
354 .lut_noac = bat_lut_noac,
355 .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
356 .lut_acin = bat_lut_acin,
357 .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
358 .volt_channel = 0,
359 .current_channel = 1,
360 .volt_mult = 4235,
361 .current_mult = 2900,
362 .internal_impedance = 200,
363};
364
365static struct platform_device rx1950_battery = {
366 .name = "s3c-adc-battery",
367 .id = -1,
368 .dev = {
369 .parent = &s3c_device_adc.dev,
370 .platform_data = &rx1950_bat_cfg,
371 },
372};
373
374static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
375 .displays = &rx1950_display,
376 .num_displays = 1,
377 .default_display = 0,
378
379 .lpcsel = 0x02,
380 .gpccon = 0xaa9556a9,
381 .gpccon_mask = 0xffc003fc,
382 .gpcup = 0x0000ffff,
383 .gpcup_mask = 0xffffffff,
384
385 .gpdcon = 0xaa90aaa1,
386 .gpdcon_mask = 0xffc0fff0,
387 .gpdup = 0x0000fcfd,
388 .gpdup_mask = 0xffffffff,
389
390};
391
392static struct pwm_device *lcd_pwm;
393
394void rx1950_lcd_power(int enable)
395{
396 int i;
397 static int enabled;
398 if (enabled == enable)
399 return;
400 if (!enable) {
401
402 /* GPC11-GPC15->OUTPUT */
403 for (i = 11; i < 16; i++)
404 gpio_direction_output(S3C2410_GPC(i), 1);
405
406 /* Wait a bit here... */
407 mdelay(100);
408
409 /* GPD2-GPD7->OUTPUT */
410 /* GPD11-GPD15->OUTPUT */
411 /* GPD2-GPD7->1, GPD11-GPD15->1 */
412 for (i = 2; i < 8; i++)
413 gpio_direction_output(S3C2410_GPD(i), 1);
414 for (i = 11; i < 16; i++)
415 gpio_direction_output(S3C2410_GPD(i), 1);
416
417 /* Wait a bit here...*/
418 mdelay(100);
419
420 /* GPB0->OUTPUT, GPB0->0 */
421 gpio_direction_output(S3C2410_GPB(0), 0);
422
423 /* GPC1-GPC4->OUTPUT, GPC1-4->0 */
424 for (i = 1; i < 5; i++)
425 gpio_direction_output(S3C2410_GPC(i), 0);
426
427 /* GPC15-GPC11->0 */
428 for (i = 11; i < 16; i++)
429 gpio_direction_output(S3C2410_GPC(i), 0);
430
431 /* GPD15-GPD11->0, GPD2->GPD7->0 */
432 for (i = 11; i < 16; i++)
433 gpio_direction_output(S3C2410_GPD(i), 0);
434
435 for (i = 2; i < 8; i++)
436 gpio_direction_output(S3C2410_GPD(i), 0);
437
438 /* GPC6->0, GPC7->0, GPC5->0 */
439 gpio_direction_output(S3C2410_GPC(6), 0);
440 gpio_direction_output(S3C2410_GPC(7), 0);
441 gpio_direction_output(S3C2410_GPC(5), 0);
442
443 /* GPB1->OUTPUT, GPB1->0 */
444 gpio_direction_output(S3C2410_GPB(1), 0);
445 pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
446 pwm_disable(lcd_pwm);
447
448 /* GPC0->0, GPC10->0 */
449 gpio_direction_output(S3C2410_GPC(0), 0);
450 gpio_direction_output(S3C2410_GPC(10), 0);
451 } else {
452 pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD);
453 pwm_enable(lcd_pwm);
454
455 gpio_direction_output(S3C2410_GPC(0), 1);
456 gpio_direction_output(S3C2410_GPC(5), 1);
457
458 s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1);
459 gpio_direction_output(S3C2410_GPC(7), 1);
460
461 for (i = 1; i < 5; i++)
462 s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
463
464 for (i = 11; i < 16; i++)
465 s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
466
467 for (i = 2; i < 8; i++)
468 s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
469
470 for (i = 11; i < 16; i++)
471 s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
472
473 gpio_direction_output(S3C2410_GPC(10), 1);
474 gpio_direction_output(S3C2410_GPC(6), 1);
475 }
476 enabled = enable;
477}
478
479static void rx1950_bl_power(int enable)
480{
481 static int enabled;
482 if (enabled == enable)
483 return;
484 if (!enable) {
485 gpio_direction_output(S3C2410_GPB(0), 0);
486 } else {
487 /* LED driver need a "push" to power on */
488 gpio_direction_output(S3C2410_GPB(0), 1);
489 /* Warm up backlight for one period of PWM.
490 * Without this trick its almost impossible to
491 * enable backlight with low brightness value
492 */
493 ndelay(48000);
494 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
495 }
496 enabled = enable;
497}
498
499static int rx1950_backlight_init(struct device *dev)
500{
501 WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight"));
502 lcd_pwm = pwm_request(1, "RX1950 LCD");
503 if (IS_ERR(lcd_pwm)) {
504 dev_err(dev, "Unable to request PWM for LCD power!\n");
505 return PTR_ERR(lcd_pwm);
506 }
507
508 rx1950_lcd_power(1);
509 rx1950_bl_power(1);
510
511 return 0;
512}
513
514static void rx1950_backlight_exit(struct device *dev)
515{
516 rx1950_bl_power(0);
517 rx1950_lcd_power(0);
518
519 pwm_free(lcd_pwm);
520 gpio_free(S3C2410_GPB(0));
521}
522
523
524static int rx1950_backlight_notify(struct device *dev, int brightness)
525{
526 if (!brightness) {
527 rx1950_bl_power(0);
528 rx1950_lcd_power(0);
529 } else {
530 rx1950_lcd_power(1);
531 rx1950_bl_power(1);
532 }
533 return brightness;
534}
535
536static struct platform_pwm_backlight_data rx1950_backlight_data = {
537 .pwm_id = 0,
538 .max_brightness = 24,
539 .dft_brightness = 4,
540 .pwm_period_ns = 48000,
541 .init = rx1950_backlight_init,
542 .notify = rx1950_backlight_notify,
543 .exit = rx1950_backlight_exit,
544};
545
546static struct platform_device rx1950_backlight = {
547 .name = "pwm-backlight",
548 .dev = {
549 .parent = &s3c_device_timer[0].dev,
550 .platform_data = &rx1950_backlight_data,
551 },
552};
553
554static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
555{
556 switch (power_mode) {
557 case MMC_POWER_OFF:
558 gpio_direction_output(S3C2410_GPJ(1), 0);
559 break;
560 case MMC_POWER_UP:
561 case MMC_POWER_ON:
562 gpio_direction_output(S3C2410_GPJ(1), 1);
563 break;
564 default:
565 break;
566 }
567}
568
569static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = {
570 .gpio_detect = S3C2410_GPF(5),
571 .gpio_wprotect = S3C2410_GPH(8),
572 .set_power = rx1950_set_mmc_power,
573 .ocr_avail = MMC_VDD_32_33,
574};
575
576static struct mtd_partition rx1950_nand_part[] = {
577 [0] = {
578 .name = "Boot0",
579 .offset = 0,
580 .size = 0x4000,
581 .mask_flags = MTD_WRITEABLE,
582 },
583 [1] = {
584 .name = "Boot1",
585 .offset = MTDPART_OFS_APPEND,
586 .size = 0x40000,
587 .mask_flags = MTD_WRITEABLE,
588 },
589 [2] = {
590 .name = "Kernel",
591 .offset = MTDPART_OFS_APPEND,
592 .size = 0x300000,
593 .mask_flags = 0,
594 },
595 [3] = {
596 .name = "Filesystem",
597 .offset = MTDPART_OFS_APPEND,
598 .size = MTDPART_SIZ_FULL,
599 .mask_flags = 0,
600 },
601};
602
603static struct s3c2410_nand_set rx1950_nand_sets[] = {
604 [0] = {
605 .name = "Internal",
606 .nr_chips = 1,
607 .nr_partitions = ARRAY_SIZE(rx1950_nand_part),
608 .partitions = rx1950_nand_part,
609 },
610};
611
612static struct s3c2410_platform_nand rx1950_nand_info = {
613 .tacls = 25,
614 .twrph0 = 50,
615 .twrph1 = 15,
616 .nr_sets = ARRAY_SIZE(rx1950_nand_sets),
617 .sets = rx1950_nand_sets,
618};
619
620static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
621 .vbus_pin = S3C2410_GPG(5),
622 .vbus_pin_inverted = 1,
623 .pullup_pin = S3C2410_GPJ(5),
624};
625
626static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = {
627 .delay = 10000,
628 .presc = 49,
629 .oversampling_shift = 3,
630};
631
632static struct gpio_keys_button rx1950_gpio_keys_table[] = {
633 {
634 .code = KEY_POWER,
635 .gpio = S3C2410_GPF(0),
636 .active_low = 1,
637 .desc = "Power button",
638 .wakeup = 1,
639 },
640 {
641 .code = KEY_F5,
642 .gpio = S3C2410_GPF(7),
643 .active_low = 1,
644 .desc = "Record button",
645 },
646 {
647 .code = KEY_F1,
648 .gpio = S3C2410_GPG(0),
649 .active_low = 1,
650 .desc = "Calendar button",
651 },
652 {
653 .code = KEY_F2,
654 .gpio = S3C2410_GPG(2),
655 .active_low = 1,
656 .desc = "Contacts button",
657 },
658 {
659 .code = KEY_F3,
660 .gpio = S3C2410_GPG(3),
661 .active_low = 1,
662 .desc = "Mail button",
663 },
664 {
665 .code = KEY_F4,
666 .gpio = S3C2410_GPG(7),
667 .active_low = 1,
668 .desc = "WLAN button",
669 },
670 {
671 .code = KEY_LEFT,
672 .gpio = S3C2410_GPG(10),
673 .active_low = 1,
674 .desc = "Left button",
675 },
676 {
677 .code = KEY_RIGHT,
678 .gpio = S3C2410_GPG(11),
679 .active_low = 1,
680 .desc = "Right button",
681 },
682 {
683 .code = KEY_UP,
684 .gpio = S3C2410_GPG(4),
685 .active_low = 1,
686 .desc = "Up button",
687 },
688 {
689 .code = KEY_DOWN,
690 .gpio = S3C2410_GPG(6),
691 .active_low = 1,
692 .desc = "Down button",
693 },
694 {
695 .code = KEY_ENTER,
696 .gpio = S3C2410_GPG(9),
697 .active_low = 1,
698 .desc = "Ok button"
699 },
700};
701
702static struct gpio_keys_platform_data rx1950_gpio_keys_data = {
703 .buttons = rx1950_gpio_keys_table,
704 .nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table),
705};
706
707static struct platform_device rx1950_device_gpiokeys = {
708 .name = "gpio-keys",
709 .dev.platform_data = &rx1950_gpio_keys_data,
710};
711
712static struct uda1380_platform_data uda1380_info = {
713 .gpio_power = S3C2410_GPJ(0),
714 .gpio_reset = S3C2410_GPD(0),
715 .dac_clk = UDA1380_DAC_CLK_SYSCLK,
716};
717
718static struct i2c_board_info rx1950_i2c_devices[] = {
719 {
720 I2C_BOARD_INFO("uda1380", 0x1a),
721 .platform_data = &uda1380_info,
722 },
723};
724
725static struct platform_device *rx1950_devices[] __initdata = {
726 &s3c_device_lcd,
727 &s3c_device_wdt,
728 &s3c_device_i2c0,
729 &s3c_device_iis,
730 &samsung_asoc_dma,
731 &s3c_device_usbgadget,
732 &s3c_device_rtc,
733 &s3c_device_nand,
734 &s3c_device_sdi,
735 &s3c_device_adc,
736 &s3c_device_ts,
737 &s3c_device_timer[0],
738 &s3c_device_timer[1],
739 &rx1950_backlight,
740 &rx1950_device_gpiokeys,
741 &power_supply,
742 &rx1950_battery,
743 &rx1950_leds,
744};
745
746static struct clk *rx1950_clocks[] __initdata = {
747 &s3c24xx_clkout0,
748 &s3c24xx_clkout1,
749};
750
751static void __init rx1950_map_io(void)
752{
753 s3c24xx_clkout0.parent = &clk_h;
754 s3c24xx_clkout1.parent = &clk_f;
755
756 s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
757
758 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
759 s3c24xx_init_clocks(16934000);
760 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
761
762 /* setup PM */
763
764#ifdef CONFIG_PM_H1940
765 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8);
766#endif
767
768 s3c_pm_init();
769}
770
771static void __init rx1950_init_machine(void)
772{
773 int i;
774
775 s3c24xx_fb_set_platdata(&rx1950_lcd_cfg);
776 s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
777 s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
778 s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
779 s3c_i2c0_set_platdata(NULL);
780 s3c_nand_set_platdata(&rx1950_nand_info);
781
782 /* Turn off suspend on both USB ports, and switch the
783 * selectable USB port to USB device mode. */
784 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
785 S3C2410_MISCCR_USBSUSPND0 |
786 S3C2410_MISCCR_USBSUSPND1, 0x0);
787
788 /* mmc power is disabled by default */
789 WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power"));
790 gpio_direction_output(S3C2410_GPJ(1), 0);
791
792 for (i = 0; i < 8; i++)
793 WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
794
795 for (i = 10; i < 16; i++)
796 WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
797
798 for (i = 2; i < 8; i++)
799 WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
800
801 for (i = 11; i < 16; i++)
802 WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
803
804 WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
805
806 WARN_ON(gpio_request(S3C2410_GPA(3), "Red blink"));
807 WARN_ON(gpio_request(S3C2410_GPA(4), "Green blink"));
808 WARN_ON(gpio_request(S3C2410_GPJ(6), "LED blink"));
809 gpio_direction_output(S3C2410_GPA(3), 0);
810 gpio_direction_output(S3C2410_GPA(4), 0);
811 gpio_direction_output(S3C2410_GPJ(6), 0);
812
813 platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
814
815 i2c_register_board_info(0, rx1950_i2c_devices,
816 ARRAY_SIZE(rx1950_i2c_devices));
817}
818
819/* H1940 and RX3715 need to reserve this for suspend */
820static void __init rx1950_reserve(void)
821{
822 memblock_reserve(0x30003000, 0x1000);
823 memblock_reserve(0x30081000, 0x1000);
824}
825
826MACHINE_START(RX1950, "HP iPAQ RX1950")
827 /* Maintainers: Vasily Khoruzhick */
828 .boot_params = S3C2410_SDRAM_PA + 0x100,
829 .map_io = rx1950_map_io,
830 .reserve = rx1950_reserve,
831 .init_irq = s3c24xx_init_irq,
832 .init_machine = rx1950_init_machine,
833 .timer = &s3c24xx_timer,
834MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
new file mode 100644
index 00000000000..1472b1a5b2f
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -0,0 +1,227 @@
1/* linux/arch/arm/mach-s3c2440/mach-rx3715.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.handhelds.org/projects/rx3715.html
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/memblock.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/tty.h>
22#include <linux/console.h>
23#include <linux/sysdev.h>
24#include <linux/platform_device.h>
25#include <linux/serial_core.h>
26#include <linux/serial.h>
27#include <linux/io.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/nand_ecc.h>
31#include <linux/mtd/partitions.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40
41#include <plat/regs-serial.h>
42#include <mach/regs-gpio.h>
43#include <mach/regs-lcd.h>
44
45#include <mach/h1940.h>
46#include <plat/nand.h>
47#include <mach/fb.h>
48
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/pm.h>
53
54static struct map_desc rx3715_iodesc[] __initdata = {
55 /* dump ISA space somewhere unused */
56
57 {
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS3),
60 .length = SZ_1M,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
64 .pfn = __phys_to_pfn(S3C2410_CS3),
65 .length = SZ_1M,
66 .type = MT_DEVICE,
67 },
68};
69
70
71static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
77 }
78};
79
80static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
89 },
90 [1] = {
91 .hwport = 1,
92 .flags = 0,
93 .ucon = 0x3c5,
94 .ulcon = 0x03,
95 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
98 },
99 /* IR port */
100 [2] = {
101 .hwport = 2,
102 .uart_flags = UPF_CONS_FLOW,
103 .ucon = 0x3c5,
104 .ulcon = 0x43,
105 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
108 }
109};
110
111/* framebuffer lcd controller information */
112
113static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
114 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
115 S3C2410_LCDCON5_FRM565 |
116 S3C2410_LCDCON5_HWSWP,
117
118 .type = S3C2410_LCDCON1_TFT,
119 .width = 240,
120 .height = 320,
121
122 .pixclock = 260000,
123 .xres = 240,
124 .yres = 320,
125 .bpp = 16,
126 .left_margin = 36,
127 .right_margin = 36,
128 .hsync_len = 8,
129 .upper_margin = 6,
130 .lower_margin = 7,
131 .vsync_len = 3,
132};
133
134static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
135
136 .displays = &rx3715_lcdcfg,
137 .num_displays = 1,
138 .default_display = 0,
139
140 .lpcsel = 0xf82,
141
142 .gpccon = 0xaa955699,
143 .gpccon_mask = 0xffc003cc,
144 .gpcup = 0x0000ffff,
145 .gpcup_mask = 0xffffffff,
146
147 .gpdcon = 0xaa95aaa1,
148 .gpdcon_mask = 0xffc0fff0,
149 .gpdup = 0x0000faff,
150 .gpdup_mask = 0xffffffff,
151};
152
153static struct mtd_partition __initdata rx3715_nand_part[] = {
154 [0] = {
155 .name = "Whole Flash",
156 .offset = 0,
157 .size = MTDPART_SIZ_FULL,
158 .mask_flags = MTD_WRITEABLE,
159 }
160};
161
162static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
163 [0] = {
164 .name = "Internal",
165 .nr_chips = 1,
166 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
167 .partitions = rx3715_nand_part,
168 },
169};
170
171static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
172 .tacls = 25,
173 .twrph0 = 50,
174 .twrph1 = 15,
175 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
176 .sets = rx3715_nand_sets,
177};
178
179static struct platform_device *rx3715_devices[] __initdata = {
180 &s3c_device_ohci,
181 &s3c_device_lcd,
182 &s3c_device_wdt,
183 &s3c_device_i2c0,
184 &s3c_device_iis,
185 &s3c_device_nand,
186};
187
188static void __init rx3715_map_io(void)
189{
190 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
191 s3c24xx_init_clocks(16934000);
192 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
193}
194
195/* H1940 and RX3715 need to reserve this for suspend */
196static void __init rx3715_reserve(void)
197{
198 memblock_reserve(0x30003000, 0x1000);
199 memblock_reserve(0x30081000, 0x1000);
200}
201
202static void __init rx3715_init_irq(void)
203{
204 s3c24xx_init_irq();
205}
206
207static void __init rx3715_init_machine(void)
208{
209#ifdef CONFIG_PM_H1940
210 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
211#endif
212 s3c_pm_init();
213
214 s3c_nand_set_platdata(&rx3715_nand_info);
215 s3c24xx_fb_set_platdata(&rx3715_fb_info);
216 platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
217}
218
219MACHINE_START(RX3715, "IPAQ-RX3715")
220 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
221 .boot_params = S3C2410_SDRAM_PA + 0x100,
222 .map_io = rx3715_map_io,
223 .reserve = rx3715_reserve,
224 .init_irq = rx3715_init_irq,
225 .init_machine = rx3715_init_machine,
226 .timer = &s3c24xx_timer,
227MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
new file mode 100644
index 00000000000..eedfe0f1164
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -0,0 +1,184 @@
1/* linux/arch/arm/mach-s3c2440/mach-smdk2440.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.fluff.org/ben/smdk2440/
7 *
8 * Thanks to Dimity Andric and TomTom for the loan of an SMDK2440.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h>
37
38#include <mach/idle.h>
39#include <mach/fb.h>
40#include <plat/iic.h>
41
42#include <plat/s3c2410.h>
43#include <plat/s3c244x.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#include <plat/common-smdk.h>
49
50static struct map_desc smdk2440_iodesc[] __initdata = {
51 /* ISA IO Space map (memory space selected by A24) */
52
53 {
54 .virtual = (u32)S3C24XX_VA_ISA_WORD,
55 .pfn = __phys_to_pfn(S3C2410_CS2),
56 .length = 0x10000,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
60 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
61 .length = SZ_4M,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
65 .pfn = __phys_to_pfn(S3C2410_CS2),
66 .length = 0x10000,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
70 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
71 .length = SZ_4M,
72 .type = MT_DEVICE,
73 }
74};
75
76#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
77#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
78#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
79
80static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 },
88 [1] = {
89 .hwport = 1,
90 .flags = 0,
91 .ucon = 0x3c5,
92 .ulcon = 0x03,
93 .ufcon = 0x51,
94 },
95 /* IR port */
96 [2] = {
97 .hwport = 2,
98 .flags = 0,
99 .ucon = 0x3c5,
100 .ulcon = 0x43,
101 .ufcon = 0x51,
102 }
103};
104
105/* LCD driver info */
106
107static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
108
109 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
110 S3C2410_LCDCON5_INVVLINE |
111 S3C2410_LCDCON5_INVVFRAME |
112 S3C2410_LCDCON5_PWREN |
113 S3C2410_LCDCON5_HWSWP,
114
115 .type = S3C2410_LCDCON1_TFT,
116
117 .width = 240,
118 .height = 320,
119
120 .pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
121 .xres = 240,
122 .yres = 320,
123 .bpp = 16,
124 .left_margin = 20,
125 .right_margin = 8,
126 .hsync_len = 4,
127 .upper_margin = 8,
128 .lower_margin = 7,
129 .vsync_len = 4,
130};
131
132static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = {
133 .displays = &smdk2440_lcd_cfg,
134 .num_displays = 1,
135 .default_display = 0,
136
137#if 0
138 /* currently setup by downloader */
139 .gpccon = 0xaa940659,
140 .gpccon_mask = 0xffffffff,
141 .gpcup = 0x0000ffff,
142 .gpcup_mask = 0xffffffff,
143 .gpdcon = 0xaa84aaa0,
144 .gpdcon_mask = 0xffffffff,
145 .gpdup = 0x0000faff,
146 .gpdup_mask = 0xffffffff,
147#endif
148
149 .lpcsel = ((0xCE6) & ~7) | 1<<4,
150};
151
152static struct platform_device *smdk2440_devices[] __initdata = {
153 &s3c_device_ohci,
154 &s3c_device_lcd,
155 &s3c_device_wdt,
156 &s3c_device_i2c0,
157 &s3c_device_iis,
158};
159
160static void __init smdk2440_map_io(void)
161{
162 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
163 s3c24xx_init_clocks(16934400);
164 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
165}
166
167static void __init smdk2440_machine_init(void)
168{
169 s3c24xx_fb_set_platdata(&smdk2440_fb_info);
170 s3c_i2c0_set_platdata(NULL);
171
172 platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
173 smdk_machine_init();
174}
175
176MACHINE_START(S3C2440, "SMDK2440")
177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
178 .boot_params = S3C2410_SDRAM_PA + 0x100,
179
180 .init_irq = s3c24xx_init_irq,
181 .map_io = smdk2440_map_io,
182 .init_machine = smdk2440_machine_init,
183 .timer = &s3c24xx_timer,
184MACHINE_END
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
new file mode 100644
index 00000000000..2270d336021
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -0,0 +1,75 @@
1/* linux/arch/arm/mach-s3c2440/s3c2440.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/serial_core.h>
21#include <linux/sysdev.h>
22#include <linux/syscore_ops.h>
23#include <linux/gpio.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/hardware.h>
32#include <asm/irq.h>
33
34#include <plat/devs.h>
35#include <plat/cpu.h>
36#include <plat/s3c244x.h>
37#include <plat/pm.h>
38
39#include <plat/gpio-core.h>
40#include <plat/gpio-cfg.h>
41#include <plat/gpio-cfg-helpers.h>
42
43static struct sys_device s3c2440_sysdev = {
44 .cls = &s3c2440_sysclass,
45};
46
47int __init s3c2440_init(void)
48{
49 printk("S3C2440: Initialising architecture\n");
50
51 /* change irq for watchdog */
52
53 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
54 s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
55
56 /* register suspend/resume handlers */
57
58#ifdef CONFIG_PM
59 register_syscore_ops(&s3c2410_pm_syscore_ops);
60#endif
61 register_syscore_ops(&s3c244x_pm_syscore_ops);
62 register_syscore_ops(&s3c24xx_irq_syscore_ops);
63
64 /* register our system device for everything else */
65
66 return sysdev_register(&s3c2440_sysdev);
67}
68
69void __init s3c2440_map_io(void)
70{
71 s3c244x_map_io();
72
73 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
74 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
75}
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
new file mode 100644
index 00000000000..6f2b65e6e06
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -0,0 +1,187 @@
1/* linux/arch/arm/mach-s3c2442/s3c2442.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2442 core and lock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/syscore_ops.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/mutex.h>
36#include <linux/gpio.h>
37#include <linux/clk.h>
38#include <linux/io.h>
39
40#include <mach/hardware.h>
41#include <linux/atomic.h>
42#include <asm/irq.h>
43
44#include <mach/regs-clock.h>
45
46#include <plat/clock.h>
47#include <plat/cpu.h>
48#include <plat/s3c244x.h>
49#include <plat/pm.h>
50
51#include <plat/gpio-core.h>
52#include <plat/gpio-cfg.h>
53#include <plat/gpio-cfg-helpers.h>
54
55/* S3C2442 extended clock support */
56
57static unsigned long s3c2442_camif_upll_round(struct clk *clk,
58 unsigned long rate)
59{
60 unsigned long parent_rate = clk_get_rate(clk->parent);
61 int div;
62
63 if (rate > parent_rate)
64 return parent_rate;
65
66 div = parent_rate / rate;
67
68 if (div == 3)
69 return parent_rate / 3;
70
71 /* note, we remove the +/- 1 calculations for the divisor */
72
73 div /= 2;
74
75 if (div < 1)
76 div = 1;
77 else if (div > 16)
78 div = 16;
79
80 return parent_rate / (div * 2);
81}
82
83static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
84{
85 unsigned long parent_rate = clk_get_rate(clk->parent);
86 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
87
88 rate = s3c2442_camif_upll_round(clk, rate);
89
90 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
91
92 if (rate == parent_rate) {
93 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
94 } else if ((parent_rate / rate) == 3) {
95 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
96 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
97 } else {
98 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
99 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
100 camdivn |= (((parent_rate / rate) / 2) - 1);
101 }
102
103 __raw_writel(camdivn, S3C2440_CAMDIVN);
104
105 return 0;
106}
107
108/* Extra S3C2442 clocks */
109
110static struct clk s3c2442_clk_cam = {
111 .name = "camif",
112 .id = -1,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2440_CLKCON_CAMERA,
115};
116
117static struct clk s3c2442_clk_cam_upll = {
118 .name = "camif-upll",
119 .id = -1,
120 .ops = &(struct clk_ops) {
121 .set_rate = s3c2442_camif_upll_setrate,
122 .round_rate = s3c2442_camif_upll_round,
123 },
124};
125
126static int s3c2442_clk_add(struct sys_device *sysdev)
127{
128 struct clk *clock_upll;
129 struct clk *clock_h;
130 struct clk *clock_p;
131
132 clock_p = clk_get(NULL, "pclk");
133 clock_h = clk_get(NULL, "hclk");
134 clock_upll = clk_get(NULL, "upll");
135
136 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
137 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
138 return -EINVAL;
139 }
140
141 s3c2442_clk_cam.parent = clock_h;
142 s3c2442_clk_cam_upll.parent = clock_upll;
143
144 s3c24xx_register_clock(&s3c2442_clk_cam);
145 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
146
147 clk_disable(&s3c2442_clk_cam);
148
149 return 0;
150}
151
152static struct sysdev_driver s3c2442_clk_driver = {
153 .add = s3c2442_clk_add,
154};
155
156static __init int s3c2442_clk_init(void)
157{
158 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
159}
160
161arch_initcall(s3c2442_clk_init);
162
163
164static struct sys_device s3c2442_sysdev = {
165 .cls = &s3c2442_sysclass,
166};
167
168int __init s3c2442_init(void)
169{
170 printk("S3C2442: Initialising architecture\n");
171
172#ifdef CONFIG_PM
173 register_syscore_ops(&s3c2410_pm_syscore_ops);
174#endif
175 register_syscore_ops(&s3c244x_pm_syscore_ops);
176 register_syscore_ops(&s3c24xx_irq_syscore_ops);
177
178 return sysdev_register(&s3c2442_sysdev);
179}
180
181void __init s3c2442_map_io(void)
182{
183 s3c244x_map_io();
184
185 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
186 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
187}
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
new file mode 100644
index 00000000000..7f5ea0a169a
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -0,0 +1,138 @@
1/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
2 *
3 * Copyright (c) 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 Common clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36
37#include <mach/hardware.h>
38#include <linux/atomic.h>
39#include <asm/irq.h>
40
41#include <mach/regs-clock.h>
42
43#include <plat/clock.h>
44#include <plat/cpu.h>
45
46static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
47{
48 unsigned long camdivn;
49 unsigned long dvs;
50
51 if (parent == &clk_f)
52 dvs = 0;
53 else if (parent == &clk_h)
54 dvs = S3C2440_CAMDIVN_DVSEN;
55 else
56 return -EINVAL;
57
58 clk->parent = parent;
59
60 camdivn = __raw_readl(S3C2440_CAMDIVN);
61 camdivn &= ~S3C2440_CAMDIVN_DVSEN;
62 camdivn |= dvs;
63 __raw_writel(camdivn, S3C2440_CAMDIVN);
64
65 return 0;
66}
67
68static struct clk clk_arm = {
69 .name = "armclk",
70 .id = -1,
71 .ops = &(struct clk_ops) {
72 .set_parent = s3c2440_setparent_armclk,
73 },
74};
75
76static int s3c244x_clk_add(struct sys_device *sysdev)
77{
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79 unsigned long clkdivn;
80 struct clk *clock_upll;
81 int ret;
82
83 printk("S3C244X: Clock Support, DVS %s\n",
84 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
85
86 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
87
88 ret = s3c24xx_register_clock(&clk_arm);
89 if (ret < 0) {
90 printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
91 return ret;
92 }
93
94 clock_upll = clk_get(NULL, "upll");
95 if (IS_ERR(clock_upll)) {
96 printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
97 return -ENOENT;
98 }
99
100 /* check rate of UPLL, and if it is near 96MHz, then change
101 * to using half the UPLL rate for the system */
102
103 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
104 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
105
106 spin_lock(&clocks_lock);
107
108 clkdivn = __raw_readl(S3C2410_CLKDIVN);
109 clkdivn |= S3C2440_CLKDIVN_UCLK;
110 __raw_writel(clkdivn, S3C2410_CLKDIVN);
111
112 spin_unlock(&clocks_lock);
113 }
114
115 return 0;
116}
117
118static struct sysdev_driver s3c2440_clk_driver = {
119 .add = s3c244x_clk_add,
120};
121
122static int s3c2440_clk_init(void)
123{
124 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
125}
126
127arch_initcall(s3c2440_clk_init);
128
129static struct sysdev_driver s3c2442_clk_driver = {
130 .add = s3c244x_clk_add,
131};
132
133static int s3c2442_clk_init(void)
134{
135 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
136}
137
138arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
new file mode 100644
index 00000000000..c63e8f26d90
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -0,0 +1,138 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/sysdev.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* camera irq */
42
43static void s3c_irq_demux_cam(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 11;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_CAM_C);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_CAM_P);
64 }
65 }
66}
67
68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69
70static void
71s3c_irq_cam_mask(struct irq_data *data)
72{
73 s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
74}
75
76static void
77s3c_irq_cam_unmask(struct irq_data *data)
78{
79 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
80}
81
82static void
83s3c_irq_cam_ack(struct irq_data *data)
84{
85 s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
86}
87
88static struct irq_chip s3c_irq_cam = {
89 .irq_mask = s3c_irq_cam_mask,
90 .irq_unmask = s3c_irq_cam_unmask,
91 .irq_ack = s3c_irq_cam_ack,
92};
93
94static int s3c244x_irq_add(struct sys_device *sysdev)
95{
96 unsigned int irqno;
97
98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
102 /* add chained handler for camera */
103
104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 handle_level_irq);
106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID);
112 }
113
114 return 0;
115}
116
117static struct sysdev_driver s3c2440_irq_driver = {
118 .add = s3c244x_irq_add,
119};
120
121static int s3c2440_irq_init(void)
122{
123 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
124}
125
126arch_initcall(s3c2440_irq_init);
127
128static struct sysdev_driver s3c2442_irq_driver = {
129 .add = s3c244x_irq_add,
130};
131
132
133static int s3c2442_irq_init(void)
134{
135 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
136}
137
138arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
new file mode 100644
index 00000000000..7e8a23d2098
--- /dev/null
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -0,0 +1,196 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/syscore_ops.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32
33#include <plat/cpu-freq.h>
34
35#include <mach/regs-clock.h>
36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h>
38#include <mach/regs-gpioj.h>
39#include <mach/regs-dsc.h>
40
41#include <plat/s3c2410.h>
42#include <plat/s3c244x.h>
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/pm.h>
47#include <plat/pll.h>
48#include <plat/nand-core.h>
49
50static struct map_desc s3c244x_iodesc[] __initdata = {
51 IODESC_ENT(CLKPWR),
52 IODESC_ENT(TIMER),
53 IODESC_ENT(WATCHDOG),
54};
55
56/* uart initialisation */
57
58void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
59{
60 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
61}
62
63void __init s3c244x_map_io(void)
64{
65 /* register our io-tables */
66
67 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
68
69 /* rename any peripherals used differing from the s3c2410 */
70
71 s3c_device_sdi.name = "s3c2440-sdi";
72 s3c_device_i2c0.name = "s3c2440-i2c";
73 s3c_nand_setname("s3c2440-nand");
74 s3c_device_ts.name = "s3c2440-ts";
75 s3c_device_usbgadget.name = "s3c2440-usbgadget";
76}
77
78void __init_or_cpufreq s3c244x_setup_clocks(void)
79{
80 struct clk *xtal_clk;
81 unsigned long clkdiv;
82 unsigned long camdiv;
83 unsigned long xtal;
84 unsigned long hclk, fclk, pclk;
85 int hdiv = 1;
86
87 xtal_clk = clk_get(NULL, "xtal");
88 xtal = clk_get_rate(xtal_clk);
89 clk_put(xtal_clk);
90
91 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
92
93 clkdiv = __raw_readl(S3C2410_CLKDIVN);
94 camdiv = __raw_readl(S3C2440_CAMDIVN);
95
96 /* work out clock scalings */
97
98 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
99 case S3C2440_CLKDIVN_HDIVN_1:
100 hdiv = 1;
101 break;
102
103 case S3C2440_CLKDIVN_HDIVN_2:
104 hdiv = 2;
105 break;
106
107 case S3C2440_CLKDIVN_HDIVN_4_8:
108 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
109 break;
110
111 case S3C2440_CLKDIVN_HDIVN_3_6:
112 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
113 break;
114 }
115
116 hclk = fclk / hdiv;
117 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
118
119 /* print brief summary of clocks, etc */
120
121 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
122 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
123
124 s3c24xx_setup_clocks(fclk, hclk, pclk);
125}
126
127void __init s3c244x_init_clocks(int xtal)
128{
129 /* initialise the clocks here, to allow other things like the
130 * console to use them, and to add new ones after the initialisation
131 */
132
133 s3c24xx_register_baseclocks(xtal);
134 s3c244x_setup_clocks();
135 s3c2410_baseclk_add();
136}
137
138/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
139
140struct sysdev_class s3c2440_sysclass = {
141 .name = "s3c2440-core",
142};
143
144struct sysdev_class s3c2442_sysclass = {
145 .name = "s3c2442-core",
146};
147
148/* need to register class before we actually register the device, and
149 * we also need to ensure that it has been initialised before any of the
150 * drivers even try to use it (even if not on an s3c2440 based system)
151 * as a driver which may support both 2410 and 2440 may try and use it.
152*/
153
154static int __init s3c2440_core_init(void)
155{
156 return sysdev_class_register(&s3c2440_sysclass);
157}
158
159core_initcall(s3c2440_core_init);
160
161static int __init s3c2442_core_init(void)
162{
163 return sysdev_class_register(&s3c2442_sysclass);
164}
165
166core_initcall(s3c2442_core_init);
167
168
169#ifdef CONFIG_PM
170static struct sleep_save s3c244x_sleep[] = {
171 SAVE_ITEM(S3C2440_DSC0),
172 SAVE_ITEM(S3C2440_DSC1),
173 SAVE_ITEM(S3C2440_GPJDAT),
174 SAVE_ITEM(S3C2440_GPJCON),
175 SAVE_ITEM(S3C2440_GPJUP)
176};
177
178static int s3c244x_suspend(void)
179{
180 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
181 return 0;
182}
183
184static void s3c244x_resume(void)
185{
186 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
187}
188#else
189#define s3c244x_suspend NULL
190#define s3c244x_resume NULL
191#endif
192
193struct syscore_ops s3c244x_pm_syscore_ops = {
194 .suspend = s3c244x_suspend,
195 .resume = s3c244x_resume,
196};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 08:11:20 -0400