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-rw-r--r--arch/arm/mach-s3c2416/Kconfig61
-rw-r--r--arch/arm/mach-s3c2416/Makefile23
-rw-r--r--arch/arm/mach-s3c2416/clock.c143
-rw-r--r--arch/arm/mach-s3c2416/irq.c247
-rw-r--r--arch/arm/mach-s3c2416/mach-smdk2416.c254
-rw-r--r--arch/arm/mach-s3c2416/pm.c81
-rw-r--r--arch/arm/mach-s3c2416/s3c2416.c144
-rw-r--r--arch/arm/mach-s3c2416/setup-sdhci-gpio.c34
-rw-r--r--arch/arm/mach-s3c2416/setup-sdhci.c61
9 files changed, 1048 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
new file mode 100644
index 00000000000..69b48a7d1db
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -0,0 +1,61 @@
1# arch/arm/mach-s3c2416/Kconfig
2#
3# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4#
5# Licensed under GPLv2
6
7# note, this also supports the S3C2450 which is so similar it has the same
8# ID code as the S3C2416.
9
10config CPU_S3C2416
11 bool
12 depends on ARCH_S3C2410
13 select CPU_ARM926T
14 select S3C2416_DMA if S3C2410_DMA
15 select CPU_LLSERIAL_S3C2440
16 select S3C_GPIO_PULL_UPDOWN
17 select SAMSUNG_CLKSRC
18 select S3C2443_CLOCK
19 help
20 Support for the S3C2416 SoC from the S3C24XX line
21
22config S3C2416_DMA
23 bool
24 depends on CPU_S3C2416
25 help
26 Internal config node for S3C2416 DMA support
27
28config S3C2416_PM
29 bool
30 select S3C2412_PM_SLEEP
31 help
32 Internal config node to apply S3C2416 power management
33
34config S3C2416_SETUP_SDHCI
35 bool
36 select S3C2416_SETUP_SDHCI_GPIO
37 help
38 Internal helper functions for S3C2416 based SDHCI systems
39
40config S3C2416_SETUP_SDHCI_GPIO
41 bool
42 help
43 Common setup code for SDHCI gpio.
44
45menu "S3C2416 Machines"
46
47config MACH_SMDK2416
48 bool "SMDK2416"
49 select CPU_S3C2416
50 select MACH_SMDK
51 select S3C_DEV_FB
52 select S3C_DEV_HSMMC
53 select S3C_DEV_HSMMC1
54 select S3C_DEV_NAND
55 select S3C_DEV_USB_HOST
56 select S3C2416_SETUP_SDHCI
57 select S3C2416_PM if PM
58 help
59 Say Y here if you are using an SMDK2416
60
61endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
new file mode 100644
index 00000000000..7b805b279ca
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -0,0 +1,23 @@
1# arch/arm/mach-s3c2416/Makefile
2#
3# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
13obj-$(CONFIG_CPU_S3C2416) += irq.o
14obj-$(CONFIG_S3C2416_PM) += pm.o
15#obj-$(CONFIG_S3C2416_DMA) += dma.o
16
17# Device setup
18obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
19obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
20
21# Machine support
22
23obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
new file mode 100644
index 00000000000..21a5e81f0ab
--- /dev/null
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -0,0 +1,143 @@
1/* linux/arch/arm/mach-s3c2416/clock.c
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
5 *
6 * S3C2416 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/clk.h>
16
17#include <plat/s3c2416.h>
18#include <plat/s3c2443.h>
19#include <plat/clock.h>
20#include <plat/clock-clksrc.h>
21#include <plat/cpu.h>
22
23#include <plat/cpu-freq.h>
24#include <plat/pll6553x.h>
25#include <plat/pll.h>
26
27#include <asm/mach/map.h>
28
29#include <mach/regs-clock.h>
30#include <mach/regs-s3c2443-clock.h>
31
32static unsigned int armdiv[8] = {
33 [0] = 1,
34 [1] = 2,
35 [2] = 3,
36 [3] = 4,
37 [5] = 6,
38 [7] = 8,
39};
40
41static struct clksrc_clk hsmmc_div[] = {
42 [0] = {
43 .clk = {
44 .name = "hsmmc-div",
45 .devname = "s3c-sdhci.0",
46 .parent = &clk_esysclk.clk,
47 },
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
49 },
50 [1] = {
51 .clk = {
52 .name = "hsmmc-div",
53 .devname = "s3c-sdhci.1",
54 .parent = &clk_esysclk.clk,
55 },
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
57 },
58};
59
60static struct clksrc_clk hsmmc_mux[] = {
61 [0] = {
62 .clk = {
63 .name = "hsmmc-if",
64 .devname = "s3c-sdhci.0",
65 .ctrlbit = (1 << 6),
66 .enable = s3c2443_clkcon_enable_s,
67 },
68 .sources = &(struct clksrc_sources) {
69 .nr_sources = 2,
70 .sources = (struct clk *[]) {
71 [0] = &hsmmc_div[0].clk,
72 [1] = NULL, /* to fix */
73 },
74 },
75 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
76 },
77 [1] = {
78 .clk = {
79 .name = "hsmmc-if",
80 .devname = "s3c-sdhci.1",
81 .ctrlbit = (1 << 12),
82 .enable = s3c2443_clkcon_enable_s,
83 },
84 .sources = &(struct clksrc_sources) {
85 .nr_sources = 2,
86 .sources = (struct clk *[]) {
87 [0] = &hsmmc_div[1].clk,
88 [1] = NULL, /* to fix */
89 },
90 },
91 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
92 },
93};
94
95static struct clk hsmmc0_clk = {
96 .name = "hsmmc",
97 .devname = "s3c-sdhci.0",
98 .parent = &clk_h,
99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
101};
102
103static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
104{
105 clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
106
107 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
108}
109
110void __init_or_cpufreq s3c2416_setup_clocks(void)
111{
112 s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
113}
114
115
116static struct clksrc_clk *clksrcs[] __initdata = {
117 &hsmmc_div[0],
118 &hsmmc_div[1],
119 &hsmmc_mux[0],
120 &hsmmc_mux[1],
121};
122
123void __init s3c2416_init_clocks(int xtal)
124{
125 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
126 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
127 int ptr;
128
129 /* s3c2416 EPLL compatible with s3c64xx */
130 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
131
132 clk_epll.parent = &clk_epllref.clk;
133
134 s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
135
136 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
137 s3c_register_clksrc(clksrcs[ptr], 1);
138
139 s3c24xx_register_clock(&hsmmc0_clk);
140
141 s3c_pwmclk_init();
142
143}
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
new file mode 100644
index 00000000000..28ad20d4244
--- /dev/null
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -0,0 +1,247 @@
1/* linux/arch/arm/mach-s3c2416/irq.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28#include <linux/sysdev.h>
29#include <linux/io.h>
30
31#include <mach/hardware.h>
32#include <asm/irq.h>
33
34#include <asm/mach/irq.h>
35
36#include <mach/regs-irq.h>
37#include <mach/regs-gpio.h>
38
39#include <plat/cpu.h>
40#include <plat/pm.h>
41#include <plat/irq.h>
42
43#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
44
45static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
46{
47 unsigned int subsrc, submsk;
48 unsigned int end;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= (irq - S3C2410_IRQSUB(0));
58 subsrc &= (1 << len)-1;
59
60 end = len + irq;
61
62 for (; irq < end && subsrc; irq++) {
63 if (subsrc & 1)
64 generic_handle_irq(irq);
65
66 subsrc >>= 1;
67 }
68}
69
70/* WDT/AC97 sub interrupts */
71
72static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
73{
74 s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
75}
76
77#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
78#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
79
80static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
81{
82 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
83}
84
85static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
86{
87 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
88}
89
90static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
91{
92 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
93}
94
95static struct irq_chip s3c2416_irq_wdtac97 = {
96 .irq_mask = s3c2416_irq_wdtac97_mask,
97 .irq_unmask = s3c2416_irq_wdtac97_unmask,
98 .irq_ack = s3c2416_irq_wdtac97_ack,
99};
100
101/* LCD sub interrupts */
102
103static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
104{
105 s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
106}
107
108#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
109#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
110
111static void s3c2416_irq_lcd_mask(struct irq_data *data)
112{
113 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
114}
115
116static void s3c2416_irq_lcd_unmask(struct irq_data *data)
117{
118 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
119}
120
121static void s3c2416_irq_lcd_ack(struct irq_data *data)
122{
123 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
124}
125
126static struct irq_chip s3c2416_irq_lcd = {
127 .irq_mask = s3c2416_irq_lcd_mask,
128 .irq_unmask = s3c2416_irq_lcd_unmask,
129 .irq_ack = s3c2416_irq_lcd_ack,
130};
131
132/* DMA sub interrupts */
133
134static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
135{
136 s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
137}
138
139#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
140#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
141
142
143static void s3c2416_irq_dma_mask(struct irq_data *data)
144{
145 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
146}
147
148static void s3c2416_irq_dma_unmask(struct irq_data *data)
149{
150 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
151}
152
153static void s3c2416_irq_dma_ack(struct irq_data *data)
154{
155 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
156}
157
158static struct irq_chip s3c2416_irq_dma = {
159 .irq_mask = s3c2416_irq_dma_mask,
160 .irq_unmask = s3c2416_irq_dma_unmask,
161 .irq_ack = s3c2416_irq_dma_ack,
162};
163
164/* UART3 sub interrupts */
165
166static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
167{
168 s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
169}
170
171#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
172#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
173
174static void s3c2416_irq_uart3_mask(struct irq_data *data)
175{
176 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
177}
178
179static void s3c2416_irq_uart3_unmask(struct irq_data *data)
180{
181 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
182}
183
184static void s3c2416_irq_uart3_ack(struct irq_data *data)
185{
186 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
187}
188
189static struct irq_chip s3c2416_irq_uart3 = {
190 .irq_mask = s3c2416_irq_uart3_mask,
191 .irq_unmask = s3c2416_irq_uart3_unmask,
192 .irq_ack = s3c2416_irq_uart3_ack,
193};
194
195/* IRQ initialisation code */
196
197static int __init s3c2416_add_sub(unsigned int base,
198 void (*demux)(unsigned int,
199 struct irq_desc *),
200 struct irq_chip *chip,
201 unsigned int start, unsigned int end)
202{
203 unsigned int irqno;
204
205 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
206 irq_set_chained_handler(base, demux);
207
208 for (irqno = start; irqno <= end; irqno++) {
209 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
210 set_irq_flags(irqno, IRQF_VALID);
211 }
212
213 return 0;
214}
215
216static int __init s3c2416_irq_add(struct sys_device *sysdev)
217{
218 printk(KERN_INFO "S3C2416: IRQ Support\n");
219
220 s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
221 IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
222
223 s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
224 &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
225
226 s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
227 &s3c2416_irq_uart3,
228 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
229
230 s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
231 &s3c2416_irq_wdtac97,
232 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
233
234 return 0;
235}
236
237static struct sysdev_driver s3c2416_irq_driver = {
238 .add = s3c2416_irq_add,
239};
240
241static int __init s3c2416_irq_init(void)
242{
243 return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
244}
245
246arch_initcall(s3c2416_irq_init);
247
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
new file mode 100644
index 00000000000..ac27ebb31c9
--- /dev/null
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -0,0 +1,254 @@
1/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/mtd/partitions.h>
24#include <linux/gpio.h>
25#include <linux/fb.h>
26#include <linux/delay.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <asm/irq.h>
34#include <asm/mach-types.h>
35
36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h>
38#include <mach/regs-lcd.h>
39#include <mach/regs-s3c2443-clock.h>
40
41#include <mach/idle.h>
42#include <mach/leds-gpio.h>
43#include <plat/iic.h>
44
45#include <plat/s3c2416.h>
46#include <plat/gpio-cfg.h>
47#include <plat/clock.h>
48#include <plat/devs.h>
49#include <plat/cpu.h>
50#include <plat/nand.h>
51#include <plat/sdhci.h>
52#include <plat/udc.h>
53
54#include <plat/regs-fb-v4.h>
55#include <plat/fb.h>
56
57#include <plat/common-smdk.h>
58
59static struct map_desc smdk2416_iodesc[] __initdata = {
60 /* ISA IO Space map (memory space selected by A24) */
61
62 {
63 .virtual = (u32)S3C24XX_VA_ISA_WORD,
64 .pfn = __phys_to_pfn(S3C2410_CS2),
65 .length = 0x10000,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
69 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
70 .length = SZ_4M,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
74 .pfn = __phys_to_pfn(S3C2410_CS2),
75 .length = 0x10000,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
79 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
80 .length = SZ_4M,
81 .type = MT_DEVICE,
82 }
83};
84
85#define UCON (S3C2410_UCON_DEFAULT | \
86 S3C2440_UCON_PCLK | \
87 S3C2443_UCON_RXERR_IRQEN)
88
89#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
90
91#define UFCON (S3C2410_UFCON_RXTRIG8 | \
92 S3C2410_UFCON_FIFOMODE | \
93 S3C2440_UFCON_TXTRIG16)
94
95static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
96 [0] = {
97 .hwport = 0,
98 .flags = 0,
99 .ucon = UCON,
100 .ulcon = ULCON,
101 .ufcon = UFCON,
102 },
103 [1] = {
104 .hwport = 1,
105 .flags = 0,
106 .ucon = UCON,
107 .ulcon = ULCON,
108 .ufcon = UFCON,
109 },
110 /* IR port */
111 [2] = {
112 .hwport = 2,
113 .flags = 0,
114 .ucon = UCON,
115 .ulcon = ULCON | 0x50,
116 .ufcon = UFCON,
117 },
118 [3] = {
119 .hwport = 3,
120 .flags = 0,
121 .ucon = UCON,
122 .ulcon = ULCON,
123 .ufcon = UFCON,
124 }
125};
126
127void smdk2416_hsudc_gpio_init(void)
128{
129 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
130 s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
131 s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(1));
132 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
133}
134
135void smdk2416_hsudc_gpio_uninit(void)
136{
137 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
138 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
139 s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
140}
141
142struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
143 .epnum = 9,
144 .gpio_init = smdk2416_hsudc_gpio_init,
145 .gpio_uninit = smdk2416_hsudc_gpio_uninit,
146};
147
148struct s3c_fb_pd_win smdk2416_fb_win[] = {
149 [0] = {
150 /* think this is the same as the smdk6410 */
151 .win_mode = {
152 .pixclock = 41094,
153 .left_margin = 8,
154 .right_margin = 13,
155 .upper_margin = 7,
156 .lower_margin = 5,
157 .hsync_len = 3,
158 .vsync_len = 1,
159 .xres = 800,
160 .yres = 480,
161 },
162 .default_bpp = 16,
163 .max_bpp = 32,
164 },
165};
166
167static void s3c2416_fb_gpio_setup_24bpp(void)
168{
169 unsigned int gpio;
170
171 for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) {
172 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
173 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
174 }
175
176 for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) {
177 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
178 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
179 }
180
181 for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) {
182 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
183 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
184 }
185}
186
187static struct s3c_fb_platdata smdk2416_fb_platdata = {
188 .win[0] = &smdk2416_fb_win[0],
189 .setup_gpio = s3c2416_fb_gpio_setup_24bpp,
190 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
191 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
192};
193
194static struct s3c_sdhci_platdata smdk2416_hsmmc0_pdata __initdata = {
195 .max_width = 4,
196 .cd_type = S3C_SDHCI_CD_GPIO,
197 .ext_cd_gpio = S3C2410_GPF(1),
198 .ext_cd_gpio_invert = 1,
199};
200
201static struct s3c_sdhci_platdata smdk2416_hsmmc1_pdata __initdata = {
202 .max_width = 4,
203 .cd_type = S3C_SDHCI_CD_NONE,
204};
205
206static struct platform_device *smdk2416_devices[] __initdata = {
207 &s3c_device_fb,
208 &s3c_device_wdt,
209 &s3c_device_ohci,
210 &s3c_device_i2c0,
211 &s3c_device_hsmmc0,
212 &s3c_device_hsmmc1,
213 &s3c_device_usb_hsudc,
214};
215
216static void __init smdk2416_map_io(void)
217{
218 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
219 s3c24xx_init_clocks(12000000);
220 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
221}
222
223static void __init smdk2416_machine_init(void)
224{
225 s3c_i2c0_set_platdata(NULL);
226 s3c_fb_set_platdata(&smdk2416_fb_platdata);
227
228 s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata);
229 s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata);
230
231 s3c24xx_hsudc_set_platdata(&smdk2416_hsudc_platdata);
232
233 gpio_request(S3C2410_GPB(4), "USBHost Power");
234 gpio_direction_output(S3C2410_GPB(4), 1);
235
236 gpio_request(S3C2410_GPB(3), "Display Power");
237 gpio_direction_output(S3C2410_GPB(3), 1);
238
239 gpio_request(S3C2410_GPB(1), "Display Reset");
240 gpio_direction_output(S3C2410_GPB(1), 1);
241
242 platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
243 smdk_machine_init();
244}
245
246MACHINE_START(SMDK2416, "SMDK2416")
247 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
248 .boot_params = S3C2410_SDRAM_PA + 0x100,
249
250 .init_irq = s3c24xx_init_irq,
251 .map_io = smdk2416_map_io,
252 .init_machine = smdk2416_machine_init,
253 .timer = &s3c24xx_timer,
254MACHINE_END
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
new file mode 100644
index 00000000000..9ec54f1d8e7
--- /dev/null
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -0,0 +1,81 @@
1/* linux/arch/arm/mach-s3c2416/pm.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S3C2416 - PM support (Based on Ben Dooks' S3C2412 PM support)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sysdev.h>
14#include <linux/syscore_ops.h>
15#include <linux/io.h>
16
17#include <asm/cacheflush.h>
18
19#include <mach/regs-power.h>
20#include <mach/regs-s3c2443-clock.h>
21
22#include <plat/cpu.h>
23#include <plat/pm.h>
24
25extern void s3c2412_sleep_enter(void);
26
27static int s3c2416_cpu_suspend(unsigned long arg)
28{
29 /* enable wakeup sources regardless of battery state */
30 __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
31
32 /* set the mode as sleep, 2BED represents "Go to BED" */
33 __raw_writel(0x2BED, S3C2443_PWRMODE);
34
35 s3c2412_sleep_enter();
36
37 panic("sleep resumed to originator?");
38}
39
40static void s3c2416_pm_prepare(void)
41{
42 /*
43 * write the magic value u-boot uses to check for resume into
44 * the INFORM0 register, and ensure INFORM1 is set to the
45 * correct address to resume from.
46 */
47 __raw_writel(0x2BED, S3C2412_INFORM0);
48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
49}
50
51static int s3c2416_pm_add(struct sys_device *sysdev)
52{
53 pm_cpu_prep = s3c2416_pm_prepare;
54 pm_cpu_sleep = s3c2416_cpu_suspend;
55
56 return 0;
57}
58
59static struct sysdev_driver s3c2416_pm_driver = {
60 .add = s3c2416_pm_add,
61};
62
63static __init int s3c2416_pm_init(void)
64{
65 return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
66}
67
68arch_initcall(s3c2416_pm_init);
69
70
71static void s3c2416_pm_resume(void)
72{
73 /* unset the return-from-sleep amd inform flags */
74 __raw_writel(0x0, S3C2443_PWRMODE);
75 __raw_writel(0x0, S3C2412_INFORM0);
76 __raw_writel(0x0, S3C2412_INFORM1);
77}
78
79struct syscore_ops s3c2416_pm_syscore_ops = {
80 .resume = s3c2416_pm_resume,
81};
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
new file mode 100644
index 00000000000..20b3fdfb305
--- /dev/null
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -0,0 +1,144 @@
1/* linux/arch/arm/mach-s3c2416/s3c2416.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * Samsung S3C2416 Mobile CPU support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23*/
24
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/timer.h>
30#include <linux/init.h>
31#include <linux/gpio.h>
32#include <linux/platform_device.h>
33#include <linux/serial_core.h>
34#include <linux/sysdev.h>
35#include <linux/syscore_ops.h>
36#include <linux/clk.h>
37#include <linux/io.h>
38
39#include <asm/mach/arch.h>
40#include <asm/mach/map.h>
41#include <asm/mach/irq.h>
42
43#include <mach/hardware.h>
44#include <asm/proc-fns.h>
45#include <asm/irq.h>
46
47#include <mach/reset.h>
48#include <mach/idle.h>
49#include <mach/regs-s3c2443-clock.h>
50
51#include <plat/gpio-core.h>
52#include <plat/gpio-cfg.h>
53#include <plat/gpio-cfg-helpers.h>
54#include <plat/s3c2416.h>
55#include <plat/devs.h>
56#include <plat/cpu.h>
57#include <plat/sdhci.h>
58#include <plat/pm.h>
59
60#include <plat/iic-core.h>
61#include <plat/fb-core.h>
62#include <plat/nand-core.h>
63
64static struct map_desc s3c2416_iodesc[] __initdata = {
65 IODESC_ENT(WATCHDOG),
66 IODESC_ENT(CLKPWR),
67 IODESC_ENT(TIMER),
68};
69
70struct sysdev_class s3c2416_sysclass = {
71 .name = "s3c2416-core",
72};
73
74static struct sys_device s3c2416_sysdev = {
75 .cls = &s3c2416_sysclass,
76};
77
78static void s3c2416_hard_reset(void)
79{
80 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
81}
82
83int __init s3c2416_init(void)
84{
85 printk(KERN_INFO "S3C2416: Initializing architecture\n");
86
87 s3c24xx_reset_hook = s3c2416_hard_reset;
88 /* s3c24xx_idle = s3c2416_idle; */
89
90 /* change WDT IRQ number */
91 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
92 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
93
94 /* the i2c devices are directly compatible with s3c2440 */
95 s3c_i2c0_setname("s3c2440-i2c");
96 s3c_i2c1_setname("s3c2440-i2c");
97
98 s3c_fb_setname("s3c2443-fb");
99
100#ifdef CONFIG_PM
101 register_syscore_ops(&s3c2416_pm_syscore_ops);
102#endif
103 register_syscore_ops(&s3c24xx_irq_syscore_ops);
104
105 return sysdev_register(&s3c2416_sysdev);
106}
107
108void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
109{
110 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
111
112 s3c_nand_setname("s3c2412-nand");
113}
114
115/* s3c2416_map_io
116 *
117 * register the standard cpu IO areas, and any passed in from the
118 * machine specific initialisation.
119 */
120
121void __init s3c2416_map_io(void)
122{
123 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
124 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
125
126 /* initialize device information early */
127 s3c2416_default_sdhci0();
128 s3c2416_default_sdhci1();
129
130 iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
131}
132
133/* need to register class before we actually register the device, and
134 * we also need to ensure that it has been initialised before any of the
135 * drivers even try to use it (even if not on an s3c2416 based system)
136 * as a driver which may support both 2443 and 2440 may try and use it.
137*/
138
139static int __init s3c2416_core_init(void)
140{
141 return sysdev_class_register(&s3c2416_sysclass);
142}
143
144core_initcall(s3c2416_core_init);
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
new file mode 100644
index 00000000000..f65cb3ef16c
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
@@ -0,0 +1,34 @@
1/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
2 *
3 * Copyright 2010 Promwad Innovation Company
4 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
5 *
6 * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * Based on mach-s3c64xx/setup-sdhci-gpio.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <mach/regs-gpio.h>
23#include <plat/gpio-cfg.h>
24
25void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
26{
27 s3c_gpio_cfgrange_nopull(S3C2410_GPE(5), 2 + width, S3C_GPIO_SFN(2));
28}
29
30void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
31{
32 s3c_gpio_cfgrange_nopull(S3C2410_GPL(0), width, S3C_GPIO_SFN(2));
33 s3c_gpio_cfgrange_nopull(S3C2410_GPL(8), 2, S3C_GPIO_SFN(2));
34}
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
new file mode 100644
index 00000000000..ed34fad8f2c
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci.c
@@ -0,0 +1,61 @@
1/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
2 *
3 * Copyright 2010 Promwad Innovation Company
4 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
5 *
6 * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * Based on mach-s3c64xx/setup-sdhci.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c2416_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "hsmmc-if",
33 /* [3] = "48m", - note not successfully used yet */
34};
35
36void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
60 __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
61}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-01 20:58:43 -0400