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1/* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/dm9000.h>
24#include <linux/ata_platform.h>
25#include <linux/i2c.h>
26#include <linux/io.h>
27
28#include <net/ax88796.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <mach/bast-map.h>
35#include <mach/bast-irq.h>
36#include <mach/bast-cpld.h>
37
38#include <mach/hardware.h>
39#include <asm/irq.h>
40#include <asm/mach-types.h>
41
42//#include <asm/debug-ll.h>
43#include <plat/regs-serial.h>
44#include <mach/regs-gpio.h>
45#include <mach/regs-mem.h>
46#include <mach/regs-lcd.h>
47
48#include <plat/hwmon.h>
49#include <plat/nand.h>
50#include <plat/iic.h>
51#include <mach/fb.h>
52
53#include <linux/mtd/mtd.h>
54#include <linux/mtd/nand.h>
55#include <linux/mtd/nand_ecc.h>
56#include <linux/mtd/partitions.h>
57
58#include <linux/serial_8250.h>
59
60#include <plat/clock.h>
61#include <plat/devs.h>
62#include <plat/cpu.h>
63#include <plat/cpu-freq.h>
64#include <plat/gpio-cfg.h>
65#include <plat/audio-simtec.h>
66
67#include "usb-simtec.h"
68#include "nor-simtec.h"
69
70#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
71
72/* macros for virtual address mods for the io space entries */
73#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
74#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
75#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
76#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
77
78/* macros to modify the physical addresses for io space */
79
80#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
81#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
82#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
83#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
84
85static struct map_desc bast_iodesc[] __initdata = {
86 /* ISA IO areas */
87 {
88 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
89 .pfn = PA_CS2(BAST_PA_ISAIO),
90 .length = SZ_16M,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (u32)S3C24XX_VA_ISA_WORD,
94 .pfn = PA_CS3(BAST_PA_ISAIO),
95 .length = SZ_16M,
96 .type = MT_DEVICE,
97 },
98 /* bast CPLD control registers, and external interrupt controls */
99 {
100 .virtual = (u32)BAST_VA_CTRL1,
101 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
102 .length = SZ_1M,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (u32)BAST_VA_CTRL2,
106 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
107 .length = SZ_1M,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (u32)BAST_VA_CTRL3,
111 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
112 .length = SZ_1M,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (u32)BAST_VA_CTRL4,
116 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
117 .length = SZ_1M,
118 .type = MT_DEVICE,
119 },
120 /* PC104 IRQ mux */
121 {
122 .virtual = (u32)BAST_VA_PC104_IRQREQ,
123 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
124 .length = SZ_1M,
125 .type = MT_DEVICE,
126 }, {
127 .virtual = (u32)BAST_VA_PC104_IRQRAW,
128 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
129 .length = SZ_1M,
130 .type = MT_DEVICE,
131 }, {
132 .virtual = (u32)BAST_VA_PC104_IRQMASK,
133 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
134 .length = SZ_1M,
135 .type = MT_DEVICE,
136 },
137
138 /* peripheral space... one for each of fast/slow/byte/16bit */
139 /* note, ide is only decoded in word space, even though some registers
140 * are only 8bit */
141
142 /* slow, byte */
143 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
144 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
145 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
146
147 /* slow, word */
148 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
149 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
150 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
151
152 /* fast, byte */
153 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
154 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
155 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
156
157 /* fast, word */
158 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
159 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
160 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
161};
162
163#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
164#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
165#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
166
167static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
168 [0] = {
169 .name = "uclk",
170 .divisor = 1,
171 .min_baud = 0,
172 .max_baud = 0,
173 },
174 [1] = {
175 .name = "pclk",
176 .divisor = 1,
177 .min_baud = 0,
178 .max_baud = 0,
179 }
180};
181
182
183static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
184 [0] = {
185 .hwport = 0,
186 .flags = 0,
187 .ucon = UCON,
188 .ulcon = ULCON,
189 .ufcon = UFCON,
190 .clocks = bast_serial_clocks,
191 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
192 },
193 [1] = {
194 .hwport = 1,
195 .flags = 0,
196 .ucon = UCON,
197 .ulcon = ULCON,
198 .ufcon = UFCON,
199 .clocks = bast_serial_clocks,
200 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
201 },
202 /* port 2 is not actually used */
203 [2] = {
204 .hwport = 2,
205 .flags = 0,
206 .ucon = UCON,
207 .ulcon = ULCON,
208 .ufcon = UFCON,
209 .clocks = bast_serial_clocks,
210 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
211 }
212};
213
214/* NAND Flash on BAST board */
215
216#ifdef CONFIG_PM
217static int bast_pm_suspend(void)
218{
219 /* ensure that an nRESET is not generated on resume. */
220 gpio_direction_output(S3C2410_GPA(21), 1);
221 return 0;
222}
223
224static void bast_pm_resume(void)
225{
226 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
227}
228
229#else
230#define bast_pm_suspend NULL
231#define bast_pm_resume NULL
232#endif
233
234static struct syscore_ops bast_pm_syscore_ops = {
235 .suspend = bast_pm_suspend,
236 .resume = bast_pm_resume,
237};
238
239static int smartmedia_map[] = { 0 };
240static int chip0_map[] = { 1 };
241static int chip1_map[] = { 2 };
242static int chip2_map[] = { 3 };
243
244static struct mtd_partition __initdata bast_default_nand_part[] = {
245 [0] = {
246 .name = "Boot Agent",
247 .size = SZ_16K,
248 .offset = 0,
249 },
250 [1] = {
251 .name = "/boot",
252 .size = SZ_4M - SZ_16K,
253 .offset = SZ_16K,
254 },
255 [2] = {
256 .name = "user",
257 .offset = SZ_4M,
258 .size = MTDPART_SIZ_FULL,
259 }
260};
261
262/* the bast has 4 selectable slots for nand-flash, the three
263 * on-board chip areas, as well as the external SmartMedia
264 * slot.
265 *
266 * Note, there is no current hot-plug support for the SmartMedia
267 * socket.
268*/
269
270static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
271 [0] = {
272 .name = "SmartMedia",
273 .nr_chips = 1,
274 .nr_map = smartmedia_map,
275 .options = NAND_SCAN_SILENT_NODEV,
276 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
277 .partitions = bast_default_nand_part,
278 },
279 [1] = {
280 .name = "chip0",
281 .nr_chips = 1,
282 .nr_map = chip0_map,
283 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
284 .partitions = bast_default_nand_part,
285 },
286 [2] = {
287 .name = "chip1",
288 .nr_chips = 1,
289 .nr_map = chip1_map,
290 .options = NAND_SCAN_SILENT_NODEV,
291 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
292 .partitions = bast_default_nand_part,
293 },
294 [3] = {
295 .name = "chip2",
296 .nr_chips = 1,
297 .nr_map = chip2_map,
298 .options = NAND_SCAN_SILENT_NODEV,
299 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
300 .partitions = bast_default_nand_part,
301 }
302};
303
304static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
305{
306 unsigned int tmp;
307
308 slot = set->nr_map[slot] & 3;
309
310 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
311 slot, set, set->nr_map);
312
313 tmp = __raw_readb(BAST_VA_CTRL2);
314 tmp &= BAST_CPLD_CTLR2_IDERST;
315 tmp |= slot;
316 tmp |= BAST_CPLD_CTRL2_WNAND;
317
318 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
319
320 __raw_writeb(tmp, BAST_VA_CTRL2);
321}
322
323static struct s3c2410_platform_nand __initdata bast_nand_info = {
324 .tacls = 30,
325 .twrph0 = 60,
326 .twrph1 = 60,
327 .nr_sets = ARRAY_SIZE(bast_nand_sets),
328 .sets = bast_nand_sets,
329 .select_chip = bast_nand_select,
330};
331
332/* DM9000 */
333
334static struct resource bast_dm9k_resource[] = {
335 [0] = {
336 .start = S3C2410_CS5 + BAST_PA_DM9000,
337 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
338 .flags = IORESOURCE_MEM,
339 },
340 [1] = {
341 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
342 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
343 .flags = IORESOURCE_MEM,
344 },
345 [2] = {
346 .start = IRQ_DM9000,
347 .end = IRQ_DM9000,
348 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
349 }
350
351};
352
353/* for the moment we limit ourselves to 16bit IO until some
354 * better IO routines can be written and tested
355*/
356
357static struct dm9000_plat_data bast_dm9k_platdata = {
358 .flags = DM9000_PLATF_16BITONLY,
359};
360
361static struct platform_device bast_device_dm9k = {
362 .name = "dm9000",
363 .id = 0,
364 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
365 .resource = bast_dm9k_resource,
366 .dev = {
367 .platform_data = &bast_dm9k_platdata,
368 }
369};
370
371/* serial devices */
372
373#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
374#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
375#define SERIAL_CLK (1843200)
376
377static struct plat_serial8250_port bast_sio_data[] = {
378 [0] = {
379 .mapbase = SERIAL_BASE + 0x2f8,
380 .irq = IRQ_PCSERIAL1,
381 .flags = SERIAL_FLAGS,
382 .iotype = UPIO_MEM,
383 .regshift = 0,
384 .uartclk = SERIAL_CLK,
385 },
386 [1] = {
387 .mapbase = SERIAL_BASE + 0x3f8,
388 .irq = IRQ_PCSERIAL2,
389 .flags = SERIAL_FLAGS,
390 .iotype = UPIO_MEM,
391 .regshift = 0,
392 .uartclk = SERIAL_CLK,
393 },
394 { }
395};
396
397static struct platform_device bast_sio = {
398 .name = "serial8250",
399 .id = PLAT8250_DEV_PLATFORM,
400 .dev = {
401 .platform_data = &bast_sio_data,
402 },
403};
404
405/* we have devices on the bus which cannot work much over the
406 * standard 100KHz i2c bus frequency
407*/
408
409static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
410 .flags = 0,
411 .slave_addr = 0x10,
412 .frequency = 100*1000,
413};
414
415/* Asix AX88796 10/100 ethernet controller */
416
417static struct ax_plat_data bast_asix_platdata = {
418 .flags = AXFLG_MAC_FROMDEV,
419 .wordlength = 2,
420 .dcr_val = 0x48,
421 .rcr_val = 0x40,
422};
423
424static struct resource bast_asix_resource[] = {
425 [0] = {
426 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
427 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 [1] = {
431 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
432 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
433 .flags = IORESOURCE_MEM,
434 },
435 [2] = {
436 .start = IRQ_ASIX,
437 .end = IRQ_ASIX,
438 .flags = IORESOURCE_IRQ
439 }
440};
441
442static struct platform_device bast_device_asix = {
443 .name = "ax88796",
444 .id = 0,
445 .num_resources = ARRAY_SIZE(bast_asix_resource),
446 .resource = bast_asix_resource,
447 .dev = {
448 .platform_data = &bast_asix_platdata
449 }
450};
451
452/* Asix AX88796 10/100 ethernet controller parallel port */
453
454static struct resource bast_asixpp_resource[] = {
455 [0] = {
456 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
457 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
458 .flags = IORESOURCE_MEM,
459 }
460};
461
462static struct platform_device bast_device_axpp = {
463 .name = "ax88796-pp",
464 .id = 0,
465 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
466 .resource = bast_asixpp_resource,
467};
468
469/* LCD/VGA controller */
470
471static struct s3c2410fb_display __initdata bast_lcd_info[] = {
472 {
473 .type = S3C2410_LCDCON1_TFT,
474 .width = 640,
475 .height = 480,
476
477 .pixclock = 33333,
478 .xres = 640,
479 .yres = 480,
480 .bpp = 4,
481 .left_margin = 40,
482 .right_margin = 20,
483 .hsync_len = 88,
484 .upper_margin = 30,
485 .lower_margin = 32,
486 .vsync_len = 3,
487
488 .lcdcon5 = 0x00014b02,
489 },
490 {
491 .type = S3C2410_LCDCON1_TFT,
492 .width = 640,
493 .height = 480,
494
495 .pixclock = 33333,
496 .xres = 640,
497 .yres = 480,
498 .bpp = 8,
499 .left_margin = 40,
500 .right_margin = 20,
501 .hsync_len = 88,
502 .upper_margin = 30,
503 .lower_margin = 32,
504 .vsync_len = 3,
505
506 .lcdcon5 = 0x00014b02,
507 },
508 {
509 .type = S3C2410_LCDCON1_TFT,
510 .width = 640,
511 .height = 480,
512
513 .pixclock = 33333,
514 .xres = 640,
515 .yres = 480,
516 .bpp = 16,
517 .left_margin = 40,
518 .right_margin = 20,
519 .hsync_len = 88,
520 .upper_margin = 30,
521 .lower_margin = 32,
522 .vsync_len = 3,
523
524 .lcdcon5 = 0x00014b02,
525 },
526};
527
528/* LCD/VGA controller */
529
530static struct s3c2410fb_mach_info __initdata bast_fb_info = {
531
532 .displays = bast_lcd_info,
533 .num_displays = ARRAY_SIZE(bast_lcd_info),
534 .default_display = 1,
535};
536
537/* I2C devices fitted. */
538
539static struct i2c_board_info bast_i2c_devs[] __initdata = {
540 {
541 I2C_BOARD_INFO("tlv320aic23", 0x1a),
542 }, {
543 I2C_BOARD_INFO("simtec-pmu", 0x6b),
544 }, {
545 I2C_BOARD_INFO("ch7013", 0x75),
546 },
547};
548
549static struct s3c_hwmon_pdata bast_hwmon_info = {
550 /* LCD contrast (0-6.6V) */
551 .in[0] = &(struct s3c_hwmon_chcfg) {
552 .name = "lcd-contrast",
553 .mult = 3300,
554 .div = 512,
555 },
556 /* LED current feedback */
557 .in[1] = &(struct s3c_hwmon_chcfg) {
558 .name = "led-feedback",
559 .mult = 3300,
560 .div = 1024,
561 },
562 /* LCD feedback (0-6.6V) */
563 .in[2] = &(struct s3c_hwmon_chcfg) {
564 .name = "lcd-feedback",
565 .mult = 3300,
566 .div = 512,
567 },
568 /* Vcore (1.8-2.0V), Vref 3.3V */
569 .in[3] = &(struct s3c_hwmon_chcfg) {
570 .name = "vcore",
571 .mult = 3300,
572 .div = 1024,
573 },
574};
575
576/* Standard BAST devices */
577// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
578
579static struct platform_device *bast_devices[] __initdata = {
580 &s3c_device_ohci,
581 &s3c_device_lcd,
582 &s3c_device_wdt,
583 &s3c_device_i2c0,
584 &s3c_device_rtc,
585 &s3c_device_nand,
586 &s3c_device_adc,
587 &s3c_device_hwmon,
588 &bast_device_dm9k,
589 &bast_device_asix,
590 &bast_device_axpp,
591 &bast_sio,
592};
593
594static struct clk *bast_clocks[] __initdata = {
595 &s3c24xx_dclk0,
596 &s3c24xx_dclk1,
597 &s3c24xx_clkout0,
598 &s3c24xx_clkout1,
599 &s3c24xx_uclk,
600};
601
602static struct s3c_cpufreq_board __initdata bast_cpufreq = {
603 .refresh = 7800, /* 7.8usec */
604 .auto_io = 1,
605 .need_io = 1,
606};
607
608static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
609 .have_mic = 1,
610 .have_lout = 1,
611};
612
613static void __init bast_map_io(void)
614{
615 /* initialise the clocks */
616
617 s3c24xx_dclk0.parent = &clk_upll;
618 s3c24xx_dclk0.rate = 12*1000*1000;
619
620 s3c24xx_dclk1.parent = &clk_upll;
621 s3c24xx_dclk1.rate = 24*1000*1000;
622
623 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
624 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
625
626 s3c24xx_uclk.parent = &s3c24xx_clkout1;
627
628 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
629
630 s3c_hwmon_set_platdata(&bast_hwmon_info);
631
632 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
633 s3c24xx_init_clocks(0);
634 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
635}
636
637static void __init bast_init(void)
638{
639 register_syscore_ops(&bast_pm_syscore_ops);
640
641 s3c_i2c0_set_platdata(&bast_i2c_info);
642 s3c_nand_set_platdata(&bast_nand_info);
643 s3c24xx_fb_set_platdata(&bast_fb_info);
644 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
645
646 i2c_register_board_info(0, bast_i2c_devs,
647 ARRAY_SIZE(bast_i2c_devs));
648
649 usb_simtec_init();
650 nor_simtec_init();
651 simtec_audio_add(NULL, true, &bast_audio);
652
653 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
654
655 s3c_cpufreq_setboard(&bast_cpufreq);
656}
657
658MACHINE_START(BAST, "Simtec-BAST")
659 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
660 .boot_params = S3C2410_SDRAM_PA + 0x100,
661 .map_io = bast_map_io,
662 .init_irq = s3c24xx_init_irq,
663 .init_machine = bast_init,
664 .timer = &s3c24xx_timer,
665MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 17:51:11 -0400