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-rw-r--r--arch/arm/mach-pxa/include/mach/corgi.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mmc.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h375
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h134
-rw-r--r--arch/arm/mach-pxa/include/mach/ssp.h109
-rw-r--r--arch/arm/mach-pxa/include/mach/tosa.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/vpac270.h42
-rw-r--r--arch/arm/mach-pxa/include/mach/z2.h41
9 files changed, 87 insertions, 621 deletions
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 7239281788d..585970ef08c 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -113,7 +113,6 @@
113 * Shared data structures 113 * Shared data structures
114 */ 114 */
115extern struct platform_device corgiscoop_device; 115extern struct platform_device corgiscoop_device;
116extern struct platform_device corgissp_device;
117 116
118#endif /* __ASM_ARCH_CORGI_H */ 117#endif /* __ASM_ARCH_CORGI_H */
119 118
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index 658b28ed129..c54cef25895 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -25,6 +25,8 @@
25#define MFP_DIR(x) (((x) >> 23) & 0x1) 25#define MFP_DIR(x) (((x) >> 23) & 0x1)
26 26
27#define MFP_LPM_CAN_WAKEUP (0x1 << 24) 27#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
28#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
29
28#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) 30#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
29#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) 31#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
30#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) 32#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h
index 02a69dc2ee6..9eb515bb799 100644
--- a/arch/arm/mach-pxa/include/mach/mmc.h
+++ b/arch/arm/mach-pxa/include/mach/mmc.h
@@ -9,7 +9,7 @@ struct mmc_host;
9 9
10struct pxamci_platform_data { 10struct pxamci_platform_data {
11 unsigned int ocr_mask; /* available voltages */ 11 unsigned int ocr_mask; /* available voltages */
12 unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */ 12 unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
13 int (*init)(struct device *, irq_handler_t , void *); 13 int (*init)(struct device *, irq_handler_t , void *);
14 int (*get_ro)(struct device *); 14 int (*get_ro)(struct device *);
15 void (*setpower)(struct device *, unsigned int); 15 void (*setpower)(struct device *, unsigned int);
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
deleted file mode 100644
index 1209c44aa6f..00000000000
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ /dev/null
@@ -1,375 +0,0 @@
1#ifndef __ASM_ARCH_PXA2XX_GPIO_H
2#define __ASM_ARCH_PXA2XX_GPIO_H
3
4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
5
6#include <mach/gpio.h>
7
8/* GPIO alternate function assignments */
9
10#define GPIO1_RST 1 /* reset */
11#define GPIO6_MMCCLK 6 /* MMC Clock */
12#define GPIO7_48MHz 7 /* 48 MHz clock output */
13#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
14#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
15#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
16#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
17#define GPIO12_32KHz 12 /* 32 kHz out */
18#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */
19#define GPIO13_MBGNT 13 /* memory controller grant */
20#define GPIO14_MBREQ 14 /* alternate bus master request */
21#define GPIO15_nCS_1 15 /* chip select 1 */
22#define GPIO16_PWM0 16 /* PWM0 output */
23#define GPIO17_PWM1 17 /* PWM1 output */
24#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */
25#define GPIO18_RDY 18 /* Ext. Bus Ready */
26#define GPIO19_DREQ1 19 /* External DMA Request */
27#define GPIO20_DREQ0 20 /* External DMA Request */
28#define GPIO23_SCLK 23 /* SSP clock */
29#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */
30#define GPIO24_SFRM 24 /* SSP Frame */
31#define GPIO24_CIF_FV 24 /* Camera frame start signal */
32#define GPIO25_STXD 25 /* SSP transmit */
33#define GPIO25_CIF_LV 25 /* Camera line start signal */
34#define GPIO26_SRXD 26 /* SSP receive */
35#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */
36#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
37#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */
38#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
39#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
40#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
41#define GPIO31_SYNC 31 /* AC97/I2S sync */
42#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
43#define GPIO32_SYSCLK 32 /* I2S System Clock */
44#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
45#define GPIO33_nCS_5 33 /* chip select 5 */
46#define GPIO34_FFRXD 34 /* FFUART receive */
47#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
48#define GPIO35_FFCTS 35 /* FFUART Clear to send */
49#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
50#define GPIO37_FFDSR 37 /* FFUART data set ready */
51#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
52#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
53#define GPIO39_FFTXD 39 /* FFUART transmit data */
54#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
55#define GPIO41_FFRTS 41 /* FFUART request to send */
56#define GPIO42_BTRXD 42 /* BTUART receive data */
57#define GPIO42_HWRXD 42 /* HWUART receive data */
58#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */
59#define GPIO43_BTTXD 43 /* BTUART transmit data */
60#define GPIO43_HWTXD 43 /* HWUART transmit data */
61#define GPIO43_CIF_FV 43 /* Camera frame start signal */
62#define GPIO44_BTCTS 44 /* BTUART clear to send */
63#define GPIO44_HWCTS 44 /* HWUART clear to send */
64#define GPIO44_CIF_LV 44 /* Camera line start signal */
65#define GPIO45_BTRTS 45 /* BTUART request to send */
66#define GPIO45_HWRTS 45 /* HWUART request to send */
67#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
68#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */
69#define GPIO46_ICPRXD 46 /* ICP receive data */
70#define GPIO46_STRXD 46 /* STD_UART receive data */
71#define GPIO47_ICPTXD 47 /* ICP transmit data */
72#define GPIO47_STTXD 47 /* STD_UART transmit data */
73#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */
74#define GPIO48_nPOE 48 /* Output Enable for Card Space */
75#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */
76#define GPIO49_nPWE 49 /* Write Enable for Card Space */
77#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
78#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
79#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
80#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */
81#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
82#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */
83#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
84#define GPIO53_MMCCLK 53 /* MMC Clock */
85#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */
86#define GPIO54_MMCCLK 54 /* MMC Clock */
87#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
88#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
89#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */
90#define GPIO55_nPREG 55 /* Card Address bit 26 */
91#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */
92#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
93#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
94#define GPIO58_LDD_0 58 /* LCD data pin 0 */
95#define GPIO59_LDD_1 59 /* LCD data pin 1 */
96#define GPIO60_LDD_2 60 /* LCD data pin 2 */
97#define GPIO61_LDD_3 61 /* LCD data pin 3 */
98#define GPIO62_LDD_4 62 /* LCD data pin 4 */
99#define GPIO63_LDD_5 63 /* LCD data pin 5 */
100#define GPIO64_LDD_6 64 /* LCD data pin 6 */
101#define GPIO65_LDD_7 65 /* LCD data pin 7 */
102#define GPIO66_LDD_8 66 /* LCD data pin 8 */
103#define GPIO66_MBREQ 66 /* alternate bus master req */
104#define GPIO67_LDD_9 67 /* LCD data pin 9 */
105#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
106#define GPIO68_LDD_10 68 /* LCD data pin 10 */
107#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
108#define GPIO69_LDD_11 69 /* LCD data pin 11 */
109#define GPIO69_MMCCLK 69 /* MMC_CLK */
110#define GPIO70_LDD_12 70 /* LCD data pin 12 */
111#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
112#define GPIO71_LDD_13 71 /* LCD data pin 13 */
113#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
114#define GPIO72_LDD_14 72 /* LCD data pin 14 */
115#define GPIO72_32kHz 72 /* 32 kHz clock */
116#define GPIO73_LDD_15 73 /* LCD data pin 15 */
117#define GPIO73_MBGNT 73 /* Memory controller grant */
118#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
119#define GPIO75_LCD_LCLK 75 /* LCD line clock */
120#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
121#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
122#define GPIO78_nCS_2 78 /* chip select 2 */
123#define GPIO79_nCS_3 79 /* chip select 3 */
124#define GPIO80_nCS_4 80 /* chip select 4 */
125#define GPIO81_NSCLK 81 /* NSSP clock */
126#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */
127#define GPIO82_NSFRM 82 /* NSSP Frame */
128#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
129#define GPIO83_NSTXD 83 /* NSSP transmit */
130#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */
131#define GPIO84_NSRXD 84 /* NSSP receive */
132#define GPIO84_CIF_FV 84 /* Camera frame start signal */
133#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
134#define GPIO85_CIF_LV 85 /* Camera line start signal */
135#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */
136#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */
137#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
138#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
139#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
140#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
141#define GPIO96_FFRXD 96 /* FFUART recieve */
142#define GPIO98_FFRTS 98 /* FFUART request to send */
143#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
144#define GPIO99_FFTXD 99 /* FFUART transmit data */
145#define GPIO100_FFCTS 100 /* FFUART Clear to send */
146#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
147#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
148#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
149#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */
150#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */
151#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */
152#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */
153#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
154#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
155#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
156#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
157#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
158#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
159#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
160#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
161#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */
162#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */
163#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */
164
165/* GPIO alternate function mode & direction */
166
167#define GPIO_IN 0x000
168#define GPIO_OUT 0x080
169#define GPIO_ALT_FN_1_IN 0x100
170#define GPIO_ALT_FN_1_OUT 0x180
171#define GPIO_ALT_FN_2_IN 0x200
172#define GPIO_ALT_FN_2_OUT 0x280
173#define GPIO_ALT_FN_3_IN 0x300
174#define GPIO_ALT_FN_3_OUT 0x380
175#define GPIO_MD_MASK_NR 0x07f
176#define GPIO_MD_MASK_DIR 0x080
177#define GPIO_MD_MASK_FN 0x300
178#define GPIO_DFLT_LOW 0x400
179#define GPIO_DFLT_HIGH 0x800
180
181#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
182#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
183#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
184#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
185#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
186#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
187#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
188#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
189#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN)
190#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
191#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
192#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
193#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
194#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
195#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN)
196#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
197#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
198#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
199#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT)
200#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
201#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT)
202#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
203#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT)
204#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
205#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
206#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN)
207#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
208#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN)
209#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
210#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
211#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
212#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
213#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
214#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
215#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
216#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
217#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
218#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
219#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
220#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT)
221#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
222#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
223#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
224#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
225#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT)
226#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
227#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
228#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
229#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
230#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
231#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
232#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
233#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
234#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
235#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
236#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT)
237#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
238#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
239#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT)
240#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
241#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
242#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT)
243#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN)
244#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
245#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
246#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
247#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
248#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
249#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN)
250#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
251#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
252#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN)
253#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
254#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
255#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
256#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
257#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
258#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
259#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
260#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
261#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
262#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
263#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
264#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
265#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
266#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
267#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN)
268#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
269#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
270#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT)
271#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
272#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
273#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
274#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN)
275#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
276#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN)
277#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
278#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
279#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
280#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
281#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
282#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
283#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
284#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
285#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
286#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
287#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
288#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
289#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
290#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
291#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
292#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
293#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
294#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
295#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
296#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
297#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
298#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
299#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
300#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
301#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
302#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
303#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
304#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
305#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
306#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
307#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
308#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT)
309#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
310#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
311#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
312#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
313#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
314#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN)
315#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
316#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
317#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
318#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
319#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
320#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN)
321#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
322#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
323#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
324#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
325#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
326#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
327#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
328#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
329#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
330#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
331#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
332#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN)
333#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN)
334#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
335#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
336#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
337#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN)
338#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
339#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
340#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT)
341#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT)
342#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
343#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
344#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
345#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
346#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN)
347#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
348#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN)
349#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
350#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
351#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN)
352#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
353#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN)
354#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
355#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN)
356#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
357#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN)
358#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
359#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
360#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
361#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
362#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
363#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
364#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
365#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
366#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
367#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
368#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
369
370/*
371 * Handy routine to set GPIO alternate functions
372 */
373extern int pxa_gpio_mode( int gpio_mode );
374
375#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
deleted file mode 100644
index 6a2ed35acd5..00000000000
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,134 +0,0 @@
1#ifndef __ASM_ARCH_REGS_SSP_H
2#define __ASM_ARCH_REGS_SSP_H
3
4/*
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */
9
10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
27/* Common PXA2xx bits first */
28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
30#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
31#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
32#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
33#define SSCR0_National (0x2 << 4) /* National Microwire */
34#define SSCR0_ECS (1 << 6) /* External clock select */
35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
42#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
43#endif
44
45#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
46#define SSCR0_EDSS (1 << 20) /* Extended data size select */
47#define SSCR0_NCS (1 << 21) /* Network clock select */
48#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
49#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
50#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
51#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
52#define SSCR0_ACS (1 << 30) /* Audio clock select */
53#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
54#endif
55
56#if defined(CONFIG_PXA3xx)
57#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
58#endif
59
60#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
61#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
62#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
63#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
64#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
65#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
66#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
67#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
68#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
69#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
70
71#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
72#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
73#define SSSR_BSY (1 << 4) /* SSP Busy */
74#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
75#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
76#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
77
78#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
79#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
80#define SSCR0_NCS (1 << 21) /* Network Clock Select */
81#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
82
83/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
84#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
85#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
86#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
87#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
88#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
89#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
90#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
91#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
92#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
93#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
94#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
95#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
96#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
97#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
98#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
99#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
100#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
101#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
102#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
103
104#define SSSR_BCE (1 << 23) /* Bit Count Error */
105#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
106#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
107#define SSSR_EOC (1 << 20) /* End Of Chain */
108#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
109#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
110
111#if defined(CONFIG_PXA3xx)
112#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
113#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
114#endif
115
116#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
117#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
118#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
119#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
120#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
121#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
122#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
123#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
124#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
125
126#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
127#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
128#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
129#if defined(CONFIG_PXA3xx)
130#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
131#endif
132
133
134#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
deleted file mode 100644
index be1be5b6db5..00000000000
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver supports the following PXA CPU/SSP ports:-
11 *
12 * PXA250 SSP
13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
17 */
18
19#ifndef __ASM_ARCH_SSP_H
20#define __ASM_ARCH_SSP_H
21
22#include <linux/list.h>
23#include <linux/io.h>
24
25enum pxa_ssp_type {
26 SSP_UNDEFINED = 0,
27 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
28 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
29 PXA27x_SSP,
30};
31
32struct ssp_device {
33 struct platform_device *pdev;
34 struct list_head node;
35
36 struct clk *clk;
37 void __iomem *mmio_base;
38 unsigned long phys_base;
39
40 const char *label;
41 int port_id;
42 int type;
43 int use_count;
44 int irq;
45 int drcmr_rx;
46 int drcmr_tx;
47};
48
49#ifdef CONFIG_PXA_SSP_LEGACY
50/*
51 * SSP initialisation flags
52 */
53#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */
54
55struct ssp_state {
56 u32 cr0;
57 u32 cr1;
58 u32 to;
59 u32 psp;
60};
61
62struct ssp_dev {
63 struct ssp_device *ssp;
64 u32 port;
65 u32 mode;
66 u32 flags;
67 u32 psp_flags;
68 u32 speed;
69 int irq;
70};
71
72int ssp_write_word(struct ssp_dev *dev, u32 data);
73int ssp_read_word(struct ssp_dev *dev, u32 *data);
74int ssp_flush(struct ssp_dev *dev);
75void ssp_enable(struct ssp_dev *dev);
76void ssp_disable(struct ssp_dev *dev);
77void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
78void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
79int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
80int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
81void ssp_exit(struct ssp_dev *dev);
82#endif /* CONFIG_PXA_SSP_LEGACY */
83
84/**
85 * ssp_write_reg - Write to a SSP register
86 *
87 * @dev: SSP device to access
88 * @reg: Register to write to
89 * @val: Value to be written.
90 */
91static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
92{
93 __raw_writel(val, dev->mmio_base + reg);
94}
95
96/**
97 * ssp_read_reg - Read from a SSP register
98 *
99 * @dev: SSP device to access
100 * @reg: Register to read from
101 */
102static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
103{
104 return __raw_readl(dev->mmio_base + reg);
105}
106
107struct ssp_device *ssp_request(int port, const char *label);
108void ssp_free(struct ssp_device *);
109#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 4df2d38507d..1bbd1f2e4be 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -167,7 +167,7 @@
167 167
168#define TOSA_KEY_SYNC KEY_102ND /* ??? */ 168#define TOSA_KEY_SYNC KEY_102ND /* ??? */
169 169
170#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES 170#ifndef CONFIG_TOSA_USE_EXT_KEYCODES
171#define TOSA_KEY_RECORD KEY_YEN 171#define TOSA_KEY_RECORD KEY_YEN
172#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA 172#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
173#define TOSA_KEY_CANCEL KEY_ESC 173#define TOSA_KEY_CANCEL KEY_ESC
diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h
new file mode 100644
index 00000000000..7bfa3dd0fd5
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/vpac270.h
@@ -0,0 +1,42 @@
1/*
2 * GPIOs and interrupts for Voipac PXA270
3 *
4 * Copyright (C) 2010
5 * Marek Vasut <marek.vasut@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _INCLUDE_VPAC270_H_
14#define _INCLUDE_VPAC270_H_
15
16#define GPIO1_VPAC270_USER_BTN 1
17
18#define GPIO15_VPAC270_LED_ORANGE 15
19
20#define GPIO81_VPAC270_BKL_ON 81
21#define GPIO83_VPAC270_NL_ON 83
22
23#define GPIO52_VPAC270_SD_READONLY 52
24#define GPIO53_VPAC270_SD_DETECT_N 53
25
26#define GPIO84_VPAC270_PCMCIA_CD 84
27#define GPIO35_VPAC270_PCMCIA_RDY 35
28#define GPIO107_VPAC270_PCMCIA_PPEN 107
29#define GPIO11_VPAC270_PCMCIA_RESET 11
30#define GPIO17_VPAC270_CF_CD 17
31#define GPIO12_VPAC270_CF_RDY 12
32#define GPIO16_VPAC270_CF_RESET 16
33
34#define GPIO41_VPAC270_UDC_DETECT 41
35
36#define GPIO114_VPAC270_ETH_IRQ 114
37
38#define GPIO36_VPAC270_IDE_IRQ 36
39
40#define GPIO113_VPAC270_TS_IRQ 113
41
42#endif
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h
new file mode 100644
index 00000000000..8835c16bc82
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/z2.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-pxa/include/mach/z2.h
3 *
4 * Author: Ken McGuire
5 * Created: Feb 6, 2009
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef ASM_ARCH_ZIPIT2_H
13#define ASM_ARCH_ZIPIT2_H
14
15/* LEDs */
16#define GPIO10_ZIPITZ2_LED_WIFI 10
17#define GPIO85_ZIPITZ2_LED_CHARGED 85
18#define GPIO83_ZIPITZ2_LED_CHARGING 83
19
20/* SD/MMC */
21#define GPIO96_ZIPITZ2_SD_DETECT 96
22
23/* GPIO Buttons */
24#define GPIO1_ZIPITZ2_POWER_BUTTON 1
25#define GPIO98_ZIPITZ2_LID_BUTTON 98
26
27/* Libertas GSPI8686 WiFi */
28#define GPIO14_ZIPITZ2_WIFI_RESET 14
29#define GPIO15_ZIPITZ2_WIFI_POWER 15
30#define GPIO24_ZIPITZ2_WIFI_CS 24
31#define GPIO36_ZIPITZ2_WIFI_IRQ 36
32
33/* LCD */
34#define GPIO19_ZIPITZ2_LCD_RESET 19
35#define GPIO88_ZIPITZ2_LCD_CS 88
36
37/* MISC GPIOs */
38#define GPIO0_ZIPITZ2_AC_DETECT 0
39#define GPIO37_ZIPITZ2_HEADSET_DETECT 37
40
41#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 20:11:13 -0500