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-rw-r--r--arch/arm/mach-orion5x/mpp.h191
1 files changed, 123 insertions, 68 deletions
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610dc01..eac68978a2c 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
1#ifndef __ARCH_ORION5X_MPP_H 1#ifndef __ARCH_ORION5X_MPP_H
2#define __ARCH_ORION5X_MPP_H 2#define __ARCH_ORION5X_MPP_H
3 3
4enum orion5x_mpp_type { 4#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
5 /* 5 /* MPP number */ ((_num) & 0xff) | \
6 * This MPP is unused. 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7 */ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8 MPP_UNUSED, 8 /* may be output signal */ ((!!(_out)) << 13) | \
9 9 /* available on F5181l */ ((!!(_F5181l)) << 14) | \
10 /* 10 /* available on F5182 */ ((!!(_F5182)) << 15) | \
11 * This MPP pin is used as a generic GPIO pin. Valid for 11 /* available on F5281 */ ((!!(_F5281)) << 16))
12 * MPPs 0-15 and device bus data pins 16-31. On 5182, also
13 * valid for MPPs 16-19.
14 */
15 MPP_GPIO,
16
17 /*
18 * This MPP is used as PCIe_RST_OUTn pin. Valid for
19 * MPP 0 only.
20 */
21 MPP_PCIE_RST_OUTn,
22
23 /*
24 * This MPP is used as PCI arbiter pin (REQn/GNTn).
25 * Valid for MPPs 0-7 only.
26 */
27 MPP_PCI_ARB,
28
29 /*
30 * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
31 */
32 MPP_PCI_PMEn,
33
34 /*
35 * This MPP is used as GigE half-duplex (COL, CRS) or GMII
36 * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
37 * MPPs 8-19 only.
38 */
39 MPP_GIGE,
40
41 /*
42 * This MPP is used as NAND REn/WEn pin. Valid for MPPs
43 * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
44 */
45 MPP_NAND,
46
47 /*
48 * This MPP is used as a PCI clock output pin. Valid for
49 * MPPs 6-7 only, and only on the 5181l.
50 */
51 MPP_PCI_CLK,
52
53 /*
54 * This MPP is used as a SATA presence/activity LED.
55 * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
56 */
57 MPP_SATA_LED,
58
59 /*
60 * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
61 * Valid for MPPs 16-19 only.
62 */
63 MPP_UART,
64};
65
66struct orion5x_mpp_mode {
67 int mpp;
68 enum orion5x_mpp_type type;
69};
70
71void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
72 12
13 /* num sel i o 5181 5182 5281 */
14
15#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
16#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
17#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
18
19#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
20#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
21#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
22#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
23
24#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
25#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
26#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
27
28#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
29#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
30#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
31#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
32
33#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
34#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
35#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
36
37#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
38#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
39#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
40#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
41#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
42
43#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
44#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
45#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
46#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
47#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
48
49#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
50#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
51#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
52#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
53#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
54#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
55
56#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
57#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
58#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
59#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
60#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
61#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
62
63#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
64#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
65#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
66
67#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
68#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
69#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
70
71#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
72#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
73#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
74
75#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
76#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
77#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
78
79#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
80#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
81#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
82#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
83#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
84
85#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
86#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
87#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
88#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
89#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
90
91#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
92#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
93#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
94#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
95#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
96
97#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
98#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
99#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
100#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
101#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
102
103#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
104#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
105#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
106#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
107#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
108
109#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
110#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
111#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
112#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
113#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
114
115#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
116#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
117#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
118#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
119
120#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
121#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
122#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
123#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
124
125#define MPP_MAX 19
126
127void orion5x_mpp_conf(unsigned int *mpp_list);
73 128
74#endif 129#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 15:18:23 -0400