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-rw-r--r--arch/arm/mach-omap2/voltage.c1020
1 files changed, 278 insertions, 742 deletions
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 12be525b8df..c6facf7becf 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -7,8 +7,9 @@
7 * Rajendra Nayak <rnayak@ti.com> 7 * Rajendra Nayak <rnayak@ti.com>
8 * Lesly A M <x0080970@ti.com> 8 * Lesly A M <x0080970@ti.com>
9 * 9 *
10 * Copyright (C) 2008 Nokia Corporation 10 * Copyright (C) 2008, 2011 Nokia Corporation
11 * Kalle Jokiniemi 11 * Kalle Jokiniemi
12 * Paul Walmsley
12 * 13 *
13 * Copyright (C) 2010 Texas Instruments, Inc. 14 * Copyright (C) 2010 Texas Instruments, Inc.
14 * Thara Gopinath <thara@ti.com> 15 * Thara Gopinath <thara@ti.com>
@@ -26,7 +27,6 @@
26#include <linux/slab.h> 27#include <linux/slab.h>
27 28
28#include <plat/common.h> 29#include <plat/common.h>
29#include <plat/voltage.h>
30 30
31#include "prm-regbits-34xx.h" 31#include "prm-regbits-34xx.h"
32#include "prm-regbits-44xx.h" 32#include "prm-regbits-44xx.h"
@@ -35,284 +35,30 @@
35#include "prminst44xx.h" 35#include "prminst44xx.h"
36#include "control.h" 36#include "control.h"
37 37
38#define VP_IDLE_TIMEOUT 200 38#include "voltage.h"
39#define VP_TRANXDONE_TIMEOUT 300 39
40#include "vc.h"
41#include "vp.h"
42
40#define VOLTAGE_DIR_SIZE 16 43#define VOLTAGE_DIR_SIZE 16
41 44
42/* Voltage processor register offsets */
43struct vp_reg_offs {
44 u8 vpconfig;
45 u8 vstepmin;
46 u8 vstepmax;
47 u8 vlimitto;
48 u8 vstatus;
49 u8 voltage;
50};
51
52/* Voltage Processor bit field values, shifts and masks */
53struct vp_reg_val {
54 /* PRM module */
55 u16 prm_mod;
56 /* VPx_VPCONFIG */
57 u32 vpconfig_erroroffset;
58 u16 vpconfig_errorgain;
59 u32 vpconfig_errorgain_mask;
60 u8 vpconfig_errorgain_shift;
61 u32 vpconfig_initvoltage_mask;
62 u8 vpconfig_initvoltage_shift;
63 u32 vpconfig_timeouten;
64 u32 vpconfig_initvdd;
65 u32 vpconfig_forceupdate;
66 u32 vpconfig_vpenable;
67 /* VPx_VSTEPMIN */
68 u8 vstepmin_stepmin;
69 u16 vstepmin_smpswaittimemin;
70 u8 vstepmin_stepmin_shift;
71 u8 vstepmin_smpswaittimemin_shift;
72 /* VPx_VSTEPMAX */
73 u8 vstepmax_stepmax;
74 u16 vstepmax_smpswaittimemax;
75 u8 vstepmax_stepmax_shift;
76 u8 vstepmax_smpswaittimemax_shift;
77 /* VPx_VLIMITTO */
78 u8 vlimitto_vddmin;
79 u8 vlimitto_vddmax;
80 u16 vlimitto_timeout;
81 u8 vlimitto_vddmin_shift;
82 u8 vlimitto_vddmax_shift;
83 u8 vlimitto_timeout_shift;
84 /* PRM_IRQSTATUS*/
85 u32 tranxdone_status;
86};
87
88/* Voltage controller registers and offsets */
89struct vc_reg_info {
90 /* PRM module */
91 u16 prm_mod;
92 /* VC register offsets */
93 u8 smps_sa_reg;
94 u8 smps_volra_reg;
95 u8 bypass_val_reg;
96 u8 cmdval_reg;
97 u8 voltsetup_reg;
98 /*VC_SMPS_SA*/
99 u8 smps_sa_shift;
100 u32 smps_sa_mask;
101 /* VC_SMPS_VOL_RA */
102 u8 smps_volra_shift;
103 u32 smps_volra_mask;
104 /* VC_BYPASS_VAL */
105 u8 data_shift;
106 u8 slaveaddr_shift;
107 u8 regaddr_shift;
108 u32 valid;
109 /* VC_CMD_VAL */
110 u8 cmd_on_shift;
111 u8 cmd_onlp_shift;
112 u8 cmd_ret_shift;
113 u8 cmd_off_shift;
114 u32 cmd_on_mask;
115 /* PRM_VOLTSETUP */
116 u8 voltsetup_shift;
117 u32 voltsetup_mask;
118};
119 45
120/** 46static struct omap_vdd_info **vdd_info;
121 * omap_vdd_info - Per Voltage Domain info 47
122 *
123 * @volt_data : voltage table having the distinct voltages supported
124 * by the domain and other associated per voltage data.
125 * @pmic_info : pmic specific parameters which should be populted by
126 * the pmic drivers.
127 * @vp_offs : structure containing the offsets for various
128 * vp registers
129 * @vp_reg : the register values, shifts, masks for various
130 * vp registers
131 * @vc_reg : structure containing various various vc registers,
132 * shifts, masks etc.
133 * @voltdm : pointer to the voltage domain structure
134 * @debug_dir : debug directory for this voltage domain.
135 * @curr_volt : current voltage for this vdd.
136 * @ocp_mod : The prm module for accessing the prm irqstatus reg.
137 * @prm_irqst_reg : prm irqstatus register.
138 * @vp_enabled : flag to keep track of whether vp is enabled or not
139 * @volt_scale : API to scale the voltage of the vdd.
140 */
141struct omap_vdd_info {
142 struct omap_volt_data *volt_data;
143 struct omap_volt_pmic_info *pmic_info;
144 struct vp_reg_offs vp_offs;
145 struct vp_reg_val vp_reg;
146 struct vc_reg_info vc_reg;
147 struct voltagedomain voltdm;
148 struct dentry *debug_dir;
149 u32 curr_volt;
150 u16 ocp_mod;
151 u8 prm_irqst_reg;
152 bool vp_enabled;
153 u32 (*read_reg) (u16 mod, u8 offset);
154 void (*write_reg) (u32 val, u16 mod, u8 offset);
155 int (*volt_scale) (struct omap_vdd_info *vdd,
156 unsigned long target_volt);
157};
158
159static struct omap_vdd_info *vdd_info;
160/* 48/*
161 * Number of scalable voltage domains. 49 * Number of scalable voltage domains.
162 */ 50 */
163static int nr_scalable_vdd; 51static int nr_scalable_vdd;
164 52
165/* OMAP3 VDD sturctures */ 53/* XXX document */
166static struct omap_vdd_info omap3_vdd_info[] = { 54static s16 prm_mod_offs;
167 { 55static s16 prm_irqst_ocp_mod_offs;
168 .vp_offs = {
169 .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
170 .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
171 .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
172 .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
173 .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
174 .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
175 },
176 .voltdm = {
177 .name = "mpu",
178 },
179 },
180 {
181 .vp_offs = {
182 .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
183 .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
184 .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
185 .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
186 .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
187 .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
188 },
189 .voltdm = {
190 .name = "core",
191 },
192 },
193};
194
195#define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
196
197/* OMAP4 VDD sturctures */
198static struct omap_vdd_info omap4_vdd_info[] = {
199 {
200 .vp_offs = {
201 .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
202 .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
203 .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
204 .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
205 .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
206 .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
207 },
208 .voltdm = {
209 .name = "mpu",
210 },
211 },
212 {
213 .vp_offs = {
214 .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
215 .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
216 .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
217 .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
218 .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
219 .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
220 },
221 .voltdm = {
222 .name = "iva",
223 },
224 },
225 {
226 .vp_offs = {
227 .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
228 .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
229 .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
230 .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
231 .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
232 .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
233 },
234 .voltdm = {
235 .name = "core",
236 },
237 },
238};
239
240#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
241
242/*
243 * Structures containing OMAP3430/OMAP3630 voltage supported and various
244 * voltage dependent data for each VDD.
245 */
246#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
247{ \
248 .volt_nominal = _v_nom, \
249 .sr_efuse_offs = _efuse_offs, \
250 .sr_errminlimit = _errminlimit, \
251 .vp_errgain = _errgain \
252}
253
254/* VDD1 */
255static struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
256 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
257 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
258 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
259 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
260 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
261 VOLT_DATA_DEFINE(0, 0, 0, 0),
262};
263
264static struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
265 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
266 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
267 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
268 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
269 VOLT_DATA_DEFINE(0, 0, 0, 0),
270};
271
272/* VDD2 */
273static struct omap_volt_data omap34xx_vddcore_volt_data[] = {
274 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
275 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
276 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
277 VOLT_DATA_DEFINE(0, 0, 0, 0),
278};
279
280static struct omap_volt_data omap36xx_vddcore_volt_data[] = {
281 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
282 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
283 VOLT_DATA_DEFINE(0, 0, 0, 0),
284};
285
286/*
287 * Structures containing OMAP4430 voltage supported and various
288 * voltage dependent data for each VDD.
289 */
290static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
291 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
292 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
293 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
294 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
295 VOLT_DATA_DEFINE(0, 0, 0, 0),
296};
297
298static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
299 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
300 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
301 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
302 VOLT_DATA_DEFINE(0, 0, 0, 0),
303};
304
305static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
306 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
307 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
308 VOLT_DATA_DEFINE(0, 0, 0, 0),
309};
310 56
311static struct dentry *voltage_dir; 57static struct dentry *voltage_dir;
312 58
313/* Init function pointers */ 59/* Init function pointers */
314static void (*vc_init) (struct omap_vdd_info *vdd); 60static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
315static int (*vdd_data_configure) (struct omap_vdd_info *vdd); 61 unsigned long target_volt);
316 62
317static u32 omap3_voltage_read_reg(u16 mod, u8 offset) 63static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
318{ 64{
@@ -335,6 +81,62 @@ static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
335 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset); 81 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
336} 82}
337 83
84static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
85{
86 char *sys_ck_name;
87 struct clk *sys_ck;
88 u32 sys_clk_speed, timeout_val, waittime;
89
90 /*
91 * XXX Clockfw should handle this, or this should be in a
92 * struct record
93 */
94 if (cpu_is_omap24xx() || cpu_is_omap34xx())
95 sys_ck_name = "sys_ck";
96 else if (cpu_is_omap44xx())
97 sys_ck_name = "sys_clkin_ck";
98 else
99 return -EINVAL;
100
101 /*
102 * Sys clk rate is require to calculate vp timeout value and
103 * smpswaittimemin and smpswaittimemax.
104 */
105 sys_ck = clk_get(NULL, sys_ck_name);
106 if (IS_ERR(sys_ck)) {
107 pr_warning("%s: Could not get the sys clk to calculate"
108 "various vdd_%s params\n", __func__, vdd->voltdm.name);
109 return -EINVAL;
110 }
111 sys_clk_speed = clk_get_rate(sys_ck);
112 clk_put(sys_ck);
113 /* Divide to avoid overflow */
114 sys_clk_speed /= 1000;
115
116 /* Generic voltage parameters */
117 vdd->curr_volt = 1200000;
118 vdd->volt_scale = vp_forceupdate_scale_voltage;
119 vdd->vp_enabled = false;
120
121 vdd->vp_rt_data.vpconfig_erroroffset =
122 (vdd->pmic_info->vp_erroroffset <<
123 vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
124
125 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
126 vdd->vp_rt_data.vlimitto_timeout = timeout_val;
127 vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
128 vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
129
130 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
131 sys_clk_speed) / 1000;
132 vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
133 vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
134 vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
135 vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
136
137 return 0;
138}
139
338/* Voltage debugfs support */ 140/* Voltage debugfs support */
339static int vp_volt_debug_get(void *data, u64 *val) 141static int vp_volt_debug_get(void *data, u64 *val)
340{ 142{
@@ -346,7 +148,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
346 return -EINVAL; 148 return -EINVAL;
347 } 149 }
348 150
349 vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage); 151 vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
350 pr_notice("curr_vsel = %x\n", vsel); 152 pr_notice("curr_vsel = %x\n", vsel);
351 153
352 if (!vdd->pmic_info->vsel_to_uv) { 154 if (!vdd->pmic_info->vsel_to_uv) {
@@ -379,7 +181,6 @@ DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
379static void vp_latch_vsel(struct omap_vdd_info *vdd) 181static void vp_latch_vsel(struct omap_vdd_info *vdd)
380{ 182{
381 u32 vpconfig; 183 u32 vpconfig;
382 u16 mod;
383 unsigned long uvdc; 184 unsigned long uvdc;
384 char vsel; 185 char vsel;
385 186
@@ -396,30 +197,27 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
396 return; 197 return;
397 } 198 }
398 199
399 mod = vdd->vp_reg.prm_mod;
400
401 vsel = vdd->pmic_info->uv_to_vsel(uvdc); 200 vsel = vdd->pmic_info->uv_to_vsel(uvdc);
402 201
403 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 202 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
404 vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask | 203 vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
405 vdd->vp_reg.vpconfig_initvdd); 204 vdd->vp_data->vp_common->vpconfig_initvdd);
406 vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift; 205 vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
407 206
408 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 207 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
409 208
410 /* Trigger initVDD value copy to voltage processor */ 209 /* Trigger initVDD value copy to voltage processor */
411 vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod, 210 vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
412 vdd->vp_offs.vpconfig); 211 prm_mod_offs, vdd->vp_data->vpconfig);
413 212
414 /* Clear initVDD copy trigger bit */ 213 /* Clear initVDD copy trigger bit */
415 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 214 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
416} 215}
417 216
418/* Generic voltage init functions */ 217/* Generic voltage init functions */
419static void __init vp_init(struct omap_vdd_info *vdd) 218static void __init vp_init(struct omap_vdd_info *vdd)
420{ 219{
421 u32 vp_val; 220 u32 vp_val;
422 u16 mod;
423 221
424 if (!vdd->read_reg || !vdd->write_reg) { 222 if (!vdd->read_reg || !vdd->write_reg) {
425 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 223 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
@@ -427,33 +225,31 @@ static void __init vp_init(struct omap_vdd_info *vdd)
427 return; 225 return;
428 } 226 }
429 227
430 mod = vdd->vp_reg.prm_mod; 228 vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
431 229 (vdd->vp_rt_data.vpconfig_errorgain <<
432 vp_val = vdd->vp_reg.vpconfig_erroroffset | 230 vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
433 (vdd->vp_reg.vpconfig_errorgain << 231 vdd->vp_data->vp_common->vpconfig_timeouten;
434 vdd->vp_reg.vpconfig_errorgain_shift) | 232 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
435 vdd->vp_reg.vpconfig_timeouten; 233
436 vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig); 234 vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
437 235 vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
438 vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin << 236 (vdd->vp_rt_data.vstepmin_stepmin <<
439 vdd->vp_reg.vstepmin_smpswaittimemin_shift) | 237 vdd->vp_data->vp_common->vstepmin_stepmin_shift));
440 (vdd->vp_reg.vstepmin_stepmin << 238 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
441 vdd->vp_reg.vstepmin_stepmin_shift)); 239
442 vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin); 240 vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
443 241 vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
444 vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax << 242 (vdd->vp_rt_data.vstepmax_stepmax <<
445 vdd->vp_reg.vstepmax_smpswaittimemax_shift) | 243 vdd->vp_data->vp_common->vstepmax_stepmax_shift));
446 (vdd->vp_reg.vstepmax_stepmax << 244 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
447 vdd->vp_reg.vstepmax_stepmax_shift)); 245
448 vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax); 246 vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
449 247 vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
450 vp_val = ((vdd->vp_reg.vlimitto_vddmax << 248 (vdd->vp_rt_data.vlimitto_vddmin <<
451 vdd->vp_reg.vlimitto_vddmax_shift) | 249 vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
452 (vdd->vp_reg.vlimitto_vddmin << 250 (vdd->vp_rt_data.vlimitto_timeout <<
453 vdd->vp_reg.vlimitto_vddmin_shift) | 251 vdd->vp_data->vp_common->vlimitto_timeout_shift));
454 (vdd->vp_reg.vlimitto_timeout << 252 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
455 vdd->vp_reg.vlimitto_timeout_shift));
456 vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto);
457} 253}
458 254
459static void __init vdd_debugfs_init(struct omap_vdd_info *vdd) 255static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
@@ -480,23 +276,23 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
480 } 276 }
481 277
482 (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir, 278 (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
483 &(vdd->vp_reg.vpconfig_errorgain)); 279 &(vdd->vp_rt_data.vpconfig_errorgain));
484 (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO, 280 (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
485 vdd->debug_dir, 281 vdd->debug_dir,
486 &(vdd->vp_reg.vstepmin_smpswaittimemin)); 282 &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
487 (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir, 283 (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
488 &(vdd->vp_reg.vstepmin_stepmin)); 284 &(vdd->vp_rt_data.vstepmin_stepmin));
489 (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO, 285 (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
490 vdd->debug_dir, 286 vdd->debug_dir,
491 &(vdd->vp_reg.vstepmax_smpswaittimemax)); 287 &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
492 (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir, 288 (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
493 &(vdd->vp_reg.vstepmax_stepmax)); 289 &(vdd->vp_rt_data.vstepmax_stepmax));
494 (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir, 290 (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
495 &(vdd->vp_reg.vlimitto_vddmax)); 291 &(vdd->vp_rt_data.vlimitto_vddmax));
496 (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir, 292 (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
497 &(vdd->vp_reg.vlimitto_vddmin)); 293 &(vdd->vp_rt_data.vlimitto_vddmin));
498 (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir, 294 (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
499 &(vdd->vp_reg.vlimitto_timeout)); 295 &(vdd->vp_rt_data.vlimitto_timeout));
500 (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir, 296 (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
501 (void *) vdd, &vp_volt_debug_fops); 297 (void *) vdd, &vp_volt_debug_fops);
502 (void) debugfs_create_file("curr_nominal_volt", S_IRUGO, 298 (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
@@ -509,8 +305,12 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
509 unsigned long target_volt, u8 *target_vsel, u8 *current_vsel) 305 unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
510{ 306{
511 struct omap_volt_data *volt_data; 307 struct omap_volt_data *volt_data;
308 const struct omap_vc_common_data *vc_common;
309 const struct omap_vp_common_data *vp_common;
512 u32 vc_cmdval, vp_errgain_val; 310 u32 vc_cmdval, vp_errgain_val;
513 u16 vp_mod, vc_mod; 311
312 vc_common = vdd->vc_data->vc_common;
313 vp_common = vdd->vp_data->vp_common;
514 314
515 /* Check if suffiecient pmic info is available for this vdd */ 315 /* Check if suffiecient pmic info is available for this vdd */
516 if (!vdd->pmic_info) { 316 if (!vdd->pmic_info) {
@@ -532,33 +332,30 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
532 return -EINVAL; 332 return -EINVAL;
533 } 333 }
534 334
535 vp_mod = vdd->vp_reg.prm_mod;
536 vc_mod = vdd->vc_reg.prm_mod;
537
538 /* Get volt_data corresponding to target_volt */ 335 /* Get volt_data corresponding to target_volt */
539 volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt); 336 volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
540 if (IS_ERR(volt_data)) 337 if (IS_ERR(volt_data))
541 volt_data = NULL; 338 volt_data = NULL;
542 339
543 *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt); 340 *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
544 *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage); 341 *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
545 342
546 /* Setting the ON voltage to the new target voltage */ 343 /* Setting the ON voltage to the new target voltage */
547 vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg); 344 vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
548 vc_cmdval &= ~vdd->vc_reg.cmd_on_mask; 345 vc_cmdval &= ~vc_common->cmd_on_mask;
549 vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift); 346 vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
550 vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg); 347 vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
551 348
552 /* Setting vp errorgain based on the voltage */ 349 /* Setting vp errorgain based on the voltage */
553 if (volt_data) { 350 if (volt_data) {
554 vp_errgain_val = vdd->read_reg(vp_mod, 351 vp_errgain_val = vdd->read_reg(prm_mod_offs,
555 vdd->vp_offs.vpconfig); 352 vdd->vp_data->vpconfig);
556 vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain; 353 vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
557 vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask; 354 vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
558 vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain << 355 vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
559 vdd->vp_reg.vpconfig_errorgain_shift; 356 vp_common->vpconfig_errorgain_shift;
560 vdd->write_reg(vp_errgain_val, vp_mod, 357 vdd->write_reg(vp_errgain_val, prm_mod_offs,
561 vdd->vp_offs.vpconfig); 358 vdd->vp_data->vpconfig);
562 } 359 }
563 360
564 return 0; 361 return 0;
@@ -584,7 +381,6 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
584{ 381{
585 u32 loop_cnt = 0, retries_cnt = 0; 382 u32 loop_cnt = 0, retries_cnt = 0;
586 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 383 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
587 u16 mod;
588 u8 target_vsel, current_vsel; 384 u8 target_vsel, current_vsel;
589 int ret; 385 int ret;
590 386
@@ -592,20 +388,19 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
592 if (ret) 388 if (ret)
593 return ret; 389 return ret;
594 390
595 mod = vdd->vc_reg.prm_mod; 391 vc_valid = vdd->vc_data->vc_common->valid;
596 392 vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
597 vc_valid = vdd->vc_reg.valid; 393 vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
598 vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg;
599 vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) |
600 (vdd->pmic_info->pmic_reg << 394 (vdd->pmic_info->pmic_reg <<
601 vdd->vc_reg.regaddr_shift) | 395 vdd->vc_data->vc_common->regaddr_shift) |
602 (vdd->pmic_info->i2c_slave_addr << 396 (vdd->pmic_info->i2c_slave_addr <<
603 vdd->vc_reg.slaveaddr_shift); 397 vdd->vc_data->vc_common->slaveaddr_shift);
604 398
605 vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg); 399 vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
606 vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg); 400 vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
401 vc_bypass_val_reg);
607 402
608 vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); 403 vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
609 /* 404 /*
610 * Loop till the bypass command is acknowledged from the SMPS. 405 * Loop till the bypass command is acknowledged from the SMPS.
611 * NOTE: This is legacy code. The loop count and retry count needs 406 * NOTE: This is legacy code. The loop count and retry count needs
@@ -624,7 +419,8 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
624 loop_cnt = 0; 419 loop_cnt = 0;
625 udelay(10); 420 udelay(10);
626 } 421 }
627 vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); 422 vc_bypass_value = vdd->read_reg(prm_mod_offs,
423 vc_bypass_val_reg);
628 } 424 }
629 425
630 _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); 426 _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
@@ -636,7 +432,6 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
636 unsigned long target_volt) 432 unsigned long target_volt)
637{ 433{
638 u32 vpconfig; 434 u32 vpconfig;
639 u16 mod, ocp_mod;
640 u8 target_vsel, current_vsel, prm_irqst_reg; 435 u8 target_vsel, current_vsel, prm_irqst_reg;
641 int ret, timeout = 0; 436 int ret, timeout = 0;
642 437
@@ -644,20 +439,18 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
644 if (ret) 439 if (ret)
645 return ret; 440 return ret;
646 441
647 mod = vdd->vp_reg.prm_mod; 442 prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
648 ocp_mod = vdd->ocp_mod;
649 prm_irqst_reg = vdd->prm_irqst_reg;
650 443
651 /* 444 /*
652 * Clear all pending TransactionDone interrupt/status. Typical latency 445 * Clear all pending TransactionDone interrupt/status. Typical latency
653 * is <3us 446 * is <3us
654 */ 447 */
655 while (timeout++ < VP_TRANXDONE_TIMEOUT) { 448 while (timeout++ < VP_TRANXDONE_TIMEOUT) {
656 vdd->write_reg(vdd->vp_reg.tranxdone_status, 449 vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
657 ocp_mod, prm_irqst_reg); 450 prm_irqst_ocp_mod_offs, prm_irqst_reg);
658 if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & 451 if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
659 vdd->vp_reg.tranxdone_status)) 452 vdd->vp_data->prm_irqst_data->tranxdone_status))
660 break; 453 break;
661 udelay(1); 454 udelay(1);
662 } 455 }
663 if (timeout >= VP_TRANXDONE_TIMEOUT) { 456 if (timeout >= VP_TRANXDONE_TIMEOUT) {
@@ -667,30 +460,30 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
667 } 460 }
668 461
669 /* Configure for VP-Force Update */ 462 /* Configure for VP-Force Update */
670 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 463 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
671 vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd | 464 vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
672 vdd->vp_reg.vpconfig_forceupdate | 465 vdd->vp_data->vp_common->vpconfig_forceupdate |
673 vdd->vp_reg.vpconfig_initvoltage_mask); 466 vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
674 vpconfig |= ((target_vsel << 467 vpconfig |= ((target_vsel <<
675 vdd->vp_reg.vpconfig_initvoltage_shift)); 468 vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
676 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 469 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
677 470
678 /* Trigger initVDD value copy to voltage processor */ 471 /* Trigger initVDD value copy to voltage processor */
679 vpconfig |= vdd->vp_reg.vpconfig_initvdd; 472 vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
680 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 473 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
681 474
682 /* Force update of voltage */ 475 /* Force update of voltage */
683 vpconfig |= vdd->vp_reg.vpconfig_forceupdate; 476 vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
684 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 477 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
685 478
686 /* 479 /*
687 * Wait for TransactionDone. Typical latency is <200us. 480 * Wait for TransactionDone. Typical latency is <200us.
688 * Depends on SMPSWAITTIMEMIN/MAX and voltage change 481 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
689 */ 482 */
690 timeout = 0; 483 timeout = 0;
691 omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) & 484 omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
692 vdd->vp_reg.tranxdone_status), 485 vdd->vp_data->prm_irqst_data->tranxdone_status),
693 VP_TRANXDONE_TIMEOUT, timeout); 486 VP_TRANXDONE_TIMEOUT, timeout);
694 if (timeout >= VP_TRANXDONE_TIMEOUT) 487 if (timeout >= VP_TRANXDONE_TIMEOUT)
695 pr_err("%s: vdd_%s TRANXDONE timeout exceeded." 488 pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
696 "TRANXDONE never got set after the voltage update\n", 489 "TRANXDONE never got set after the voltage update\n",
@@ -704,11 +497,11 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
704 */ 497 */
705 timeout = 0; 498 timeout = 0;
706 while (timeout++ < VP_TRANXDONE_TIMEOUT) { 499 while (timeout++ < VP_TRANXDONE_TIMEOUT) {
707 vdd->write_reg(vdd->vp_reg.tranxdone_status, 500 vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
708 ocp_mod, prm_irqst_reg); 501 prm_irqst_ocp_mod_offs, prm_irqst_reg);
709 if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & 502 if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
710 vdd->vp_reg.tranxdone_status)) 503 vdd->vp_data->prm_irqst_data->tranxdone_status))
711 break; 504 break;
712 udelay(1); 505 udelay(1);
713 } 506 }
714 507
@@ -717,222 +510,95 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
717 "to clear the TRANXDONE status\n", 510 "to clear the TRANXDONE status\n",
718 __func__, vdd->voltdm.name); 511 __func__, vdd->voltdm.name);
719 512
720 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 513 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
721 /* Clear initVDD copy trigger bit */ 514 /* Clear initVDD copy trigger bit */
722 vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;; 515 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
723 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 516 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
724 /* Clear force bit */ 517 /* Clear force bit */
725 vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate; 518 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
726 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 519 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
727 520
728 return 0; 521 return 0;
729} 522}
730 523
731/* OMAP3 specific voltage init functions */ 524static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
525{
526 /*
527 * Voltage Manager FSM parameters init
528 * XXX This data should be passed in from the board file
529 */
530 vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
531 vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
532 OMAP3_PRM_VOLTOFFSET_OFFSET);
533 vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
534 OMAP3_PRM_VOLTSETUP2_OFFSET);
535}
732 536
733/*
734 * Intializes the voltage controller registers with the PMIC and board
735 * specific parameters and voltage setup times for OMAP3.
736 */
737static void __init omap3_vc_init(struct omap_vdd_info *vdd) 537static void __init omap3_vc_init(struct omap_vdd_info *vdd)
738{ 538{
739 u32 vc_val;
740 u16 mod;
741 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
742 static bool is_initialized; 539 static bool is_initialized;
540 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
541 u32 vc_val;
743 542
744 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { 543 if (is_initialized)
745 pr_err("%s: PMIC info requried to configure vc for"
746 "vdd_%s not populated.Hence cannot initialize vc\n",
747 __func__, vdd->voltdm.name);
748 return;
749 }
750
751 if (!vdd->read_reg || !vdd->write_reg) {
752 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
753 __func__, vdd->voltdm.name);
754 return; 544 return;
755 }
756
757 mod = vdd->vc_reg.prm_mod;
758
759 /* Set up the SMPS_SA(i2c slave address in VC */
760 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
761 vc_val &= ~vdd->vc_reg.smps_sa_mask;
762 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
763 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
764
765 /* Setup the VOLRA(pmic reg addr) in VC */
766 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
767 vc_val &= ~vdd->vc_reg.smps_volra_mask;
768 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
769 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
770
771 /*Configure the setup times */
772 vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg);
773 vc_val &= ~vdd->vc_reg.voltsetup_mask;
774 vc_val |= vdd->pmic_info->volt_setup_time <<
775 vdd->vc_reg.voltsetup_shift;
776 vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
777 545
778 /* Set up the on, inactive, retention and off voltage */ 546 /* Set up the on, inactive, retention and off voltage */
779 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); 547 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
780 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt); 548 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
781 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt); 549 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
782 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt); 550 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
783 vc_val = ((on_vsel << vdd->vc_reg.cmd_on_shift) | 551 vc_val = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
784 (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) | 552 (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
785 (ret_vsel << vdd->vc_reg.cmd_ret_shift) | 553 (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
786 (off_vsel << vdd->vc_reg.cmd_off_shift)); 554 (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
787 vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg); 555 vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
788
789 if (is_initialized)
790 return;
791 556
792 /* Generic VC parameters init */ 557 /*
793 vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod, 558 * Generic VC parameters init
559 * XXX This data should be abstracted out
560 */
561 vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
794 OMAP3_PRM_VC_CH_CONF_OFFSET); 562 OMAP3_PRM_VC_CH_CONF_OFFSET);
795 vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod, 563 vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
796 OMAP3_PRM_VC_I2C_CFG_OFFSET); 564 OMAP3_PRM_VC_I2C_CFG_OFFSET);
797 vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET); 565
798 vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET); 566 omap3_vfsm_init(vdd);
799 vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET); 567
800 is_initialized = true; 568 is_initialized = true;
801} 569}
802 570
803/* Sets up all the VDD related info for OMAP3 */ 571
804static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) 572/* OMAP4 specific voltage init functions */
573static void __init omap4_vc_init(struct omap_vdd_info *vdd)
805{ 574{
806 struct clk *sys_ck; 575 static bool is_initialized;
807 u32 sys_clk_speed, timeout_val, waittime; 576 u32 vc_val;
808 577
809 if (!vdd->pmic_info) { 578 if (is_initialized)
810 pr_err("%s: PMIC info requried to configure vdd_%s not" 579 return;
811 "populated.Hence cannot initialize vdd_%s\n",
812 __func__, vdd->voltdm.name, vdd->voltdm.name);
813 return -EINVAL;
814 }
815 580
816 if (!strcmp(vdd->voltdm.name, "mpu")) { 581 /* TODO: Configure setup times and CMD_VAL values*/
817 if (cpu_is_omap3630())
818 vdd->volt_data = omap36xx_vddmpu_volt_data;
819 else
820 vdd->volt_data = omap34xx_vddmpu_volt_data;
821
822 vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK;
823 vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET;
824 vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT;
825 vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK;
826 vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT;
827 vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK;
828 vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT;
829 vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK;
830 } else if (!strcmp(vdd->voltdm.name, "core")) {
831 if (cpu_is_omap3630())
832 vdd->volt_data = omap36xx_vddcore_volt_data;
833 else
834 vdd->volt_data = omap34xx_vddcore_volt_data;
835
836 vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK;
837 vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET;
838 vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT;
839 vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK;
840 vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT;
841 vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK;
842 vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT;
843 vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK;
844 } else {
845 pr_warning("%s: vdd_%s does not exisit in OMAP3\n",
846 __func__, vdd->voltdm.name);
847 return -EINVAL;
848 }
849 582
850 /* 583 /*
851 * Sys clk rate is require to calculate vp timeout value and 584 * Generic VC parameters init
852 * smpswaittimemin and smpswaittimemax. 585 * XXX This data should be abstracted out
853 */ 586 */
854 sys_ck = clk_get(NULL, "sys_ck"); 587 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
855 if (IS_ERR(sys_ck)) { 588 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
856 pr_warning("%s: Could not get the sys clk to calculate" 589 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
857 "various vdd_%s params\n", __func__, vdd->voltdm.name); 590 vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
858 return -EINVAL;
859 }
860 sys_clk_speed = clk_get_rate(sys_ck);
861 clk_put(sys_ck);
862 /* Divide to avoid overflow */
863 sys_clk_speed /= 1000;
864
865 /* Generic voltage parameters */
866 vdd->curr_volt = 1200000;
867 vdd->ocp_mod = OCP_MOD;
868 vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
869 vdd->read_reg = omap3_voltage_read_reg;
870 vdd->write_reg = omap3_voltage_write_reg;
871 vdd->volt_scale = vp_forceupdate_scale_voltage;
872 vdd->vp_enabled = false;
873 591
874 /* VC parameters */ 592 /* XXX These are magic numbers and do not belong! */
875 vdd->vc_reg.prm_mod = OMAP3430_GR_MOD; 593 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
876 vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET; 594 vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
877 vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET;
878 vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET;
879 vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET;
880 vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT;
881 vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT;
882 vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT;
883 vdd->vc_reg.valid = OMAP3430_VALID_MASK;
884 vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT;
885 vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
886 vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT;
887 vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT;
888 vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT;
889
890 vdd->vp_reg.prm_mod = OMAP3430_GR_MOD;
891
892 /* VPCONFIG bit fields */
893 vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
894 OMAP3430_ERROROFFSET_SHIFT);
895 vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK;
896 vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT;
897 vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT;
898 vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK;
899 vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK;
900 vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK;
901 vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK;
902 vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK;
903
904 /* VSTEPMIN VSTEPMAX bit fields */
905 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
906 sys_clk_speed) / 1000;
907 vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
908 vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
909 vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
910 vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
911 vdd->vp_reg.vstepmin_smpswaittimemin_shift =
912 OMAP3430_SMPSWAITTIMEMIN_SHIFT;
913 vdd->vp_reg.vstepmax_smpswaittimemax_shift =
914 OMAP3430_SMPSWAITTIMEMAX_SHIFT;
915 vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT;
916 vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT;
917
918 /* VLIMITTO bit fields */
919 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
920 vdd->vp_reg.vlimitto_timeout = timeout_val;
921 vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
922 vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
923 vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT;
924 vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT;
925 vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
926 595
927 return 0; 596 is_initialized = true;
928} 597}
929 598
930/* OMAP4 specific voltage init functions */ 599static void __init omap_vc_init(struct omap_vdd_info *vdd)
931static void __init omap4_vc_init(struct omap_vdd_info *vdd)
932{ 600{
933 u32 vc_val; 601 u32 vc_val;
934 u16 mod;
935 static bool is_initialized;
936 602
937 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { 603 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
938 pr_err("%s: PMIC info requried to configure vc for" 604 pr_err("%s: PMIC info requried to configure vc for"
@@ -947,173 +613,61 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
947 return; 613 return;
948 } 614 }
949 615
950 mod = vdd->vc_reg.prm_mod;
951
952 /* Set up the SMPS_SA(i2c slave address in VC */ 616 /* Set up the SMPS_SA(i2c slave address in VC */
953 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); 617 vc_val = vdd->read_reg(prm_mod_offs,
954 vc_val &= ~vdd->vc_reg.smps_sa_mask; 618 vdd->vc_data->vc_common->smps_sa_reg);
955 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; 619 vc_val &= ~vdd->vc_data->smps_sa_mask;
956 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); 620 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
621 vdd->write_reg(vc_val, prm_mod_offs,
622 vdd->vc_data->vc_common->smps_sa_reg);
957 623
958 /* Setup the VOLRA(pmic reg addr) in VC */ 624 /* Setup the VOLRA(pmic reg addr) in VC */
959 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); 625 vc_val = vdd->read_reg(prm_mod_offs,
960 vc_val &= ~vdd->vc_reg.smps_volra_mask; 626 vdd->vc_data->vc_common->smps_volra_reg);
961 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; 627 vc_val &= ~vdd->vc_data->smps_volra_mask;
962 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); 628 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
963 629 vdd->write_reg(vc_val, prm_mod_offs,
964 /* TODO: Configure setup times and CMD_VAL values*/ 630 vdd->vc_data->vc_common->smps_volra_reg);
965 631
966 if (is_initialized) 632 /* Configure the setup times */
967 return; 633 vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
968 634 vc_val &= ~vdd->vfsm->voltsetup_mask;
969 /* Generic VC parameters init */ 635 vc_val |= vdd->pmic_info->volt_setup_time <<
970 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | 636 vdd->vfsm->voltsetup_shift;
971 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | 637 vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
972 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
973 vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
974
975 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
976 vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
977 638
978 is_initialized = true; 639 if (cpu_is_omap34xx())
640 omap3_vc_init(vdd);
641 else if (cpu_is_omap44xx())
642 omap4_vc_init(vdd);
979} 643}
980 644
981/* Sets up all the VDD related info for OMAP4 */ 645static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
982static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
983{ 646{
984 struct clk *sys_ck; 647 int ret = -EINVAL;
985 u32 sys_clk_speed, timeout_val, waittime;
986 648
987 if (!vdd->pmic_info) { 649 if (!vdd->pmic_info) {
988 pr_err("%s: PMIC info requried to configure vdd_%s not" 650 pr_err("%s: PMIC info requried to configure vdd_%s not"
989 "populated.Hence cannot initialize vdd_%s\n", 651 "populated.Hence cannot initialize vdd_%s\n",
990 __func__, vdd->voltdm.name, vdd->voltdm.name); 652 __func__, vdd->voltdm.name, vdd->voltdm.name);
991 return -EINVAL; 653 goto ovdc_out;
992 } 654 }
993 655
994 if (!strcmp(vdd->voltdm.name, "mpu")) { 656 if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
995 vdd->volt_data = omap44xx_vdd_mpu_volt_data; 657 goto ovdc_out;
996 vdd->vp_reg.tranxdone_status =
997 OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
998 vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
999 vdd->vc_reg.smps_sa_shift =
1000 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
1001 vdd->vc_reg.smps_sa_mask =
1002 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
1003 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
1004 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK;
1005 vdd->vc_reg.voltsetup_reg =
1006 OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
1007 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
1008 } else if (!strcmp(vdd->voltdm.name, "core")) {
1009 vdd->volt_data = omap44xx_vdd_core_volt_data;
1010 vdd->vp_reg.tranxdone_status =
1011 OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
1012 vdd->vc_reg.cmdval_reg =
1013 OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
1014 vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
1015 vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
1016 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
1017 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
1018 vdd->vc_reg.voltsetup_reg =
1019 OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
1020 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
1021 } else if (!strcmp(vdd->voltdm.name, "iva")) {
1022 vdd->volt_data = omap44xx_vdd_iva_volt_data;
1023 vdd->vp_reg.tranxdone_status =
1024 OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
1025 vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
1026 vdd->vc_reg.smps_sa_shift =
1027 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
1028 vdd->vc_reg.smps_sa_mask =
1029 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
1030 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
1031 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK;
1032 vdd->vc_reg.voltsetup_reg =
1033 OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
1034 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
1035 } else {
1036 pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
1037 __func__, vdd->voltdm.name);
1038 return -EINVAL;
1039 }
1040 658
1041 /* 659 if (cpu_is_omap34xx()) {
1042 * Sys clk rate is require to calculate vp timeout value and 660 vdd->read_reg = omap3_voltage_read_reg;
1043 * smpswaittimemin and smpswaittimemax. 661 vdd->write_reg = omap3_voltage_write_reg;
1044 */ 662 ret = 0;
1045 sys_ck = clk_get(NULL, "sys_clkin_ck"); 663 } else if (cpu_is_omap44xx()) {
1046 if (IS_ERR(sys_ck)) { 664 vdd->read_reg = omap4_voltage_read_reg;
1047 pr_warning("%s: Could not get the sys clk to calculate" 665 vdd->write_reg = omap4_voltage_write_reg;
1048 "various vdd_%s params\n", __func__, vdd->voltdm.name); 666 ret = 0;
1049 return -EINVAL;
1050 } 667 }
1051 sys_clk_speed = clk_get_rate(sys_ck);
1052 clk_put(sys_ck);
1053 /* Divide to avoid overflow */
1054 sys_clk_speed /= 1000;
1055
1056 /* Generic voltage parameters */
1057 vdd->curr_volt = 1200000;
1058 vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
1059 vdd->read_reg = omap4_voltage_read_reg;
1060 vdd->write_reg = omap4_voltage_write_reg;
1061 vdd->volt_scale = vp_forceupdate_scale_voltage;
1062 vdd->vp_enabled = false;
1063 668
1064 /* VC parameters */ 669ovdc_out:
1065 vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; 670 return ret;
1066 vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
1067 vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
1068 vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
1069 vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
1070 vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT;
1071 vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
1072 vdd->vc_reg.valid = OMAP4430_VALID_MASK;
1073 vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
1074 vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
1075 vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
1076 vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
1077 vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
1078
1079 vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
1080
1081 /* VPCONFIG bit fields */
1082 vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
1083 OMAP4430_ERROROFFSET_SHIFT);
1084 vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
1085 vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
1086 vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
1087 vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
1088 vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
1089 vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
1090 vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
1091 vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
1092
1093 /* VSTEPMIN VSTEPMAX bit fields */
1094 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
1095 sys_clk_speed) / 1000;
1096 vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
1097 vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
1098 vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
1099 vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
1100 vdd->vp_reg.vstepmin_smpswaittimemin_shift =
1101 OMAP4430_SMPSWAITTIMEMIN_SHIFT;
1102 vdd->vp_reg.vstepmax_smpswaittimemax_shift =
1103 OMAP4430_SMPSWAITTIMEMAX_SHIFT;
1104 vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
1105 vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
1106
1107 /* VLIMITTO bit fields */
1108 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
1109 vdd->vp_reg.vlimitto_timeout = timeout_val;
1110 vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
1111 vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
1112 vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
1113 vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
1114 vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
1115
1116 return 0;
1117} 671}
1118 672
1119/* Public functions */ 673/* Public functions */
@@ -1161,8 +715,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
1161 return 0; 715 return 0;
1162 } 716 }
1163 717
1164 curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod, 718 curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
1165 vdd->vp_offs.voltage);
1166 719
1167 if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) { 720 if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
1168 pr_warning("%s: PMIC function to convert vsel to voltage" 721 pr_warning("%s: PMIC function to convert vsel to voltage"
@@ -1184,7 +737,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1184{ 737{
1185 struct omap_vdd_info *vdd; 738 struct omap_vdd_info *vdd;
1186 u32 vpconfig; 739 u32 vpconfig;
1187 u16 mod;
1188 740
1189 if (!voltdm || IS_ERR(voltdm)) { 741 if (!voltdm || IS_ERR(voltdm)) {
1190 pr_warning("%s: VDD specified does not exist!\n", __func__); 742 pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -1198,8 +750,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1198 return; 750 return;
1199 } 751 }
1200 752
1201 mod = vdd->vp_reg.prm_mod;
1202
1203 /* If VP is already enabled, do nothing. Return */ 753 /* If VP is already enabled, do nothing. Return */
1204 if (vdd->vp_enabled) 754 if (vdd->vp_enabled)
1205 return; 755 return;
@@ -1207,9 +757,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1207 vp_latch_vsel(vdd); 757 vp_latch_vsel(vdd);
1208 758
1209 /* Enable VP */ 759 /* Enable VP */
1210 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 760 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
1211 vpconfig |= vdd->vp_reg.vpconfig_vpenable; 761 vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
1212 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 762 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
1213 vdd->vp_enabled = true; 763 vdd->vp_enabled = true;
1214} 764}
1215 765
@@ -1224,7 +774,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1224{ 774{
1225 struct omap_vdd_info *vdd; 775 struct omap_vdd_info *vdd;
1226 u32 vpconfig; 776 u32 vpconfig;
1227 u16 mod;
1228 int timeout; 777 int timeout;
1229 778
1230 if (!voltdm || IS_ERR(voltdm)) { 779 if (!voltdm || IS_ERR(voltdm)) {
@@ -1239,8 +788,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1239 return; 788 return;
1240 } 789 }
1241 790
1242 mod = vdd->vp_reg.prm_mod;
1243
1244 /* If VP is already disabled, do nothing. Return */ 791 /* If VP is already disabled, do nothing. Return */
1245 if (!vdd->vp_enabled) { 792 if (!vdd->vp_enabled) {
1246 pr_warning("%s: Trying to disable VP for vdd_%s when" 793 pr_warning("%s: Trying to disable VP for vdd_%s when"
@@ -1249,14 +796,14 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1249 } 796 }
1250 797
1251 /* Disable VP */ 798 /* Disable VP */
1252 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 799 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
1253 vpconfig &= ~vdd->vp_reg.vpconfig_vpenable; 800 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
1254 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 801 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
1255 802
1256 /* 803 /*
1257 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us 804 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
1258 */ 805 */
1259 omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)), 806 omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
1260 VP_IDLE_TIMEOUT, timeout); 807 VP_IDLE_TIMEOUT, timeout);
1261 808
1262 if (timeout >= VP_IDLE_TIMEOUT) 809 if (timeout >= VP_IDLE_TIMEOUT)
@@ -1509,8 +1056,8 @@ struct voltagedomain *omap_voltage_domain_lookup(char *name)
1509 } 1056 }
1510 1057
1511 for (i = 0; i < nr_scalable_vdd; i++) { 1058 for (i = 0; i < nr_scalable_vdd; i++) {
1512 if (!(strcmp(name, vdd_info[i].voltdm.name))) 1059 if (!(strcmp(name, vdd_info[i]->voltdm.name)))
1513 return &vdd_info[i].voltdm; 1060 return &vdd_info[i]->voltdm;
1514 } 1061 }
1515 1062
1516 return ERR_PTR(-EINVAL); 1063 return ERR_PTR(-EINVAL);
@@ -1538,35 +1085,24 @@ int __init omap_voltage_late_init(void)
1538 pr_err("%s: Unable to create voltage debugfs main dir\n", 1085 pr_err("%s: Unable to create voltage debugfs main dir\n",
1539 __func__); 1086 __func__);
1540 for (i = 0; i < nr_scalable_vdd; i++) { 1087 for (i = 0; i < nr_scalable_vdd; i++) {
1541 if (vdd_data_configure(&vdd_info[i])) 1088 if (omap_vdd_data_configure(vdd_info[i]))
1542 continue; 1089 continue;
1543 vc_init(&vdd_info[i]); 1090 omap_vc_init(vdd_info[i]);
1544 vp_init(&vdd_info[i]); 1091 vp_init(vdd_info[i]);
1545 vdd_debugfs_init(&vdd_info[i]); 1092 vdd_debugfs_init(vdd_info[i]);
1546 } 1093 }
1547 1094
1548 return 0; 1095 return 0;
1549} 1096}
1550 1097
1551/** 1098/* XXX document */
1552 * omap_voltage_early_init()- Volatage driver early init 1099int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
1553 */ 1100 struct omap_vdd_info *omap_vdd_array[],
1554static int __init omap_voltage_early_init(void) 1101 u8 omap_vdd_count)
1555{ 1102{
1556 if (cpu_is_omap34xx()) { 1103 prm_mod_offs = prm_mod;
1557 vdd_info = omap3_vdd_info; 1104 prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
1558 nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD; 1105 vdd_info = omap_vdd_array;
1559 vc_init = omap3_vc_init; 1106 nr_scalable_vdd = omap_vdd_count;
1560 vdd_data_configure = omap3_vdd_data_configure;
1561 } else if (cpu_is_omap44xx()) {
1562 vdd_info = omap4_vdd_info;
1563 nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
1564 vc_init = omap4_vc_init;
1565 vdd_data_configure = omap4_vdd_data_configure;
1566 } else {
1567 pr_warning("%s: voltage driver support not added\n", __func__);
1568 }
1569
1570 return 0; 1107 return 0;
1571} 1108}
1572core_initcall(omap_voltage_early_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 22:19:26 -0400