diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 182 |
1 files changed, 116 insertions, 66 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index becae45db6d..00d7130dd6c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -124,6 +124,11 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { | |||
124 | .name = "dmm", | 124 | .name = "dmm", |
125 | .class = &omap44xx_dmm_hwmod_class, | 125 | .class = &omap44xx_dmm_hwmod_class, |
126 | .clkdm_name = "l3_emif_clkdm", | 126 | .clkdm_name = "l3_emif_clkdm", |
127 | .prcm = { | ||
128 | .omap4 = { | ||
129 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | ||
130 | }, | ||
131 | }, | ||
127 | .slaves = omap44xx_dmm_slaves, | 132 | .slaves = omap44xx_dmm_slaves, |
128 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | 133 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), |
129 | .mpu_irqs = omap44xx_dmm_irqs, | 134 | .mpu_irqs = omap44xx_dmm_irqs, |
@@ -175,6 +180,11 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |||
175 | .name = "emif_fw", | 180 | .name = "emif_fw", |
176 | .class = &omap44xx_emif_fw_hwmod_class, | 181 | .class = &omap44xx_emif_fw_hwmod_class, |
177 | .clkdm_name = "l3_emif_clkdm", | 182 | .clkdm_name = "l3_emif_clkdm", |
183 | .prcm = { | ||
184 | .omap4 = { | ||
185 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | ||
186 | }, | ||
187 | }, | ||
178 | .slaves = omap44xx_emif_fw_slaves, | 188 | .slaves = omap44xx_emif_fw_slaves, |
179 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | 189 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), |
180 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 190 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -215,6 +225,11 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |||
215 | .name = "l3_instr", | 225 | .name = "l3_instr", |
216 | .class = &omap44xx_l3_hwmod_class, | 226 | .class = &omap44xx_l3_hwmod_class, |
217 | .clkdm_name = "l3_instr_clkdm", | 227 | .clkdm_name = "l3_instr_clkdm", |
228 | .prcm = { | ||
229 | .omap4 = { | ||
230 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | ||
231 | }, | ||
232 | }, | ||
218 | .slaves = omap44xx_l3_instr_slaves, | 233 | .slaves = omap44xx_l3_instr_slaves, |
219 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | 234 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), |
220 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 235 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -309,6 +324,11 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |||
309 | .class = &omap44xx_l3_hwmod_class, | 324 | .class = &omap44xx_l3_hwmod_class, |
310 | .clkdm_name = "l3_1_clkdm", | 325 | .clkdm_name = "l3_1_clkdm", |
311 | .mpu_irqs = omap44xx_l3_main_1_irqs, | 326 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
327 | .prcm = { | ||
328 | .omap4 = { | ||
329 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | ||
330 | }, | ||
331 | }, | ||
312 | .slaves = omap44xx_l3_main_1_slaves, | 332 | .slaves = omap44xx_l3_main_1_slaves, |
313 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | 333 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), |
314 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 334 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -405,6 +425,11 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |||
405 | .name = "l3_main_2", | 425 | .name = "l3_main_2", |
406 | .class = &omap44xx_l3_hwmod_class, | 426 | .class = &omap44xx_l3_hwmod_class, |
407 | .clkdm_name = "l3_2_clkdm", | 427 | .clkdm_name = "l3_2_clkdm", |
428 | .prcm = { | ||
429 | .omap4 = { | ||
430 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | ||
431 | }, | ||
432 | }, | ||
408 | .slaves = omap44xx_l3_main_2_slaves, | 433 | .slaves = omap44xx_l3_main_2_slaves, |
409 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | 434 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), |
410 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 435 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -456,6 +481,11 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |||
456 | .name = "l3_main_3", | 481 | .name = "l3_main_3", |
457 | .class = &omap44xx_l3_hwmod_class, | 482 | .class = &omap44xx_l3_hwmod_class, |
458 | .clkdm_name = "l3_instr_clkdm", | 483 | .clkdm_name = "l3_instr_clkdm", |
484 | .prcm = { | ||
485 | .omap4 = { | ||
486 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | ||
487 | }, | ||
488 | }, | ||
459 | .slaves = omap44xx_l3_main_3_slaves, | 489 | .slaves = omap44xx_l3_main_3_slaves, |
460 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | 490 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), |
461 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 491 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -514,6 +544,11 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |||
514 | .name = "l4_abe", | 544 | .name = "l4_abe", |
515 | .class = &omap44xx_l4_hwmod_class, | 545 | .class = &omap44xx_l4_hwmod_class, |
516 | .clkdm_name = "abe_clkdm", | 546 | .clkdm_name = "abe_clkdm", |
547 | .prcm = { | ||
548 | .omap4 = { | ||
549 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | ||
550 | }, | ||
551 | }, | ||
517 | .slaves = omap44xx_l4_abe_slaves, | 552 | .slaves = omap44xx_l4_abe_slaves, |
518 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | 553 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), |
519 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 554 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -537,6 +572,11 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |||
537 | .name = "l4_cfg", | 572 | .name = "l4_cfg", |
538 | .class = &omap44xx_l4_hwmod_class, | 573 | .class = &omap44xx_l4_hwmod_class, |
539 | .clkdm_name = "l4_cfg_clkdm", | 574 | .clkdm_name = "l4_cfg_clkdm", |
575 | .prcm = { | ||
576 | .omap4 = { | ||
577 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | ||
578 | }, | ||
579 | }, | ||
540 | .slaves = omap44xx_l4_cfg_slaves, | 580 | .slaves = omap44xx_l4_cfg_slaves, |
541 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | 581 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), |
542 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 582 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -560,6 +600,11 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { | |||
560 | .name = "l4_per", | 600 | .name = "l4_per", |
561 | .class = &omap44xx_l4_hwmod_class, | 601 | .class = &omap44xx_l4_hwmod_class, |
562 | .clkdm_name = "l4_per_clkdm", | 602 | .clkdm_name = "l4_per_clkdm", |
603 | .prcm = { | ||
604 | .omap4 = { | ||
605 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | ||
606 | }, | ||
607 | }, | ||
563 | .slaves = omap44xx_l4_per_slaves, | 608 | .slaves = omap44xx_l4_per_slaves, |
564 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | 609 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), |
565 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 610 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -583,6 +628,11 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |||
583 | .name = "l4_wkup", | 628 | .name = "l4_wkup", |
584 | .class = &omap44xx_l4_hwmod_class, | 629 | .class = &omap44xx_l4_hwmod_class, |
585 | .clkdm_name = "l4_wkup_clkdm", | 630 | .clkdm_name = "l4_wkup_clkdm", |
631 | .prcm = { | ||
632 | .omap4 = { | ||
633 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | ||
634 | }, | ||
635 | }, | ||
586 | .slaves = omap44xx_l4_wkup_slaves, | 636 | .slaves = omap44xx_l4_wkup_slaves, |
587 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | 637 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), |
588 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 638 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -758,7 +808,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { | |||
758 | .main_clk = "aess_fck", | 808 | .main_clk = "aess_fck", |
759 | .prcm = { | 809 | .prcm = { |
760 | .omap4 = { | 810 | .omap4 = { |
761 | .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | 811 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
762 | }, | 812 | }, |
763 | }, | 813 | }, |
764 | .slaves = omap44xx_aess_slaves, | 814 | .slaves = omap44xx_aess_slaves, |
@@ -788,7 +838,7 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = { | |||
788 | .clkdm_name = "l4_wkup_clkdm", | 838 | .clkdm_name = "l4_wkup_clkdm", |
789 | .prcm = { | 839 | .prcm = { |
790 | .omap4 = { | 840 | .omap4 = { |
791 | .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | 841 | .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, |
792 | }, | 842 | }, |
793 | }, | 843 | }, |
794 | .opt_clks = bandgap_opt_clks, | 844 | .opt_clks = bandgap_opt_clks, |
@@ -848,7 +898,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { | |||
848 | .main_clk = "sys_32k_ck", | 898 | .main_clk = "sys_32k_ck", |
849 | .prcm = { | 899 | .prcm = { |
850 | .omap4 = { | 900 | .omap4 = { |
851 | .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, | 901 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
852 | }, | 902 | }, |
853 | }, | 903 | }, |
854 | .slaves = omap44xx_counter_32k_slaves, | 904 | .slaves = omap44xx_counter_32k_slaves, |
@@ -932,7 +982,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { | |||
932 | .main_clk = "l3_div_ck", | 982 | .main_clk = "l3_div_ck", |
933 | .prcm = { | 983 | .prcm = { |
934 | .omap4 = { | 984 | .omap4 = { |
935 | .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, | 985 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
936 | }, | 986 | }, |
937 | }, | 987 | }, |
938 | .dev_attr = &dma_dev_attr, | 988 | .dev_attr = &dma_dev_attr, |
@@ -1026,7 +1076,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { | |||
1026 | .main_clk = "dmic_fck", | 1076 | .main_clk = "dmic_fck", |
1027 | .prcm = { | 1077 | .prcm = { |
1028 | .omap4 = { | 1078 | .omap4 = { |
1029 | .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | 1079 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
1030 | }, | 1080 | }, |
1031 | }, | 1081 | }, |
1032 | .slaves = omap44xx_dmic_slaves, | 1082 | .slaves = omap44xx_dmic_slaves, |
@@ -1110,7 +1160,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { | |||
1110 | .main_clk = "dsp_fck", | 1160 | .main_clk = "dsp_fck", |
1111 | .prcm = { | 1161 | .prcm = { |
1112 | .omap4 = { | 1162 | .omap4 = { |
1113 | .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | 1163 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
1114 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, | 1164 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, |
1115 | }, | 1165 | }, |
1116 | }, | 1166 | }, |
@@ -1199,7 +1249,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = { | |||
1199 | .main_clk = "dss_dss_clk", | 1249 | .main_clk = "dss_dss_clk", |
1200 | .prcm = { | 1250 | .prcm = { |
1201 | .omap4 = { | 1251 | .omap4 = { |
1202 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1252 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1203 | }, | 1253 | }, |
1204 | }, | 1254 | }, |
1205 | .opt_clks = dss_opt_clks, | 1255 | .opt_clks = dss_opt_clks, |
@@ -1303,7 +1353,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |||
1303 | .main_clk = "dss_dss_clk", | 1353 | .main_clk = "dss_dss_clk", |
1304 | .prcm = { | 1354 | .prcm = { |
1305 | .omap4 = { | 1355 | .omap4 = { |
1306 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1356 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1307 | }, | 1357 | }, |
1308 | }, | 1358 | }, |
1309 | .opt_clks = dss_dispc_opt_clks, | 1359 | .opt_clks = dss_dispc_opt_clks, |
@@ -1401,7 +1451,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { | |||
1401 | .main_clk = "dss_dss_clk", | 1451 | .main_clk = "dss_dss_clk", |
1402 | .prcm = { | 1452 | .prcm = { |
1403 | .omap4 = { | 1453 | .omap4 = { |
1404 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1454 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1405 | }, | 1455 | }, |
1406 | }, | 1456 | }, |
1407 | .opt_clks = dss_dsi1_opt_clks, | 1457 | .opt_clks = dss_dsi1_opt_clks, |
@@ -1478,7 +1528,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { | |||
1478 | .main_clk = "dss_dss_clk", | 1528 | .main_clk = "dss_dss_clk", |
1479 | .prcm = { | 1529 | .prcm = { |
1480 | .omap4 = { | 1530 | .omap4 = { |
1481 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1531 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1482 | }, | 1532 | }, |
1483 | }, | 1533 | }, |
1484 | .opt_clks = dss_dsi2_opt_clks, | 1534 | .opt_clks = dss_dsi2_opt_clks, |
@@ -1575,7 +1625,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { | |||
1575 | .main_clk = "dss_dss_clk", | 1625 | .main_clk = "dss_dss_clk", |
1576 | .prcm = { | 1626 | .prcm = { |
1577 | .omap4 = { | 1627 | .omap4 = { |
1578 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1628 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1579 | }, | 1629 | }, |
1580 | }, | 1630 | }, |
1581 | .opt_clks = dss_hdmi_opt_clks, | 1631 | .opt_clks = dss_hdmi_opt_clks, |
@@ -1666,7 +1716,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { | |||
1666 | .main_clk = "dss_dss_clk", | 1716 | .main_clk = "dss_dss_clk", |
1667 | .prcm = { | 1717 | .prcm = { |
1668 | .omap4 = { | 1718 | .omap4 = { |
1669 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1719 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1670 | }, | 1720 | }, |
1671 | }, | 1721 | }, |
1672 | .opt_clks = dss_rfbi_opt_clks, | 1722 | .opt_clks = dss_rfbi_opt_clks, |
@@ -1736,7 +1786,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |||
1736 | .main_clk = "dss_dss_clk", | 1786 | .main_clk = "dss_dss_clk", |
1737 | .prcm = { | 1787 | .prcm = { |
1738 | .omap4 = { | 1788 | .omap4 = { |
1739 | .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1789 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
1740 | }, | 1790 | }, |
1741 | }, | 1791 | }, |
1742 | .slaves = omap44xx_dss_venc_slaves, | 1792 | .slaves = omap44xx_dss_venc_slaves, |
@@ -1815,7 +1865,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
1815 | .main_clk = "gpio1_ick", | 1865 | .main_clk = "gpio1_ick", |
1816 | .prcm = { | 1866 | .prcm = { |
1817 | .omap4 = { | 1867 | .omap4 = { |
1818 | .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | 1868 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
1819 | }, | 1869 | }, |
1820 | }, | 1870 | }, |
1821 | .opt_clks = gpio1_opt_clks, | 1871 | .opt_clks = gpio1_opt_clks, |
@@ -1869,7 +1919,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
1869 | .main_clk = "gpio2_ick", | 1919 | .main_clk = "gpio2_ick", |
1870 | .prcm = { | 1920 | .prcm = { |
1871 | .omap4 = { | 1921 | .omap4 = { |
1872 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | 1922 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
1873 | }, | 1923 | }, |
1874 | }, | 1924 | }, |
1875 | .opt_clks = gpio2_opt_clks, | 1925 | .opt_clks = gpio2_opt_clks, |
@@ -1923,7 +1973,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
1923 | .main_clk = "gpio3_ick", | 1973 | .main_clk = "gpio3_ick", |
1924 | .prcm = { | 1974 | .prcm = { |
1925 | .omap4 = { | 1975 | .omap4 = { |
1926 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | 1976 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
1927 | }, | 1977 | }, |
1928 | }, | 1978 | }, |
1929 | .opt_clks = gpio3_opt_clks, | 1979 | .opt_clks = gpio3_opt_clks, |
@@ -1977,7 +2027,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
1977 | .main_clk = "gpio4_ick", | 2027 | .main_clk = "gpio4_ick", |
1978 | .prcm = { | 2028 | .prcm = { |
1979 | .omap4 = { | 2029 | .omap4 = { |
1980 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | 2030 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
1981 | }, | 2031 | }, |
1982 | }, | 2032 | }, |
1983 | .opt_clks = gpio4_opt_clks, | 2033 | .opt_clks = gpio4_opt_clks, |
@@ -2031,7 +2081,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
2031 | .main_clk = "gpio5_ick", | 2081 | .main_clk = "gpio5_ick", |
2032 | .prcm = { | 2082 | .prcm = { |
2033 | .omap4 = { | 2083 | .omap4 = { |
2034 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | 2084 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
2035 | }, | 2085 | }, |
2036 | }, | 2086 | }, |
2037 | .opt_clks = gpio5_opt_clks, | 2087 | .opt_clks = gpio5_opt_clks, |
@@ -2085,7 +2135,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { | |||
2085 | .main_clk = "gpio6_ick", | 2135 | .main_clk = "gpio6_ick", |
2086 | .prcm = { | 2136 | .prcm = { |
2087 | .omap4 = { | 2137 | .omap4 = { |
2088 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | 2138 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
2089 | }, | 2139 | }, |
2090 | }, | 2140 | }, |
2091 | .opt_clks = gpio6_opt_clks, | 2141 | .opt_clks = gpio6_opt_clks, |
@@ -2164,7 +2214,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { | |||
2164 | .main_clk = "hsi_fck", | 2214 | .main_clk = "hsi_fck", |
2165 | .prcm = { | 2215 | .prcm = { |
2166 | .omap4 = { | 2216 | .omap4 = { |
2167 | .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 2217 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
2168 | }, | 2218 | }, |
2169 | }, | 2219 | }, |
2170 | .slaves = omap44xx_hsi_slaves, | 2220 | .slaves = omap44xx_hsi_slaves, |
@@ -2247,7 +2297,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { | |||
2247 | .main_clk = "i2c1_fck", | 2297 | .main_clk = "i2c1_fck", |
2248 | .prcm = { | 2298 | .prcm = { |
2249 | .omap4 = { | 2299 | .omap4 = { |
2250 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | 2300 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
2251 | }, | 2301 | }, |
2252 | }, | 2302 | }, |
2253 | .slaves = omap44xx_i2c1_slaves, | 2303 | .slaves = omap44xx_i2c1_slaves, |
@@ -2302,7 +2352,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { | |||
2302 | .main_clk = "i2c2_fck", | 2352 | .main_clk = "i2c2_fck", |
2303 | .prcm = { | 2353 | .prcm = { |
2304 | .omap4 = { | 2354 | .omap4 = { |
2305 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | 2355 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
2306 | }, | 2356 | }, |
2307 | }, | 2357 | }, |
2308 | .slaves = omap44xx_i2c2_slaves, | 2358 | .slaves = omap44xx_i2c2_slaves, |
@@ -2357,7 +2407,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { | |||
2357 | .main_clk = "i2c3_fck", | 2407 | .main_clk = "i2c3_fck", |
2358 | .prcm = { | 2408 | .prcm = { |
2359 | .omap4 = { | 2409 | .omap4 = { |
2360 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | 2410 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
2361 | }, | 2411 | }, |
2362 | }, | 2412 | }, |
2363 | .slaves = omap44xx_i2c3_slaves, | 2413 | .slaves = omap44xx_i2c3_slaves, |
@@ -2412,7 +2462,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { | |||
2412 | .main_clk = "i2c4_fck", | 2462 | .main_clk = "i2c4_fck", |
2413 | .prcm = { | 2463 | .prcm = { |
2414 | .omap4 = { | 2464 | .omap4 = { |
2415 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | 2465 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
2416 | }, | 2466 | }, |
2417 | }, | 2467 | }, |
2418 | .slaves = omap44xx_i2c4_slaves, | 2468 | .slaves = omap44xx_i2c4_slaves, |
@@ -2508,7 +2558,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { | |||
2508 | .main_clk = "ipu_fck", | 2558 | .main_clk = "ipu_fck", |
2509 | .prcm = { | 2559 | .prcm = { |
2510 | .omap4 = { | 2560 | .omap4 = { |
2511 | .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | 2561 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
2512 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, | 2562 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, |
2513 | }, | 2563 | }, |
2514 | }, | 2564 | }, |
@@ -2595,7 +2645,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = { | |||
2595 | .main_clk = "iss_fck", | 2645 | .main_clk = "iss_fck", |
2596 | .prcm = { | 2646 | .prcm = { |
2597 | .omap4 = { | 2647 | .omap4 = { |
2598 | .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | 2648 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
2599 | }, | 2649 | }, |
2600 | }, | 2650 | }, |
2601 | .opt_clks = iss_opt_clks, | 2651 | .opt_clks = iss_opt_clks, |
@@ -2708,7 +2758,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = { | |||
2708 | .main_clk = "iva_fck", | 2758 | .main_clk = "iva_fck", |
2709 | .prcm = { | 2759 | .prcm = { |
2710 | .omap4 = { | 2760 | .omap4 = { |
2711 | .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | 2761 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
2712 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | 2762 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, |
2713 | }, | 2763 | }, |
2714 | }, | 2764 | }, |
@@ -2779,7 +2829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { | |||
2779 | .main_clk = "kbd_fck", | 2829 | .main_clk = "kbd_fck", |
2780 | .prcm = { | 2830 | .prcm = { |
2781 | .omap4 = { | 2831 | .omap4 = { |
2782 | .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | 2832 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
2783 | }, | 2833 | }, |
2784 | }, | 2834 | }, |
2785 | .slaves = omap44xx_kbd_slaves, | 2835 | .slaves = omap44xx_kbd_slaves, |
@@ -2844,7 +2894,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { | |||
2844 | .mpu_irqs = omap44xx_mailbox_irqs, | 2894 | .mpu_irqs = omap44xx_mailbox_irqs, |
2845 | .prcm = { | 2895 | .prcm = { |
2846 | .omap4 = { | 2896 | .omap4 = { |
2847 | .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, | 2897 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
2848 | }, | 2898 | }, |
2849 | }, | 2899 | }, |
2850 | .slaves = omap44xx_mailbox_slaves, | 2900 | .slaves = omap44xx_mailbox_slaves, |
@@ -2937,7 +2987,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
2937 | .main_clk = "mcbsp1_fck", | 2987 | .main_clk = "mcbsp1_fck", |
2938 | .prcm = { | 2988 | .prcm = { |
2939 | .omap4 = { | 2989 | .omap4 = { |
2940 | .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | 2990 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
2941 | }, | 2991 | }, |
2942 | }, | 2992 | }, |
2943 | .slaves = omap44xx_mcbsp1_slaves, | 2993 | .slaves = omap44xx_mcbsp1_slaves, |
@@ -3011,7 +3061,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
3011 | .main_clk = "mcbsp2_fck", | 3061 | .main_clk = "mcbsp2_fck", |
3012 | .prcm = { | 3062 | .prcm = { |
3013 | .omap4 = { | 3063 | .omap4 = { |
3014 | .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | 3064 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
3015 | }, | 3065 | }, |
3016 | }, | 3066 | }, |
3017 | .slaves = omap44xx_mcbsp2_slaves, | 3067 | .slaves = omap44xx_mcbsp2_slaves, |
@@ -3085,7 +3135,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
3085 | .main_clk = "mcbsp3_fck", | 3135 | .main_clk = "mcbsp3_fck", |
3086 | .prcm = { | 3136 | .prcm = { |
3087 | .omap4 = { | 3137 | .omap4 = { |
3088 | .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | 3138 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
3089 | }, | 3139 | }, |
3090 | }, | 3140 | }, |
3091 | .slaves = omap44xx_mcbsp3_slaves, | 3141 | .slaves = omap44xx_mcbsp3_slaves, |
@@ -3138,7 +3188,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |||
3138 | .main_clk = "mcbsp4_fck", | 3188 | .main_clk = "mcbsp4_fck", |
3139 | .prcm = { | 3189 | .prcm = { |
3140 | .omap4 = { | 3190 | .omap4 = { |
3141 | .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | 3191 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
3142 | }, | 3192 | }, |
3143 | }, | 3193 | }, |
3144 | .slaves = omap44xx_mcbsp4_slaves, | 3194 | .slaves = omap44xx_mcbsp4_slaves, |
@@ -3231,7 +3281,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |||
3231 | .main_clk = "mcpdm_fck", | 3281 | .main_clk = "mcpdm_fck", |
3232 | .prcm = { | 3282 | .prcm = { |
3233 | .omap4 = { | 3283 | .omap4 = { |
3234 | .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | 3284 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
3235 | }, | 3285 | }, |
3236 | }, | 3286 | }, |
3237 | .slaves = omap44xx_mcpdm_slaves, | 3287 | .slaves = omap44xx_mcpdm_slaves, |
@@ -3317,7 +3367,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
3317 | .main_clk = "mcspi1_fck", | 3367 | .main_clk = "mcspi1_fck", |
3318 | .prcm = { | 3368 | .prcm = { |
3319 | .omap4 = { | 3369 | .omap4 = { |
3320 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | 3370 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
3321 | }, | 3371 | }, |
3322 | }, | 3372 | }, |
3323 | .dev_attr = &mcspi1_dev_attr, | 3373 | .dev_attr = &mcspi1_dev_attr, |
@@ -3378,7 +3428,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
3378 | .main_clk = "mcspi2_fck", | 3428 | .main_clk = "mcspi2_fck", |
3379 | .prcm = { | 3429 | .prcm = { |
3380 | .omap4 = { | 3430 | .omap4 = { |
3381 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | 3431 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
3382 | }, | 3432 | }, |
3383 | }, | 3433 | }, |
3384 | .dev_attr = &mcspi2_dev_attr, | 3434 | .dev_attr = &mcspi2_dev_attr, |
@@ -3439,7 +3489,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
3439 | .main_clk = "mcspi3_fck", | 3489 | .main_clk = "mcspi3_fck", |
3440 | .prcm = { | 3490 | .prcm = { |
3441 | .omap4 = { | 3491 | .omap4 = { |
3442 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | 3492 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
3443 | }, | 3493 | }, |
3444 | }, | 3494 | }, |
3445 | .dev_attr = &mcspi3_dev_attr, | 3495 | .dev_attr = &mcspi3_dev_attr, |
@@ -3498,7 +3548,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { | |||
3498 | .main_clk = "mcspi4_fck", | 3548 | .main_clk = "mcspi4_fck", |
3499 | .prcm = { | 3549 | .prcm = { |
3500 | .omap4 = { | 3550 | .omap4 = { |
3501 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | 3551 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
3502 | }, | 3552 | }, |
3503 | }, | 3553 | }, |
3504 | .dev_attr = &mcspi4_dev_attr, | 3554 | .dev_attr = &mcspi4_dev_attr, |
@@ -3583,7 +3633,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
3583 | .main_clk = "mmc1_fck", | 3633 | .main_clk = "mmc1_fck", |
3584 | .prcm = { | 3634 | .prcm = { |
3585 | .omap4 = { | 3635 | .omap4 = { |
3586 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | 3636 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
3587 | }, | 3637 | }, |
3588 | }, | 3638 | }, |
3589 | .dev_attr = &mmc1_dev_attr, | 3639 | .dev_attr = &mmc1_dev_attr, |
@@ -3643,7 +3693,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
3643 | .main_clk = "mmc2_fck", | 3693 | .main_clk = "mmc2_fck", |
3644 | .prcm = { | 3694 | .prcm = { |
3645 | .omap4 = { | 3695 | .omap4 = { |
3646 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | 3696 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
3647 | }, | 3697 | }, |
3648 | }, | 3698 | }, |
3649 | .slaves = omap44xx_mmc2_slaves, | 3699 | .slaves = omap44xx_mmc2_slaves, |
@@ -3698,7 +3748,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
3698 | .main_clk = "mmc3_fck", | 3748 | .main_clk = "mmc3_fck", |
3699 | .prcm = { | 3749 | .prcm = { |
3700 | .omap4 = { | 3750 | .omap4 = { |
3701 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | 3751 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
3702 | }, | 3752 | }, |
3703 | }, | 3753 | }, |
3704 | .slaves = omap44xx_mmc3_slaves, | 3754 | .slaves = omap44xx_mmc3_slaves, |
@@ -3752,7 +3802,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
3752 | .main_clk = "mmc4_fck", | 3802 | .main_clk = "mmc4_fck", |
3753 | .prcm = { | 3803 | .prcm = { |
3754 | .omap4 = { | 3804 | .omap4 = { |
3755 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | 3805 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
3756 | }, | 3806 | }, |
3757 | }, | 3807 | }, |
3758 | .slaves = omap44xx_mmc4_slaves, | 3808 | .slaves = omap44xx_mmc4_slaves, |
@@ -3805,7 +3855,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { | |||
3805 | .main_clk = "mmc5_fck", | 3855 | .main_clk = "mmc5_fck", |
3806 | .prcm = { | 3856 | .prcm = { |
3807 | .omap4 = { | 3857 | .omap4 = { |
3808 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | 3858 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
3809 | }, | 3859 | }, |
3810 | }, | 3860 | }, |
3811 | .slaves = omap44xx_mmc5_slaves, | 3861 | .slaves = omap44xx_mmc5_slaves, |
@@ -3846,7 +3896,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { | |||
3846 | .main_clk = "dpll_mpu_m2_ck", | 3896 | .main_clk = "dpll_mpu_m2_ck", |
3847 | .prcm = { | 3897 | .prcm = { |
3848 | .omap4 = { | 3898 | .omap4 = { |
3849 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, | 3899 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
3850 | }, | 3900 | }, |
3851 | }, | 3901 | }, |
3852 | .masters = omap44xx_mpu_masters, | 3902 | .masters = omap44xx_mpu_masters, |
@@ -3920,7 +3970,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |||
3920 | .vdd_name = "core", | 3970 | .vdd_name = "core", |
3921 | .prcm = { | 3971 | .prcm = { |
3922 | .omap4 = { | 3972 | .omap4 = { |
3923 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | 3973 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
3924 | }, | 3974 | }, |
3925 | }, | 3975 | }, |
3926 | .slaves = omap44xx_smartreflex_core_slaves, | 3976 | .slaves = omap44xx_smartreflex_core_slaves, |
@@ -3967,7 +4017,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |||
3967 | .vdd_name = "iva", | 4017 | .vdd_name = "iva", |
3968 | .prcm = { | 4018 | .prcm = { |
3969 | .omap4 = { | 4019 | .omap4 = { |
3970 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | 4020 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
3971 | }, | 4021 | }, |
3972 | }, | 4022 | }, |
3973 | .slaves = omap44xx_smartreflex_iva_slaves, | 4023 | .slaves = omap44xx_smartreflex_iva_slaves, |
@@ -4014,7 +4064,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |||
4014 | .vdd_name = "mpu", | 4064 | .vdd_name = "mpu", |
4015 | .prcm = { | 4065 | .prcm = { |
4016 | .omap4 = { | 4066 | .omap4 = { |
4017 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | 4067 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
4018 | }, | 4068 | }, |
4019 | }, | 4069 | }, |
4020 | .slaves = omap44xx_smartreflex_mpu_slaves, | 4070 | .slaves = omap44xx_smartreflex_mpu_slaves, |
@@ -4076,7 +4126,7 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { | |||
4076 | .clkdm_name = "l4_cfg_clkdm", | 4126 | .clkdm_name = "l4_cfg_clkdm", |
4077 | .prcm = { | 4127 | .prcm = { |
4078 | .omap4 = { | 4128 | .omap4 = { |
4079 | .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, | 4129 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
4080 | }, | 4130 | }, |
4081 | }, | 4131 | }, |
4082 | .slaves = omap44xx_spinlock_slaves, | 4132 | .slaves = omap44xx_spinlock_slaves, |
@@ -4160,7 +4210,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { | |||
4160 | .main_clk = "timer1_fck", | 4210 | .main_clk = "timer1_fck", |
4161 | .prcm = { | 4211 | .prcm = { |
4162 | .omap4 = { | 4212 | .omap4 = { |
4163 | .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | 4213 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
4164 | }, | 4214 | }, |
4165 | }, | 4215 | }, |
4166 | .slaves = omap44xx_timer1_slaves, | 4216 | .slaves = omap44xx_timer1_slaves, |
@@ -4206,7 +4256,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { | |||
4206 | .main_clk = "timer2_fck", | 4256 | .main_clk = "timer2_fck", |
4207 | .prcm = { | 4257 | .prcm = { |
4208 | .omap4 = { | 4258 | .omap4 = { |
4209 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | 4259 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
4210 | }, | 4260 | }, |
4211 | }, | 4261 | }, |
4212 | .slaves = omap44xx_timer2_slaves, | 4262 | .slaves = omap44xx_timer2_slaves, |
@@ -4252,7 +4302,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { | |||
4252 | .main_clk = "timer3_fck", | 4302 | .main_clk = "timer3_fck", |
4253 | .prcm = { | 4303 | .prcm = { |
4254 | .omap4 = { | 4304 | .omap4 = { |
4255 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | 4305 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
4256 | }, | 4306 | }, |
4257 | }, | 4307 | }, |
4258 | .slaves = omap44xx_timer3_slaves, | 4308 | .slaves = omap44xx_timer3_slaves, |
@@ -4298,7 +4348,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { | |||
4298 | .main_clk = "timer4_fck", | 4348 | .main_clk = "timer4_fck", |
4299 | .prcm = { | 4349 | .prcm = { |
4300 | .omap4 = { | 4350 | .omap4 = { |
4301 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | 4351 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
4302 | }, | 4352 | }, |
4303 | }, | 4353 | }, |
4304 | .slaves = omap44xx_timer4_slaves, | 4354 | .slaves = omap44xx_timer4_slaves, |
@@ -4363,7 +4413,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { | |||
4363 | .main_clk = "timer5_fck", | 4413 | .main_clk = "timer5_fck", |
4364 | .prcm = { | 4414 | .prcm = { |
4365 | .omap4 = { | 4415 | .omap4 = { |
4366 | .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | 4416 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
4367 | }, | 4417 | }, |
4368 | }, | 4418 | }, |
4369 | .slaves = omap44xx_timer5_slaves, | 4419 | .slaves = omap44xx_timer5_slaves, |
@@ -4429,7 +4479,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { | |||
4429 | .main_clk = "timer6_fck", | 4479 | .main_clk = "timer6_fck", |
4430 | .prcm = { | 4480 | .prcm = { |
4431 | .omap4 = { | 4481 | .omap4 = { |
4432 | .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | 4482 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
4433 | }, | 4483 | }, |
4434 | }, | 4484 | }, |
4435 | .slaves = omap44xx_timer6_slaves, | 4485 | .slaves = omap44xx_timer6_slaves, |
@@ -4494,7 +4544,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { | |||
4494 | .main_clk = "timer7_fck", | 4544 | .main_clk = "timer7_fck", |
4495 | .prcm = { | 4545 | .prcm = { |
4496 | .omap4 = { | 4546 | .omap4 = { |
4497 | .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | 4547 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
4498 | }, | 4548 | }, |
4499 | }, | 4549 | }, |
4500 | .slaves = omap44xx_timer7_slaves, | 4550 | .slaves = omap44xx_timer7_slaves, |
@@ -4559,7 +4609,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { | |||
4559 | .main_clk = "timer8_fck", | 4609 | .main_clk = "timer8_fck", |
4560 | .prcm = { | 4610 | .prcm = { |
4561 | .omap4 = { | 4611 | .omap4 = { |
4562 | .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | 4612 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
4563 | }, | 4613 | }, |
4564 | }, | 4614 | }, |
4565 | .slaves = omap44xx_timer8_slaves, | 4615 | .slaves = omap44xx_timer8_slaves, |
@@ -4605,7 +4655,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { | |||
4605 | .main_clk = "timer9_fck", | 4655 | .main_clk = "timer9_fck", |
4606 | .prcm = { | 4656 | .prcm = { |
4607 | .omap4 = { | 4657 | .omap4 = { |
4608 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | 4658 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
4609 | }, | 4659 | }, |
4610 | }, | 4660 | }, |
4611 | .slaves = omap44xx_timer9_slaves, | 4661 | .slaves = omap44xx_timer9_slaves, |
@@ -4651,7 +4701,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { | |||
4651 | .main_clk = "timer10_fck", | 4701 | .main_clk = "timer10_fck", |
4652 | .prcm = { | 4702 | .prcm = { |
4653 | .omap4 = { | 4703 | .omap4 = { |
4654 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | 4704 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
4655 | }, | 4705 | }, |
4656 | }, | 4706 | }, |
4657 | .slaves = omap44xx_timer10_slaves, | 4707 | .slaves = omap44xx_timer10_slaves, |
@@ -4697,7 +4747,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { | |||
4697 | .main_clk = "timer11_fck", | 4747 | .main_clk = "timer11_fck", |
4698 | .prcm = { | 4748 | .prcm = { |
4699 | .omap4 = { | 4749 | .omap4 = { |
4700 | .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | 4750 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
4701 | }, | 4751 | }, |
4702 | }, | 4752 | }, |
4703 | .slaves = omap44xx_timer11_slaves, | 4753 | .slaves = omap44xx_timer11_slaves, |
@@ -4772,7 +4822,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { | |||
4772 | .main_clk = "uart1_fck", | 4822 | .main_clk = "uart1_fck", |
4773 | .prcm = { | 4823 | .prcm = { |
4774 | .omap4 = { | 4824 | .omap4 = { |
4775 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | 4825 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
4776 | }, | 4826 | }, |
4777 | }, | 4827 | }, |
4778 | .slaves = omap44xx_uart1_slaves, | 4828 | .slaves = omap44xx_uart1_slaves, |
@@ -4825,7 +4875,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { | |||
4825 | .main_clk = "uart2_fck", | 4875 | .main_clk = "uart2_fck", |
4826 | .prcm = { | 4876 | .prcm = { |
4827 | .omap4 = { | 4877 | .omap4 = { |
4828 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | 4878 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
4829 | }, | 4879 | }, |
4830 | }, | 4880 | }, |
4831 | .slaves = omap44xx_uart2_slaves, | 4881 | .slaves = omap44xx_uart2_slaves, |
@@ -4879,7 +4929,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { | |||
4879 | .main_clk = "uart3_fck", | 4929 | .main_clk = "uart3_fck", |
4880 | .prcm = { | 4930 | .prcm = { |
4881 | .omap4 = { | 4931 | .omap4 = { |
4882 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | 4932 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
4883 | }, | 4933 | }, |
4884 | }, | 4934 | }, |
4885 | .slaves = omap44xx_uart3_slaves, | 4935 | .slaves = omap44xx_uart3_slaves, |
@@ -4932,7 +4982,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { | |||
4932 | .main_clk = "uart4_fck", | 4982 | .main_clk = "uart4_fck", |
4933 | .prcm = { | 4983 | .prcm = { |
4934 | .omap4 = { | 4984 | .omap4 = { |
4935 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | 4985 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
4936 | }, | 4986 | }, |
4937 | }, | 4987 | }, |
4938 | .slaves = omap44xx_uart4_slaves, | 4988 | .slaves = omap44xx_uart4_slaves, |
@@ -5011,7 +5061,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |||
5011 | .main_clk = "usb_otg_hs_ick", | 5061 | .main_clk = "usb_otg_hs_ick", |
5012 | .prcm = { | 5062 | .prcm = { |
5013 | .omap4 = { | 5063 | .omap4 = { |
5014 | .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | 5064 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, |
5015 | }, | 5065 | }, |
5016 | }, | 5066 | }, |
5017 | .opt_clks = usb_otg_hs_opt_clks, | 5067 | .opt_clks = usb_otg_hs_opt_clks, |
@@ -5084,7 +5134,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | |||
5084 | .main_clk = "wd_timer2_fck", | 5134 | .main_clk = "wd_timer2_fck", |
5085 | .prcm = { | 5135 | .prcm = { |
5086 | .omap4 = { | 5136 | .omap4 = { |
5087 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | 5137 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
5088 | }, | 5138 | }, |
5089 | }, | 5139 | }, |
5090 | .slaves = omap44xx_wd_timer2_slaves, | 5140 | .slaves = omap44xx_wd_timer2_slaves, |
@@ -5149,7 +5199,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |||
5149 | .main_clk = "wd_timer3_fck", | 5199 | .main_clk = "wd_timer3_fck", |
5150 | .prcm = { | 5200 | .prcm = { |
5151 | .omap4 = { | 5201 | .omap4 = { |
5152 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | 5202 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
5153 | }, | 5203 | }, |
5154 | }, | 5204 | }, |
5155 | .slaves = omap44xx_wd_timer3_slaves, | 5205 | .slaves = omap44xx_wd_timer3_slaves, |