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-rw-r--r--arch/arm/mach-omap2/include/mach/barriers.h33
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S118
-rw-r--r--arch/arm/mach-omap2/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-omap2/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-omap2/include/mach/serial.h103
-rw-r--r--arch/arm/mach-omap2/include/mach/uncompress.h175
6 files changed, 62 insertions, 371 deletions
diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h
deleted file mode 100644
index 1c582a8592b..00000000000
--- a/arch/arm/mach-omap2/include/mach/barriers.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * OMAP memory barrier header.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __MACH_BARRIERS_H
23#define __MACH_BARRIERS_H
24
25#include <asm/outercache.h>
26
27extern void omap_bus_sync(void);
28
29#define rmb() dsb()
30#define wmb() do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
31#define mb() wmb()
32
33#endif /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cfaed13d004..48adfe9fe4f 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,10 +13,15 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <mach/serial.h> 16#include <asm/memory.h>
17
18#include <plat/serial.h>
17 19
18#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 20#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
19 21
22#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
23#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
24
20 .pushsection .data 25 .pushsection .data
21omap_uart_phys: .word 0 26omap_uart_phys: .word 0
22omap_uart_virt: .word 0 27omap_uart_virt: .word 0
@@ -29,25 +34,26 @@ omap_uart_lsr: .word 0
29 * the desired UART phys and virt addresses temporarily into 34 * the desired UART phys and virt addresses temporarily into
30 * the omap_uart_phys and omap_uart_virt above. 35 * the omap_uart_phys and omap_uart_virt above.
31 */ 36 */
32 .macro addruart, rp, rv, tmp 37 .macro addruart, rp, rv
33 38
34 /* Use omap_uart_phys/virt if already configured */ 39 /* Use omap_uart_phys/virt if already configured */
3510: adr \rp, 99f @ get effective addr of 99f 4010: mrc p15, 0, \rp, c1, c0
36 ldr \rv, [\rp] @ get absolute addr of 99f 41 tst \rp, #1 @ MMU enabled?
37 sub \rv, \rv, \rp @ offset between the two 42 ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
38 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys 43 ldrne \rp, =omap_uart_phys @ MMU enabled
39 sub \tmp, \rp, \rv @ make it effective 44 add \rv, \rp, #4 @ omap_uart_virt
40 ldr \rp, [\tmp, #0] @ omap_uart_phys 45 ldr \rp, [\rp, #0]
41 ldr \rv, [\tmp, #4] @ omap_uart_virt 46 ldr \rv, [\rv, #0]
42 cmp \rp, #0 @ is port configured? 47 cmp \rp, #0 @ is port configured?
43 cmpne \rv, #0 48 cmpne \rv, #0
44 bne 100f @ already configured 49 bne 99f @ already configured
45 50
46 /* Check the debug UART configuration set in uncompress.h */ 51 /* Check the debug UART configuration set in uncompress.h */
47 mov \rp, pc 52 mrc p15, 0, \rp, c1, c0
48 ldr \rv, =OMAP_UART_INFO_OFS 53 tst \rp, #1 @ MMU enabled?
49 and \rp, \rp, #0xff000000 54 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled
50 ldr \rp, [\rp, \rv] 55 ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled
56 ldr \rp, [\rp, #0]
51 57
52 /* Select the UART to use based on the UART1 scratchpad value */ 58 /* Select the UART to use based on the UART1 scratchpad value */
53 cmp \rp, #0 @ no port configured? 59 cmp \rp, #0 @ no port configured?
@@ -60,20 +66,18 @@ omap_uart_lsr: .word 0
60 beq 23f @ configure OMAP2UART3 66 beq 23f @ configure OMAP2UART3
61 cmp \rp, #OMAP3UART3 @ only on 34xx 67 cmp \rp, #OMAP3UART3 @ only on 34xx
62 beq 33f @ configure OMAP3UART3 68 beq 33f @ configure OMAP3UART3
63 cmp \rp, #OMAP4UART3 @ only on 44xx/54xx 69 cmp \rp, #OMAP4UART3 @ only on 44xx
64 beq 43f @ configure OMAP4/5UART3 70 beq 43f @ configure OMAP4UART3
65 cmp \rp, #OMAP3UART4 @ only on 36xx 71 cmp \rp, #OMAP3UART4 @ only on 36xx
66 beq 34f @ configure OMAP3UART4 72 beq 34f @ configure OMAP3UART4
67 cmp \rp, #OMAP4UART4 @ only on 44xx/54xx 73 cmp \rp, #OMAP4UART4 @ only on 44xx
68 beq 44f @ configure OMAP4/5UART4 74 beq 44f @ configure OMAP4UART4
69 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different 75 cmp \rp, #TI816XUART1 @ ti816x UART offsets different
70 beq 81f @ configure UART1 76 beq 81f @ configure UART1
71 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different 77 cmp \rp, #TI816XUART2 @ ti816x UART offsets different
72 beq 82f @ configure UART2 78 beq 82f @ configure UART2
73 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different 79 cmp \rp, #TI816XUART3 @ ti816x UART offsets different
74 beq 83f @ configure UART3 80 beq 83f @ configure UART3
75 cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
76 beq 84f @ configure UART1
77 cmp \rp, #ZOOM_UART @ only on zoom2/3 81 cmp \rp, #ZOOM_UART @ only on zoom2/3
78 beq 95f @ configure ZOOM_UART 82 beq 95f @ configure ZOOM_UART
79 83
@@ -96,66 +100,56 @@ omap_uart_lsr: .word 0
96 b 98f 100 b 98f
9744: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) 10144: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
98 b 98f 102 b 98f
9981: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE) 10381: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
100 b 98f 104 b 98f
10182: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE) 10582: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
102 b 98f 106 b 98f
10383: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) 10783: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
104 b 98f 108 b 98f
10584: ldr \rp, =AM33XX_UART1_BASE
106 and \rp, \rp, #0x00ffffff
107 b 97f
10895: ldr \rp, =ZOOM_UART_BASE 10995: ldr \rp, =ZOOM_UART_BASE
109 str \rp, [\tmp, #0] @ omap_uart_phys 110 mrc p15, 0, \rv, c1, c0
111 tst \rv, #1 @ MMU enabled?
112 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
113 ldrne \rv, =omap_uart_phys @ MMU enabled
114 str \rp, [\rv, #0]
110 ldr \rp, =ZOOM_UART_VIRT 115 ldr \rp, =ZOOM_UART_VIRT
111 str \rp, [\tmp, #4] @ omap_uart_virt 116 add \rv, \rv, #4 @ omap_uart_virt
117 str \rp, [\rv, #0]
112 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT) 118 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
113 str \rp, [\tmp, #8] @ omap_uart_lsr 119 add \rv, \rv, #4 @ omap_uart_lsr
114 b 10b 120 str \rp, [\rv, #0]
115
116 /* AM33XX: Store both phys and virt address for the uart */
11797: add \rp, \rp, #0x44000000 @ phys base
118 str \rp, [\tmp, #0] @ omap_uart_phys
119 sub \rp, \rp, #0x44000000 @ phys base
120 add \rp, \rp, #0xf9000000 @ virt base
121 str \rp, [\tmp, #4] @ omap_uart_virt
122 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
123 str \rp, [\tmp, #8] @ omap_uart_lsr
124
125 b 10b 121 b 10b
126 122
127 /* Store both phys and virt address for the uart */ 123 /* Store both phys and virt address for the uart */
12898: add \rp, \rp, #0x48000000 @ phys base 12498: add \rp, \rp, #0x48000000 @ phys base
129 str \rp, [\tmp, #0] @ omap_uart_phys 125 mrc p15, 0, \rv, c1, c0
126 tst \rv, #1 @ MMU enabled?
127 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
128 ldrne \rv, =omap_uart_phys @ MMU enabled
129 str \rp, [\rv, #0]
130 sub \rp, \rp, #0x48000000 @ phys base 130 sub \rp, \rp, #0x48000000 @ phys base
131 add \rp, \rp, #0xfa000000 @ virt base 131 add \rp, \rp, #0xfa000000 @ virt base
132 str \rp, [\tmp, #4] @ omap_uart_virt 132 add \rv, \rv, #4 @ omap_uart_virt
133 str \rp, [\rv, #0]
133 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) 134 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
134 str \rp, [\tmp, #8] @ omap_uart_lsr 135 add \rv, \rv, #4 @ omap_uart_lsr
136 str \rp, [\rv, #0]
135 137
136 b 10b 138 b 10b
137 13999:
138 .align
13999: .word .
140 .word omap_uart_phys
141 .ltorg
142
143100: /* Pass the UART_LSR reg address */
144 ldr \tmp, [\tmp, #8] @ omap_uart_lsr
145 add \rp, \rp, \tmp
146 add \rv, \rv, \tmp
147 .endm 140 .endm
148 141
149 .macro senduart,rd,rx 142 .macro senduart,rd,rx
150 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset 143 strb \rd, [\rx]
151 bic \rx, \rx, #0xff @ get base (THR) reg address
152 strb \rd, [\rx] @ send lower byte of rd
153 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
154 bic \rd, \rd, #(0xff << 24) @ restore original rd
155 .endm 144 .endm
156 145
157 .macro busyuart,rd,rx 146 .macro busyuart,rd,rx
1581001: ldrb \rd, [\rx] @ rx contains UART_LSR address 1471001: mrc p15, 0, \rd, c1, c0
148 tst \rd, #1 @ MMU enabled?
149 ldreq \rd, =omap_uart_v2p(omap_uart_lsr) @ MMU disabled
150 ldrne \rd, =omap_uart_lsr @ MMU enabled
151 ldr \rd, [\rd, #0]
152 ldrb \rd, [\rx, \rd]
159 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 153 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
160 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 154 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
161 bne 1001b 155 bne 1001b
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
index 54492dbf697..78edf9d33f7 100644
--- a/arch/arm/mach-omap2/include/mach/hardware.h
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -1,3 +1,5 @@
1/* 1/*
2 * arch/arm/mach-omap2/include/mach/hardware.h 2 * arch/arm/mach-omap2/include/mach/hardware.h
3 */ 3 */
4
5#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index ba5282cafa4..44dab772569 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,3 +1,5 @@
1/* 1/*
2 * arch/arm/mach-omap2/include/mach/irqs.h 2 * arch/arm/mach-omap2/include/mach/irqs.h
3 */ 3 */
4
5#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
deleted file mode 100644
index 70eda00db7a..00000000000
--- a/arch/arm/mach-omap2/include/mach/serial.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Copyright (C) 2009 Texas Instruments
3 * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 */
10
11/*
12 * Memory entry used for the DEBUG_LL UART configuration, relative to
13 * start of RAM. See also uncompress.h and debug-macro.S.
14 *
15 * Note that using a memory location for storing the UART configuration
16 * has at least two limitations:
17 *
18 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
19 * uncompress code could then partially overwrite itself
20 * 2. We assume printascii is called at least once before paging_init,
21 * and addruart has a chance to read OMAP_UART_INFO
22 */
23#define OMAP_UART_INFO_OFS 0x3ffc
24
25/* OMAP2 serial ports */
26#define OMAP2_UART1_BASE 0x4806a000
27#define OMAP2_UART2_BASE 0x4806c000
28#define OMAP2_UART3_BASE 0x4806e000
29
30/* OMAP3 serial ports */
31#define OMAP3_UART1_BASE OMAP2_UART1_BASE
32#define OMAP3_UART2_BASE OMAP2_UART2_BASE
33#define OMAP3_UART3_BASE 0x49020000
34#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
35#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
36
37/* OMAP4 serial ports */
38#define OMAP4_UART1_BASE OMAP2_UART1_BASE
39#define OMAP4_UART2_BASE OMAP2_UART2_BASE
40#define OMAP4_UART3_BASE 0x48020000
41#define OMAP4_UART4_BASE 0x4806e000
42
43/* TI81XX serial ports */
44#define TI81XX_UART1_BASE 0x48020000
45#define TI81XX_UART2_BASE 0x48022000
46#define TI81XX_UART3_BASE 0x48024000
47
48/* AM3505/3517 UART4 */
49#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
50
51/* AM33XX serial port */
52#define AM33XX_UART1_BASE 0x44E09000
53
54/* OMAP5 serial ports */
55#define OMAP5_UART1_BASE OMAP2_UART1_BASE
56#define OMAP5_UART2_BASE OMAP2_UART2_BASE
57#define OMAP5_UART3_BASE OMAP4_UART3_BASE
58#define OMAP5_UART4_BASE OMAP4_UART4_BASE
59#define OMAP5_UART5_BASE 0x48066000
60#define OMAP5_UART6_BASE 0x48068000
61
62/* External port on Zoom2/3 */
63#define ZOOM_UART_BASE 0x10000000
64#define ZOOM_UART_VIRT 0xfa400000
65
66#define OMAP_PORT_SHIFT 2
67#define ZOOM_PORT_SHIFT 1
68
69#define OMAP24XX_BASE_BAUD (48000000/16)
70
71/*
72 * DEBUG_LL port encoding stored into the UART1 scratchpad register by
73 * decomp_setup in uncompress.h
74 */
75#define OMAP2UART1 21
76#define OMAP2UART2 22
77#define OMAP2UART3 23
78#define OMAP3UART1 OMAP2UART1
79#define OMAP3UART2 OMAP2UART2
80#define OMAP3UART3 33
81#define OMAP3UART4 34 /* Only on 36xx */
82#define OMAP4UART1 OMAP2UART1
83#define OMAP4UART2 OMAP2UART2
84#define OMAP4UART3 43
85#define OMAP4UART4 44
86#define TI81XXUART1 81
87#define TI81XXUART2 82
88#define TI81XXUART3 83
89#define AM33XXUART1 84
90#define OMAP5UART3 OMAP4UART3
91#define OMAP5UART4 OMAP4UART4
92#define ZOOM_UART 95 /* Only on zoom2/3 */
93
94#ifndef __ASSEMBLER__
95
96struct omap_board_data;
97struct omap_uart_port_info;
98
99extern void omap_serial_init(void);
100extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
101extern void omap_serial_init_port(struct omap_board_data *bdata,
102 struct omap_uart_port_info *platform_data);
103#endif
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
index 8e3546d3e04..78e0557bfd4 100644
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -1,176 +1,5 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/uncompress.h 2 * arch/arm/mach-omap2/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */ 3 */
19 4
20#include <linux/types.h> 5#include <plat/uncompress.h>
21#include <linux/serial_reg.h>
22
23#include <asm/memory.h>
24#include <asm/mach-types.h>
25
26#include <mach/serial.h>
27
28#define MDR1_MODE_MASK 0x07
29
30volatile u8 *uart_base;
31int uart_shift;
32
33/*
34 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code.
36 */
37static void set_omap_uart_info(unsigned char port)
38{
39 /*
40 * Get address of some.bss variable and round it down
41 * a la CONFIG_AUTO_ZRELADDR.
42 */
43 u32 ram_start = (u32)&uart_shift & 0xf8000000;
44 u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
45 *uart_info = port;
46}
47
48static void putc(int c)
49{
50 if (!uart_base)
51 return;
52
53 /* Check for UART 16x mode */
54 if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
55 return;
56
57 while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
58 barrier();
59 uart_base[UART_TX << uart_shift] = c;
60}
61
62static inline void flush(void)
63{
64}
65
66/*
67 * Macros to configure UART1 and debug UART
68 */
69#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
70 if (machine_is_##mach()) { \
71 uart_base = (volatile u8 *)(dbg_uart); \
72 uart_shift = (dbg_shft); \
73 port = (dbg_id); \
74 set_omap_uart_info(port); \
75 break; \
76 }
77
78#define DEBUG_LL_OMAP2(p, mach) \
79 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
80 OMAP2UART##p)
81
82#define DEBUG_LL_OMAP3(p, mach) \
83 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
84 OMAP3UART##p)
85
86#define DEBUG_LL_OMAP4(p, mach) \
87 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
88 OMAP4UART##p)
89
90#define DEBUG_LL_OMAP5(p, mach) \
91 _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
92 OMAP5UART##p)
93/* Zoom2/3 shift is different for UART1 and external port */
94#define DEBUG_LL_ZOOM(mach) \
95 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
96
97#define DEBUG_LL_TI81XX(p, mach) \
98 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
99 TI81XXUART##p)
100
101#define DEBUG_LL_AM33XX(p, mach) \
102 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
103 AM33XXUART##p)
104
105static inline void arch_decomp_setup(void)
106{
107 int port = 0;
108
109 /*
110 * Initialize the port based on the machine ID from the bootloader.
111 * Note that we're using macros here instead of switch statement
112 * as machine_is functions are optimized out for the boards that
113 * are not selected.
114 */
115 do {
116 /* omap2 based boards using UART1 */
117 DEBUG_LL_OMAP2(1, omap_2430sdp);
118 DEBUG_LL_OMAP2(1, omap_apollon);
119 DEBUG_LL_OMAP2(1, omap_h4);
120
121 /* omap2 based boards using UART3 */
122 DEBUG_LL_OMAP2(3, nokia_n800);
123 DEBUG_LL_OMAP2(3, nokia_n810);
124 DEBUG_LL_OMAP2(3, nokia_n810_wimax);
125
126 /* omap3 based boards using UART1 */
127 DEBUG_LL_OMAP2(1, omap3evm);
128 DEBUG_LL_OMAP3(1, omap_3430sdp);
129 DEBUG_LL_OMAP3(1, omap_3630sdp);
130 DEBUG_LL_OMAP3(1, omap3530_lv_som);
131 DEBUG_LL_OMAP3(1, omap3_torpedo);
132
133 /* omap3 based boards using UART3 */
134 DEBUG_LL_OMAP3(3, cm_t35);
135 DEBUG_LL_OMAP3(3, cm_t3517);
136 DEBUG_LL_OMAP3(3, cm_t3730);
137 DEBUG_LL_OMAP3(3, craneboard);
138 DEBUG_LL_OMAP3(3, devkit8000);
139 DEBUG_LL_OMAP3(3, igep0020);
140 DEBUG_LL_OMAP3(3, igep0030);
141 DEBUG_LL_OMAP3(3, nokia_rm680);
142 DEBUG_LL_OMAP3(3, nokia_rm696);
143 DEBUG_LL_OMAP3(3, nokia_rx51);
144 DEBUG_LL_OMAP3(3, omap3517evm);
145 DEBUG_LL_OMAP3(3, omap3_beagle);
146 DEBUG_LL_OMAP3(3, omap3_pandora);
147 DEBUG_LL_OMAP3(3, omap_ldp);
148 DEBUG_LL_OMAP3(3, overo);
149 DEBUG_LL_OMAP3(3, touchbook);
150
151 /* omap4 based boards using UART3 */
152 DEBUG_LL_OMAP4(3, omap_4430sdp);
153 DEBUG_LL_OMAP4(3, omap4_panda);
154
155 /* omap5 based boards using UART3 */
156 DEBUG_LL_OMAP5(3, omap5_sevm);
157
158 /* zoom2/3 external uart */
159 DEBUG_LL_ZOOM(omap_zoom2);
160 DEBUG_LL_ZOOM(omap_zoom3);
161
162 /* TI8168 base boards using UART3 */
163 DEBUG_LL_TI81XX(3, ti8168evm);
164
165 /* TI8148 base boards using UART1 */
166 DEBUG_LL_TI81XX(1, ti8148evm);
167
168 /* AM33XX base boards using UART1 */
169 DEBUG_LL_AM33XX(1, am335xevm);
170 } while (0);
171}
172
173/*
174 * nothing to do
175 */
176#define arch_decomp_wdog()
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