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-rw-r--r--arch/arm/mach-omap2/cm.h134
1 files changed, 3 insertions, 131 deletions
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index bf21375eee7..a7bc096bd40 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -1,8 +1,5 @@
1#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
2#define __ARCH_ASM_MACH_OMAP2_CM_H
3
4/* 1/*
5 * OMAP2/3 Clock Management (CM) register definitions 2 * OMAP2+ Clock Management prototypes
6 * 3 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2009 Nokia Corporation
@@ -13,133 +10,8 @@
13 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
15 */ 12 */
16 13#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
17#include "prcm-common.h" 14#define __ARCH_ASM_MACH_OMAP2_CM_H
18
19#define OMAP2420_CM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
21#define OMAP2430_CM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23#define OMAP34XX_CM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
25
26
27#include "cm44xx.h"
28
29/*
30 * Architecture-specific global CM registers
31 * Use cm_{read,write}_reg() with these registers.
32 * These registers appear once per CM module.
33 */
34
35#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
36#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
37#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
38
39#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
40#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
41
42/*
43 * Module specific CM registers from CM_BASE + domain offset
44 * Use cm_{read,write}_mod_reg() with these registers.
45 * These register offsets generally appear in more than one PRCM submodule.
46 */
47
48/* Common between 24xx and 34xx */
49
50#define CM_FCLKEN 0x0000
51#define CM_FCLKEN1 CM_FCLKEN
52#define CM_CLKEN CM_FCLKEN
53#define CM_ICLKEN 0x0010
54#define CM_ICLKEN1 CM_ICLKEN
55#define CM_ICLKEN2 0x0014
56#define CM_ICLKEN3 0x0018
57#define CM_IDLEST 0x0020
58#define CM_IDLEST1 CM_IDLEST
59#define CM_IDLEST2 0x0024
60#define CM_AUTOIDLE 0x0030
61#define CM_AUTOIDLE1 CM_AUTOIDLE
62#define CM_AUTOIDLE2 0x0034
63#define CM_AUTOIDLE3 0x0038
64#define CM_CLKSEL 0x0040
65#define CM_CLKSEL1 CM_CLKSEL
66#define CM_CLKSEL2 0x0044
67#define OMAP2_CM_CLKSTCTRL 0x0048
68#define OMAP4_CM_CLKSTCTRL 0x0000
69
70
71/* Architecture-specific registers */
72
73#define OMAP24XX_CM_FCLKEN2 0x0004
74#define OMAP24XX_CM_ICLKEN4 0x001c
75#define OMAP24XX_CM_AUTOIDLE4 0x003c
76
77#define OMAP2430_CM_IDLEST3 0x0028
78
79#define OMAP3430_CM_CLKEN_PLL 0x0004
80#define OMAP3430ES2_CM_CLKEN2 0x0004
81#define OMAP3430ES2_CM_FCLKEN3 0x0008
82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
84#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
85#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
86#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
87#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
88#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
89#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
90#define OMAP3430_CM_CLKSTST 0x004c
91#define OMAP3430ES2_CM_CLKSEL4 0x004c
92#define OMAP3430ES2_CM_CLKSEL5 0x0050
93#define OMAP3430_CM_CLKSEL2_EMU 0x0050
94#define OMAP3430_CM_CLKSEL3_EMU 0x0054
95
96/* CM2.CEFUSE_CM2 register offsets */
97
98/* OMAP4 modulemode control */
99#define OMAP4430_MODULEMODE_HWCTRL 0
100#define OMAP4430_MODULEMODE_SWCTRL 1
101
102/* Clock management domain register get/set */
103
104#ifndef __ASSEMBLER__
105
106extern u32 cm_read_mod_reg(s16 module, u16 idx);
107extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
108extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
109
110extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
111 u8 idlest_shift);
112extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
113
114static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
115{
116 return cm_rmw_mod_reg_bits(bits, bits, module, idx);
117}
118
119static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
120{
121 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
122}
123
124#endif
125
126/* CM register bits shared between 24XX and 3430 */
127
128/* CM_CLKSEL_GFX */
129#define OMAP_CLKSEL_GFX_SHIFT 0
130#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
131
132/* CM_ICLKEN_GFX */
133#define OMAP_EN_GFX_SHIFT 0
134#define OMAP_EN_GFX_MASK (1 << 0)
135
136/* CM_IDLEST_GFX */
137#define OMAP_ST_GFX_MASK (1 << 0)
138
139
140/* CM_IDLEST indicator */
141#define OMAP24XX_CM_IDLEST_VAL 0
142#define OMAP34XX_CM_IDLEST_VAL 1
143 15
144/* 16/*
145 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the 17 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 02:19:25 -0400