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-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c3578
1 files changed, 3578 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
new file mode 100644
index 00000000000..b9b84468314
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -0,0 +1,3578 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/list.h>
22
23#include <plat/clkdev_omap.h>
24
25#include "clock.h"
26#include "clock3xxx.h"
27#include "clock34xx.h"
28#include "clock36xx.h"
29#include "clock3517.h"
30
31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-34xx.h"
33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h"
35#include "control.h"
36
37/*
38 * clocks
39 */
40
41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43/* Maximum DPLL multiplier, divider values for OMAP3 */
44#define OMAP3_MAX_DPLL_MULT 2047
45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46#define OMAP3_MAX_DPLL_DIV 128
47
48/*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56/* Forward declarations for DPLL bypass clocks */
57static struct clk dpll1_fck;
58static struct clk dpll2_fck;
59
60/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67};
68
69static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73};
74
75/* Virtual source clocks for osc_sys_ck */
76static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80};
81
82static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92};
93
94static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
98};
99
100static struct clk virt_26m_ck = {
101 .name = "virt_26m_ck",
102 .ops = &clkops_null,
103 .rate = 26000000,
104};
105
106static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null,
109 .rate = 38400000,
110};
111
112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 }
115};
116
117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 }
120};
121
122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 }
125};
126
127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 }
130};
131
132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 }
135};
136
137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 }
140};
141
142static const struct clksel osc_sys_clksel[] = {
143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
149 { .parent = NULL },
150};
151
152/* Oscillator clock */
153/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154static struct clk osc_sys_ck = {
155 .name = "osc_sys_ck",
156 .ops = &clkops_null,
157 .init = &omap2_init_clksel_parent,
158 .clksel_reg = OMAP3430_PRM_CLKSEL,
159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
160 .clksel = osc_sys_clksel,
161 /* REVISIT: deal with autoextclkmode? */
162 .recalc = &omap2_clksel_recalc,
163};
164
165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 }
169};
170
171static const struct clksel sys_clksel[] = {
172 { .parent = &osc_sys_ck, .rates = div2_rates },
173 { .parent = NULL }
174};
175
176/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178static struct clk sys_ck = {
179 .name = "sys_ck",
180 .ops = &clkops_null,
181 .parent = &osc_sys_ck,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
184 .clksel_mask = OMAP_SYSCLKDIV_MASK,
185 .clksel = sys_clksel,
186 .recalc = &omap2_clksel_recalc,
187};
188
189static struct clk sys_altclk = {
190 .name = "sys_altclk",
191 .ops = &clkops_null,
192};
193
194/* Optional external clock input for some McBSPs */
195static struct clk mcbsp_clks = {
196 .name = "mcbsp_clks",
197 .ops = &clkops_null,
198};
199
200/* PRM EXTERNAL CLOCK OUTPUT */
201
202static struct clk sys_clkout1 = {
203 .name = "sys_clkout1",
204 .ops = &clkops_omap2_dflt,
205 .parent = &osc_sys_ck,
206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
208 .recalc = &followparent_recalc,
209};
210
211/* DPLLS */
212
213/* CM CLOCKS */
214
215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 }
233};
234
235static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
269};
270
271/* DPLL1 */
272/* MPU clock source */
273/* Type: DPLL */
274static struct dpll_data dpll1_dd = {
275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
278 .clk_bypass = &dpll1_fck,
279 .clk_ref = &sys_ck,
280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV,
294};
295
296static struct clk dpll1_ck = {
297 .name = "dpll1_ck",
298 .ops = &clkops_omap3_noncore_dpll_ops,
299 .parent = &sys_ck,
300 .dpll_data = &dpll1_dd,
301 .round_rate = &omap2_dpll_round_rate,
302 .set_rate = &omap3_noncore_dpll_set_rate,
303 .clkdm_name = "dpll1_clkdm",
304 .recalc = &omap3_dpll_recalc,
305};
306
307/*
308 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
309 * DPLL isn't bypassed.
310 */
311static struct clk dpll1_x2_ck = {
312 .name = "dpll1_x2_ck",
313 .ops = &clkops_null,
314 .parent = &dpll1_ck,
315 .clkdm_name = "dpll1_clkdm",
316 .recalc = &omap3_clkoutx2_recalc,
317};
318
319/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
320static const struct clksel div16_dpll1_x2m2_clksel[] = {
321 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
322 { .parent = NULL }
323};
324
325/*
326 * Does not exist in the TRM - needed to separate the M2 divider from
327 * bypass selection in mpu_ck
328 */
329static struct clk dpll1_x2m2_ck = {
330 .name = "dpll1_x2m2_ck",
331 .ops = &clkops_null,
332 .parent = &dpll1_x2_ck,
333 .init = &omap2_init_clksel_parent,
334 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
335 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
336 .clksel = div16_dpll1_x2m2_clksel,
337 .clkdm_name = "dpll1_clkdm",
338 .recalc = &omap2_clksel_recalc,
339};
340
341/* DPLL2 */
342/* IVA2 clock source */
343/* Type: DPLL */
344
345static struct dpll_data dpll2_dd = {
346 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
347 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
348 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
349 .clk_bypass = &dpll2_fck,
350 .clk_ref = &sys_ck,
351 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
352 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
353 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
354 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
355 (1 << DPLL_LOW_POWER_BYPASS),
356 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
357 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
358 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
359 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
360 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
361 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
362 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
363 .max_multiplier = OMAP3_MAX_DPLL_MULT,
364 .min_divider = 1,
365 .max_divider = OMAP3_MAX_DPLL_DIV,
366};
367
368static struct clk dpll2_ck = {
369 .name = "dpll2_ck",
370 .ops = &clkops_omap3_noncore_dpll_ops,
371 .parent = &sys_ck,
372 .dpll_data = &dpll2_dd,
373 .round_rate = &omap2_dpll_round_rate,
374 .set_rate = &omap3_noncore_dpll_set_rate,
375 .clkdm_name = "dpll2_clkdm",
376 .recalc = &omap3_dpll_recalc,
377};
378
379static const struct clksel div16_dpll2_m2x2_clksel[] = {
380 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
381 { .parent = NULL }
382};
383
384/*
385 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
386 * or CLKOUTX2. CLKOUT seems most plausible.
387 */
388static struct clk dpll2_m2_ck = {
389 .name = "dpll2_m2_ck",
390 .ops = &clkops_null,
391 .parent = &dpll2_ck,
392 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
394 OMAP3430_CM_CLKSEL2_PLL),
395 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
396 .clksel = div16_dpll2_m2x2_clksel,
397 .clkdm_name = "dpll2_clkdm",
398 .recalc = &omap2_clksel_recalc,
399};
400
401/*
402 * DPLL3
403 * Source clock for all interfaces and for some device fclks
404 * REVISIT: Also supports fast relock bypass - not included below
405 */
406static struct dpll_data dpll3_dd = {
407 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
408 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
409 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
410 .clk_bypass = &sys_ck,
411 .clk_ref = &sys_ck,
412 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
413 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
414 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
415 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
416 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
417 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
418 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
419 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
420 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
421 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
422 .max_multiplier = OMAP3_MAX_DPLL_MULT,
423 .min_divider = 1,
424 .max_divider = OMAP3_MAX_DPLL_DIV,
425};
426
427static struct clk dpll3_ck = {
428 .name = "dpll3_ck",
429 .ops = &clkops_omap3_core_dpll_ops,
430 .parent = &sys_ck,
431 .dpll_data = &dpll3_dd,
432 .round_rate = &omap2_dpll_round_rate,
433 .clkdm_name = "dpll3_clkdm",
434 .recalc = &omap3_dpll_recalc,
435};
436
437/*
438 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
439 * DPLL isn't bypassed
440 */
441static struct clk dpll3_x2_ck = {
442 .name = "dpll3_x2_ck",
443 .ops = &clkops_null,
444 .parent = &dpll3_ck,
445 .clkdm_name = "dpll3_clkdm",
446 .recalc = &omap3_clkoutx2_recalc,
447};
448
449static const struct clksel_rate div31_dpll3_rates[] = {
450 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
451 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
452 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
453 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
454 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
455 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 0 },
482};
483
484static const struct clksel div31_dpll3m2_clksel[] = {
485 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
486 { .parent = NULL }
487};
488
489/* DPLL3 output M2 - primary control point for CORE speed */
490static struct clk dpll3_m2_ck = {
491 .name = "dpll3_m2_ck",
492 .ops = &clkops_null,
493 .parent = &dpll3_ck,
494 .init = &omap2_init_clksel_parent,
495 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
496 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
497 .clksel = div31_dpll3m2_clksel,
498 .clkdm_name = "dpll3_clkdm",
499 .round_rate = &omap2_clksel_round_rate,
500 .set_rate = &omap3_core_dpll_m2_set_rate,
501 .recalc = &omap2_clksel_recalc,
502};
503
504static struct clk core_ck = {
505 .name = "core_ck",
506 .ops = &clkops_null,
507 .parent = &dpll3_m2_ck,
508 .recalc = &followparent_recalc,
509};
510
511static struct clk dpll3_m2x2_ck = {
512 .name = "dpll3_m2x2_ck",
513 .ops = &clkops_null,
514 .parent = &dpll3_m2_ck,
515 .clkdm_name = "dpll3_clkdm",
516 .recalc = &omap3_clkoutx2_recalc,
517};
518
519/* The PWRDN bit is apparently only available on 3430ES2 and above */
520static const struct clksel div16_dpll3_clksel[] = {
521 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
522 { .parent = NULL }
523};
524
525/* This virtual clock is the source for dpll3_m3x2_ck */
526static struct clk dpll3_m3_ck = {
527 .name = "dpll3_m3_ck",
528 .ops = &clkops_null,
529 .parent = &dpll3_ck,
530 .init = &omap2_init_clksel_parent,
531 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
532 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
533 .clksel = div16_dpll3_clksel,
534 .clkdm_name = "dpll3_clkdm",
535 .recalc = &omap2_clksel_recalc,
536};
537
538/* The PWRDN bit is apparently only available on 3430ES2 and above */
539static struct clk dpll3_m3x2_ck = {
540 .name = "dpll3_m3x2_ck",
541 .ops = &clkops_omap2_dflt_wait,
542 .parent = &dpll3_m3_ck,
543 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
544 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
545 .flags = INVERT_ENABLE,
546 .clkdm_name = "dpll3_clkdm",
547 .recalc = &omap3_clkoutx2_recalc,
548};
549
550static struct clk emu_core_alwon_ck = {
551 .name = "emu_core_alwon_ck",
552 .ops = &clkops_null,
553 .parent = &dpll3_m3x2_ck,
554 .clkdm_name = "dpll3_clkdm",
555 .recalc = &followparent_recalc,
556};
557
558/* DPLL4 */
559/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
560/* Type: DPLL */
561static struct dpll_data dpll4_dd;
562
563static struct dpll_data dpll4_dd_34xx __initdata = {
564 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
565 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
566 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
567 .clk_bypass = &sys_ck,
568 .clk_ref = &sys_ck,
569 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
570 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
572 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
573 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
574 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
575 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
576 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
577 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
578 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
579 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
580 .max_multiplier = OMAP3_MAX_DPLL_MULT,
581 .min_divider = 1,
582 .max_divider = OMAP3_MAX_DPLL_DIV,
583};
584
585static struct dpll_data dpll4_dd_3630 __initdata = {
586 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
587 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
588 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
589 .clk_bypass = &sys_ck,
590 .clk_ref = &sys_ck,
591 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
592 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
593 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
594 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
595 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
596 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
597 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
598 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
599 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
600 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
601 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
602 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
604 .min_divider = 1,
605 .max_divider = OMAP3_MAX_DPLL_DIV,
606 .flags = DPLL_J_TYPE
607};
608
609static struct clk dpll4_ck = {
610 .name = "dpll4_ck",
611 .ops = &clkops_omap3_noncore_dpll_ops,
612 .parent = &sys_ck,
613 .dpll_data = &dpll4_dd,
614 .round_rate = &omap2_dpll_round_rate,
615 .set_rate = &omap3_dpll4_set_rate,
616 .clkdm_name = "dpll4_clkdm",
617 .recalc = &omap3_dpll_recalc,
618};
619
620/*
621 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
622 * DPLL isn't bypassed --
623 * XXX does this serve any downstream clocks?
624 */
625static struct clk dpll4_x2_ck = {
626 .name = "dpll4_x2_ck",
627 .ops = &clkops_null,
628 .parent = &dpll4_ck,
629 .clkdm_name = "dpll4_clkdm",
630 .recalc = &omap3_clkoutx2_recalc,
631};
632
633static const struct clksel dpll4_clksel[] = {
634 { .parent = &dpll4_ck, .rates = dpll4_rates },
635 { .parent = NULL }
636};
637
638/* This virtual clock is the source for dpll4_m2x2_ck */
639static struct clk dpll4_m2_ck = {
640 .name = "dpll4_m2_ck",
641 .ops = &clkops_null,
642 .parent = &dpll4_ck,
643 .init = &omap2_init_clksel_parent,
644 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
645 .clksel_mask = OMAP3630_DIV_96M_MASK,
646 .clksel = dpll4_clksel,
647 .clkdm_name = "dpll4_clkdm",
648 .recalc = &omap2_clksel_recalc,
649};
650
651/* The PWRDN bit is apparently only available on 3430ES2 and above */
652static struct clk dpll4_m2x2_ck = {
653 .name = "dpll4_m2x2_ck",
654 .ops = &clkops_omap2_dflt_wait,
655 .parent = &dpll4_m2_ck,
656 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
657 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
658 .flags = INVERT_ENABLE,
659 .clkdm_name = "dpll4_clkdm",
660 .recalc = &omap3_clkoutx2_recalc,
661};
662
663/*
664 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
665 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
666 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
667 * CM_96K_(F)CLK.
668 */
669
670/* Adding 192MHz Clock node needed by SGX */
671static struct clk omap_192m_alwon_fck = {
672 .name = "omap_192m_alwon_fck",
673 .ops = &clkops_null,
674 .parent = &dpll4_m2x2_ck,
675 .recalc = &followparent_recalc,
676};
677
678static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
679 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
680 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
681 { .div = 0 }
682};
683
684static const struct clksel omap_96m_alwon_fck_clksel[] = {
685 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
686 { .parent = NULL }
687};
688
689static const struct clksel_rate omap_96m_dpll_rates[] = {
690 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
691 { .div = 0 }
692};
693
694static const struct clksel_rate omap_96m_sys_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
696 { .div = 0 }
697};
698
699static struct clk omap_96m_alwon_fck = {
700 .name = "omap_96m_alwon_fck",
701 .ops = &clkops_null,
702 .parent = &dpll4_m2x2_ck,
703 .recalc = &followparent_recalc,
704};
705
706static struct clk omap_96m_alwon_fck_3630 = {
707 .name = "omap_96m_alwon_fck",
708 .parent = &omap_192m_alwon_fck,
709 .init = &omap2_init_clksel_parent,
710 .ops = &clkops_null,
711 .recalc = &omap2_clksel_recalc,
712 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
713 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
714 .clksel = omap_96m_alwon_fck_clksel
715};
716
717static struct clk cm_96m_fck = {
718 .name = "cm_96m_fck",
719 .ops = &clkops_null,
720 .parent = &omap_96m_alwon_fck,
721 .recalc = &followparent_recalc,
722};
723
724static const struct clksel omap_96m_fck_clksel[] = {
725 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
726 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
727 { .parent = NULL }
728};
729
730static struct clk omap_96m_fck = {
731 .name = "omap_96m_fck",
732 .ops = &clkops_null,
733 .parent = &sys_ck,
734 .init = &omap2_init_clksel_parent,
735 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
736 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
737 .clksel = omap_96m_fck_clksel,
738 .recalc = &omap2_clksel_recalc,
739};
740
741/* This virtual clock is the source for dpll4_m3x2_ck */
742static struct clk dpll4_m3_ck = {
743 .name = "dpll4_m3_ck",
744 .ops = &clkops_null,
745 .parent = &dpll4_ck,
746 .init = &omap2_init_clksel_parent,
747 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
748 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
749 .clksel = dpll4_clksel,
750 .clkdm_name = "dpll4_clkdm",
751 .recalc = &omap2_clksel_recalc,
752};
753
754/* The PWRDN bit is apparently only available on 3430ES2 and above */
755static struct clk dpll4_m3x2_ck = {
756 .name = "dpll4_m3x2_ck",
757 .ops = &clkops_omap2_dflt_wait,
758 .parent = &dpll4_m3_ck,
759 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
760 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
761 .flags = INVERT_ENABLE,
762 .clkdm_name = "dpll4_clkdm",
763 .recalc = &omap3_clkoutx2_recalc,
764};
765
766static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
767 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
768 { .div = 0 }
769};
770
771static const struct clksel_rate omap_54m_alt_rates[] = {
772 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
773 { .div = 0 }
774};
775
776static const struct clksel omap_54m_clksel[] = {
777 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
778 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
779 { .parent = NULL }
780};
781
782static struct clk omap_54m_fck = {
783 .name = "omap_54m_fck",
784 .ops = &clkops_null,
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
787 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
788 .clksel = omap_54m_clksel,
789 .recalc = &omap2_clksel_recalc,
790};
791
792static const struct clksel_rate omap_48m_cm96m_rates[] = {
793 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
794 { .div = 0 }
795};
796
797static const struct clksel_rate omap_48m_alt_rates[] = {
798 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
799 { .div = 0 }
800};
801
802static const struct clksel omap_48m_clksel[] = {
803 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
804 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
805 { .parent = NULL }
806};
807
808static struct clk omap_48m_fck = {
809 .name = "omap_48m_fck",
810 .ops = &clkops_null,
811 .init = &omap2_init_clksel_parent,
812 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
813 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
814 .clksel = omap_48m_clksel,
815 .recalc = &omap2_clksel_recalc,
816};
817
818static struct clk omap_12m_fck = {
819 .name = "omap_12m_fck",
820 .ops = &clkops_null,
821 .parent = &omap_48m_fck,
822 .fixed_div = 4,
823 .recalc = &omap_fixed_divisor_recalc,
824};
825
826/* This virtual clock is the source for dpll4_m4x2_ck */
827static struct clk dpll4_m4_ck = {
828 .name = "dpll4_m4_ck",
829 .ops = &clkops_null,
830 .parent = &dpll4_ck,
831 .init = &omap2_init_clksel_parent,
832 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
833 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
834 .clksel = dpll4_clksel,
835 .clkdm_name = "dpll4_clkdm",
836 .recalc = &omap2_clksel_recalc,
837 .set_rate = &omap2_clksel_set_rate,
838 .round_rate = &omap2_clksel_round_rate,
839};
840
841/* The PWRDN bit is apparently only available on 3430ES2 and above */
842static struct clk dpll4_m4x2_ck = {
843 .name = "dpll4_m4x2_ck",
844 .ops = &clkops_omap2_dflt_wait,
845 .parent = &dpll4_m4_ck,
846 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
847 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
848 .flags = INVERT_ENABLE,
849 .clkdm_name = "dpll4_clkdm",
850 .recalc = &omap3_clkoutx2_recalc,
851};
852
853/* This virtual clock is the source for dpll4_m5x2_ck */
854static struct clk dpll4_m5_ck = {
855 .name = "dpll4_m5_ck",
856 .ops = &clkops_null,
857 .parent = &dpll4_ck,
858 .init = &omap2_init_clksel_parent,
859 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
860 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
861 .clksel = dpll4_clksel,
862 .clkdm_name = "dpll4_clkdm",
863 .set_rate = &omap2_clksel_set_rate,
864 .round_rate = &omap2_clksel_round_rate,
865 .recalc = &omap2_clksel_recalc,
866};
867
868/* The PWRDN bit is apparently only available on 3430ES2 and above */
869static struct clk dpll4_m5x2_ck = {
870 .name = "dpll4_m5x2_ck",
871 .ops = &clkops_omap2_dflt_wait,
872 .parent = &dpll4_m5_ck,
873 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
874 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
875 .flags = INVERT_ENABLE,
876 .clkdm_name = "dpll4_clkdm",
877 .recalc = &omap3_clkoutx2_recalc,
878};
879
880/* This virtual clock is the source for dpll4_m6x2_ck */
881static struct clk dpll4_m6_ck = {
882 .name = "dpll4_m6_ck",
883 .ops = &clkops_null,
884 .parent = &dpll4_ck,
885 .init = &omap2_init_clksel_parent,
886 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
887 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
888 .clksel = dpll4_clksel,
889 .clkdm_name = "dpll4_clkdm",
890 .recalc = &omap2_clksel_recalc,
891};
892
893/* The PWRDN bit is apparently only available on 3430ES2 and above */
894static struct clk dpll4_m6x2_ck = {
895 .name = "dpll4_m6x2_ck",
896 .ops = &clkops_omap2_dflt_wait,
897 .parent = &dpll4_m6_ck,
898 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
899 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
900 .flags = INVERT_ENABLE,
901 .clkdm_name = "dpll4_clkdm",
902 .recalc = &omap3_clkoutx2_recalc,
903};
904
905static struct clk emu_per_alwon_ck = {
906 .name = "emu_per_alwon_ck",
907 .ops = &clkops_null,
908 .parent = &dpll4_m6x2_ck,
909 .clkdm_name = "dpll4_clkdm",
910 .recalc = &followparent_recalc,
911};
912
913/* DPLL5 */
914/* Supplies 120MHz clock, USIM source clock */
915/* Type: DPLL */
916/* 3430ES2 only */
917static struct dpll_data dpll5_dd = {
918 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
919 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
920 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
921 .clk_bypass = &sys_ck,
922 .clk_ref = &sys_ck,
923 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
924 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
925 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
926 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
927 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
928 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
929 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
930 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
931 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
932 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
933 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
934 .max_multiplier = OMAP3_MAX_DPLL_MULT,
935 .min_divider = 1,
936 .max_divider = OMAP3_MAX_DPLL_DIV,
937};
938
939static struct clk dpll5_ck = {
940 .name = "dpll5_ck",
941 .ops = &clkops_omap3_noncore_dpll_ops,
942 .parent = &sys_ck,
943 .dpll_data = &dpll5_dd,
944 .round_rate = &omap2_dpll_round_rate,
945 .set_rate = &omap3_noncore_dpll_set_rate,
946 .clkdm_name = "dpll5_clkdm",
947 .recalc = &omap3_dpll_recalc,
948};
949
950static const struct clksel div16_dpll5_clksel[] = {
951 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
952 { .parent = NULL }
953};
954
955static struct clk dpll5_m2_ck = {
956 .name = "dpll5_m2_ck",
957 .ops = &clkops_null,
958 .parent = &dpll5_ck,
959 .init = &omap2_init_clksel_parent,
960 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
961 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
962 .clksel = div16_dpll5_clksel,
963 .clkdm_name = "dpll5_clkdm",
964 .recalc = &omap2_clksel_recalc,
965};
966
967/* CM EXTERNAL CLOCK OUTPUTS */
968
969static const struct clksel_rate clkout2_src_core_rates[] = {
970 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
971 { .div = 0 }
972};
973
974static const struct clksel_rate clkout2_src_sys_rates[] = {
975 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
976 { .div = 0 }
977};
978
979static const struct clksel_rate clkout2_src_96m_rates[] = {
980 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
981 { .div = 0 }
982};
983
984static const struct clksel_rate clkout2_src_54m_rates[] = {
985 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
986 { .div = 0 }
987};
988
989static const struct clksel clkout2_src_clksel[] = {
990 { .parent = &core_ck, .rates = clkout2_src_core_rates },
991 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
992 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
993 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
994 { .parent = NULL }
995};
996
997static struct clk clkout2_src_ck = {
998 .name = "clkout2_src_ck",
999 .ops = &clkops_omap2_dflt,
1000 .init = &omap2_init_clksel_parent,
1001 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1002 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1003 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1004 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1005 .clksel = clkout2_src_clksel,
1006 .clkdm_name = "core_clkdm",
1007 .recalc = &omap2_clksel_recalc,
1008};
1009
1010static const struct clksel_rate sys_clkout2_rates[] = {
1011 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1012 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1013 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1014 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1015 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1016 { .div = 0 },
1017};
1018
1019static const struct clksel sys_clkout2_clksel[] = {
1020 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1021 { .parent = NULL },
1022};
1023
1024static struct clk sys_clkout2 = {
1025 .name = "sys_clkout2",
1026 .ops = &clkops_null,
1027 .init = &omap2_init_clksel_parent,
1028 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1029 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1030 .clksel = sys_clkout2_clksel,
1031 .recalc = &omap2_clksel_recalc,
1032 .round_rate = &omap2_clksel_round_rate,
1033 .set_rate = &omap2_clksel_set_rate
1034};
1035
1036/* CM OUTPUT CLOCKS */
1037
1038static struct clk corex2_fck = {
1039 .name = "corex2_fck",
1040 .ops = &clkops_null,
1041 .parent = &dpll3_m2x2_ck,
1042 .recalc = &followparent_recalc,
1043};
1044
1045/* DPLL power domain clock controls */
1046
1047static const struct clksel_rate div4_rates[] = {
1048 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1049 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1050 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1051 { .div = 0 }
1052};
1053
1054static const struct clksel div4_core_clksel[] = {
1055 { .parent = &core_ck, .rates = div4_rates },
1056 { .parent = NULL }
1057};
1058
1059/*
1060 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1061 * may be inconsistent here?
1062 */
1063static struct clk dpll1_fck = {
1064 .name = "dpll1_fck",
1065 .ops = &clkops_null,
1066 .parent = &core_ck,
1067 .init = &omap2_init_clksel_parent,
1068 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1069 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1070 .clksel = div4_core_clksel,
1071 .recalc = &omap2_clksel_recalc,
1072};
1073
1074static struct clk mpu_ck = {
1075 .name = "mpu_ck",
1076 .ops = &clkops_null,
1077 .parent = &dpll1_x2m2_ck,
1078 .clkdm_name = "mpu_clkdm",
1079 .recalc = &followparent_recalc,
1080};
1081
1082/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1083static const struct clksel_rate arm_fck_rates[] = {
1084 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1085 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1086 { .div = 0 },
1087};
1088
1089static const struct clksel arm_fck_clksel[] = {
1090 { .parent = &mpu_ck, .rates = arm_fck_rates },
1091 { .parent = NULL }
1092};
1093
1094static struct clk arm_fck = {
1095 .name = "arm_fck",
1096 .ops = &clkops_null,
1097 .parent = &mpu_ck,
1098 .init = &omap2_init_clksel_parent,
1099 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1100 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1101 .clksel = arm_fck_clksel,
1102 .clkdm_name = "mpu_clkdm",
1103 .recalc = &omap2_clksel_recalc,
1104};
1105
1106/* XXX What about neon_clkdm ? */
1107
1108/*
1109 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1110 * although it is referenced - so this is a guess
1111 */
1112static struct clk emu_mpu_alwon_ck = {
1113 .name = "emu_mpu_alwon_ck",
1114 .ops = &clkops_null,
1115 .parent = &mpu_ck,
1116 .recalc = &followparent_recalc,
1117};
1118
1119static struct clk dpll2_fck = {
1120 .name = "dpll2_fck",
1121 .ops = &clkops_null,
1122 .parent = &core_ck,
1123 .init = &omap2_init_clksel_parent,
1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1126 .clksel = div4_core_clksel,
1127 .recalc = &omap2_clksel_recalc,
1128};
1129
1130static struct clk iva2_ck = {
1131 .name = "iva2_ck",
1132 .ops = &clkops_omap2_dflt_wait,
1133 .parent = &dpll2_m2_ck,
1134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1135 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1136 .clkdm_name = "iva2_clkdm",
1137 .recalc = &followparent_recalc,
1138};
1139
1140/* Common interface clocks */
1141
1142static const struct clksel div2_core_clksel[] = {
1143 { .parent = &core_ck, .rates = div2_rates },
1144 { .parent = NULL }
1145};
1146
1147static struct clk l3_ick = {
1148 .name = "l3_ick",
1149 .ops = &clkops_null,
1150 .parent = &core_ck,
1151 .init = &omap2_init_clksel_parent,
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1153 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1154 .clksel = div2_core_clksel,
1155 .clkdm_name = "core_l3_clkdm",
1156 .recalc = &omap2_clksel_recalc,
1157};
1158
1159static const struct clksel div2_l3_clksel[] = {
1160 { .parent = &l3_ick, .rates = div2_rates },
1161 { .parent = NULL }
1162};
1163
1164static struct clk l4_ick = {
1165 .name = "l4_ick",
1166 .ops = &clkops_null,
1167 .parent = &l3_ick,
1168 .init = &omap2_init_clksel_parent,
1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1170 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1171 .clksel = div2_l3_clksel,
1172 .clkdm_name = "core_l4_clkdm",
1173 .recalc = &omap2_clksel_recalc,
1174
1175};
1176
1177static const struct clksel div2_l4_clksel[] = {
1178 { .parent = &l4_ick, .rates = div2_rates },
1179 { .parent = NULL }
1180};
1181
1182static struct clk rm_ick = {
1183 .name = "rm_ick",
1184 .ops = &clkops_null,
1185 .parent = &l4_ick,
1186 .init = &omap2_init_clksel_parent,
1187 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1189 .clksel = div2_l4_clksel,
1190 .recalc = &omap2_clksel_recalc,
1191};
1192
1193/* GFX power domain */
1194
1195/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1196
1197static const struct clksel gfx_l3_clksel[] = {
1198 { .parent = &l3_ick, .rates = gfx_l3_rates },
1199 { .parent = NULL }
1200};
1201
1202/*
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1205 */
1206static struct clk gfx_l3_ck = {
1207 .name = "gfx_l3_ck",
1208 .ops = &clkops_omap2_dflt_wait,
1209 .parent = &l3_ick,
1210 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1211 .enable_bit = OMAP_EN_GFX_SHIFT,
1212 .recalc = &followparent_recalc,
1213};
1214
1215static struct clk gfx_l3_fck = {
1216 .name = "gfx_l3_fck",
1217 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck,
1219 .init = &omap2_init_clksel_parent,
1220 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1221 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1222 .clksel = gfx_l3_clksel,
1223 .clkdm_name = "gfx_3430es1_clkdm",
1224 .recalc = &omap2_clksel_recalc,
1225};
1226
1227static struct clk gfx_l3_ick = {
1228 .name = "gfx_l3_ick",
1229 .ops = &clkops_null,
1230 .parent = &gfx_l3_ck,
1231 .clkdm_name = "gfx_3430es1_clkdm",
1232 .recalc = &followparent_recalc,
1233};
1234
1235static struct clk gfx_cg1_ck = {
1236 .name = "gfx_cg1_ck",
1237 .ops = &clkops_omap2_dflt_wait,
1238 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1241 .clkdm_name = "gfx_3430es1_clkdm",
1242 .recalc = &followparent_recalc,
1243};
1244
1245static struct clk gfx_cg2_ck = {
1246 .name = "gfx_cg2_ck",
1247 .ops = &clkops_omap2_dflt_wait,
1248 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1249 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1250 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1251 .clkdm_name = "gfx_3430es1_clkdm",
1252 .recalc = &followparent_recalc,
1253};
1254
1255/* SGX power domain - 3430ES2 only */
1256
1257static const struct clksel_rate sgx_core_rates[] = {
1258 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1259 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1260 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1261 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1262 { .div = 0 },
1263};
1264
1265static const struct clksel_rate sgx_192m_rates[] = {
1266 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1267 { .div = 0 },
1268};
1269
1270static const struct clksel_rate sgx_corex2_rates[] = {
1271 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1272 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1273 { .div = 0 },
1274};
1275
1276static const struct clksel_rate sgx_96m_rates[] = {
1277 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1278 { .div = 0 },
1279};
1280
1281static const struct clksel sgx_clksel[] = {
1282 { .parent = &core_ck, .rates = sgx_core_rates },
1283 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1284 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1285 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1286 { .parent = NULL }
1287};
1288
1289static struct clk sgx_fck = {
1290 .name = "sgx_fck",
1291 .ops = &clkops_omap2_dflt_wait,
1292 .init = &omap2_init_clksel_parent,
1293 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1294 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1295 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1296 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1297 .clksel = sgx_clksel,
1298 .clkdm_name = "sgx_clkdm",
1299 .recalc = &omap2_clksel_recalc,
1300 .set_rate = &omap2_clksel_set_rate,
1301 .round_rate = &omap2_clksel_round_rate
1302};
1303
1304/* This interface clock does not have a CM_AUTOIDLE bit */
1305static struct clk sgx_ick = {
1306 .name = "sgx_ick",
1307 .ops = &clkops_omap2_dflt_wait,
1308 .parent = &l3_ick,
1309 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311 .clkdm_name = "sgx_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315/* CORE power domain */
1316
1317static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1319 .ops = &clkops_omap2_dflt_wait,
1320 .parent = &sys_ck,
1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1323 .clkdm_name = "d2d_clkdm",
1324 .recalc = &followparent_recalc,
1325};
1326
1327static struct clk modem_fck = {
1328 .name = "modem_fck",
1329 .ops = &clkops_omap2_mdmclk_dflt_wait,
1330 .parent = &sys_ck,
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1333 .clkdm_name = "d2d_clkdm",
1334 .recalc = &followparent_recalc,
1335};
1336
1337static struct clk sad2d_ick = {
1338 .name = "sad2d_ick",
1339 .ops = &clkops_omap2_iclk_dflt_wait,
1340 .parent = &l3_ick,
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1343 .clkdm_name = "d2d_clkdm",
1344 .recalc = &followparent_recalc,
1345};
1346
1347static struct clk mad2d_ick = {
1348 .name = "mad2d_ick",
1349 .ops = &clkops_omap2_iclk_dflt_wait,
1350 .parent = &l3_ick,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1353 .clkdm_name = "d2d_clkdm",
1354 .recalc = &followparent_recalc,
1355};
1356
1357static const struct clksel omap343x_gpt_clksel[] = {
1358 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1359 { .parent = &sys_ck, .rates = gpt_sys_rates },
1360 { .parent = NULL}
1361};
1362
1363static struct clk gpt10_fck = {
1364 .name = "gpt10_fck",
1365 .ops = &clkops_omap2_dflt_wait,
1366 .parent = &sys_ck,
1367 .init = &omap2_init_clksel_parent,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1370 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1371 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1372 .clksel = omap343x_gpt_clksel,
1373 .clkdm_name = "core_l4_clkdm",
1374 .recalc = &omap2_clksel_recalc,
1375};
1376
1377static struct clk gpt11_fck = {
1378 .name = "gpt11_fck",
1379 .ops = &clkops_omap2_dflt_wait,
1380 .parent = &sys_ck,
1381 .init = &omap2_init_clksel_parent,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1384 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1386 .clksel = omap343x_gpt_clksel,
1387 .clkdm_name = "core_l4_clkdm",
1388 .recalc = &omap2_clksel_recalc,
1389};
1390
1391static struct clk cpefuse_fck = {
1392 .name = "cpefuse_fck",
1393 .ops = &clkops_omap2_dflt,
1394 .parent = &sys_ck,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1396 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk ts_fck = {
1401 .name = "ts_fck",
1402 .ops = &clkops_omap2_dflt,
1403 .parent = &omap_32k_fck,
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1405 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1406 .recalc = &followparent_recalc,
1407};
1408
1409static struct clk usbtll_fck = {
1410 .name = "usbtll_fck",
1411 .ops = &clkops_omap2_dflt_wait,
1412 .parent = &dpll5_m2_ck,
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1414 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1415 .recalc = &followparent_recalc,
1416};
1417
1418/* CORE 96M FCLK-derived clocks */
1419
1420static struct clk core_96m_fck = {
1421 .name = "core_96m_fck",
1422 .ops = &clkops_null,
1423 .parent = &omap_96m_fck,
1424 .clkdm_name = "core_l4_clkdm",
1425 .recalc = &followparent_recalc,
1426};
1427
1428static struct clk mmchs3_fck = {
1429 .name = "mmchs3_fck",
1430 .ops = &clkops_omap2_dflt_wait,
1431 .parent = &core_96m_fck,
1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1434 .clkdm_name = "core_l4_clkdm",
1435 .recalc = &followparent_recalc,
1436};
1437
1438static struct clk mmchs2_fck = {
1439 .name = "mmchs2_fck",
1440 .ops = &clkops_omap2_dflt_wait,
1441 .parent = &core_96m_fck,
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1444 .clkdm_name = "core_l4_clkdm",
1445 .recalc = &followparent_recalc,
1446};
1447
1448static struct clk mspro_fck = {
1449 .name = "mspro_fck",
1450 .ops = &clkops_omap2_dflt_wait,
1451 .parent = &core_96m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1454 .clkdm_name = "core_l4_clkdm",
1455 .recalc = &followparent_recalc,
1456};
1457
1458static struct clk mmchs1_fck = {
1459 .name = "mmchs1_fck",
1460 .ops = &clkops_omap2_dflt_wait,
1461 .parent = &core_96m_fck,
1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1464 .clkdm_name = "core_l4_clkdm",
1465 .recalc = &followparent_recalc,
1466};
1467
1468static struct clk i2c3_fck = {
1469 .name = "i2c3_fck",
1470 .ops = &clkops_omap2_dflt_wait,
1471 .parent = &core_96m_fck,
1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1474 .clkdm_name = "core_l4_clkdm",
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk i2c2_fck = {
1479 .name = "i2c2_fck",
1480 .ops = &clkops_omap2_dflt_wait,
1481 .parent = &core_96m_fck,
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1484 .clkdm_name = "core_l4_clkdm",
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk i2c1_fck = {
1489 .name = "i2c1_fck",
1490 .ops = &clkops_omap2_dflt_wait,
1491 .parent = &core_96m_fck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1494 .clkdm_name = "core_l4_clkdm",
1495 .recalc = &followparent_recalc,
1496};
1497
1498/*
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1501 */
1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1504 { .div = 0 }
1505};
1506
1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1509 { .div = 0 }
1510};
1511
1512static const struct clksel mcbsp_15_clksel[] = {
1513 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1514 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1515 { .parent = NULL }
1516};
1517
1518static struct clk mcbsp5_fck = {
1519 .name = "mcbsp5_fck",
1520 .ops = &clkops_omap2_dflt_wait,
1521 .init = &omap2_init_clksel_parent,
1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1524 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1525 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1526 .clksel = mcbsp_15_clksel,
1527 .clkdm_name = "core_l4_clkdm",
1528 .recalc = &omap2_clksel_recalc,
1529};
1530
1531static struct clk mcbsp1_fck = {
1532 .name = "mcbsp1_fck",
1533 .ops = &clkops_omap2_dflt_wait,
1534 .init = &omap2_init_clksel_parent,
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1537 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1538 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1539 .clksel = mcbsp_15_clksel,
1540 .clkdm_name = "core_l4_clkdm",
1541 .recalc = &omap2_clksel_recalc,
1542};
1543
1544/* CORE_48M_FCK-derived clocks */
1545
1546static struct clk core_48m_fck = {
1547 .name = "core_48m_fck",
1548 .ops = &clkops_null,
1549 .parent = &omap_48m_fck,
1550 .clkdm_name = "core_l4_clkdm",
1551 .recalc = &followparent_recalc,
1552};
1553
1554static struct clk mcspi4_fck = {
1555 .name = "mcspi4_fck",
1556 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &core_48m_fck,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1560 .recalc = &followparent_recalc,
1561 .clkdm_name = "core_l4_clkdm",
1562};
1563
1564static struct clk mcspi3_fck = {
1565 .name = "mcspi3_fck",
1566 .ops = &clkops_omap2_dflt_wait,
1567 .parent = &core_48m_fck,
1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1570 .recalc = &followparent_recalc,
1571 .clkdm_name = "core_l4_clkdm",
1572};
1573
1574static struct clk mcspi2_fck = {
1575 .name = "mcspi2_fck",
1576 .ops = &clkops_omap2_dflt_wait,
1577 .parent = &core_48m_fck,
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1579 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1580 .recalc = &followparent_recalc,
1581 .clkdm_name = "core_l4_clkdm",
1582};
1583
1584static struct clk mcspi1_fck = {
1585 .name = "mcspi1_fck",
1586 .ops = &clkops_omap2_dflt_wait,
1587 .parent = &core_48m_fck,
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1589 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1590 .recalc = &followparent_recalc,
1591 .clkdm_name = "core_l4_clkdm",
1592};
1593
1594static struct clk uart2_fck = {
1595 .name = "uart2_fck",
1596 .ops = &clkops_omap2_dflt_wait,
1597 .parent = &core_48m_fck,
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1600 .clkdm_name = "core_l4_clkdm",
1601 .recalc = &followparent_recalc,
1602};
1603
1604static struct clk uart1_fck = {
1605 .name = "uart1_fck",
1606 .ops = &clkops_omap2_dflt_wait,
1607 .parent = &core_48m_fck,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1610 .clkdm_name = "core_l4_clkdm",
1611 .recalc = &followparent_recalc,
1612};
1613
1614static struct clk fshostusb_fck = {
1615 .name = "fshostusb_fck",
1616 .ops = &clkops_omap2_dflt_wait,
1617 .parent = &core_48m_fck,
1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1620 .recalc = &followparent_recalc,
1621};
1622
1623/* CORE_12M_FCK based clocks */
1624
1625static struct clk core_12m_fck = {
1626 .name = "core_12m_fck",
1627 .ops = &clkops_null,
1628 .parent = &omap_12m_fck,
1629 .clkdm_name = "core_l4_clkdm",
1630 .recalc = &followparent_recalc,
1631};
1632
1633static struct clk hdq_fck = {
1634 .name = "hdq_fck",
1635 .ops = &clkops_omap2_dflt_wait,
1636 .parent = &core_12m_fck,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1639 .recalc = &followparent_recalc,
1640};
1641
1642/* DPLL3-derived clock */
1643
1644static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1645 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1646 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1647 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1648 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1649 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1650 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1651 { .div = 0 }
1652};
1653
1654static const struct clksel ssi_ssr_clksel[] = {
1655 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1656 { .parent = NULL }
1657};
1658
1659static struct clk ssi_ssr_fck_3430es1 = {
1660 .name = "ssi_ssr_fck",
1661 .ops = &clkops_omap2_dflt,
1662 .init = &omap2_init_clksel_parent,
1663 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1664 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1665 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1666 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1667 .clksel = ssi_ssr_clksel,
1668 .clkdm_name = "core_l4_clkdm",
1669 .recalc = &omap2_clksel_recalc,
1670};
1671
1672static struct clk ssi_ssr_fck_3430es2 = {
1673 .name = "ssi_ssr_fck",
1674 .ops = &clkops_omap3430es2_ssi_wait,
1675 .init = &omap2_init_clksel_parent,
1676 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1677 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1678 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1679 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1680 .clksel = ssi_ssr_clksel,
1681 .clkdm_name = "core_l4_clkdm",
1682 .recalc = &omap2_clksel_recalc,
1683};
1684
1685static struct clk ssi_sst_fck_3430es1 = {
1686 .name = "ssi_sst_fck",
1687 .ops = &clkops_null,
1688 .parent = &ssi_ssr_fck_3430es1,
1689 .fixed_div = 2,
1690 .recalc = &omap_fixed_divisor_recalc,
1691};
1692
1693static struct clk ssi_sst_fck_3430es2 = {
1694 .name = "ssi_sst_fck",
1695 .ops = &clkops_null,
1696 .parent = &ssi_ssr_fck_3430es2,
1697 .fixed_div = 2,
1698 .recalc = &omap_fixed_divisor_recalc,
1699};
1700
1701
1702
1703/* CORE_L3_ICK based clocks */
1704
1705/*
1706 * XXX must add clk_enable/clk_disable for these if standard code won't
1707 * handle it
1708 */
1709static struct clk core_l3_ick = {
1710 .name = "core_l3_ick",
1711 .ops = &clkops_null,
1712 .parent = &l3_ick,
1713 .clkdm_name = "core_l3_clkdm",
1714 .recalc = &followparent_recalc,
1715};
1716
1717static struct clk hsotgusb_ick_3430es1 = {
1718 .name = "hsotgusb_ick",
1719 .ops = &clkops_omap2_iclk_dflt,
1720 .parent = &core_l3_ick,
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1722 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1723 .clkdm_name = "core_l3_clkdm",
1724 .recalc = &followparent_recalc,
1725};
1726
1727static struct clk hsotgusb_ick_3430es2 = {
1728 .name = "hsotgusb_ick",
1729 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1730 .parent = &core_l3_ick,
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1733 .clkdm_name = "core_l3_clkdm",
1734 .recalc = &followparent_recalc,
1735};
1736
1737/* This interface clock does not have a CM_AUTOIDLE bit */
1738static struct clk sdrc_ick = {
1739 .name = "sdrc_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1741 .parent = &core_l3_ick,
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1743 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1744 .flags = ENABLE_ON_INIT,
1745 .clkdm_name = "core_l3_clkdm",
1746 .recalc = &followparent_recalc,
1747};
1748
1749static struct clk gpmc_fck = {
1750 .name = "gpmc_fck",
1751 .ops = &clkops_null,
1752 .parent = &core_l3_ick,
1753 .flags = ENABLE_ON_INIT, /* huh? */
1754 .clkdm_name = "core_l3_clkdm",
1755 .recalc = &followparent_recalc,
1756};
1757
1758/* SECURITY_L3_ICK based clocks */
1759
1760static struct clk security_l3_ick = {
1761 .name = "security_l3_ick",
1762 .ops = &clkops_null,
1763 .parent = &l3_ick,
1764 .recalc = &followparent_recalc,
1765};
1766
1767static struct clk pka_ick = {
1768 .name = "pka_ick",
1769 .ops = &clkops_omap2_iclk_dflt_wait,
1770 .parent = &security_l3_ick,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1772 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1773 .recalc = &followparent_recalc,
1774};
1775
1776/* CORE_L4_ICK based clocks */
1777
1778static struct clk core_l4_ick = {
1779 .name = "core_l4_ick",
1780 .ops = &clkops_null,
1781 .parent = &l4_ick,
1782 .clkdm_name = "core_l4_clkdm",
1783 .recalc = &followparent_recalc,
1784};
1785
1786static struct clk usbtll_ick = {
1787 .name = "usbtll_ick",
1788 .ops = &clkops_omap2_iclk_dflt_wait,
1789 .parent = &core_l4_ick,
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1791 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1792 .clkdm_name = "core_l4_clkdm",
1793 .recalc = &followparent_recalc,
1794};
1795
1796static struct clk mmchs3_ick = {
1797 .name = "mmchs3_ick",
1798 .ops = &clkops_omap2_iclk_dflt_wait,
1799 .parent = &core_l4_ick,
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1802 .clkdm_name = "core_l4_clkdm",
1803 .recalc = &followparent_recalc,
1804};
1805
1806/* Intersystem Communication Registers - chassis mode only */
1807static struct clk icr_ick = {
1808 .name = "icr_ick",
1809 .ops = &clkops_omap2_iclk_dflt_wait,
1810 .parent = &core_l4_ick,
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1813 .clkdm_name = "core_l4_clkdm",
1814 .recalc = &followparent_recalc,
1815};
1816
1817static struct clk aes2_ick = {
1818 .name = "aes2_ick",
1819 .ops = &clkops_omap2_iclk_dflt_wait,
1820 .parent = &core_l4_ick,
1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1823 .clkdm_name = "core_l4_clkdm",
1824 .recalc = &followparent_recalc,
1825};
1826
1827static struct clk sha12_ick = {
1828 .name = "sha12_ick",
1829 .ops = &clkops_omap2_iclk_dflt_wait,
1830 .parent = &core_l4_ick,
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1833 .clkdm_name = "core_l4_clkdm",
1834 .recalc = &followparent_recalc,
1835};
1836
1837static struct clk des2_ick = {
1838 .name = "des2_ick",
1839 .ops = &clkops_omap2_iclk_dflt_wait,
1840 .parent = &core_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1843 .clkdm_name = "core_l4_clkdm",
1844 .recalc = &followparent_recalc,
1845};
1846
1847static struct clk mmchs2_ick = {
1848 .name = "mmchs2_ick",
1849 .ops = &clkops_omap2_iclk_dflt_wait,
1850 .parent = &core_l4_ick,
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1853 .clkdm_name = "core_l4_clkdm",
1854 .recalc = &followparent_recalc,
1855};
1856
1857static struct clk mmchs1_ick = {
1858 .name = "mmchs1_ick",
1859 .ops = &clkops_omap2_iclk_dflt_wait,
1860 .parent = &core_l4_ick,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1863 .clkdm_name = "core_l4_clkdm",
1864 .recalc = &followparent_recalc,
1865};
1866
1867static struct clk mspro_ick = {
1868 .name = "mspro_ick",
1869 .ops = &clkops_omap2_iclk_dflt_wait,
1870 .parent = &core_l4_ick,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1873 .clkdm_name = "core_l4_clkdm",
1874 .recalc = &followparent_recalc,
1875};
1876
1877static struct clk hdq_ick = {
1878 .name = "hdq_ick",
1879 .ops = &clkops_omap2_iclk_dflt_wait,
1880 .parent = &core_l4_ick,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1883 .clkdm_name = "core_l4_clkdm",
1884 .recalc = &followparent_recalc,
1885};
1886
1887static struct clk mcspi4_ick = {
1888 .name = "mcspi4_ick",
1889 .ops = &clkops_omap2_iclk_dflt_wait,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1895};
1896
1897static struct clk mcspi3_ick = {
1898 .name = "mcspi3_ick",
1899 .ops = &clkops_omap2_iclk_dflt_wait,
1900 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1903 .clkdm_name = "core_l4_clkdm",
1904 .recalc = &followparent_recalc,
1905};
1906
1907static struct clk mcspi2_ick = {
1908 .name = "mcspi2_ick",
1909 .ops = &clkops_omap2_iclk_dflt_wait,
1910 .parent = &core_l4_ick,
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk mcspi1_ick = {
1918 .name = "mcspi1_ick",
1919 .ops = &clkops_omap2_iclk_dflt_wait,
1920 .parent = &core_l4_ick,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1923 .clkdm_name = "core_l4_clkdm",
1924 .recalc = &followparent_recalc,
1925};
1926
1927static struct clk i2c3_ick = {
1928 .name = "i2c3_ick",
1929 .ops = &clkops_omap2_iclk_dflt_wait,
1930 .parent = &core_l4_ick,
1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1933 .clkdm_name = "core_l4_clkdm",
1934 .recalc = &followparent_recalc,
1935};
1936
1937static struct clk i2c2_ick = {
1938 .name = "i2c2_ick",
1939 .ops = &clkops_omap2_iclk_dflt_wait,
1940 .parent = &core_l4_ick,
1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1942 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1943 .clkdm_name = "core_l4_clkdm",
1944 .recalc = &followparent_recalc,
1945};
1946
1947static struct clk i2c1_ick = {
1948 .name = "i2c1_ick",
1949 .ops = &clkops_omap2_iclk_dflt_wait,
1950 .parent = &core_l4_ick,
1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1952 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1953 .clkdm_name = "core_l4_clkdm",
1954 .recalc = &followparent_recalc,
1955};
1956
1957static struct clk uart2_ick = {
1958 .name = "uart2_ick",
1959 .ops = &clkops_omap2_iclk_dflt_wait,
1960 .parent = &core_l4_ick,
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1963 .clkdm_name = "core_l4_clkdm",
1964 .recalc = &followparent_recalc,
1965};
1966
1967static struct clk uart1_ick = {
1968 .name = "uart1_ick",
1969 .ops = &clkops_omap2_iclk_dflt_wait,
1970 .parent = &core_l4_ick,
1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1972 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1973 .clkdm_name = "core_l4_clkdm",
1974 .recalc = &followparent_recalc,
1975};
1976
1977static struct clk gpt11_ick = {
1978 .name = "gpt11_ick",
1979 .ops = &clkops_omap2_iclk_dflt_wait,
1980 .parent = &core_l4_ick,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1983 .clkdm_name = "core_l4_clkdm",
1984 .recalc = &followparent_recalc,
1985};
1986
1987static struct clk gpt10_ick = {
1988 .name = "gpt10_ick",
1989 .ops = &clkops_omap2_iclk_dflt_wait,
1990 .parent = &core_l4_ick,
1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1993 .clkdm_name = "core_l4_clkdm",
1994 .recalc = &followparent_recalc,
1995};
1996
1997static struct clk mcbsp5_ick = {
1998 .name = "mcbsp5_ick",
1999 .ops = &clkops_omap2_iclk_dflt_wait,
2000 .parent = &core_l4_ick,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2003 .clkdm_name = "core_l4_clkdm",
2004 .recalc = &followparent_recalc,
2005};
2006
2007static struct clk mcbsp1_ick = {
2008 .name = "mcbsp1_ick",
2009 .ops = &clkops_omap2_iclk_dflt_wait,
2010 .parent = &core_l4_ick,
2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2012 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2013 .clkdm_name = "core_l4_clkdm",
2014 .recalc = &followparent_recalc,
2015};
2016
2017static struct clk fac_ick = {
2018 .name = "fac_ick",
2019 .ops = &clkops_omap2_iclk_dflt_wait,
2020 .parent = &core_l4_ick,
2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2022 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2023 .clkdm_name = "core_l4_clkdm",
2024 .recalc = &followparent_recalc,
2025};
2026
2027static struct clk mailboxes_ick = {
2028 .name = "mailboxes_ick",
2029 .ops = &clkops_omap2_iclk_dflt_wait,
2030 .parent = &core_l4_ick,
2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2032 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2033 .clkdm_name = "core_l4_clkdm",
2034 .recalc = &followparent_recalc,
2035};
2036
2037static struct clk omapctrl_ick = {
2038 .name = "omapctrl_ick",
2039 .ops = &clkops_omap2_iclk_dflt_wait,
2040 .parent = &core_l4_ick,
2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2043 .flags = ENABLE_ON_INIT,
2044 .recalc = &followparent_recalc,
2045};
2046
2047/* SSI_L4_ICK based clocks */
2048
2049static struct clk ssi_l4_ick = {
2050 .name = "ssi_l4_ick",
2051 .ops = &clkops_null,
2052 .parent = &l4_ick,
2053 .clkdm_name = "core_l4_clkdm",
2054 .recalc = &followparent_recalc,
2055};
2056
2057static struct clk ssi_ick_3430es1 = {
2058 .name = "ssi_ick",
2059 .ops = &clkops_omap2_iclk_dflt,
2060 .parent = &ssi_l4_ick,
2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2063 .clkdm_name = "core_l4_clkdm",
2064 .recalc = &followparent_recalc,
2065};
2066
2067static struct clk ssi_ick_3430es2 = {
2068 .name = "ssi_ick",
2069 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2070 .parent = &ssi_l4_ick,
2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2072 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2073 .clkdm_name = "core_l4_clkdm",
2074 .recalc = &followparent_recalc,
2075};
2076
2077/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2078 * but l4_ick makes more sense to me */
2079
2080static const struct clksel usb_l4_clksel[] = {
2081 { .parent = &l4_ick, .rates = div2_rates },
2082 { .parent = NULL },
2083};
2084
2085static struct clk usb_l4_ick = {
2086 .name = "usb_l4_ick",
2087 .ops = &clkops_omap2_iclk_dflt_wait,
2088 .parent = &l4_ick,
2089 .init = &omap2_init_clksel_parent,
2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2092 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2093 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2094 .clksel = usb_l4_clksel,
2095 .recalc = &omap2_clksel_recalc,
2096};
2097
2098/* SECURITY_L4_ICK2 based clocks */
2099
2100static struct clk security_l4_ick2 = {
2101 .name = "security_l4_ick2",
2102 .ops = &clkops_null,
2103 .parent = &l4_ick,
2104 .recalc = &followparent_recalc,
2105};
2106
2107static struct clk aes1_ick = {
2108 .name = "aes1_ick",
2109 .ops = &clkops_omap2_iclk_dflt_wait,
2110 .parent = &security_l4_ick2,
2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk rng_ick = {
2117 .name = "rng_ick",
2118 .ops = &clkops_omap2_iclk_dflt_wait,
2119 .parent = &security_l4_ick2,
2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2122 .recalc = &followparent_recalc,
2123};
2124
2125static struct clk sha11_ick = {
2126 .name = "sha11_ick",
2127 .ops = &clkops_omap2_iclk_dflt_wait,
2128 .parent = &security_l4_ick2,
2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2131 .recalc = &followparent_recalc,
2132};
2133
2134static struct clk des1_ick = {
2135 .name = "des1_ick",
2136 .ops = &clkops_omap2_iclk_dflt_wait,
2137 .parent = &security_l4_ick2,
2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2140 .recalc = &followparent_recalc,
2141};
2142
2143/* DSS */
2144static struct clk dss1_alwon_fck_3430es1 = {
2145 .name = "dss1_alwon_fck",
2146 .ops = &clkops_omap2_dflt,
2147 .parent = &dpll4_m4x2_ck,
2148 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2149 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2150 .clkdm_name = "dss_clkdm",
2151 .recalc = &followparent_recalc,
2152};
2153
2154static struct clk dss1_alwon_fck_3430es2 = {
2155 .name = "dss1_alwon_fck",
2156 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2157 .parent = &dpll4_m4x2_ck,
2158 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2159 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2160 .clkdm_name = "dss_clkdm",
2161 .recalc = &followparent_recalc,
2162};
2163
2164static struct clk dss_tv_fck = {
2165 .name = "dss_tv_fck",
2166 .ops = &clkops_omap2_dflt,
2167 .parent = &omap_54m_fck,
2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2169 .enable_bit = OMAP3430_EN_TV_SHIFT,
2170 .clkdm_name = "dss_clkdm",
2171 .recalc = &followparent_recalc,
2172};
2173
2174static struct clk dss_96m_fck = {
2175 .name = "dss_96m_fck",
2176 .ops = &clkops_omap2_dflt,
2177 .parent = &omap_96m_fck,
2178 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2179 .enable_bit = OMAP3430_EN_TV_SHIFT,
2180 .clkdm_name = "dss_clkdm",
2181 .recalc = &followparent_recalc,
2182};
2183
2184static struct clk dss2_alwon_fck = {
2185 .name = "dss2_alwon_fck",
2186 .ops = &clkops_omap2_dflt,
2187 .parent = &sys_ck,
2188 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2189 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2190 .clkdm_name = "dss_clkdm",
2191 .recalc = &followparent_recalc,
2192};
2193
2194static struct clk dss_ick_3430es1 = {
2195 /* Handles both L3 and L4 clocks */
2196 .name = "dss_ick",
2197 .ops = &clkops_omap2_iclk_dflt,
2198 .parent = &l4_ick,
2199 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2200 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2201 .clkdm_name = "dss_clkdm",
2202 .recalc = &followparent_recalc,
2203};
2204
2205static struct clk dss_ick_3430es2 = {
2206 /* Handles both L3 and L4 clocks */
2207 .name = "dss_ick",
2208 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2209 .parent = &l4_ick,
2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2211 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2212 .clkdm_name = "dss_clkdm",
2213 .recalc = &followparent_recalc,
2214};
2215
2216/* CAM */
2217
2218static struct clk cam_mclk = {
2219 .name = "cam_mclk",
2220 .ops = &clkops_omap2_dflt,
2221 .parent = &dpll4_m5x2_ck,
2222 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2223 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2224 .clkdm_name = "cam_clkdm",
2225 .recalc = &followparent_recalc,
2226};
2227
2228static struct clk cam_ick = {
2229 /* Handles both L3 and L4 clocks */
2230 .name = "cam_ick",
2231 .ops = &clkops_omap2_iclk_dflt,
2232 .parent = &l4_ick,
2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2234 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2235 .clkdm_name = "cam_clkdm",
2236 .recalc = &followparent_recalc,
2237};
2238
2239static struct clk csi2_96m_fck = {
2240 .name = "csi2_96m_fck",
2241 .ops = &clkops_omap2_dflt,
2242 .parent = &core_96m_fck,
2243 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2244 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2245 .clkdm_name = "cam_clkdm",
2246 .recalc = &followparent_recalc,
2247};
2248
2249/* USBHOST - 3430ES2 only */
2250
2251static struct clk usbhost_120m_fck = {
2252 .name = "usbhost_120m_fck",
2253 .ops = &clkops_omap2_dflt,
2254 .parent = &dpll5_m2_ck,
2255 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2256 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2257 .clkdm_name = "usbhost_clkdm",
2258 .recalc = &followparent_recalc,
2259};
2260
2261static struct clk usbhost_48m_fck = {
2262 .name = "usbhost_48m_fck",
2263 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2264 .parent = &omap_48m_fck,
2265 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2266 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2267 .clkdm_name = "usbhost_clkdm",
2268 .recalc = &followparent_recalc,
2269};
2270
2271static struct clk usbhost_ick = {
2272 /* Handles both L3 and L4 clocks */
2273 .name = "usbhost_ick",
2274 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2275 .parent = &l4_ick,
2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2277 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2278 .clkdm_name = "usbhost_clkdm",
2279 .recalc = &followparent_recalc,
2280};
2281
2282/* WKUP */
2283
2284static const struct clksel_rate usim_96m_rates[] = {
2285 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2286 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2287 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2288 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2289 { .div = 0 },
2290};
2291
2292static const struct clksel_rate usim_120m_rates[] = {
2293 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2294 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2295 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2296 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2297 { .div = 0 },
2298};
2299
2300static const struct clksel usim_clksel[] = {
2301 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2302 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2303 { .parent = &sys_ck, .rates = div2_rates },
2304 { .parent = NULL },
2305};
2306
2307/* 3430ES2 only */
2308static struct clk usim_fck = {
2309 .name = "usim_fck",
2310 .ops = &clkops_omap2_dflt_wait,
2311 .init = &omap2_init_clksel_parent,
2312 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2313 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2314 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2315 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2316 .clksel = usim_clksel,
2317 .recalc = &omap2_clksel_recalc,
2318};
2319
2320/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2321static struct clk gpt1_fck = {
2322 .name = "gpt1_fck",
2323 .ops = &clkops_omap2_dflt_wait,
2324 .init = &omap2_init_clksel_parent,
2325 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2326 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2327 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2328 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2329 .clksel = omap343x_gpt_clksel,
2330 .clkdm_name = "wkup_clkdm",
2331 .recalc = &omap2_clksel_recalc,
2332};
2333
2334static struct clk wkup_32k_fck = {
2335 .name = "wkup_32k_fck",
2336 .ops = &clkops_null,
2337 .parent = &omap_32k_fck,
2338 .clkdm_name = "wkup_clkdm",
2339 .recalc = &followparent_recalc,
2340};
2341
2342static struct clk gpio1_dbck = {
2343 .name = "gpio1_dbck",
2344 .ops = &clkops_omap2_dflt,
2345 .parent = &wkup_32k_fck,
2346 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2348 .clkdm_name = "wkup_clkdm",
2349 .recalc = &followparent_recalc,
2350};
2351
2352static struct clk wdt2_fck = {
2353 .name = "wdt2_fck",
2354 .ops = &clkops_omap2_dflt_wait,
2355 .parent = &wkup_32k_fck,
2356 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2357 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2358 .clkdm_name = "wkup_clkdm",
2359 .recalc = &followparent_recalc,
2360};
2361
2362static struct clk wkup_l4_ick = {
2363 .name = "wkup_l4_ick",
2364 .ops = &clkops_null,
2365 .parent = &sys_ck,
2366 .clkdm_name = "wkup_clkdm",
2367 .recalc = &followparent_recalc,
2368};
2369
2370/* 3430ES2 only */
2371/* Never specifically named in the TRM, so we have to infer a likely name */
2372static struct clk usim_ick = {
2373 .name = "usim_ick",
2374 .ops = &clkops_omap2_iclk_dflt_wait,
2375 .parent = &wkup_l4_ick,
2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2377 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2378 .clkdm_name = "wkup_clkdm",
2379 .recalc = &followparent_recalc,
2380};
2381
2382static struct clk wdt2_ick = {
2383 .name = "wdt2_ick",
2384 .ops = &clkops_omap2_iclk_dflt_wait,
2385 .parent = &wkup_l4_ick,
2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2387 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2388 .clkdm_name = "wkup_clkdm",
2389 .recalc = &followparent_recalc,
2390};
2391
2392static struct clk wdt1_ick = {
2393 .name = "wdt1_ick",
2394 .ops = &clkops_omap2_iclk_dflt_wait,
2395 .parent = &wkup_l4_ick,
2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2397 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2398 .clkdm_name = "wkup_clkdm",
2399 .recalc = &followparent_recalc,
2400};
2401
2402static struct clk gpio1_ick = {
2403 .name = "gpio1_ick",
2404 .ops = &clkops_omap2_iclk_dflt_wait,
2405 .parent = &wkup_l4_ick,
2406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2407 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2408 .clkdm_name = "wkup_clkdm",
2409 .recalc = &followparent_recalc,
2410};
2411
2412static struct clk omap_32ksync_ick = {
2413 .name = "omap_32ksync_ick",
2414 .ops = &clkops_omap2_iclk_dflt_wait,
2415 .parent = &wkup_l4_ick,
2416 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2417 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2418 .clkdm_name = "wkup_clkdm",
2419 .recalc = &followparent_recalc,
2420};
2421
2422/* XXX This clock no longer exists in 3430 TRM rev F */
2423static struct clk gpt12_ick = {
2424 .name = "gpt12_ick",
2425 .ops = &clkops_omap2_iclk_dflt_wait,
2426 .parent = &wkup_l4_ick,
2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2428 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2429 .clkdm_name = "wkup_clkdm",
2430 .recalc = &followparent_recalc,
2431};
2432
2433static struct clk gpt1_ick = {
2434 .name = "gpt1_ick",
2435 .ops = &clkops_omap2_iclk_dflt_wait,
2436 .parent = &wkup_l4_ick,
2437 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2438 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2439 .clkdm_name = "wkup_clkdm",
2440 .recalc = &followparent_recalc,
2441};
2442
2443
2444
2445/* PER clock domain */
2446
2447static struct clk per_96m_fck = {
2448 .name = "per_96m_fck",
2449 .ops = &clkops_null,
2450 .parent = &omap_96m_alwon_fck,
2451 .clkdm_name = "per_clkdm",
2452 .recalc = &followparent_recalc,
2453};
2454
2455static struct clk per_48m_fck = {
2456 .name = "per_48m_fck",
2457 .ops = &clkops_null,
2458 .parent = &omap_48m_fck,
2459 .clkdm_name = "per_clkdm",
2460 .recalc = &followparent_recalc,
2461};
2462
2463static struct clk uart3_fck = {
2464 .name = "uart3_fck",
2465 .ops = &clkops_omap2_dflt_wait,
2466 .parent = &per_48m_fck,
2467 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2469 .clkdm_name = "per_clkdm",
2470 .recalc = &followparent_recalc,
2471};
2472
2473static struct clk uart4_fck = {
2474 .name = "uart4_fck",
2475 .ops = &clkops_omap2_dflt_wait,
2476 .parent = &per_48m_fck,
2477 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2478 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2479 .clkdm_name = "per_clkdm",
2480 .recalc = &followparent_recalc,
2481};
2482
2483static struct clk gpt2_fck = {
2484 .name = "gpt2_fck",
2485 .ops = &clkops_omap2_dflt_wait,
2486 .init = &omap2_init_clksel_parent,
2487 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2488 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2489 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2490 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2491 .clksel = omap343x_gpt_clksel,
2492 .clkdm_name = "per_clkdm",
2493 .recalc = &omap2_clksel_recalc,
2494};
2495
2496static struct clk gpt3_fck = {
2497 .name = "gpt3_fck",
2498 .ops = &clkops_omap2_dflt_wait,
2499 .init = &omap2_init_clksel_parent,
2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2501 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2502 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2503 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2504 .clksel = omap343x_gpt_clksel,
2505 .clkdm_name = "per_clkdm",
2506 .recalc = &omap2_clksel_recalc,
2507};
2508
2509static struct clk gpt4_fck = {
2510 .name = "gpt4_fck",
2511 .ops = &clkops_omap2_dflt_wait,
2512 .init = &omap2_init_clksel_parent,
2513 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2514 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2515 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2516 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2517 .clksel = omap343x_gpt_clksel,
2518 .clkdm_name = "per_clkdm",
2519 .recalc = &omap2_clksel_recalc,
2520};
2521
2522static struct clk gpt5_fck = {
2523 .name = "gpt5_fck",
2524 .ops = &clkops_omap2_dflt_wait,
2525 .init = &omap2_init_clksel_parent,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2528 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2530 .clksel = omap343x_gpt_clksel,
2531 .clkdm_name = "per_clkdm",
2532 .recalc = &omap2_clksel_recalc,
2533};
2534
2535static struct clk gpt6_fck = {
2536 .name = "gpt6_fck",
2537 .ops = &clkops_omap2_dflt_wait,
2538 .init = &omap2_init_clksel_parent,
2539 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2540 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2541 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2542 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2543 .clksel = omap343x_gpt_clksel,
2544 .clkdm_name = "per_clkdm",
2545 .recalc = &omap2_clksel_recalc,
2546};
2547
2548static struct clk gpt7_fck = {
2549 .name = "gpt7_fck",
2550 .ops = &clkops_omap2_dflt_wait,
2551 .init = &omap2_init_clksel_parent,
2552 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2553 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2554 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2555 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2556 .clksel = omap343x_gpt_clksel,
2557 .clkdm_name = "per_clkdm",
2558 .recalc = &omap2_clksel_recalc,
2559};
2560
2561static struct clk gpt8_fck = {
2562 .name = "gpt8_fck",
2563 .ops = &clkops_omap2_dflt_wait,
2564 .init = &omap2_init_clksel_parent,
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2567 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2568 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2569 .clksel = omap343x_gpt_clksel,
2570 .clkdm_name = "per_clkdm",
2571 .recalc = &omap2_clksel_recalc,
2572};
2573
2574static struct clk gpt9_fck = {
2575 .name = "gpt9_fck",
2576 .ops = &clkops_omap2_dflt_wait,
2577 .init = &omap2_init_clksel_parent,
2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2580 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2581 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2582 .clksel = omap343x_gpt_clksel,
2583 .clkdm_name = "per_clkdm",
2584 .recalc = &omap2_clksel_recalc,
2585};
2586
2587static struct clk per_32k_alwon_fck = {
2588 .name = "per_32k_alwon_fck",
2589 .ops = &clkops_null,
2590 .parent = &omap_32k_fck,
2591 .clkdm_name = "per_clkdm",
2592 .recalc = &followparent_recalc,
2593};
2594
2595static struct clk gpio6_dbck = {
2596 .name = "gpio6_dbck",
2597 .ops = &clkops_omap2_dflt,
2598 .parent = &per_32k_alwon_fck,
2599 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2600 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2601 .clkdm_name = "per_clkdm",
2602 .recalc = &followparent_recalc,
2603};
2604
2605static struct clk gpio5_dbck = {
2606 .name = "gpio5_dbck",
2607 .ops = &clkops_omap2_dflt,
2608 .parent = &per_32k_alwon_fck,
2609 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2610 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2611 .clkdm_name = "per_clkdm",
2612 .recalc = &followparent_recalc,
2613};
2614
2615static struct clk gpio4_dbck = {
2616 .name = "gpio4_dbck",
2617 .ops = &clkops_omap2_dflt,
2618 .parent = &per_32k_alwon_fck,
2619 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2620 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2621 .clkdm_name = "per_clkdm",
2622 .recalc = &followparent_recalc,
2623};
2624
2625static struct clk gpio3_dbck = {
2626 .name = "gpio3_dbck",
2627 .ops = &clkops_omap2_dflt,
2628 .parent = &per_32k_alwon_fck,
2629 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2630 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2631 .clkdm_name = "per_clkdm",
2632 .recalc = &followparent_recalc,
2633};
2634
2635static struct clk gpio2_dbck = {
2636 .name = "gpio2_dbck",
2637 .ops = &clkops_omap2_dflt,
2638 .parent = &per_32k_alwon_fck,
2639 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2640 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2641 .clkdm_name = "per_clkdm",
2642 .recalc = &followparent_recalc,
2643};
2644
2645static struct clk wdt3_fck = {
2646 .name = "wdt3_fck",
2647 .ops = &clkops_omap2_dflt_wait,
2648 .parent = &per_32k_alwon_fck,
2649 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2650 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2651 .clkdm_name = "per_clkdm",
2652 .recalc = &followparent_recalc,
2653};
2654
2655static struct clk per_l4_ick = {
2656 .name = "per_l4_ick",
2657 .ops = &clkops_null,
2658 .parent = &l4_ick,
2659 .clkdm_name = "per_clkdm",
2660 .recalc = &followparent_recalc,
2661};
2662
2663static struct clk gpio6_ick = {
2664 .name = "gpio6_ick",
2665 .ops = &clkops_omap2_iclk_dflt_wait,
2666 .parent = &per_l4_ick,
2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2668 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2669 .clkdm_name = "per_clkdm",
2670 .recalc = &followparent_recalc,
2671};
2672
2673static struct clk gpio5_ick = {
2674 .name = "gpio5_ick",
2675 .ops = &clkops_omap2_iclk_dflt_wait,
2676 .parent = &per_l4_ick,
2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2678 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2679 .clkdm_name = "per_clkdm",
2680 .recalc = &followparent_recalc,
2681};
2682
2683static struct clk gpio4_ick = {
2684 .name = "gpio4_ick",
2685 .ops = &clkops_omap2_iclk_dflt_wait,
2686 .parent = &per_l4_ick,
2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2688 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2689 .clkdm_name = "per_clkdm",
2690 .recalc = &followparent_recalc,
2691};
2692
2693static struct clk gpio3_ick = {
2694 .name = "gpio3_ick",
2695 .ops = &clkops_omap2_iclk_dflt_wait,
2696 .parent = &per_l4_ick,
2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2698 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2699 .clkdm_name = "per_clkdm",
2700 .recalc = &followparent_recalc,
2701};
2702
2703static struct clk gpio2_ick = {
2704 .name = "gpio2_ick",
2705 .ops = &clkops_omap2_iclk_dflt_wait,
2706 .parent = &per_l4_ick,
2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2708 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2709 .clkdm_name = "per_clkdm",
2710 .recalc = &followparent_recalc,
2711};
2712
2713static struct clk wdt3_ick = {
2714 .name = "wdt3_ick",
2715 .ops = &clkops_omap2_iclk_dflt_wait,
2716 .parent = &per_l4_ick,
2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2718 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2719 .clkdm_name = "per_clkdm",
2720 .recalc = &followparent_recalc,
2721};
2722
2723static struct clk uart3_ick = {
2724 .name = "uart3_ick",
2725 .ops = &clkops_omap2_iclk_dflt_wait,
2726 .parent = &per_l4_ick,
2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2728 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2729 .clkdm_name = "per_clkdm",
2730 .recalc = &followparent_recalc,
2731};
2732
2733static struct clk uart4_ick = {
2734 .name = "uart4_ick",
2735 .ops = &clkops_omap2_iclk_dflt_wait,
2736 .parent = &per_l4_ick,
2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2738 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2739 .clkdm_name = "per_clkdm",
2740 .recalc = &followparent_recalc,
2741};
2742
2743static struct clk gpt9_ick = {
2744 .name = "gpt9_ick",
2745 .ops = &clkops_omap2_iclk_dflt_wait,
2746 .parent = &per_l4_ick,
2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2748 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2749 .clkdm_name = "per_clkdm",
2750 .recalc = &followparent_recalc,
2751};
2752
2753static struct clk gpt8_ick = {
2754 .name = "gpt8_ick",
2755 .ops = &clkops_omap2_iclk_dflt_wait,
2756 .parent = &per_l4_ick,
2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2758 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2759 .clkdm_name = "per_clkdm",
2760 .recalc = &followparent_recalc,
2761};
2762
2763static struct clk gpt7_ick = {
2764 .name = "gpt7_ick",
2765 .ops = &clkops_omap2_iclk_dflt_wait,
2766 .parent = &per_l4_ick,
2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2768 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2769 .clkdm_name = "per_clkdm",
2770 .recalc = &followparent_recalc,
2771};
2772
2773static struct clk gpt6_ick = {
2774 .name = "gpt6_ick",
2775 .ops = &clkops_omap2_iclk_dflt_wait,
2776 .parent = &per_l4_ick,
2777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2778 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2779 .clkdm_name = "per_clkdm",
2780 .recalc = &followparent_recalc,
2781};
2782
2783static struct clk gpt5_ick = {
2784 .name = "gpt5_ick",
2785 .ops = &clkops_omap2_iclk_dflt_wait,
2786 .parent = &per_l4_ick,
2787 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2788 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2789 .clkdm_name = "per_clkdm",
2790 .recalc = &followparent_recalc,
2791};
2792
2793static struct clk gpt4_ick = {
2794 .name = "gpt4_ick",
2795 .ops = &clkops_omap2_iclk_dflt_wait,
2796 .parent = &per_l4_ick,
2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2798 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2799 .clkdm_name = "per_clkdm",
2800 .recalc = &followparent_recalc,
2801};
2802
2803static struct clk gpt3_ick = {
2804 .name = "gpt3_ick",
2805 .ops = &clkops_omap2_iclk_dflt_wait,
2806 .parent = &per_l4_ick,
2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2808 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2809 .clkdm_name = "per_clkdm",
2810 .recalc = &followparent_recalc,
2811};
2812
2813static struct clk gpt2_ick = {
2814 .name = "gpt2_ick",
2815 .ops = &clkops_omap2_iclk_dflt_wait,
2816 .parent = &per_l4_ick,
2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2818 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2819 .clkdm_name = "per_clkdm",
2820 .recalc = &followparent_recalc,
2821};
2822
2823static struct clk mcbsp2_ick = {
2824 .name = "mcbsp2_ick",
2825 .ops = &clkops_omap2_iclk_dflt_wait,
2826 .parent = &per_l4_ick,
2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2829 .clkdm_name = "per_clkdm",
2830 .recalc = &followparent_recalc,
2831};
2832
2833static struct clk mcbsp3_ick = {
2834 .name = "mcbsp3_ick",
2835 .ops = &clkops_omap2_iclk_dflt_wait,
2836 .parent = &per_l4_ick,
2837 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2838 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2839 .clkdm_name = "per_clkdm",
2840 .recalc = &followparent_recalc,
2841};
2842
2843static struct clk mcbsp4_ick = {
2844 .name = "mcbsp4_ick",
2845 .ops = &clkops_omap2_iclk_dflt_wait,
2846 .parent = &per_l4_ick,
2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2849 .clkdm_name = "per_clkdm",
2850 .recalc = &followparent_recalc,
2851};
2852
2853static const struct clksel mcbsp_234_clksel[] = {
2854 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2855 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2856 { .parent = NULL }
2857};
2858
2859static struct clk mcbsp2_fck = {
2860 .name = "mcbsp2_fck",
2861 .ops = &clkops_omap2_dflt_wait,
2862 .init = &omap2_init_clksel_parent,
2863 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2864 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2865 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2866 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2867 .clksel = mcbsp_234_clksel,
2868 .clkdm_name = "per_clkdm",
2869 .recalc = &omap2_clksel_recalc,
2870};
2871
2872static struct clk mcbsp3_fck = {
2873 .name = "mcbsp3_fck",
2874 .ops = &clkops_omap2_dflt_wait,
2875 .init = &omap2_init_clksel_parent,
2876 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2877 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2878 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2879 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2880 .clksel = mcbsp_234_clksel,
2881 .clkdm_name = "per_clkdm",
2882 .recalc = &omap2_clksel_recalc,
2883};
2884
2885static struct clk mcbsp4_fck = {
2886 .name = "mcbsp4_fck",
2887 .ops = &clkops_omap2_dflt_wait,
2888 .init = &omap2_init_clksel_parent,
2889 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2890 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2891 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2892 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2893 .clksel = mcbsp_234_clksel,
2894 .clkdm_name = "per_clkdm",
2895 .recalc = &omap2_clksel_recalc,
2896};
2897
2898/* EMU clocks */
2899
2900/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2901
2902static const struct clksel_rate emu_src_sys_rates[] = {
2903 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2904 { .div = 0 },
2905};
2906
2907static const struct clksel_rate emu_src_core_rates[] = {
2908 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2909 { .div = 0 },
2910};
2911
2912static const struct clksel_rate emu_src_per_rates[] = {
2913 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2914 { .div = 0 },
2915};
2916
2917static const struct clksel_rate emu_src_mpu_rates[] = {
2918 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2919 { .div = 0 },
2920};
2921
2922static const struct clksel emu_src_clksel[] = {
2923 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2924 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2925 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2926 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2927 { .parent = NULL },
2928};
2929
2930/*
2931 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2932 * to switch the source of some of the EMU clocks.
2933 * XXX Are there CLKEN bits for these EMU clks?
2934 */
2935static struct clk emu_src_ck = {
2936 .name = "emu_src_ck",
2937 .ops = &clkops_null,
2938 .init = &omap2_init_clksel_parent,
2939 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2940 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2941 .clksel = emu_src_clksel,
2942 .clkdm_name = "emu_clkdm",
2943 .recalc = &omap2_clksel_recalc,
2944};
2945
2946static const struct clksel_rate pclk_emu_rates[] = {
2947 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2948 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2949 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2950 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2951 { .div = 0 },
2952};
2953
2954static const struct clksel pclk_emu_clksel[] = {
2955 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2956 { .parent = NULL },
2957};
2958
2959static struct clk pclk_fck = {
2960 .name = "pclk_fck",
2961 .ops = &clkops_null,
2962 .init = &omap2_init_clksel_parent,
2963 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2964 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2965 .clksel = pclk_emu_clksel,
2966 .clkdm_name = "emu_clkdm",
2967 .recalc = &omap2_clksel_recalc,
2968};
2969
2970static const struct clksel_rate pclkx2_emu_rates[] = {
2971 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2972 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2973 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2974 { .div = 0 },
2975};
2976
2977static const struct clksel pclkx2_emu_clksel[] = {
2978 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2979 { .parent = NULL },
2980};
2981
2982static struct clk pclkx2_fck = {
2983 .name = "pclkx2_fck",
2984 .ops = &clkops_null,
2985 .init = &omap2_init_clksel_parent,
2986 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2987 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2988 .clksel = pclkx2_emu_clksel,
2989 .clkdm_name = "emu_clkdm",
2990 .recalc = &omap2_clksel_recalc,
2991};
2992
2993static const struct clksel atclk_emu_clksel[] = {
2994 { .parent = &emu_src_ck, .rates = div2_rates },
2995 { .parent = NULL },
2996};
2997
2998static struct clk atclk_fck = {
2999 .name = "atclk_fck",
3000 .ops = &clkops_null,
3001 .init = &omap2_init_clksel_parent,
3002 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3003 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3004 .clksel = atclk_emu_clksel,
3005 .clkdm_name = "emu_clkdm",
3006 .recalc = &omap2_clksel_recalc,
3007};
3008
3009static struct clk traceclk_src_fck = {
3010 .name = "traceclk_src_fck",
3011 .ops = &clkops_null,
3012 .init = &omap2_init_clksel_parent,
3013 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3014 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3015 .clksel = emu_src_clksel,
3016 .clkdm_name = "emu_clkdm",
3017 .recalc = &omap2_clksel_recalc,
3018};
3019
3020static const struct clksel_rate traceclk_rates[] = {
3021 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3022 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3023 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3024 { .div = 0 },
3025};
3026
3027static const struct clksel traceclk_clksel[] = {
3028 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3029 { .parent = NULL },
3030};
3031
3032static struct clk traceclk_fck = {
3033 .name = "traceclk_fck",
3034 .ops = &clkops_null,
3035 .init = &omap2_init_clksel_parent,
3036 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3037 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3038 .clksel = traceclk_clksel,
3039 .clkdm_name = "emu_clkdm",
3040 .recalc = &omap2_clksel_recalc,
3041};
3042
3043/* SR clocks */
3044
3045/* SmartReflex fclk (VDD1) */
3046static struct clk sr1_fck = {
3047 .name = "sr1_fck",
3048 .ops = &clkops_omap2_dflt_wait,
3049 .parent = &sys_ck,
3050 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3051 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3052 .clkdm_name = "wkup_clkdm",
3053 .recalc = &followparent_recalc,
3054};
3055
3056/* SmartReflex fclk (VDD2) */
3057static struct clk sr2_fck = {
3058 .name = "sr2_fck",
3059 .ops = &clkops_omap2_dflt_wait,
3060 .parent = &sys_ck,
3061 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3062 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3063 .clkdm_name = "wkup_clkdm",
3064 .recalc = &followparent_recalc,
3065};
3066
3067static struct clk sr_l4_ick = {
3068 .name = "sr_l4_ick",
3069 .ops = &clkops_null, /* RMK: missing? */
3070 .parent = &l4_ick,
3071 .clkdm_name = "core_l4_clkdm",
3072 .recalc = &followparent_recalc,
3073};
3074
3075/* SECURE_32K_FCK clocks */
3076
3077static struct clk gpt12_fck = {
3078 .name = "gpt12_fck",
3079 .ops = &clkops_null,
3080 .parent = &secure_32k_fck,
3081 .clkdm_name = "wkup_clkdm",
3082 .recalc = &followparent_recalc,
3083};
3084
3085static struct clk wdt1_fck = {
3086 .name = "wdt1_fck",
3087 .ops = &clkops_null,
3088 .parent = &secure_32k_fck,
3089 .clkdm_name = "wkup_clkdm",
3090 .recalc = &followparent_recalc,
3091};
3092
3093/* Clocks for AM35XX */
3094static struct clk ipss_ick = {
3095 .name = "ipss_ick",
3096 .ops = &clkops_am35xx_ipss_wait,
3097 .parent = &core_l3_ick,
3098 .clkdm_name = "core_l3_clkdm",
3099 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3100 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3101 .recalc = &followparent_recalc,
3102};
3103
3104static struct clk emac_ick = {
3105 .name = "emac_ick",
3106 .ops = &clkops_am35xx_ipss_module_wait,
3107 .parent = &ipss_ick,
3108 .clkdm_name = "core_l3_clkdm",
3109 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3110 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3111 .recalc = &followparent_recalc,
3112};
3113
3114static struct clk rmii_ck = {
3115 .name = "rmii_ck",
3116 .ops = &clkops_null,
3117 .rate = 50000000,
3118};
3119
3120static struct clk emac_fck = {
3121 .name = "emac_fck",
3122 .ops = &clkops_omap2_dflt,
3123 .parent = &rmii_ck,
3124 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3125 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3126 .recalc = &followparent_recalc,
3127};
3128
3129static struct clk hsotgusb_ick_am35xx = {
3130 .name = "hsotgusb_ick",
3131 .ops = &clkops_am35xx_ipss_module_wait,
3132 .parent = &ipss_ick,
3133 .clkdm_name = "core_l3_clkdm",
3134 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3135 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3136 .recalc = &followparent_recalc,
3137};
3138
3139static struct clk hsotgusb_fck_am35xx = {
3140 .name = "hsotgusb_fck",
3141 .ops = &clkops_omap2_dflt,
3142 .parent = &sys_ck,
3143 .clkdm_name = "core_l3_clkdm",
3144 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3145 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3146 .recalc = &followparent_recalc,
3147};
3148
3149static struct clk hecc_ck = {
3150 .name = "hecc_ck",
3151 .ops = &clkops_am35xx_ipss_module_wait,
3152 .parent = &sys_ck,
3153 .clkdm_name = "core_l3_clkdm",
3154 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3155 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3156 .recalc = &followparent_recalc,
3157};
3158
3159static struct clk vpfe_ick = {
3160 .name = "vpfe_ick",
3161 .ops = &clkops_am35xx_ipss_module_wait,
3162 .parent = &ipss_ick,
3163 .clkdm_name = "core_l3_clkdm",
3164 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3165 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3166 .recalc = &followparent_recalc,
3167};
3168
3169static struct clk pclk_ck = {
3170 .name = "pclk_ck",
3171 .ops = &clkops_null,
3172 .rate = 27000000,
3173};
3174
3175static struct clk vpfe_fck = {
3176 .name = "vpfe_fck",
3177 .ops = &clkops_omap2_dflt,
3178 .parent = &pclk_ck,
3179 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3180 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3181 .recalc = &followparent_recalc,
3182};
3183
3184/*
3185 * The UART1/2 functional clock acts as the functional
3186 * clock for UART4. No separate fclk control available.
3187 */
3188static struct clk uart4_ick_am35xx = {
3189 .name = "uart4_ick",
3190 .ops = &clkops_omap2_iclk_dflt_wait,
3191 .parent = &core_l4_ick,
3192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3193 .enable_bit = AM35XX_EN_UART4_SHIFT,
3194 .clkdm_name = "core_l4_clkdm",
3195 .recalc = &followparent_recalc,
3196};
3197
3198static struct clk dummy_apb_pclk = {
3199 .name = "apb_pclk",
3200 .ops = &clkops_null,
3201};
3202
3203/*
3204 * clkdev
3205 */
3206
3207/* XXX At some point we should rename this file to clock3xxx_data.c */
3208static struct omap_clk omap3xxx_clks[] = {
3209 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3210 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3211 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3212 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3213 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3214 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3215 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3216 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3217 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3218 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3219 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3220 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3221 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3222 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3223 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3224 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3225 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3226 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3227 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3228 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3229 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3230 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3231 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3232 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3233 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3234 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3235 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3236 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3237 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3238 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3239 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3240 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3241 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3242 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3243 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3244 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3245 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3246 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3247 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3248 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3249 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3250 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3251 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3252 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3253 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3254 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3255 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3258 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3259 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3260 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3261 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3262 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3263 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3264 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3265 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3266 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3267 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3268 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3269 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3270 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3271 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3272 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3273 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3274 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3275 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3276 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3277 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3278 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3279 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3280 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3281 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3282 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3283 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3284 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3285 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3286 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3287 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3288 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3292 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3293 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3294 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3295 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3296 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3297 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3298 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3299 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3300 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3301 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3302 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3303 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3304 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3305 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3306 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3307 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3308 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3309 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3310 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3311 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3312 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3313 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3314 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3315 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3317 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3318 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3319 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3320 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3321 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3322 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3323 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3324 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3325 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3327 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3328 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3329 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3330 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3331 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3332 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3333 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3334 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3335 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3336 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3337 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3338 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3339 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3340 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3341 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3342 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3343 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3344 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3345 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3346 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3347 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3348 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3349 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3350 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3351 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3352 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3353 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3354 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3355 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3356 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3357 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3358 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3359 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3360 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3361 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3362 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3363 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3364 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3365 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3366 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3367 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3368 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3369 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3370 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3371 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3372 CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3373 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374 CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3375 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3376 CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3377 CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3378 CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3379 CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3380 CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3381 CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3382 CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3383 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3384 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3385 CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX),
3386 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3387 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3388 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3389 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3390 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3391 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3392 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3393 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3394 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3395 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3396 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3397 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3398 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3399 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3400 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3401 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3402 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3403 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3404 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3405 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3406 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3407 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3408 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3409 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3410 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3411 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3412 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3413 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3414 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3415 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3416 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3417 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3418 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3419 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3420 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3421 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3422 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3423 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3424 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3425 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3426 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3427 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3428 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3429 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3430 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3431 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3432 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3433 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3434 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3435 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3436 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3437 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3438 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3439 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3440 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3441 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3442 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3443 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3444 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3445 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3446 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3447 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3448 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3449 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3450 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3451 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3452 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3453 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3454 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3455 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3456 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3457 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3458 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3459 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3460 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3461 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3462 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3463 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3464 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3465 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3466 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3467};
3468
3469
3470int __init omap3xxx_clk_init(void)
3471{
3472 struct omap_clk *c;
3473 u32 cpu_clkflg = 0;
3474
3475 if (cpu_is_omap3517()) {
3476 cpu_mask = RATE_IN_34XX;
3477 cpu_clkflg = CK_3517;
3478 } else if (cpu_is_omap3505()) {
3479 cpu_mask = RATE_IN_34XX;
3480 cpu_clkflg = CK_3505;
3481 } else if (cpu_is_omap3630()) {
3482 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3483 cpu_clkflg = CK_36XX;
3484 } else if (cpu_is_ti816x()) {
3485 cpu_mask = RATE_IN_TI816X;
3486 cpu_clkflg = CK_TI816X;
3487 } else if (cpu_is_omap34xx()) {
3488 if (omap_rev() == OMAP3430_REV_ES1_0) {
3489 cpu_mask = RATE_IN_3430ES1;
3490 cpu_clkflg = CK_3430ES1;
3491 } else {
3492 /*
3493 * Assume that anything that we haven't matched yet
3494 * has 3430ES2-type clocks.
3495 */
3496 cpu_mask = RATE_IN_3430ES2PLUS;
3497 cpu_clkflg = CK_3430ES2PLUS;
3498 }
3499 } else {
3500 WARN(1, "clock: could not identify OMAP3 variant\n");
3501 }
3502
3503 if (omap3_has_192mhz_clk())
3504 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3505
3506 if (cpu_is_omap3630()) {
3507 /*
3508 * XXX This type of dynamic rewriting of the clock tree is
3509 * deprecated and should be revised soon.
3510 *
3511 * For 3630: override clkops_omap2_dflt_wait for the
3512 * clocks affected from PWRDN reset Limitation
3513 */
3514 dpll3_m3x2_ck.ops =
3515 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3516 dpll4_m2x2_ck.ops =
3517 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3518 dpll4_m3x2_ck.ops =
3519 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3520 dpll4_m4x2_ck.ops =
3521 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3522 dpll4_m5x2_ck.ops =
3523 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3524 dpll4_m6x2_ck.ops =
3525 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3526 }
3527
3528 /*
3529 * XXX This type of dynamic rewriting of the clock tree is
3530 * deprecated and should be revised soon.
3531 */
3532 if (cpu_is_omap3630())
3533 dpll4_dd = dpll4_dd_3630;
3534 else
3535 dpll4_dd = dpll4_dd_34xx;
3536
3537 clk_init(&omap2_clk_functions);
3538
3539 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3540 c++)
3541 clk_preinit(c->lk.clk);
3542
3543 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3544 c++)
3545 if (c->cpu & cpu_clkflg) {
3546 clkdev_add(&c->lk);
3547 clk_register(c->lk.clk);
3548 omap2_init_clk_clkdm(c->lk.clk);
3549 }
3550
3551 /* Disable autoidle on all clocks; let the PM code enable it later */
3552 omap_clk_disable_autoidle_all();
3553
3554 recalculate_root_clocks();
3555
3556 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3557 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3558 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3559
3560 /*
3561 * Only enable those clocks we will need, let the drivers
3562 * enable other clocks as necessary
3563 */
3564 clk_enable_init_clocks();
3565
3566 /*
3567 * Lock DPLL5 -- here only until other device init code can
3568 * handle this
3569 */
3570 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3571 omap3_clk_lock_dpll5();
3572
3573 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3574 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3575 arm_fck_p = clk_get(NULL, "arm_fck");
3576
3577 return 0;
3578}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-30 01:05:34 -0400