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diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
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1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/clkdev_omap.h>
21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx_3xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
33
34/*
35 * 2430 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56 .clkdm_name = "wkup_clkdm",
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .clkdm_name = "wkup_clkdm",
64};
65
66/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
69 .ops = &clkops_oscck,
70 .clkdm_name = "wkup_clkdm",
71 .recalc = &omap2_osc_clk_recalc,
72};
73
74/* Without modem likely 12MHz, with modem likely 13MHz */
75static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
77 .ops = &clkops_null,
78 .parent = &osc_ck,
79 .clkdm_name = "wkup_clkdm",
80 .recalc = &omap2xxx_sys_clk_recalc,
81};
82
83static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
85 .ops = &clkops_null,
86 .rate = 54000000,
87 .clkdm_name = "wkup_clkdm",
88};
89
90/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
96/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
105static struct dpll_data dpll_dd = {
106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
113 .max_multiplier = 1023,
114 .min_divider = 1,
115 .max_divider = 16,
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_omap2xxx_dpll_ops,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .dpll_data = &dpll_dd,
127 .clkdm_name = "wkup_clkdm",
128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
134 .ops = &clkops_apll96,
135 .parent = &sys_ck,
136 .rate = 96000000,
137 .flags = ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
145 .ops = &clkops_apll54,
146 .parent = &sys_ck,
147 .rate = 54000000,
148 .flags = ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
152};
153
154/*
155 * PRCM digital base sources
156 */
157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
161 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
178 .ops = &clkops_null,
179 .parent = &apll54_ck, /* can also be alt_clk */
180 .clkdm_name = "wkup_clkdm",
181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
183 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
186};
187
188static struct clk core_ck = {
189 .name = "core_ck",
190 .ops = &clkops_null,
191 .parent = &dpll_ck, /* can also be 32k */
192 .clkdm_name = "wkup_clkdm",
193 .recalc = &followparent_recalc,
194};
195
196/* func_96m_ck */
197static const struct clksel_rate func_96m_apll96_rates[] = {
198 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
199 { .div = 0 },
200};
201
202static const struct clksel_rate func_96m_alt_rates[] = {
203 { .div = 1, .val = 1, .flags = RATE_IN_243X },
204 { .div = 0 },
205};
206
207static const struct clksel func_96m_clksel[] = {
208 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
209 { .parent = &alt_ck, .rates = func_96m_alt_rates },
210 { .parent = NULL }
211};
212
213static struct clk func_96m_ck = {
214 .name = "func_96m_ck",
215 .ops = &clkops_null,
216 .parent = &apll96_ck,
217 .clkdm_name = "wkup_clkdm",
218 .init = &omap2_init_clksel_parent,
219 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
220 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
221 .clksel = func_96m_clksel,
222 .recalc = &omap2_clksel_recalc,
223};
224
225/* func_48m_ck */
226
227static const struct clksel_rate func_48m_apll96_rates[] = {
228 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
229 { .div = 0 },
230};
231
232static const struct clksel_rate func_48m_alt_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
234 { .div = 0 },
235};
236
237static const struct clksel func_48m_clksel[] = {
238 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
239 { .parent = &alt_ck, .rates = func_48m_alt_rates },
240 { .parent = NULL }
241};
242
243static struct clk func_48m_ck = {
244 .name = "func_48m_ck",
245 .ops = &clkops_null,
246 .parent = &apll96_ck, /* 96M or Alt */
247 .clkdm_name = "wkup_clkdm",
248 .init = &omap2_init_clksel_parent,
249 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
250 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
251 .clksel = func_48m_clksel,
252 .recalc = &omap2_clksel_recalc,
253 .round_rate = &omap2_clksel_round_rate,
254 .set_rate = &omap2_clksel_set_rate
255};
256
257static struct clk func_12m_ck = {
258 .name = "func_12m_ck",
259 .ops = &clkops_null,
260 .parent = &func_48m_ck,
261 .fixed_div = 4,
262 .clkdm_name = "wkup_clkdm",
263 .recalc = &omap_fixed_divisor_recalc,
264};
265
266/* Secure timer, only available in secure mode */
267static struct clk wdt1_osc_ck = {
268 .name = "ck_wdt1_osc",
269 .ops = &clkops_null, /* RMK: missing? */
270 .parent = &osc_ck,
271 .recalc = &followparent_recalc,
272};
273
274/*
275 * The common_clkout* clksel_rate structs are common to
276 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
277 * sys_clkout2_* are 2420-only, so the
278 * clksel_rate flags fields are inaccurate for those clocks. This is
279 * harmless since access to those clocks are gated by the struct clk
280 * flags fields, which mark them as 2420-only.
281 */
282static const struct clksel_rate common_clkout_src_core_rates[] = {
283 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
284 { .div = 0 }
285};
286
287static const struct clksel_rate common_clkout_src_sys_rates[] = {
288 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
289 { .div = 0 }
290};
291
292static const struct clksel_rate common_clkout_src_96m_rates[] = {
293 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
294 { .div = 0 }
295};
296
297static const struct clksel_rate common_clkout_src_54m_rates[] = {
298 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
299 { .div = 0 }
300};
301
302static const struct clksel common_clkout_src_clksel[] = {
303 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
304 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
305 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
306 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
307 { .parent = NULL }
308};
309
310static struct clk sys_clkout_src = {
311 .name = "sys_clkout_src",
312 .ops = &clkops_omap2_dflt,
313 .parent = &func_54m_ck,
314 .clkdm_name = "wkup_clkdm",
315 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
316 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
317 .init = &omap2_init_clksel_parent,
318 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
319 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
320 .clksel = common_clkout_src_clksel,
321 .recalc = &omap2_clksel_recalc,
322 .round_rate = &omap2_clksel_round_rate,
323 .set_rate = &omap2_clksel_set_rate
324};
325
326static const struct clksel_rate common_clkout_rates[] = {
327 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
328 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
329 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
330 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
331 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
332 { .div = 0 },
333};
334
335static const struct clksel sys_clkout_clksel[] = {
336 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
337 { .parent = NULL }
338};
339
340static struct clk sys_clkout = {
341 .name = "sys_clkout",
342 .ops = &clkops_null,
343 .parent = &sys_clkout_src,
344 .clkdm_name = "wkup_clkdm",
345 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
346 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
347 .clksel = sys_clkout_clksel,
348 .recalc = &omap2_clksel_recalc,
349 .round_rate = &omap2_clksel_round_rate,
350 .set_rate = &omap2_clksel_set_rate
351};
352
353static struct clk emul_ck = {
354 .name = "emul_ck",
355 .ops = &clkops_omap2_dflt,
356 .parent = &func_54m_ck,
357 .clkdm_name = "wkup_clkdm",
358 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
359 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
360 .recalc = &followparent_recalc,
361
362};
363
364/*
365 * MPU clock domain
366 * Clocks:
367 * MPU_FCLK, MPU_ICLK
368 * INT_M_FCLK, INT_M_I_CLK
369 *
370 * - Individual clocks are hardware managed.
371 * - Base divider comes from: CM_CLKSEL_MPU
372 *
373 */
374static const struct clksel_rate mpu_core_rates[] = {
375 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
376 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
377 { .div = 0 },
378};
379
380static const struct clksel mpu_clksel[] = {
381 { .parent = &core_ck, .rates = mpu_core_rates },
382 { .parent = NULL }
383};
384
385static struct clk mpu_ck = { /* Control cpu */
386 .name = "mpu_ck",
387 .ops = &clkops_null,
388 .parent = &core_ck,
389 .clkdm_name = "mpu_clkdm",
390 .init = &omap2_init_clksel_parent,
391 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
392 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
393 .clksel = mpu_clksel,
394 .recalc = &omap2_clksel_recalc,
395};
396
397/*
398 * DSP (2430-IVA2.1) clock domain
399 * Clocks:
400 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
401 *
402 * Won't be too specific here. The core clock comes into this block
403 * it is divided then tee'ed. One branch goes directly to xyz enable
404 * controls. The other branch gets further divided by 2 then possibly
405 * routed into a synchronizer and out of clocks abc.
406 */
407static const struct clksel_rate dsp_fck_core_rates[] = {
408 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
409 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
410 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
411 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
412 { .div = 0 },
413};
414
415static const struct clksel dsp_fck_clksel[] = {
416 { .parent = &core_ck, .rates = dsp_fck_core_rates },
417 { .parent = NULL }
418};
419
420static struct clk dsp_fck = {
421 .name = "dsp_fck",
422 .ops = &clkops_omap2_dflt_wait,
423 .parent = &core_ck,
424 .clkdm_name = "dsp_clkdm",
425 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
426 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
427 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
428 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
429 .clksel = dsp_fck_clksel,
430 .recalc = &omap2_clksel_recalc,
431};
432
433static const struct clksel dsp_ick_clksel[] = {
434 { .parent = &dsp_fck, .rates = dsp_ick_rates },
435 { .parent = NULL }
436};
437
438/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
439static struct clk iva2_1_ick = {
440 .name = "iva2_1_ick",
441 .ops = &clkops_omap2_dflt_wait,
442 .parent = &dsp_fck,
443 .clkdm_name = "dsp_clkdm",
444 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
445 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
446 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
447 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
448 .clksel = dsp_ick_clksel,
449 .recalc = &omap2_clksel_recalc,
450};
451
452/*
453 * L3 clock domain
454 * L3 clocks are used for both interface and functional clocks to
455 * multiple entities. Some of these clocks are completely managed
456 * by hardware, and some others allow software control. Hardware
457 * managed ones general are based on directly CLK_REQ signals and
458 * various auto idle settings. The functional spec sets many of these
459 * as 'tie-high' for their enables.
460 *
461 * I-CLOCKS:
462 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
463 * CAM, HS-USB.
464 * F-CLOCK
465 * SSI.
466 *
467 * GPMC memories and SDRC have timing and clock sensitive registers which
468 * may very well need notification when the clock changes. Currently for low
469 * operating points, these are taken care of in sleep.S.
470 */
471static const struct clksel_rate core_l3_core_rates[] = {
472 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
473 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
474 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
475 { .div = 0 }
476};
477
478static const struct clksel core_l3_clksel[] = {
479 { .parent = &core_ck, .rates = core_l3_core_rates },
480 { .parent = NULL }
481};
482
483static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
484 .name = "core_l3_ck",
485 .ops = &clkops_null,
486 .parent = &core_ck,
487 .clkdm_name = "core_l3_clkdm",
488 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
489 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
490 .clksel = core_l3_clksel,
491 .recalc = &omap2_clksel_recalc,
492};
493
494/* usb_l4_ick */
495static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
496 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
497 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
498 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
499 { .div = 0 }
500};
501
502static const struct clksel usb_l4_ick_clksel[] = {
503 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
504 { .parent = NULL },
505};
506
507/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
508static struct clk usb_l4_ick = { /* FS-USB interface clock */
509 .name = "usb_l4_ick",
510 .ops = &clkops_omap2_iclk_dflt_wait,
511 .parent = &core_l3_ck,
512 .clkdm_name = "core_l4_clkdm",
513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
514 .enable_bit = OMAP24XX_EN_USB_SHIFT,
515 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
516 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
517 .clksel = usb_l4_ick_clksel,
518 .recalc = &omap2_clksel_recalc,
519};
520
521/*
522 * L4 clock management domain
523 *
524 * This domain contains lots of interface clocks from the L4 interface, some
525 * functional clocks. Fixed APLL functional source clocks are managed in
526 * this domain.
527 */
528static const struct clksel_rate l4_core_l3_rates[] = {
529 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
530 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
531 { .div = 0 }
532};
533
534static const struct clksel l4_clksel[] = {
535 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
536 { .parent = NULL }
537};
538
539static struct clk l4_ck = { /* used both as an ick and fck */
540 .name = "l4_ck",
541 .ops = &clkops_null,
542 .parent = &core_l3_ck,
543 .clkdm_name = "core_l4_clkdm",
544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
545 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
546 .clksel = l4_clksel,
547 .recalc = &omap2_clksel_recalc,
548};
549
550/*
551 * SSI is in L3 management domain, its direct parent is core not l3,
552 * many core power domain entities are grouped into the L3 clock
553 * domain.
554 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
555 *
556 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
557 */
558static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
559 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
560 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
561 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
562 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
563 { .div = 5, .val = 5, .flags = RATE_IN_243X },
564 { .div = 0 }
565};
566
567static const struct clksel ssi_ssr_sst_fck_clksel[] = {
568 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
569 { .parent = NULL }
570};
571
572static struct clk ssi_ssr_sst_fck = {
573 .name = "ssi_fck",
574 .ops = &clkops_omap2_dflt_wait,
575 .parent = &core_ck,
576 .clkdm_name = "core_l3_clkdm",
577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
578 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
579 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
580 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
581 .clksel = ssi_ssr_sst_fck_clksel,
582 .recalc = &omap2_clksel_recalc,
583};
584
585/*
586 * Presumably this is the same as SSI_ICLK.
587 * TRM contradicts itself on what clockdomain SSI_ICLK is in
588 */
589static struct clk ssi_l4_ick = {
590 .name = "ssi_l4_ick",
591 .ops = &clkops_omap2_iclk_dflt_wait,
592 .parent = &l4_ck,
593 .clkdm_name = "core_l4_clkdm",
594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
595 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
596 .recalc = &followparent_recalc,
597};
598
599
600/*
601 * GFX clock domain
602 * Clocks:
603 * GFX_FCLK, GFX_ICLK
604 * GFX_CG1(2d), GFX_CG2(3d)
605 *
606 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
607 * The 2d and 3d clocks run at a hardware determined
608 * divided value of fclk.
609 *
610 */
611
612/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
613static const struct clksel gfx_fck_clksel[] = {
614 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
615 { .parent = NULL },
616};
617
618static struct clk gfx_3d_fck = {
619 .name = "gfx_3d_fck",
620 .ops = &clkops_omap2_dflt_wait,
621 .parent = &core_l3_ck,
622 .clkdm_name = "gfx_clkdm",
623 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
624 .enable_bit = OMAP24XX_EN_3D_SHIFT,
625 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
627 .clksel = gfx_fck_clksel,
628 .recalc = &omap2_clksel_recalc,
629 .round_rate = &omap2_clksel_round_rate,
630 .set_rate = &omap2_clksel_set_rate
631};
632
633static struct clk gfx_2d_fck = {
634 .name = "gfx_2d_fck",
635 .ops = &clkops_omap2_dflt_wait,
636 .parent = &core_l3_ck,
637 .clkdm_name = "gfx_clkdm",
638 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
639 .enable_bit = OMAP24XX_EN_2D_SHIFT,
640 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
641 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
642 .clksel = gfx_fck_clksel,
643 .recalc = &omap2_clksel_recalc,
644};
645
646/* This interface clock does not have a CM_AUTOIDLE bit */
647static struct clk gfx_ick = {
648 .name = "gfx_ick", /* From l3 */
649 .ops = &clkops_omap2_dflt_wait,
650 .parent = &core_l3_ck,
651 .clkdm_name = "gfx_clkdm",
652 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
653 .enable_bit = OMAP_EN_GFX_SHIFT,
654 .recalc = &followparent_recalc,
655};
656
657/*
658 * Modem clock domain (2430)
659 * CLOCKS:
660 * MDM_OSC_CLK
661 * MDM_ICLK
662 * These clocks are usable in chassis mode only.
663 */
664static const struct clksel_rate mdm_ick_core_rates[] = {
665 { .div = 1, .val = 1, .flags = RATE_IN_243X },
666 { .div = 4, .val = 4, .flags = RATE_IN_243X },
667 { .div = 6, .val = 6, .flags = RATE_IN_243X },
668 { .div = 9, .val = 9, .flags = RATE_IN_243X },
669 { .div = 0 }
670};
671
672static const struct clksel mdm_ick_clksel[] = {
673 { .parent = &core_ck, .rates = mdm_ick_core_rates },
674 { .parent = NULL }
675};
676
677static struct clk mdm_ick = { /* used both as a ick and fck */
678 .name = "mdm_ick",
679 .ops = &clkops_omap2_iclk_dflt_wait,
680 .parent = &core_ck,
681 .clkdm_name = "mdm_clkdm",
682 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
683 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
684 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
685 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
686 .clksel = mdm_ick_clksel,
687 .recalc = &omap2_clksel_recalc,
688};
689
690static struct clk mdm_osc_ck = {
691 .name = "mdm_osc_ck",
692 .ops = &clkops_omap2_mdmclk_dflt_wait,
693 .parent = &osc_ck,
694 .clkdm_name = "mdm_clkdm",
695 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
696 .enable_bit = OMAP2430_EN_OSC_SHIFT,
697 .recalc = &followparent_recalc,
698};
699
700/*
701 * DSS clock domain
702 * CLOCKs:
703 * DSS_L4_ICLK, DSS_L3_ICLK,
704 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
705 *
706 * DSS is both initiator and target.
707 */
708/* XXX Add RATE_NOT_VALIDATED */
709
710static const struct clksel_rate dss1_fck_sys_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
712 { .div = 0 }
713};
714
715static const struct clksel_rate dss1_fck_core_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
717 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
718 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
719 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
720 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
721 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
722 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
723 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
724 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
725 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
726 { .div = 0 }
727};
728
729static const struct clksel dss1_fck_clksel[] = {
730 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
731 { .parent = &core_ck, .rates = dss1_fck_core_rates },
732 { .parent = NULL },
733};
734
735static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
736 .name = "dss_ick",
737 .ops = &clkops_omap2_iclk_dflt,
738 .parent = &l4_ck, /* really both l3 and l4 */
739 .clkdm_name = "dss_clkdm",
740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
741 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
742 .recalc = &followparent_recalc,
743};
744
745static struct clk dss1_fck = {
746 .name = "dss1_fck",
747 .ops = &clkops_omap2_dflt,
748 .parent = &core_ck, /* Core or sys */
749 .clkdm_name = "dss_clkdm",
750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
751 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
754 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
755 .clksel = dss1_fck_clksel,
756 .recalc = &omap2_clksel_recalc,
757};
758
759static const struct clksel_rate dss2_fck_sys_rates[] = {
760 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
761 { .div = 0 }
762};
763
764static const struct clksel_rate dss2_fck_48m_rates[] = {
765 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
766 { .div = 0 }
767};
768
769static const struct clksel dss2_fck_clksel[] = {
770 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
771 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
772 { .parent = NULL }
773};
774
775static struct clk dss2_fck = { /* Alt clk used in power management */
776 .name = "dss2_fck",
777 .ops = &clkops_omap2_dflt,
778 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
779 .clkdm_name = "dss_clkdm",
780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
781 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
782 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
785 .clksel = dss2_fck_clksel,
786 .recalc = &omap2_clksel_recalc,
787};
788
789static struct clk dss_54m_fck = { /* Alt clk used in power management */
790 .name = "dss_54m_fck", /* 54m tv clk */
791 .ops = &clkops_omap2_dflt_wait,
792 .parent = &func_54m_ck,
793 .clkdm_name = "dss_clkdm",
794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 .enable_bit = OMAP24XX_EN_TV_SHIFT,
796 .recalc = &followparent_recalc,
797};
798
799static struct clk wu_l4_ick = {
800 .name = "wu_l4_ick",
801 .ops = &clkops_null,
802 .parent = &sys_ck,
803 .clkdm_name = "wkup_clkdm",
804 .recalc = &followparent_recalc,
805};
806
807/*
808 * CORE power domain ICLK & FCLK defines.
809 * Many of the these can have more than one possible parent. Entries
810 * here will likely have an L4 interface parent, and may have multiple
811 * functional clock parents.
812 */
813static const struct clksel_rate gpt_alt_rates[] = {
814 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
815 { .div = 0 }
816};
817
818static const struct clksel omap24xx_gpt_clksel[] = {
819 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
820 { .parent = &sys_ck, .rates = gpt_sys_rates },
821 { .parent = &alt_ck, .rates = gpt_alt_rates },
822 { .parent = NULL },
823};
824
825static struct clk gpt1_ick = {
826 .name = "gpt1_ick",
827 .ops = &clkops_omap2_iclk_dflt_wait,
828 .parent = &wu_l4_ick,
829 .clkdm_name = "wkup_clkdm",
830 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
831 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
832 .recalc = &followparent_recalc,
833};
834
835static struct clk gpt1_fck = {
836 .name = "gpt1_fck",
837 .ops = &clkops_omap2_dflt_wait,
838 .parent = &func_32k_ck,
839 .clkdm_name = "core_l4_clkdm",
840 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
841 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
842 .init = &omap2_init_clksel_parent,
843 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
844 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
845 .clksel = omap24xx_gpt_clksel,
846 .recalc = &omap2_clksel_recalc,
847 .round_rate = &omap2_clksel_round_rate,
848 .set_rate = &omap2_clksel_set_rate
849};
850
851static struct clk gpt2_ick = {
852 .name = "gpt2_ick",
853 .ops = &clkops_omap2_iclk_dflt_wait,
854 .parent = &l4_ck,
855 .clkdm_name = "core_l4_clkdm",
856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
857 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
858 .recalc = &followparent_recalc,
859};
860
861static struct clk gpt2_fck = {
862 .name = "gpt2_fck",
863 .ops = &clkops_omap2_dflt_wait,
864 .parent = &func_32k_ck,
865 .clkdm_name = "core_l4_clkdm",
866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
867 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
868 .init = &omap2_init_clksel_parent,
869 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
870 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
871 .clksel = omap24xx_gpt_clksel,
872 .recalc = &omap2_clksel_recalc,
873};
874
875static struct clk gpt3_ick = {
876 .name = "gpt3_ick",
877 .ops = &clkops_omap2_iclk_dflt_wait,
878 .parent = &l4_ck,
879 .clkdm_name = "core_l4_clkdm",
880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
881 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
882 .recalc = &followparent_recalc,
883};
884
885static struct clk gpt3_fck = {
886 .name = "gpt3_fck",
887 .ops = &clkops_omap2_dflt_wait,
888 .parent = &func_32k_ck,
889 .clkdm_name = "core_l4_clkdm",
890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
891 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
892 .init = &omap2_init_clksel_parent,
893 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
894 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
895 .clksel = omap24xx_gpt_clksel,
896 .recalc = &omap2_clksel_recalc,
897};
898
899static struct clk gpt4_ick = {
900 .name = "gpt4_ick",
901 .ops = &clkops_omap2_iclk_dflt_wait,
902 .parent = &l4_ck,
903 .clkdm_name = "core_l4_clkdm",
904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
905 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
906 .recalc = &followparent_recalc,
907};
908
909static struct clk gpt4_fck = {
910 .name = "gpt4_fck",
911 .ops = &clkops_omap2_dflt_wait,
912 .parent = &func_32k_ck,
913 .clkdm_name = "core_l4_clkdm",
914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
915 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
916 .init = &omap2_init_clksel_parent,
917 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
918 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
919 .clksel = omap24xx_gpt_clksel,
920 .recalc = &omap2_clksel_recalc,
921};
922
923static struct clk gpt5_ick = {
924 .name = "gpt5_ick",
925 .ops = &clkops_omap2_iclk_dflt_wait,
926 .parent = &l4_ck,
927 .clkdm_name = "core_l4_clkdm",
928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
929 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
930 .recalc = &followparent_recalc,
931};
932
933static struct clk gpt5_fck = {
934 .name = "gpt5_fck",
935 .ops = &clkops_omap2_dflt_wait,
936 .parent = &func_32k_ck,
937 .clkdm_name = "core_l4_clkdm",
938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
939 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
940 .init = &omap2_init_clksel_parent,
941 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
942 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
943 .clksel = omap24xx_gpt_clksel,
944 .recalc = &omap2_clksel_recalc,
945};
946
947static struct clk gpt6_ick = {
948 .name = "gpt6_ick",
949 .ops = &clkops_omap2_iclk_dflt_wait,
950 .parent = &l4_ck,
951 .clkdm_name = "core_l4_clkdm",
952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
953 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
954 .recalc = &followparent_recalc,
955};
956
957static struct clk gpt6_fck = {
958 .name = "gpt6_fck",
959 .ops = &clkops_omap2_dflt_wait,
960 .parent = &func_32k_ck,
961 .clkdm_name = "core_l4_clkdm",
962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
963 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
964 .init = &omap2_init_clksel_parent,
965 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
966 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
967 .clksel = omap24xx_gpt_clksel,
968 .recalc = &omap2_clksel_recalc,
969};
970
971static struct clk gpt7_ick = {
972 .name = "gpt7_ick",
973 .ops = &clkops_omap2_iclk_dflt_wait,
974 .parent = &l4_ck,
975 .clkdm_name = "core_l4_clkdm",
976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
977 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
978 .recalc = &followparent_recalc,
979};
980
981static struct clk gpt7_fck = {
982 .name = "gpt7_fck",
983 .ops = &clkops_omap2_dflt_wait,
984 .parent = &func_32k_ck,
985 .clkdm_name = "core_l4_clkdm",
986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
987 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
988 .init = &omap2_init_clksel_parent,
989 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
990 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
991 .clksel = omap24xx_gpt_clksel,
992 .recalc = &omap2_clksel_recalc,
993};
994
995static struct clk gpt8_ick = {
996 .name = "gpt8_ick",
997 .ops = &clkops_omap2_iclk_dflt_wait,
998 .parent = &l4_ck,
999 .clkdm_name = "core_l4_clkdm",
1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1001 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1002 .recalc = &followparent_recalc,
1003};
1004
1005static struct clk gpt8_fck = {
1006 .name = "gpt8_fck",
1007 .ops = &clkops_omap2_dflt_wait,
1008 .parent = &func_32k_ck,
1009 .clkdm_name = "core_l4_clkdm",
1010 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1011 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1012 .init = &omap2_init_clksel_parent,
1013 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1014 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1015 .clksel = omap24xx_gpt_clksel,
1016 .recalc = &omap2_clksel_recalc,
1017};
1018
1019static struct clk gpt9_ick = {
1020 .name = "gpt9_ick",
1021 .ops = &clkops_omap2_iclk_dflt_wait,
1022 .parent = &l4_ck,
1023 .clkdm_name = "core_l4_clkdm",
1024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1025 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1026 .recalc = &followparent_recalc,
1027};
1028
1029static struct clk gpt9_fck = {
1030 .name = "gpt9_fck",
1031 .ops = &clkops_omap2_dflt_wait,
1032 .parent = &func_32k_ck,
1033 .clkdm_name = "core_l4_clkdm",
1034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1035 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1036 .init = &omap2_init_clksel_parent,
1037 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1038 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1039 .clksel = omap24xx_gpt_clksel,
1040 .recalc = &omap2_clksel_recalc,
1041};
1042
1043static struct clk gpt10_ick = {
1044 .name = "gpt10_ick",
1045 .ops = &clkops_omap2_iclk_dflt_wait,
1046 .parent = &l4_ck,
1047 .clkdm_name = "core_l4_clkdm",
1048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1049 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1050 .recalc = &followparent_recalc,
1051};
1052
1053static struct clk gpt10_fck = {
1054 .name = "gpt10_fck",
1055 .ops = &clkops_omap2_dflt_wait,
1056 .parent = &func_32k_ck,
1057 .clkdm_name = "core_l4_clkdm",
1058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1059 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1060 .init = &omap2_init_clksel_parent,
1061 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1062 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1063 .clksel = omap24xx_gpt_clksel,
1064 .recalc = &omap2_clksel_recalc,
1065};
1066
1067static struct clk gpt11_ick = {
1068 .name = "gpt11_ick",
1069 .ops = &clkops_omap2_iclk_dflt_wait,
1070 .parent = &l4_ck,
1071 .clkdm_name = "core_l4_clkdm",
1072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1073 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1074 .recalc = &followparent_recalc,
1075};
1076
1077static struct clk gpt11_fck = {
1078 .name = "gpt11_fck",
1079 .ops = &clkops_omap2_dflt_wait,
1080 .parent = &func_32k_ck,
1081 .clkdm_name = "core_l4_clkdm",
1082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1083 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1084 .init = &omap2_init_clksel_parent,
1085 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1086 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1087 .clksel = omap24xx_gpt_clksel,
1088 .recalc = &omap2_clksel_recalc,
1089};
1090
1091static struct clk gpt12_ick = {
1092 .name = "gpt12_ick",
1093 .ops = &clkops_omap2_iclk_dflt_wait,
1094 .parent = &l4_ck,
1095 .clkdm_name = "core_l4_clkdm",
1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1097 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1098 .recalc = &followparent_recalc,
1099};
1100
1101static struct clk gpt12_fck = {
1102 .name = "gpt12_fck",
1103 .ops = &clkops_omap2_dflt_wait,
1104 .parent = &secure_32k_ck,
1105 .clkdm_name = "core_l4_clkdm",
1106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1107 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1108 .init = &omap2_init_clksel_parent,
1109 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1110 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1111 .clksel = omap24xx_gpt_clksel,
1112 .recalc = &omap2_clksel_recalc,
1113};
1114
1115static struct clk mcbsp1_ick = {
1116 .name = "mcbsp1_ick",
1117 .ops = &clkops_omap2_iclk_dflt_wait,
1118 .parent = &l4_ck,
1119 .clkdm_name = "core_l4_clkdm",
1120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1121 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1122 .recalc = &followparent_recalc,
1123};
1124
1125static const struct clksel_rate common_mcbsp_96m_rates[] = {
1126 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1127 { .div = 0 }
1128};
1129
1130static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1132 { .div = 0 }
1133};
1134
1135static const struct clksel mcbsp_fck_clksel[] = {
1136 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1137 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1138 { .parent = NULL }
1139};
1140
1141static struct clk mcbsp1_fck = {
1142 .name = "mcbsp1_fck",
1143 .ops = &clkops_omap2_dflt_wait,
1144 .parent = &func_96m_ck,
1145 .init = &omap2_init_clksel_parent,
1146 .clkdm_name = "core_l4_clkdm",
1147 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1148 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1149 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1150 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1151 .clksel = mcbsp_fck_clksel,
1152 .recalc = &omap2_clksel_recalc,
1153};
1154
1155static struct clk mcbsp2_ick = {
1156 .name = "mcbsp2_ick",
1157 .ops = &clkops_omap2_iclk_dflt_wait,
1158 .parent = &l4_ck,
1159 .clkdm_name = "core_l4_clkdm",
1160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1161 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1162 .recalc = &followparent_recalc,
1163};
1164
1165static struct clk mcbsp2_fck = {
1166 .name = "mcbsp2_fck",
1167 .ops = &clkops_omap2_dflt_wait,
1168 .parent = &func_96m_ck,
1169 .init = &omap2_init_clksel_parent,
1170 .clkdm_name = "core_l4_clkdm",
1171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1172 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1173 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1174 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1175 .clksel = mcbsp_fck_clksel,
1176 .recalc = &omap2_clksel_recalc,
1177};
1178
1179static struct clk mcbsp3_ick = {
1180 .name = "mcbsp3_ick",
1181 .ops = &clkops_omap2_iclk_dflt_wait,
1182 .parent = &l4_ck,
1183 .clkdm_name = "core_l4_clkdm",
1184 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1185 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1186 .recalc = &followparent_recalc,
1187};
1188
1189static struct clk mcbsp3_fck = {
1190 .name = "mcbsp3_fck",
1191 .ops = &clkops_omap2_dflt_wait,
1192 .parent = &func_96m_ck,
1193 .init = &omap2_init_clksel_parent,
1194 .clkdm_name = "core_l4_clkdm",
1195 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1196 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1197 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1198 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1199 .clksel = mcbsp_fck_clksel,
1200 .recalc = &omap2_clksel_recalc,
1201};
1202
1203static struct clk mcbsp4_ick = {
1204 .name = "mcbsp4_ick",
1205 .ops = &clkops_omap2_iclk_dflt_wait,
1206 .parent = &l4_ck,
1207 .clkdm_name = "core_l4_clkdm",
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1209 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1210 .recalc = &followparent_recalc,
1211};
1212
1213static struct clk mcbsp4_fck = {
1214 .name = "mcbsp4_fck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &func_96m_ck,
1217 .init = &omap2_init_clksel_parent,
1218 .clkdm_name = "core_l4_clkdm",
1219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1220 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1221 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1222 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1223 .clksel = mcbsp_fck_clksel,
1224 .recalc = &omap2_clksel_recalc,
1225};
1226
1227static struct clk mcbsp5_ick = {
1228 .name = "mcbsp5_ick",
1229 .ops = &clkops_omap2_iclk_dflt_wait,
1230 .parent = &l4_ck,
1231 .clkdm_name = "core_l4_clkdm",
1232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1233 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1234 .recalc = &followparent_recalc,
1235};
1236
1237static struct clk mcbsp5_fck = {
1238 .name = "mcbsp5_fck",
1239 .ops = &clkops_omap2_dflt_wait,
1240 .parent = &func_96m_ck,
1241 .init = &omap2_init_clksel_parent,
1242 .clkdm_name = "core_l4_clkdm",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1244 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1245 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1246 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1247 .clksel = mcbsp_fck_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249};
1250
1251static struct clk mcspi1_ick = {
1252 .name = "mcspi1_ick",
1253 .ops = &clkops_omap2_iclk_dflt_wait,
1254 .parent = &l4_ck,
1255 .clkdm_name = "core_l4_clkdm",
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1258 .recalc = &followparent_recalc,
1259};
1260
1261static struct clk mcspi1_fck = {
1262 .name = "mcspi1_fck",
1263 .ops = &clkops_omap2_dflt_wait,
1264 .parent = &func_48m_ck,
1265 .clkdm_name = "core_l4_clkdm",
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1268 .recalc = &followparent_recalc,
1269};
1270
1271static struct clk mcspi2_ick = {
1272 .name = "mcspi2_ick",
1273 .ops = &clkops_omap2_iclk_dflt_wait,
1274 .parent = &l4_ck,
1275 .clkdm_name = "core_l4_clkdm",
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1277 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1278 .recalc = &followparent_recalc,
1279};
1280
1281static struct clk mcspi2_fck = {
1282 .name = "mcspi2_fck",
1283 .ops = &clkops_omap2_dflt_wait,
1284 .parent = &func_48m_ck,
1285 .clkdm_name = "core_l4_clkdm",
1286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1287 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1288 .recalc = &followparent_recalc,
1289};
1290
1291static struct clk mcspi3_ick = {
1292 .name = "mcspi3_ick",
1293 .ops = &clkops_omap2_iclk_dflt_wait,
1294 .parent = &l4_ck,
1295 .clkdm_name = "core_l4_clkdm",
1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1297 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1298 .recalc = &followparent_recalc,
1299};
1300
1301static struct clk mcspi3_fck = {
1302 .name = "mcspi3_fck",
1303 .ops = &clkops_omap2_dflt_wait,
1304 .parent = &func_48m_ck,
1305 .clkdm_name = "core_l4_clkdm",
1306 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1307 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static struct clk uart1_ick = {
1312 .name = "uart1_ick",
1313 .ops = &clkops_omap2_iclk_dflt_wait,
1314 .parent = &l4_ck,
1315 .clkdm_name = "core_l4_clkdm",
1316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1317 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1318 .recalc = &followparent_recalc,
1319};
1320
1321static struct clk uart1_fck = {
1322 .name = "uart1_fck",
1323 .ops = &clkops_omap2_dflt_wait,
1324 .parent = &func_48m_ck,
1325 .clkdm_name = "core_l4_clkdm",
1326 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1327 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1328 .recalc = &followparent_recalc,
1329};
1330
1331static struct clk uart2_ick = {
1332 .name = "uart2_ick",
1333 .ops = &clkops_omap2_iclk_dflt_wait,
1334 .parent = &l4_ck,
1335 .clkdm_name = "core_l4_clkdm",
1336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1337 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1338 .recalc = &followparent_recalc,
1339};
1340
1341static struct clk uart2_fck = {
1342 .name = "uart2_fck",
1343 .ops = &clkops_omap2_dflt_wait,
1344 .parent = &func_48m_ck,
1345 .clkdm_name = "core_l4_clkdm",
1346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1347 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1348 .recalc = &followparent_recalc,
1349};
1350
1351static struct clk uart3_ick = {
1352 .name = "uart3_ick",
1353 .ops = &clkops_omap2_iclk_dflt_wait,
1354 .parent = &l4_ck,
1355 .clkdm_name = "core_l4_clkdm",
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1357 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1358 .recalc = &followparent_recalc,
1359};
1360
1361static struct clk uart3_fck = {
1362 .name = "uart3_fck",
1363 .ops = &clkops_omap2_dflt_wait,
1364 .parent = &func_48m_ck,
1365 .clkdm_name = "core_l4_clkdm",
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1367 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk gpios_ick = {
1372 .name = "gpios_ick",
1373 .ops = &clkops_omap2_iclk_dflt_wait,
1374 .parent = &wu_l4_ick,
1375 .clkdm_name = "wkup_clkdm",
1376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1377 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk gpios_fck = {
1382 .name = "gpios_fck",
1383 .ops = &clkops_omap2_dflt_wait,
1384 .parent = &func_32k_ck,
1385 .clkdm_name = "wkup_clkdm",
1386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1387 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk mpu_wdt_ick = {
1392 .name = "mpu_wdt_ick",
1393 .ops = &clkops_omap2_iclk_dflt_wait,
1394 .parent = &wu_l4_ick,
1395 .clkdm_name = "wkup_clkdm",
1396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1397 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1398 .recalc = &followparent_recalc,
1399};
1400
1401static struct clk mpu_wdt_fck = {
1402 .name = "mpu_wdt_fck",
1403 .ops = &clkops_omap2_dflt_wait,
1404 .parent = &func_32k_ck,
1405 .clkdm_name = "wkup_clkdm",
1406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1407 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1408 .recalc = &followparent_recalc,
1409};
1410
1411static struct clk sync_32k_ick = {
1412 .name = "sync_32k_ick",
1413 .ops = &clkops_omap2_iclk_dflt_wait,
1414 .flags = ENABLE_ON_INIT,
1415 .parent = &wu_l4_ick,
1416 .clkdm_name = "wkup_clkdm",
1417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1418 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1419 .recalc = &followparent_recalc,
1420};
1421
1422static struct clk wdt1_ick = {
1423 .name = "wdt1_ick",
1424 .ops = &clkops_omap2_iclk_dflt_wait,
1425 .parent = &wu_l4_ick,
1426 .clkdm_name = "wkup_clkdm",
1427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1428 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1429 .recalc = &followparent_recalc,
1430};
1431
1432static struct clk omapctrl_ick = {
1433 .name = "omapctrl_ick",
1434 .ops = &clkops_omap2_iclk_dflt_wait,
1435 .flags = ENABLE_ON_INIT,
1436 .parent = &wu_l4_ick,
1437 .clkdm_name = "wkup_clkdm",
1438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1439 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1440 .recalc = &followparent_recalc,
1441};
1442
1443static struct clk icr_ick = {
1444 .name = "icr_ick",
1445 .ops = &clkops_omap2_iclk_dflt_wait,
1446 .parent = &wu_l4_ick,
1447 .clkdm_name = "wkup_clkdm",
1448 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1449 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1450 .recalc = &followparent_recalc,
1451};
1452
1453static struct clk cam_ick = {
1454 .name = "cam_ick",
1455 .ops = &clkops_omap2_iclk_dflt,
1456 .parent = &l4_ck,
1457 .clkdm_name = "core_l4_clkdm",
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1459 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1460 .recalc = &followparent_recalc,
1461};
1462
1463/*
1464 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1465 * split into two separate clocks, since the parent clocks are different
1466 * and the clockdomains are also different.
1467 */
1468static struct clk cam_fck = {
1469 .name = "cam_fck",
1470 .ops = &clkops_omap2_dflt,
1471 .parent = &func_96m_ck,
1472 .clkdm_name = "core_l3_clkdm",
1473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk mailboxes_ick = {
1479 .name = "mailboxes_ick",
1480 .ops = &clkops_omap2_iclk_dflt_wait,
1481 .parent = &l4_ck,
1482 .clkdm_name = "core_l4_clkdm",
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1484 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk wdt4_ick = {
1489 .name = "wdt4_ick",
1490 .ops = &clkops_omap2_iclk_dflt_wait,
1491 .parent = &l4_ck,
1492 .clkdm_name = "core_l4_clkdm",
1493 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1494 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1495 .recalc = &followparent_recalc,
1496};
1497
1498static struct clk wdt4_fck = {
1499 .name = "wdt4_fck",
1500 .ops = &clkops_omap2_dflt_wait,
1501 .parent = &func_32k_ck,
1502 .clkdm_name = "core_l4_clkdm",
1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1505 .recalc = &followparent_recalc,
1506};
1507
1508static struct clk mspro_ick = {
1509 .name = "mspro_ick",
1510 .ops = &clkops_omap2_iclk_dflt_wait,
1511 .parent = &l4_ck,
1512 .clkdm_name = "core_l4_clkdm",
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1514 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1515 .recalc = &followparent_recalc,
1516};
1517
1518static struct clk mspro_fck = {
1519 .name = "mspro_fck",
1520 .ops = &clkops_omap2_dflt_wait,
1521 .parent = &func_96m_ck,
1522 .clkdm_name = "core_l4_clkdm",
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1525 .recalc = &followparent_recalc,
1526};
1527
1528static struct clk fac_ick = {
1529 .name = "fac_ick",
1530 .ops = &clkops_omap2_iclk_dflt_wait,
1531 .parent = &l4_ck,
1532 .clkdm_name = "core_l4_clkdm",
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1534 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1535 .recalc = &followparent_recalc,
1536};
1537
1538static struct clk fac_fck = {
1539 .name = "fac_fck",
1540 .ops = &clkops_omap2_dflt_wait,
1541 .parent = &func_12m_ck,
1542 .clkdm_name = "core_l4_clkdm",
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1545 .recalc = &followparent_recalc,
1546};
1547
1548static struct clk hdq_ick = {
1549 .name = "hdq_ick",
1550 .ops = &clkops_omap2_iclk_dflt_wait,
1551 .parent = &l4_ck,
1552 .clkdm_name = "core_l4_clkdm",
1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1554 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1555 .recalc = &followparent_recalc,
1556};
1557
1558static struct clk hdq_fck = {
1559 .name = "hdq_fck",
1560 .ops = &clkops_omap2_dflt_wait,
1561 .parent = &func_12m_ck,
1562 .clkdm_name = "core_l4_clkdm",
1563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1565 .recalc = &followparent_recalc,
1566};
1567
1568/*
1569 * XXX This is marked as a 2420-only define, but it claims to be present
1570 * on 2430 also. Double-check.
1571 */
1572static struct clk i2c2_ick = {
1573 .name = "i2c2_ick",
1574 .ops = &clkops_omap2_iclk_dflt_wait,
1575 .parent = &l4_ck,
1576 .clkdm_name = "core_l4_clkdm",
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1578 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1579 .recalc = &followparent_recalc,
1580};
1581
1582static struct clk i2chs2_fck = {
1583 .name = "i2chs2_fck",
1584 .ops = &clkops_omap2430_i2chs_wait,
1585 .parent = &func_96m_ck,
1586 .clkdm_name = "core_l4_clkdm",
1587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1588 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1589 .recalc = &followparent_recalc,
1590};
1591
1592/*
1593 * XXX This is marked as a 2420-only define, but it claims to be present
1594 * on 2430 also. Double-check.
1595 */
1596static struct clk i2c1_ick = {
1597 .name = "i2c1_ick",
1598 .ops = &clkops_omap2_iclk_dflt_wait,
1599 .parent = &l4_ck,
1600 .clkdm_name = "core_l4_clkdm",
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1602 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1603 .recalc = &followparent_recalc,
1604};
1605
1606static struct clk i2chs1_fck = {
1607 .name = "i2chs1_fck",
1608 .ops = &clkops_omap2430_i2chs_wait,
1609 .parent = &func_96m_ck,
1610 .clkdm_name = "core_l4_clkdm",
1611 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1612 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1613 .recalc = &followparent_recalc,
1614};
1615
1616/*
1617 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1618 * accesses derived from this data.
1619 */
1620static struct clk gpmc_fck = {
1621 .name = "gpmc_fck",
1622 .ops = &clkops_omap2_iclk_idle_only,
1623 .parent = &core_l3_ck,
1624 .flags = ENABLE_ON_INIT,
1625 .clkdm_name = "core_l3_clkdm",
1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1627 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1628 .recalc = &followparent_recalc,
1629};
1630
1631static struct clk sdma_fck = {
1632 .name = "sdma_fck",
1633 .ops = &clkops_null, /* RMK: missing? */
1634 .parent = &core_l3_ck,
1635 .clkdm_name = "core_l3_clkdm",
1636 .recalc = &followparent_recalc,
1637};
1638
1639/*
1640 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1641 * accesses derived from this data.
1642 */
1643static struct clk sdma_ick = {
1644 .name = "sdma_ick",
1645 .ops = &clkops_omap2_iclk_idle_only,
1646 .parent = &core_l3_ck,
1647 .clkdm_name = "core_l3_clkdm",
1648 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1649 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1650 .recalc = &followparent_recalc,
1651};
1652
1653static struct clk sdrc_ick = {
1654 .name = "sdrc_ick",
1655 .ops = &clkops_omap2_iclk_idle_only,
1656 .parent = &core_l3_ck,
1657 .flags = ENABLE_ON_INIT,
1658 .clkdm_name = "core_l3_clkdm",
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1660 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1661 .recalc = &followparent_recalc,
1662};
1663
1664static struct clk des_ick = {
1665 .name = "des_ick",
1666 .ops = &clkops_omap2_iclk_dflt_wait,
1667 .parent = &l4_ck,
1668 .clkdm_name = "core_l4_clkdm",
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1670 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1671 .recalc = &followparent_recalc,
1672};
1673
1674static struct clk sha_ick = {
1675 .name = "sha_ick",
1676 .ops = &clkops_omap2_iclk_dflt_wait,
1677 .parent = &l4_ck,
1678 .clkdm_name = "core_l4_clkdm",
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1680 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1681 .recalc = &followparent_recalc,
1682};
1683
1684static struct clk rng_ick = {
1685 .name = "rng_ick",
1686 .ops = &clkops_omap2_iclk_dflt_wait,
1687 .parent = &l4_ck,
1688 .clkdm_name = "core_l4_clkdm",
1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1690 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1691 .recalc = &followparent_recalc,
1692};
1693
1694static struct clk aes_ick = {
1695 .name = "aes_ick",
1696 .ops = &clkops_omap2_iclk_dflt_wait,
1697 .parent = &l4_ck,
1698 .clkdm_name = "core_l4_clkdm",
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1700 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1701 .recalc = &followparent_recalc,
1702};
1703
1704static struct clk pka_ick = {
1705 .name = "pka_ick",
1706 .ops = &clkops_omap2_iclk_dflt_wait,
1707 .parent = &l4_ck,
1708 .clkdm_name = "core_l4_clkdm",
1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1710 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1711 .recalc = &followparent_recalc,
1712};
1713
1714static struct clk usb_fck = {
1715 .name = "usb_fck",
1716 .ops = &clkops_omap2_dflt_wait,
1717 .parent = &func_48m_ck,
1718 .clkdm_name = "core_l3_clkdm",
1719 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1720 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1721 .recalc = &followparent_recalc,
1722};
1723
1724static struct clk usbhs_ick = {
1725 .name = "usbhs_ick",
1726 .ops = &clkops_omap2_iclk_dflt_wait,
1727 .parent = &core_l3_ck,
1728 .clkdm_name = "core_l3_clkdm",
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1730 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1731 .recalc = &followparent_recalc,
1732};
1733
1734static struct clk mmchs1_ick = {
1735 .name = "mmchs1_ick",
1736 .ops = &clkops_omap2_iclk_dflt_wait,
1737 .parent = &l4_ck,
1738 .clkdm_name = "core_l4_clkdm",
1739 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1740 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1741 .recalc = &followparent_recalc,
1742};
1743
1744static struct clk mmchs1_fck = {
1745 .name = "mmchs1_fck",
1746 .ops = &clkops_omap2_dflt_wait,
1747 .parent = &func_96m_ck,
1748 .clkdm_name = "core_l4_clkdm",
1749 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1750 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1751 .recalc = &followparent_recalc,
1752};
1753
1754static struct clk mmchs2_ick = {
1755 .name = "mmchs2_ick",
1756 .ops = &clkops_omap2_iclk_dflt_wait,
1757 .parent = &l4_ck,
1758 .clkdm_name = "core_l4_clkdm",
1759 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1760 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1761 .recalc = &followparent_recalc,
1762};
1763
1764static struct clk mmchs2_fck = {
1765 .name = "mmchs2_fck",
1766 .ops = &clkops_omap2_dflt_wait,
1767 .parent = &func_96m_ck,
1768 .clkdm_name = "core_l4_clkdm",
1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1770 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1771 .recalc = &followparent_recalc,
1772};
1773
1774static struct clk gpio5_ick = {
1775 .name = "gpio5_ick",
1776 .ops = &clkops_omap2_iclk_dflt_wait,
1777 .parent = &l4_ck,
1778 .clkdm_name = "core_l4_clkdm",
1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1780 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1781 .recalc = &followparent_recalc,
1782};
1783
1784static struct clk gpio5_fck = {
1785 .name = "gpio5_fck",
1786 .ops = &clkops_omap2_dflt_wait,
1787 .parent = &func_32k_ck,
1788 .clkdm_name = "core_l4_clkdm",
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1790 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1791 .recalc = &followparent_recalc,
1792};
1793
1794static struct clk mdm_intc_ick = {
1795 .name = "mdm_intc_ick",
1796 .ops = &clkops_omap2_iclk_dflt_wait,
1797 .parent = &l4_ck,
1798 .clkdm_name = "core_l4_clkdm",
1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1800 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1801 .recalc = &followparent_recalc,
1802};
1803
1804static struct clk mmchsdb1_fck = {
1805 .name = "mmchsdb1_fck",
1806 .ops = &clkops_omap2_dflt_wait,
1807 .parent = &func_32k_ck,
1808 .clkdm_name = "core_l4_clkdm",
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1810 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1811 .recalc = &followparent_recalc,
1812};
1813
1814static struct clk mmchsdb2_fck = {
1815 .name = "mmchsdb2_fck",
1816 .ops = &clkops_omap2_dflt_wait,
1817 .parent = &func_32k_ck,
1818 .clkdm_name = "core_l4_clkdm",
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1820 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1821 .recalc = &followparent_recalc,
1822};
1823
1824/*
1825 * This clock is a composite clock which does entire set changes then
1826 * forces a rebalance. It keys on the MPU speed, but it really could
1827 * be any key speed part of a set in the rate table.
1828 *
1829 * to really change a set, you need memory table sets which get changed
1830 * in sram, pre-notifiers & post notifiers, changing the top set, without
1831 * having low level display recalc's won't work... this is why dpm notifiers
1832 * work, isr's off, walk a list of clocks already _off_ and not messing with
1833 * the bus.
1834 *
1835 * This clock should have no parent. It embodies the entire upper level
1836 * active set. A parent will mess up some of the init also.
1837 */
1838static struct clk virt_prcm_set = {
1839 .name = "virt_prcm_set",
1840 .ops = &clkops_null,
1841 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1842 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1843 .set_rate = &omap2_select_table_rate,
1844 .round_rate = &omap2_round_to_table_rate,
1845};
1846
1847
1848/*
1849 * clkdev integration
1850 */
1851
1852static struct omap_clk omap2430_clks[] = {
1853 /* external root sources */
1854 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1855 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1856 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1857 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1858 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1859 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
1860 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
1861 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
1862 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
1863 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
1864 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1865 /* internal analog sources */
1866 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1867 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1868 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1869 /* internal prcm root sources */
1870 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1871 CLK(NULL, "core_ck", &core_ck, CK_243X),
1872 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
1873 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
1874 CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
1875 CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
1876 CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
1877 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1878 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1879 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1880 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1881 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1882 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1883 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1884 /* mpu domain clocks */
1885 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1886 /* dsp domain clocks */
1887 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1888 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1889 /* GFX domain clocks */
1890 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1891 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1892 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1893 /* Modem domain clocks */
1894 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1895 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1896 /* DSS domain clocks */
1897 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1898 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1899 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1900 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1901 /* L3 domain clocks */
1902 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1903 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1904 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1905 /* L4 domain clocks */
1906 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1907 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1908 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1909 /* virtual meta-group clock */
1910 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1911 /* general l4 interface ck, multi-parent functional clk */
1912 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1913 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1914 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1915 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1916 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1917 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1918 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1919 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1920 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1921 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1922 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1923 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1924 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1925 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1926 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1927 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1928 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1929 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1930 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1931 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1932 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1933 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1934 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1935 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1936 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1937 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1938 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1939 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1940 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1941 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1942 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1943 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1944 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1945 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1946 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1947 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1948 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1952 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1953 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1954 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1955 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1956 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1957 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1958 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1959 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1960 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1961 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1962 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1963 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1964 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1965 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1966 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1967 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1968 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1969 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1970 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1971 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1972 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1973 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1974 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1975 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1976 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1977 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1978 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1979 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1980 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1981 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1982 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1983 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1984 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1985 CLK(NULL, "des_ick", &des_ick, CK_243X),
1986 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1987 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1988 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1989 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1993 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1994 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2000 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2001};
2002
2003/*
2004 * init code
2005 */
2006
2007int __init omap2430_clk_init(void)
2008{
2009 const struct prcm_config *prcm;
2010 struct omap_clk *c;
2011 u32 clkrate;
2012
2013 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2014 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
2015 cpu_mask = RATE_IN_243X;
2016 rate_table = omap2430_rate_table;
2017
2018 clk_init(&omap2_clk_functions);
2019
2020 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2021 c++)
2022 clk_preinit(c->lk.clk);
2023
2024 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2025 propagate_rate(&osc_ck);
2026 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2027 propagate_rate(&sys_ck);
2028
2029 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2030 c++) {
2031 clkdev_add(&c->lk);
2032 clk_register(c->lk.clk);
2033 omap2_init_clk_clkdm(c->lk.clk);
2034 }
2035
2036 /* Disable autoidle on all clocks; let the PM code enable it later */
2037 omap_clk_disable_autoidle_all();
2038
2039 /* Check the MPU rate set by bootloader */
2040 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2041 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2042 if (!(prcm->flags & cpu_mask))
2043 continue;
2044 if (prcm->xtal_speed != sys_ck.rate)
2045 continue;
2046 if (prcm->dpll_speed <= clkrate)
2047 break;
2048 }
2049 curr_prcm_set = prcm;
2050
2051 recalculate_root_clocks();
2052
2053 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2054 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2055 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2056
2057 /*
2058 * Only enable those clocks we will need, let the drivers
2059 * enable other clocks as necessary
2060 */
2061 clk_enable_init_clocks();
2062
2063 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2064 vclk = clk_get(NULL, "virt_prcm_set");
2065 sclk = clk_get(NULL, "sys_ck");
2066 dclk = clk_get(NULL, "dpll_ck");
2067
2068 return 0;
2069}
2070
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