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-rw-r--r--arch/arm/mach-omap2/clock2420_data.c1970
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2070
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c3578
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c3416
-rw-r--r--arch/arm/mach-omap2/clockdomain2xxx_3xxx.c276
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c132
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.c557
-rw-r--r--arch/arm/mach-omap2/include/mach/am35xx.h44
-rw-r--r--arch/arm/mach-omap2/include/mach/board-rx51.h11
-rw-r--r--arch/arm/mach-omap2/include/mach/board-zoom.h12
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h391
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h1409
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h236
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h92
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S167
-rw-r--r--arch/arm/mach-omap2/include/mach/gpio.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/id.h22
-rw-r--r--arch/arm/mach-omap2/include/mach/io.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/memory.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h43
-rw-r--r--arch/arm/mach-omap2/include/mach/smp.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/system.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-omap2/io.h7
-rw-r--r--arch/arm/mach-omap2/iommu2.c361
-rw-r--r--arch/arm/mach-omap2/omap44xx-smc.S57
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c248
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h132
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c299
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h338
-rw-r--r--arch/arm/mach-omap2/powerdomain2xxx_3xxx.c241
-rw-r--r--arch/arm/mach-omap2/powerdomain44xx.c225
-rw-r--r--arch/arm/mach-omap2/prcm.c167
-rw-r--r--arch/arm/mach-omap2/smartreflex.c1046
-rw-r--r--arch/arm/mach-omap2/smartreflex.h246
-rw-r--r--arch/arm/mach-omap2/timer-mpu.c39
-rw-r--r--arch/arm/mach-omap2/usb-fs.c359
37 files changed, 18236 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
new file mode 100644
index 00000000000..debc040872f
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -0,0 +1,1970 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/clkdev_omap.h>
21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx_3xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
33
34/*
35 * 2420 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56 .clkdm_name = "wkup_clkdm",
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .clkdm_name = "wkup_clkdm",
64};
65
66/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
69 .ops = &clkops_oscck,
70 .clkdm_name = "wkup_clkdm",
71 .recalc = &omap2_osc_clk_recalc,
72};
73
74/* Without modem likely 12MHz, with modem likely 13MHz */
75static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
77 .ops = &clkops_null,
78 .parent = &osc_ck,
79 .clkdm_name = "wkup_clkdm",
80 .recalc = &omap2xxx_sys_clk_recalc,
81};
82
83static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
85 .ops = &clkops_null,
86 .rate = 54000000,
87 .clkdm_name = "wkup_clkdm",
88};
89
90/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
96/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
105static struct dpll_data dpll_dd = {
106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
113 .max_multiplier = 1023,
114 .min_divider = 1,
115 .max_divider = 16,
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_omap2xxx_dpll_ops,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .dpll_data = &dpll_dd,
127 .clkdm_name = "wkup_clkdm",
128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
134 .ops = &clkops_apll96,
135 .parent = &sys_ck,
136 .rate = 96000000,
137 .flags = ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
145 .ops = &clkops_apll54,
146 .parent = &sys_ck,
147 .rate = 54000000,
148 .flags = ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
152};
153
154/*
155 * PRCM digital base sources
156 */
157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
161 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
178 .ops = &clkops_null,
179 .parent = &apll54_ck, /* can also be alt_clk */
180 .clkdm_name = "wkup_clkdm",
181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
183 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
186};
187
188static struct clk core_ck = {
189 .name = "core_ck",
190 .ops = &clkops_null,
191 .parent = &dpll_ck, /* can also be 32k */
192 .clkdm_name = "wkup_clkdm",
193 .recalc = &followparent_recalc,
194};
195
196static struct clk func_96m_ck = {
197 .name = "func_96m_ck",
198 .ops = &clkops_null,
199 .parent = &apll96_ck,
200 .clkdm_name = "wkup_clkdm",
201 .recalc = &followparent_recalc,
202};
203
204/* func_48m_ck */
205
206static const struct clksel_rate func_48m_apll96_rates[] = {
207 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
208 { .div = 0 },
209};
210
211static const struct clksel_rate func_48m_alt_rates[] = {
212 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
213 { .div = 0 },
214};
215
216static const struct clksel func_48m_clksel[] = {
217 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
218 { .parent = &alt_ck, .rates = func_48m_alt_rates },
219 { .parent = NULL }
220};
221
222static struct clk func_48m_ck = {
223 .name = "func_48m_ck",
224 .ops = &clkops_null,
225 .parent = &apll96_ck, /* 96M or Alt */
226 .clkdm_name = "wkup_clkdm",
227 .init = &omap2_init_clksel_parent,
228 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
229 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
230 .clksel = func_48m_clksel,
231 .recalc = &omap2_clksel_recalc,
232 .round_rate = &omap2_clksel_round_rate,
233 .set_rate = &omap2_clksel_set_rate
234};
235
236static struct clk func_12m_ck = {
237 .name = "func_12m_ck",
238 .ops = &clkops_null,
239 .parent = &func_48m_ck,
240 .fixed_div = 4,
241 .clkdm_name = "wkup_clkdm",
242 .recalc = &omap_fixed_divisor_recalc,
243};
244
245/* Secure timer, only available in secure mode */
246static struct clk wdt1_osc_ck = {
247 .name = "ck_wdt1_osc",
248 .ops = &clkops_null, /* RMK: missing? */
249 .parent = &osc_ck,
250 .recalc = &followparent_recalc,
251};
252
253/*
254 * The common_clkout* clksel_rate structs are common to
255 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
256 * sys_clkout2_* are 2420-only, so the
257 * clksel_rate flags fields are inaccurate for those clocks. This is
258 * harmless since access to those clocks are gated by the struct clk
259 * flags fields, which mark them as 2420-only.
260 */
261static const struct clksel_rate common_clkout_src_core_rates[] = {
262 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
263 { .div = 0 }
264};
265
266static const struct clksel_rate common_clkout_src_sys_rates[] = {
267 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
268 { .div = 0 }
269};
270
271static const struct clksel_rate common_clkout_src_96m_rates[] = {
272 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
273 { .div = 0 }
274};
275
276static const struct clksel_rate common_clkout_src_54m_rates[] = {
277 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
278 { .div = 0 }
279};
280
281static const struct clksel common_clkout_src_clksel[] = {
282 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
283 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
284 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
285 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
286 { .parent = NULL }
287};
288
289static struct clk sys_clkout_src = {
290 .name = "sys_clkout_src",
291 .ops = &clkops_omap2_dflt,
292 .parent = &func_54m_ck,
293 .clkdm_name = "wkup_clkdm",
294 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
295 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
296 .init = &omap2_init_clksel_parent,
297 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
298 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
299 .clksel = common_clkout_src_clksel,
300 .recalc = &omap2_clksel_recalc,
301 .round_rate = &omap2_clksel_round_rate,
302 .set_rate = &omap2_clksel_set_rate
303};
304
305static const struct clksel_rate common_clkout_rates[] = {
306 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
307 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
308 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
309 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
310 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
311 { .div = 0 },
312};
313
314static const struct clksel sys_clkout_clksel[] = {
315 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
316 { .parent = NULL }
317};
318
319static struct clk sys_clkout = {
320 .name = "sys_clkout",
321 .ops = &clkops_null,
322 .parent = &sys_clkout_src,
323 .clkdm_name = "wkup_clkdm",
324 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
325 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
326 .clksel = sys_clkout_clksel,
327 .recalc = &omap2_clksel_recalc,
328 .round_rate = &omap2_clksel_round_rate,
329 .set_rate = &omap2_clksel_set_rate
330};
331
332/* In 2430, new in 2420 ES2 */
333static struct clk sys_clkout2_src = {
334 .name = "sys_clkout2_src",
335 .ops = &clkops_omap2_dflt,
336 .parent = &func_54m_ck,
337 .clkdm_name = "wkup_clkdm",
338 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
339 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
340 .init = &omap2_init_clksel_parent,
341 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
342 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
343 .clksel = common_clkout_src_clksel,
344 .recalc = &omap2_clksel_recalc,
345 .round_rate = &omap2_clksel_round_rate,
346 .set_rate = &omap2_clksel_set_rate
347};
348
349static const struct clksel sys_clkout2_clksel[] = {
350 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
351 { .parent = NULL }
352};
353
354/* In 2430, new in 2420 ES2 */
355static struct clk sys_clkout2 = {
356 .name = "sys_clkout2",
357 .ops = &clkops_null,
358 .parent = &sys_clkout2_src,
359 .clkdm_name = "wkup_clkdm",
360 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
361 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
362 .clksel = sys_clkout2_clksel,
363 .recalc = &omap2_clksel_recalc,
364 .round_rate = &omap2_clksel_round_rate,
365 .set_rate = &omap2_clksel_set_rate
366};
367
368static struct clk emul_ck = {
369 .name = "emul_ck",
370 .ops = &clkops_omap2_dflt,
371 .parent = &func_54m_ck,
372 .clkdm_name = "wkup_clkdm",
373 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
374 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
375 .recalc = &followparent_recalc,
376
377};
378
379/*
380 * MPU clock domain
381 * Clocks:
382 * MPU_FCLK, MPU_ICLK
383 * INT_M_FCLK, INT_M_I_CLK
384 *
385 * - Individual clocks are hardware managed.
386 * - Base divider comes from: CM_CLKSEL_MPU
387 *
388 */
389static const struct clksel_rate mpu_core_rates[] = {
390 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
391 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
392 { .div = 4, .val = 4, .flags = RATE_IN_242X },
393 { .div = 6, .val = 6, .flags = RATE_IN_242X },
394 { .div = 8, .val = 8, .flags = RATE_IN_242X },
395 { .div = 0 },
396};
397
398static const struct clksel mpu_clksel[] = {
399 { .parent = &core_ck, .rates = mpu_core_rates },
400 { .parent = NULL }
401};
402
403static struct clk mpu_ck = { /* Control cpu */
404 .name = "mpu_ck",
405 .ops = &clkops_null,
406 .parent = &core_ck,
407 .clkdm_name = "mpu_clkdm",
408 .init = &omap2_init_clksel_parent,
409 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
410 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
411 .clksel = mpu_clksel,
412 .recalc = &omap2_clksel_recalc,
413};
414
415/*
416 * DSP (2420-UMA+IVA1) clock domain
417 * Clocks:
418 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
419 *
420 * Won't be too specific here. The core clock comes into this block
421 * it is divided then tee'ed. One branch goes directly to xyz enable
422 * controls. The other branch gets further divided by 2 then possibly
423 * routed into a synchronizer and out of clocks abc.
424 */
425static const struct clksel_rate dsp_fck_core_rates[] = {
426 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
427 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
428 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
429 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
430 { .div = 6, .val = 6, .flags = RATE_IN_242X },
431 { .div = 8, .val = 8, .flags = RATE_IN_242X },
432 { .div = 12, .val = 12, .flags = RATE_IN_242X },
433 { .div = 0 },
434};
435
436static const struct clksel dsp_fck_clksel[] = {
437 { .parent = &core_ck, .rates = dsp_fck_core_rates },
438 { .parent = NULL }
439};
440
441static struct clk dsp_fck = {
442 .name = "dsp_fck",
443 .ops = &clkops_omap2_dflt_wait,
444 .parent = &core_ck,
445 .clkdm_name = "dsp_clkdm",
446 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
447 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
448 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
449 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
450 .clksel = dsp_fck_clksel,
451 .recalc = &omap2_clksel_recalc,
452};
453
454static const struct clksel dsp_ick_clksel[] = {
455 { .parent = &dsp_fck, .rates = dsp_ick_rates },
456 { .parent = NULL }
457};
458
459static struct clk dsp_ick = {
460 .name = "dsp_ick", /* apparently ipi and isp */
461 .ops = &clkops_omap2_iclk_dflt_wait,
462 .parent = &dsp_fck,
463 .clkdm_name = "dsp_clkdm",
464 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
465 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
466 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
467 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
468 .clksel = dsp_ick_clksel,
469 .recalc = &omap2_clksel_recalc,
470};
471
472/*
473 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
474 * the C54x, but which is contained in the DSP powerdomain. Does not
475 * exist on later OMAPs.
476 */
477static struct clk iva1_ifck = {
478 .name = "iva1_ifck",
479 .ops = &clkops_omap2_dflt_wait,
480 .parent = &core_ck,
481 .clkdm_name = "iva1_clkdm",
482 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
483 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
484 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
485 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
486 .clksel = dsp_fck_clksel,
487 .recalc = &omap2_clksel_recalc,
488};
489
490/* IVA1 mpu/int/i/f clocks are /2 of parent */
491static struct clk iva1_mpu_int_ifck = {
492 .name = "iva1_mpu_int_ifck",
493 .ops = &clkops_omap2_dflt_wait,
494 .parent = &iva1_ifck,
495 .clkdm_name = "iva1_clkdm",
496 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
497 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
498 .fixed_div = 2,
499 .recalc = &omap_fixed_divisor_recalc,
500};
501
502/*
503 * L3 clock domain
504 * L3 clocks are used for both interface and functional clocks to
505 * multiple entities. Some of these clocks are completely managed
506 * by hardware, and some others allow software control. Hardware
507 * managed ones general are based on directly CLK_REQ signals and
508 * various auto idle settings. The functional spec sets many of these
509 * as 'tie-high' for their enables.
510 *
511 * I-CLOCKS:
512 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
513 * CAM, HS-USB.
514 * F-CLOCK
515 * SSI.
516 *
517 * GPMC memories and SDRC have timing and clock sensitive registers which
518 * may very well need notification when the clock changes. Currently for low
519 * operating points, these are taken care of in sleep.S.
520 */
521static const struct clksel_rate core_l3_core_rates[] = {
522 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
523 { .div = 2, .val = 2, .flags = RATE_IN_242X },
524 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
525 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
526 { .div = 8, .val = 8, .flags = RATE_IN_242X },
527 { .div = 12, .val = 12, .flags = RATE_IN_242X },
528 { .div = 16, .val = 16, .flags = RATE_IN_242X },
529 { .div = 0 }
530};
531
532static const struct clksel core_l3_clksel[] = {
533 { .parent = &core_ck, .rates = core_l3_core_rates },
534 { .parent = NULL }
535};
536
537static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
538 .name = "core_l3_ck",
539 .ops = &clkops_null,
540 .parent = &core_ck,
541 .clkdm_name = "core_l3_clkdm",
542 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
543 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
544 .clksel = core_l3_clksel,
545 .recalc = &omap2_clksel_recalc,
546};
547
548/* usb_l4_ick */
549static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
550 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
551 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
552 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
553 { .div = 0 }
554};
555
556static const struct clksel usb_l4_ick_clksel[] = {
557 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
558 { .parent = NULL },
559};
560
561/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
562static struct clk usb_l4_ick = { /* FS-USB interface clock */
563 .name = "usb_l4_ick",
564 .ops = &clkops_omap2_iclk_dflt_wait,
565 .parent = &core_l3_ck,
566 .clkdm_name = "core_l4_clkdm",
567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
568 .enable_bit = OMAP24XX_EN_USB_SHIFT,
569 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
570 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
571 .clksel = usb_l4_ick_clksel,
572 .recalc = &omap2_clksel_recalc,
573};
574
575/*
576 * L4 clock management domain
577 *
578 * This domain contains lots of interface clocks from the L4 interface, some
579 * functional clocks. Fixed APLL functional source clocks are managed in
580 * this domain.
581 */
582static const struct clksel_rate l4_core_l3_rates[] = {
583 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
584 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
585 { .div = 0 }
586};
587
588static const struct clksel l4_clksel[] = {
589 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
590 { .parent = NULL }
591};
592
593static struct clk l4_ck = { /* used both as an ick and fck */
594 .name = "l4_ck",
595 .ops = &clkops_null,
596 .parent = &core_l3_ck,
597 .clkdm_name = "core_l4_clkdm",
598 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
599 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
600 .clksel = l4_clksel,
601 .recalc = &omap2_clksel_recalc,
602};
603
604/*
605 * SSI is in L3 management domain, its direct parent is core not l3,
606 * many core power domain entities are grouped into the L3 clock
607 * domain.
608 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
609 *
610 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
611 */
612static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
613 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
614 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
615 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
616 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
617 { .div = 6, .val = 6, .flags = RATE_IN_242X },
618 { .div = 8, .val = 8, .flags = RATE_IN_242X },
619 { .div = 0 }
620};
621
622static const struct clksel ssi_ssr_sst_fck_clksel[] = {
623 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
624 { .parent = NULL }
625};
626
627static struct clk ssi_ssr_sst_fck = {
628 .name = "ssi_fck",
629 .ops = &clkops_omap2_dflt_wait,
630 .parent = &core_ck,
631 .clkdm_name = "core_l3_clkdm",
632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
633 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
634 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
635 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
636 .clksel = ssi_ssr_sst_fck_clksel,
637 .recalc = &omap2_clksel_recalc,
638};
639
640/*
641 * Presumably this is the same as SSI_ICLK.
642 * TRM contradicts itself on what clockdomain SSI_ICLK is in
643 */
644static struct clk ssi_l4_ick = {
645 .name = "ssi_l4_ick",
646 .ops = &clkops_omap2_iclk_dflt_wait,
647 .parent = &l4_ck,
648 .clkdm_name = "core_l4_clkdm",
649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
650 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
651 .recalc = &followparent_recalc,
652};
653
654
655/*
656 * GFX clock domain
657 * Clocks:
658 * GFX_FCLK, GFX_ICLK
659 * GFX_CG1(2d), GFX_CG2(3d)
660 *
661 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
662 * The 2d and 3d clocks run at a hardware determined
663 * divided value of fclk.
664 *
665 */
666
667/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
668static const struct clksel gfx_fck_clksel[] = {
669 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
670 { .parent = NULL },
671};
672
673static struct clk gfx_3d_fck = {
674 .name = "gfx_3d_fck",
675 .ops = &clkops_omap2_dflt_wait,
676 .parent = &core_l3_ck,
677 .clkdm_name = "gfx_clkdm",
678 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
679 .enable_bit = OMAP24XX_EN_3D_SHIFT,
680 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
681 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
682 .clksel = gfx_fck_clksel,
683 .recalc = &omap2_clksel_recalc,
684 .round_rate = &omap2_clksel_round_rate,
685 .set_rate = &omap2_clksel_set_rate
686};
687
688static struct clk gfx_2d_fck = {
689 .name = "gfx_2d_fck",
690 .ops = &clkops_omap2_dflt_wait,
691 .parent = &core_l3_ck,
692 .clkdm_name = "gfx_clkdm",
693 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
694 .enable_bit = OMAP24XX_EN_2D_SHIFT,
695 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
696 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
697 .clksel = gfx_fck_clksel,
698 .recalc = &omap2_clksel_recalc,
699};
700
701/* This interface clock does not have a CM_AUTOIDLE bit */
702static struct clk gfx_ick = {
703 .name = "gfx_ick", /* From l3 */
704 .ops = &clkops_omap2_dflt_wait,
705 .parent = &core_l3_ck,
706 .clkdm_name = "gfx_clkdm",
707 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
708 .enable_bit = OMAP_EN_GFX_SHIFT,
709 .recalc = &followparent_recalc,
710};
711
712/*
713 * DSS clock domain
714 * CLOCKs:
715 * DSS_L4_ICLK, DSS_L3_ICLK,
716 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
717 *
718 * DSS is both initiator and target.
719 */
720/* XXX Add RATE_NOT_VALIDATED */
721
722static const struct clksel_rate dss1_fck_sys_rates[] = {
723 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
724 { .div = 0 }
725};
726
727static const struct clksel_rate dss1_fck_core_rates[] = {
728 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
729 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
730 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
731 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
732 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
733 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
734 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
735 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
736 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
737 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
738 { .div = 0 }
739};
740
741static const struct clksel dss1_fck_clksel[] = {
742 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
743 { .parent = &core_ck, .rates = dss1_fck_core_rates },
744 { .parent = NULL },
745};
746
747static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
748 .name = "dss_ick",
749 .ops = &clkops_omap2_iclk_dflt,
750 .parent = &l4_ck, /* really both l3 and l4 */
751 .clkdm_name = "dss_clkdm",
752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
753 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
754 .recalc = &followparent_recalc,
755};
756
757static struct clk dss1_fck = {
758 .name = "dss1_fck",
759 .ops = &clkops_omap2_dflt,
760 .parent = &core_ck, /* Core or sys */
761 .clkdm_name = "dss_clkdm",
762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
763 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
764 .init = &omap2_init_clksel_parent,
765 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
766 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
767 .clksel = dss1_fck_clksel,
768 .recalc = &omap2_clksel_recalc,
769};
770
771static const struct clksel_rate dss2_fck_sys_rates[] = {
772 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
773 { .div = 0 }
774};
775
776static const struct clksel_rate dss2_fck_48m_rates[] = {
777 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
778 { .div = 0 }
779};
780
781static const struct clksel dss2_fck_clksel[] = {
782 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
783 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
784 { .parent = NULL }
785};
786
787static struct clk dss2_fck = { /* Alt clk used in power management */
788 .name = "dss2_fck",
789 .ops = &clkops_omap2_dflt,
790 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
791 .clkdm_name = "dss_clkdm",
792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
793 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
794 .init = &omap2_init_clksel_parent,
795 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
796 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
797 .clksel = dss2_fck_clksel,
798 .recalc = &omap2_clksel_recalc,
799};
800
801static struct clk dss_54m_fck = { /* Alt clk used in power management */
802 .name = "dss_54m_fck", /* 54m tv clk */
803 .ops = &clkops_omap2_dflt_wait,
804 .parent = &func_54m_ck,
805 .clkdm_name = "dss_clkdm",
806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
807 .enable_bit = OMAP24XX_EN_TV_SHIFT,
808 .recalc = &followparent_recalc,
809};
810
811static struct clk wu_l4_ick = {
812 .name = "wu_l4_ick",
813 .ops = &clkops_null,
814 .parent = &sys_ck,
815 .clkdm_name = "wkup_clkdm",
816 .recalc = &followparent_recalc,
817};
818
819/*
820 * CORE power domain ICLK & FCLK defines.
821 * Many of the these can have more than one possible parent. Entries
822 * here will likely have an L4 interface parent, and may have multiple
823 * functional clock parents.
824 */
825static const struct clksel_rate gpt_alt_rates[] = {
826 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
827 { .div = 0 }
828};
829
830static const struct clksel omap24xx_gpt_clksel[] = {
831 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
832 { .parent = &sys_ck, .rates = gpt_sys_rates },
833 { .parent = &alt_ck, .rates = gpt_alt_rates },
834 { .parent = NULL },
835};
836
837static struct clk gpt1_ick = {
838 .name = "gpt1_ick",
839 .ops = &clkops_omap2_iclk_dflt_wait,
840 .parent = &wu_l4_ick,
841 .clkdm_name = "wkup_clkdm",
842 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
843 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
844 .recalc = &followparent_recalc,
845};
846
847static struct clk gpt1_fck = {
848 .name = "gpt1_fck",
849 .ops = &clkops_omap2_dflt_wait,
850 .parent = &func_32k_ck,
851 .clkdm_name = "core_l4_clkdm",
852 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
853 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
854 .init = &omap2_init_clksel_parent,
855 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
856 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
857 .clksel = omap24xx_gpt_clksel,
858 .recalc = &omap2_clksel_recalc,
859 .round_rate = &omap2_clksel_round_rate,
860 .set_rate = &omap2_clksel_set_rate
861};
862
863static struct clk gpt2_ick = {
864 .name = "gpt2_ick",
865 .ops = &clkops_omap2_iclk_dflt_wait,
866 .parent = &l4_ck,
867 .clkdm_name = "core_l4_clkdm",
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
870 .recalc = &followparent_recalc,
871};
872
873static struct clk gpt2_fck = {
874 .name = "gpt2_fck",
875 .ops = &clkops_omap2_dflt_wait,
876 .parent = &func_32k_ck,
877 .clkdm_name = "core_l4_clkdm",
878 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
879 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
882 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
883 .clksel = omap24xx_gpt_clksel,
884 .recalc = &omap2_clksel_recalc,
885};
886
887static struct clk gpt3_ick = {
888 .name = "gpt3_ick",
889 .ops = &clkops_omap2_iclk_dflt_wait,
890 .parent = &l4_ck,
891 .clkdm_name = "core_l4_clkdm",
892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
893 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
894 .recalc = &followparent_recalc,
895};
896
897static struct clk gpt3_fck = {
898 .name = "gpt3_fck",
899 .ops = &clkops_omap2_dflt_wait,
900 .parent = &func_32k_ck,
901 .clkdm_name = "core_l4_clkdm",
902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
903 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
904 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
906 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
907 .clksel = omap24xx_gpt_clksel,
908 .recalc = &omap2_clksel_recalc,
909};
910
911static struct clk gpt4_ick = {
912 .name = "gpt4_ick",
913 .ops = &clkops_omap2_iclk_dflt_wait,
914 .parent = &l4_ck,
915 .clkdm_name = "core_l4_clkdm",
916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
917 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
918 .recalc = &followparent_recalc,
919};
920
921static struct clk gpt4_fck = {
922 .name = "gpt4_fck",
923 .ops = &clkops_omap2_dflt_wait,
924 .parent = &func_32k_ck,
925 .clkdm_name = "core_l4_clkdm",
926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
927 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
928 .init = &omap2_init_clksel_parent,
929 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
930 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
931 .clksel = omap24xx_gpt_clksel,
932 .recalc = &omap2_clksel_recalc,
933};
934
935static struct clk gpt5_ick = {
936 .name = "gpt5_ick",
937 .ops = &clkops_omap2_iclk_dflt_wait,
938 .parent = &l4_ck,
939 .clkdm_name = "core_l4_clkdm",
940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
941 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
942 .recalc = &followparent_recalc,
943};
944
945static struct clk gpt5_fck = {
946 .name = "gpt5_fck",
947 .ops = &clkops_omap2_dflt_wait,
948 .parent = &func_32k_ck,
949 .clkdm_name = "core_l4_clkdm",
950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
951 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
952 .init = &omap2_init_clksel_parent,
953 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
954 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
955 .clksel = omap24xx_gpt_clksel,
956 .recalc = &omap2_clksel_recalc,
957};
958
959static struct clk gpt6_ick = {
960 .name = "gpt6_ick",
961 .ops = &clkops_omap2_iclk_dflt_wait,
962 .parent = &l4_ck,
963 .clkdm_name = "core_l4_clkdm",
964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
965 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
966 .recalc = &followparent_recalc,
967};
968
969static struct clk gpt6_fck = {
970 .name = "gpt6_fck",
971 .ops = &clkops_omap2_dflt_wait,
972 .parent = &func_32k_ck,
973 .clkdm_name = "core_l4_clkdm",
974 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
975 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
976 .init = &omap2_init_clksel_parent,
977 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
978 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
979 .clksel = omap24xx_gpt_clksel,
980 .recalc = &omap2_clksel_recalc,
981};
982
983static struct clk gpt7_ick = {
984 .name = "gpt7_ick",
985 .ops = &clkops_omap2_iclk_dflt_wait,
986 .parent = &l4_ck,
987 .clkdm_name = "core_l4_clkdm",
988 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
989 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
990 .recalc = &followparent_recalc,
991};
992
993static struct clk gpt7_fck = {
994 .name = "gpt7_fck",
995 .ops = &clkops_omap2_dflt_wait,
996 .parent = &func_32k_ck,
997 .clkdm_name = "core_l4_clkdm",
998 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
999 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1000 .init = &omap2_init_clksel_parent,
1001 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1002 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1003 .clksel = omap24xx_gpt_clksel,
1004 .recalc = &omap2_clksel_recalc,
1005};
1006
1007static struct clk gpt8_ick = {
1008 .name = "gpt8_ick",
1009 .ops = &clkops_omap2_iclk_dflt_wait,
1010 .parent = &l4_ck,
1011 .clkdm_name = "core_l4_clkdm",
1012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1013 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1014 .recalc = &followparent_recalc,
1015};
1016
1017static struct clk gpt8_fck = {
1018 .name = "gpt8_fck",
1019 .ops = &clkops_omap2_dflt_wait,
1020 .parent = &func_32k_ck,
1021 .clkdm_name = "core_l4_clkdm",
1022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1023 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1024 .init = &omap2_init_clksel_parent,
1025 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1026 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1027 .clksel = omap24xx_gpt_clksel,
1028 .recalc = &omap2_clksel_recalc,
1029};
1030
1031static struct clk gpt9_ick = {
1032 .name = "gpt9_ick",
1033 .ops = &clkops_omap2_iclk_dflt_wait,
1034 .parent = &l4_ck,
1035 .clkdm_name = "core_l4_clkdm",
1036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1037 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1038 .recalc = &followparent_recalc,
1039};
1040
1041static struct clk gpt9_fck = {
1042 .name = "gpt9_fck",
1043 .ops = &clkops_omap2_dflt_wait,
1044 .parent = &func_32k_ck,
1045 .clkdm_name = "core_l4_clkdm",
1046 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1047 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1048 .init = &omap2_init_clksel_parent,
1049 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1050 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1051 .clksel = omap24xx_gpt_clksel,
1052 .recalc = &omap2_clksel_recalc,
1053};
1054
1055static struct clk gpt10_ick = {
1056 .name = "gpt10_ick",
1057 .ops = &clkops_omap2_iclk_dflt_wait,
1058 .parent = &l4_ck,
1059 .clkdm_name = "core_l4_clkdm",
1060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1061 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1062 .recalc = &followparent_recalc,
1063};
1064
1065static struct clk gpt10_fck = {
1066 .name = "gpt10_fck",
1067 .ops = &clkops_omap2_dflt_wait,
1068 .parent = &func_32k_ck,
1069 .clkdm_name = "core_l4_clkdm",
1070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1071 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1072 .init = &omap2_init_clksel_parent,
1073 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1074 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1075 .clksel = omap24xx_gpt_clksel,
1076 .recalc = &omap2_clksel_recalc,
1077};
1078
1079static struct clk gpt11_ick = {
1080 .name = "gpt11_ick",
1081 .ops = &clkops_omap2_iclk_dflt_wait,
1082 .parent = &l4_ck,
1083 .clkdm_name = "core_l4_clkdm",
1084 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1085 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1086 .recalc = &followparent_recalc,
1087};
1088
1089static struct clk gpt11_fck = {
1090 .name = "gpt11_fck",
1091 .ops = &clkops_omap2_dflt_wait,
1092 .parent = &func_32k_ck,
1093 .clkdm_name = "core_l4_clkdm",
1094 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1096 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1098 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1099 .clksel = omap24xx_gpt_clksel,
1100 .recalc = &omap2_clksel_recalc,
1101};
1102
1103static struct clk gpt12_ick = {
1104 .name = "gpt12_ick",
1105 .ops = &clkops_omap2_iclk_dflt_wait,
1106 .parent = &l4_ck,
1107 .clkdm_name = "core_l4_clkdm",
1108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1109 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1110 .recalc = &followparent_recalc,
1111};
1112
1113static struct clk gpt12_fck = {
1114 .name = "gpt12_fck",
1115 .ops = &clkops_omap2_dflt_wait,
1116 .parent = &secure_32k_ck,
1117 .clkdm_name = "core_l4_clkdm",
1118 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1119 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1120 .init = &omap2_init_clksel_parent,
1121 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1122 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1123 .clksel = omap24xx_gpt_clksel,
1124 .recalc = &omap2_clksel_recalc,
1125};
1126
1127static struct clk mcbsp1_ick = {
1128 .name = "mcbsp1_ick",
1129 .ops = &clkops_omap2_iclk_dflt_wait,
1130 .parent = &l4_ck,
1131 .clkdm_name = "core_l4_clkdm",
1132 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1133 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1134 .recalc = &followparent_recalc,
1135};
1136
1137static const struct clksel_rate common_mcbsp_96m_rates[] = {
1138 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1139 { .div = 0 }
1140};
1141
1142static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1143 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1144 { .div = 0 }
1145};
1146
1147static const struct clksel mcbsp_fck_clksel[] = {
1148 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1149 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1150 { .parent = NULL }
1151};
1152
1153static struct clk mcbsp1_fck = {
1154 .name = "mcbsp1_fck",
1155 .ops = &clkops_omap2_dflt_wait,
1156 .parent = &func_96m_ck,
1157 .init = &omap2_init_clksel_parent,
1158 .clkdm_name = "core_l4_clkdm",
1159 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1160 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1161 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1162 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1163 .clksel = mcbsp_fck_clksel,
1164 .recalc = &omap2_clksel_recalc,
1165};
1166
1167static struct clk mcbsp2_ick = {
1168 .name = "mcbsp2_ick",
1169 .ops = &clkops_omap2_iclk_dflt_wait,
1170 .parent = &l4_ck,
1171 .clkdm_name = "core_l4_clkdm",
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1174 .recalc = &followparent_recalc,
1175};
1176
1177static struct clk mcbsp2_fck = {
1178 .name = "mcbsp2_fck",
1179 .ops = &clkops_omap2_dflt_wait,
1180 .parent = &func_96m_ck,
1181 .init = &omap2_init_clksel_parent,
1182 .clkdm_name = "core_l4_clkdm",
1183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1185 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1186 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1187 .clksel = mcbsp_fck_clksel,
1188 .recalc = &omap2_clksel_recalc,
1189};
1190
1191static struct clk mcspi1_ick = {
1192 .name = "mcspi1_ick",
1193 .ops = &clkops_omap2_iclk_dflt_wait,
1194 .parent = &l4_ck,
1195 .clkdm_name = "core_l4_clkdm",
1196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1197 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1198 .recalc = &followparent_recalc,
1199};
1200
1201static struct clk mcspi1_fck = {
1202 .name = "mcspi1_fck",
1203 .ops = &clkops_omap2_dflt_wait,
1204 .parent = &func_48m_ck,
1205 .clkdm_name = "core_l4_clkdm",
1206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1207 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1208 .recalc = &followparent_recalc,
1209};
1210
1211static struct clk mcspi2_ick = {
1212 .name = "mcspi2_ick",
1213 .ops = &clkops_omap2_iclk_dflt_wait,
1214 .parent = &l4_ck,
1215 .clkdm_name = "core_l4_clkdm",
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1217 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1218 .recalc = &followparent_recalc,
1219};
1220
1221static struct clk mcspi2_fck = {
1222 .name = "mcspi2_fck",
1223 .ops = &clkops_omap2_dflt_wait,
1224 .parent = &func_48m_ck,
1225 .clkdm_name = "core_l4_clkdm",
1226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1227 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1228 .recalc = &followparent_recalc,
1229};
1230
1231static struct clk uart1_ick = {
1232 .name = "uart1_ick",
1233 .ops = &clkops_omap2_iclk_dflt_wait,
1234 .parent = &l4_ck,
1235 .clkdm_name = "core_l4_clkdm",
1236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1237 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1238 .recalc = &followparent_recalc,
1239};
1240
1241static struct clk uart1_fck = {
1242 .name = "uart1_fck",
1243 .ops = &clkops_omap2_dflt_wait,
1244 .parent = &func_48m_ck,
1245 .clkdm_name = "core_l4_clkdm",
1246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1247 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1248 .recalc = &followparent_recalc,
1249};
1250
1251static struct clk uart2_ick = {
1252 .name = "uart2_ick",
1253 .ops = &clkops_omap2_iclk_dflt_wait,
1254 .parent = &l4_ck,
1255 .clkdm_name = "core_l4_clkdm",
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1258 .recalc = &followparent_recalc,
1259};
1260
1261static struct clk uart2_fck = {
1262 .name = "uart2_fck",
1263 .ops = &clkops_omap2_dflt_wait,
1264 .parent = &func_48m_ck,
1265 .clkdm_name = "core_l4_clkdm",
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1268 .recalc = &followparent_recalc,
1269};
1270
1271static struct clk uart3_ick = {
1272 .name = "uart3_ick",
1273 .ops = &clkops_omap2_iclk_dflt_wait,
1274 .parent = &l4_ck,
1275 .clkdm_name = "core_l4_clkdm",
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1277 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1278 .recalc = &followparent_recalc,
1279};
1280
1281static struct clk uart3_fck = {
1282 .name = "uart3_fck",
1283 .ops = &clkops_omap2_dflt_wait,
1284 .parent = &func_48m_ck,
1285 .clkdm_name = "core_l4_clkdm",
1286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1287 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1288 .recalc = &followparent_recalc,
1289};
1290
1291static struct clk gpios_ick = {
1292 .name = "gpios_ick",
1293 .ops = &clkops_omap2_iclk_dflt_wait,
1294 .parent = &wu_l4_ick,
1295 .clkdm_name = "wkup_clkdm",
1296 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1297 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1298 .recalc = &followparent_recalc,
1299};
1300
1301static struct clk gpios_fck = {
1302 .name = "gpios_fck",
1303 .ops = &clkops_omap2_dflt_wait,
1304 .parent = &func_32k_ck,
1305 .clkdm_name = "wkup_clkdm",
1306 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1307 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static struct clk mpu_wdt_ick = {
1312 .name = "mpu_wdt_ick",
1313 .ops = &clkops_omap2_iclk_dflt_wait,
1314 .parent = &wu_l4_ick,
1315 .clkdm_name = "wkup_clkdm",
1316 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1317 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1318 .recalc = &followparent_recalc,
1319};
1320
1321static struct clk mpu_wdt_fck = {
1322 .name = "mpu_wdt_fck",
1323 .ops = &clkops_omap2_dflt_wait,
1324 .parent = &func_32k_ck,
1325 .clkdm_name = "wkup_clkdm",
1326 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1327 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1328 .recalc = &followparent_recalc,
1329};
1330
1331static struct clk sync_32k_ick = {
1332 .name = "sync_32k_ick",
1333 .ops = &clkops_omap2_iclk_dflt_wait,
1334 .parent = &wu_l4_ick,
1335 .clkdm_name = "wkup_clkdm",
1336 .flags = ENABLE_ON_INIT,
1337 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1338 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1339 .recalc = &followparent_recalc,
1340};
1341
1342static struct clk wdt1_ick = {
1343 .name = "wdt1_ick",
1344 .ops = &clkops_omap2_iclk_dflt_wait,
1345 .parent = &wu_l4_ick,
1346 .clkdm_name = "wkup_clkdm",
1347 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1348 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1349 .recalc = &followparent_recalc,
1350};
1351
1352static struct clk omapctrl_ick = {
1353 .name = "omapctrl_ick",
1354 .ops = &clkops_omap2_iclk_dflt_wait,
1355 .parent = &wu_l4_ick,
1356 .clkdm_name = "wkup_clkdm",
1357 .flags = ENABLE_ON_INIT,
1358 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1359 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1360 .recalc = &followparent_recalc,
1361};
1362
1363static struct clk cam_ick = {
1364 .name = "cam_ick",
1365 .ops = &clkops_omap2_iclk_dflt,
1366 .parent = &l4_ck,
1367 .clkdm_name = "core_l4_clkdm",
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1369 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1370 .recalc = &followparent_recalc,
1371};
1372
1373/*
1374 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1375 * split into two separate clocks, since the parent clocks are different
1376 * and the clockdomains are also different.
1377 */
1378static struct clk cam_fck = {
1379 .name = "cam_fck",
1380 .ops = &clkops_omap2_dflt,
1381 .parent = &func_96m_ck,
1382 .clkdm_name = "core_l3_clkdm",
1383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1385 .recalc = &followparent_recalc,
1386};
1387
1388static struct clk mailboxes_ick = {
1389 .name = "mailboxes_ick",
1390 .ops = &clkops_omap2_iclk_dflt_wait,
1391 .parent = &l4_ck,
1392 .clkdm_name = "core_l4_clkdm",
1393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1394 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1395 .recalc = &followparent_recalc,
1396};
1397
1398static struct clk wdt4_ick = {
1399 .name = "wdt4_ick",
1400 .ops = &clkops_omap2_iclk_dflt_wait,
1401 .parent = &l4_ck,
1402 .clkdm_name = "core_l4_clkdm",
1403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1404 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1405 .recalc = &followparent_recalc,
1406};
1407
1408static struct clk wdt4_fck = {
1409 .name = "wdt4_fck",
1410 .ops = &clkops_omap2_dflt_wait,
1411 .parent = &func_32k_ck,
1412 .clkdm_name = "core_l4_clkdm",
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1415 .recalc = &followparent_recalc,
1416};
1417
1418static struct clk wdt3_ick = {
1419 .name = "wdt3_ick",
1420 .ops = &clkops_omap2_iclk_dflt_wait,
1421 .parent = &l4_ck,
1422 .clkdm_name = "core_l4_clkdm",
1423 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1424 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1425 .recalc = &followparent_recalc,
1426};
1427
1428static struct clk wdt3_fck = {
1429 .name = "wdt3_fck",
1430 .ops = &clkops_omap2_dflt_wait,
1431 .parent = &func_32k_ck,
1432 .clkdm_name = "core_l4_clkdm",
1433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1435 .recalc = &followparent_recalc,
1436};
1437
1438static struct clk mspro_ick = {
1439 .name = "mspro_ick",
1440 .ops = &clkops_omap2_iclk_dflt_wait,
1441 .parent = &l4_ck,
1442 .clkdm_name = "core_l4_clkdm",
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1444 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1445 .recalc = &followparent_recalc,
1446};
1447
1448static struct clk mspro_fck = {
1449 .name = "mspro_fck",
1450 .ops = &clkops_omap2_dflt_wait,
1451 .parent = &func_96m_ck,
1452 .clkdm_name = "core_l4_clkdm",
1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1455 .recalc = &followparent_recalc,
1456};
1457
1458static struct clk mmc_ick = {
1459 .name = "mmc_ick",
1460 .ops = &clkops_omap2_iclk_dflt_wait,
1461 .parent = &l4_ck,
1462 .clkdm_name = "core_l4_clkdm",
1463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1464 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1465 .recalc = &followparent_recalc,
1466};
1467
1468static struct clk mmc_fck = {
1469 .name = "mmc_fck",
1470 .ops = &clkops_omap2_dflt_wait,
1471 .parent = &func_96m_ck,
1472 .clkdm_name = "core_l4_clkdm",
1473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk fac_ick = {
1479 .name = "fac_ick",
1480 .ops = &clkops_omap2_iclk_dflt_wait,
1481 .parent = &l4_ck,
1482 .clkdm_name = "core_l4_clkdm",
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1484 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk fac_fck = {
1489 .name = "fac_fck",
1490 .ops = &clkops_omap2_dflt_wait,
1491 .parent = &func_12m_ck,
1492 .clkdm_name = "core_l4_clkdm",
1493 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1495 .recalc = &followparent_recalc,
1496};
1497
1498static struct clk eac_ick = {
1499 .name = "eac_ick",
1500 .ops = &clkops_omap2_iclk_dflt_wait,
1501 .parent = &l4_ck,
1502 .clkdm_name = "core_l4_clkdm",
1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1504 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1505 .recalc = &followparent_recalc,
1506};
1507
1508static struct clk eac_fck = {
1509 .name = "eac_fck",
1510 .ops = &clkops_omap2_dflt_wait,
1511 .parent = &func_96m_ck,
1512 .clkdm_name = "core_l4_clkdm",
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1515 .recalc = &followparent_recalc,
1516};
1517
1518static struct clk hdq_ick = {
1519 .name = "hdq_ick",
1520 .ops = &clkops_omap2_iclk_dflt_wait,
1521 .parent = &l4_ck,
1522 .clkdm_name = "core_l4_clkdm",
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1524 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1525 .recalc = &followparent_recalc,
1526};
1527
1528static struct clk hdq_fck = {
1529 .name = "hdq_fck",
1530 .ops = &clkops_omap2_dflt_wait,
1531 .parent = &func_12m_ck,
1532 .clkdm_name = "core_l4_clkdm",
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1535 .recalc = &followparent_recalc,
1536};
1537
1538static struct clk i2c2_ick = {
1539 .name = "i2c2_ick",
1540 .ops = &clkops_omap2_iclk_dflt_wait,
1541 .parent = &l4_ck,
1542 .clkdm_name = "core_l4_clkdm",
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1545 .recalc = &followparent_recalc,
1546};
1547
1548static struct clk i2c2_fck = {
1549 .name = "i2c2_fck",
1550 .ops = &clkops_omap2_dflt_wait,
1551 .parent = &func_12m_ck,
1552 .clkdm_name = "core_l4_clkdm",
1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1555 .recalc = &followparent_recalc,
1556};
1557
1558static struct clk i2c1_ick = {
1559 .name = "i2c1_ick",
1560 .ops = &clkops_omap2_iclk_dflt_wait,
1561 .parent = &l4_ck,
1562 .clkdm_name = "core_l4_clkdm",
1563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1564 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1565 .recalc = &followparent_recalc,
1566};
1567
1568static struct clk i2c1_fck = {
1569 .name = "i2c1_fck",
1570 .ops = &clkops_omap2_dflt_wait,
1571 .parent = &func_12m_ck,
1572 .clkdm_name = "core_l4_clkdm",
1573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1575 .recalc = &followparent_recalc,
1576};
1577
1578/*
1579 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1580 * accesses derived from this data.
1581 */
1582static struct clk gpmc_fck = {
1583 .name = "gpmc_fck",
1584 .ops = &clkops_omap2_iclk_idle_only,
1585 .parent = &core_l3_ck,
1586 .flags = ENABLE_ON_INIT,
1587 .clkdm_name = "core_l3_clkdm",
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1589 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1590 .recalc = &followparent_recalc,
1591};
1592
1593static struct clk sdma_fck = {
1594 .name = "sdma_fck",
1595 .ops = &clkops_null, /* RMK: missing? */
1596 .parent = &core_l3_ck,
1597 .clkdm_name = "core_l3_clkdm",
1598 .recalc = &followparent_recalc,
1599};
1600
1601/*
1602 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1603 * accesses derived from this data.
1604 */
1605static struct clk sdma_ick = {
1606 .name = "sdma_ick",
1607 .ops = &clkops_omap2_iclk_idle_only,
1608 .parent = &core_l3_ck,
1609 .clkdm_name = "core_l3_clkdm",
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1611 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1612 .recalc = &followparent_recalc,
1613};
1614
1615/*
1616 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1617 * accesses derived from this data.
1618 */
1619static struct clk sdrc_ick = {
1620 .name = "sdrc_ick",
1621 .ops = &clkops_omap2_iclk_idle_only,
1622 .parent = &core_l3_ck,
1623 .flags = ENABLE_ON_INIT,
1624 .clkdm_name = "core_l3_clkdm",
1625 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1626 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1627 .recalc = &followparent_recalc,
1628};
1629
1630static struct clk vlynq_ick = {
1631 .name = "vlynq_ick",
1632 .ops = &clkops_omap2_iclk_dflt_wait,
1633 .parent = &core_l3_ck,
1634 .clkdm_name = "core_l3_clkdm",
1635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1636 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1637 .recalc = &followparent_recalc,
1638};
1639
1640static const struct clksel_rate vlynq_fck_96m_rates[] = {
1641 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1642 { .div = 0 }
1643};
1644
1645static const struct clksel_rate vlynq_fck_core_rates[] = {
1646 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1647 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1648 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1649 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1650 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1651 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1652 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1653 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1654 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1655 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1656 { .div = 0 }
1657};
1658
1659static const struct clksel vlynq_fck_clksel[] = {
1660 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1661 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1662 { .parent = NULL }
1663};
1664
1665static struct clk vlynq_fck = {
1666 .name = "vlynq_fck",
1667 .ops = &clkops_omap2_dflt_wait,
1668 .parent = &func_96m_ck,
1669 .clkdm_name = "core_l3_clkdm",
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1672 .init = &omap2_init_clksel_parent,
1673 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1674 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1675 .clksel = vlynq_fck_clksel,
1676 .recalc = &omap2_clksel_recalc,
1677};
1678
1679static struct clk des_ick = {
1680 .name = "des_ick",
1681 .ops = &clkops_omap2_iclk_dflt_wait,
1682 .parent = &l4_ck,
1683 .clkdm_name = "core_l4_clkdm",
1684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1685 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1686 .recalc = &followparent_recalc,
1687};
1688
1689static struct clk sha_ick = {
1690 .name = "sha_ick",
1691 .ops = &clkops_omap2_iclk_dflt_wait,
1692 .parent = &l4_ck,
1693 .clkdm_name = "core_l4_clkdm",
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1695 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1696 .recalc = &followparent_recalc,
1697};
1698
1699static struct clk rng_ick = {
1700 .name = "rng_ick",
1701 .ops = &clkops_omap2_iclk_dflt_wait,
1702 .parent = &l4_ck,
1703 .clkdm_name = "core_l4_clkdm",
1704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1705 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1706 .recalc = &followparent_recalc,
1707};
1708
1709static struct clk aes_ick = {
1710 .name = "aes_ick",
1711 .ops = &clkops_omap2_iclk_dflt_wait,
1712 .parent = &l4_ck,
1713 .clkdm_name = "core_l4_clkdm",
1714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1715 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1716 .recalc = &followparent_recalc,
1717};
1718
1719static struct clk pka_ick = {
1720 .name = "pka_ick",
1721 .ops = &clkops_omap2_iclk_dflt_wait,
1722 .parent = &l4_ck,
1723 .clkdm_name = "core_l4_clkdm",
1724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1725 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1726 .recalc = &followparent_recalc,
1727};
1728
1729static struct clk usb_fck = {
1730 .name = "usb_fck",
1731 .ops = &clkops_omap2_dflt_wait,
1732 .parent = &func_48m_ck,
1733 .clkdm_name = "core_l3_clkdm",
1734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1735 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1736 .recalc = &followparent_recalc,
1737};
1738
1739/*
1740 * This clock is a composite clock which does entire set changes then
1741 * forces a rebalance. It keys on the MPU speed, but it really could
1742 * be any key speed part of a set in the rate table.
1743 *
1744 * to really change a set, you need memory table sets which get changed
1745 * in sram, pre-notifiers & post notifiers, changing the top set, without
1746 * having low level display recalc's won't work... this is why dpm notifiers
1747 * work, isr's off, walk a list of clocks already _off_ and not messing with
1748 * the bus.
1749 *
1750 * This clock should have no parent. It embodies the entire upper level
1751 * active set. A parent will mess up some of the init also.
1752 */
1753static struct clk virt_prcm_set = {
1754 .name = "virt_prcm_set",
1755 .ops = &clkops_null,
1756 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1757 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1758 .set_rate = &omap2_select_table_rate,
1759 .round_rate = &omap2_round_to_table_rate,
1760};
1761
1762
1763/*
1764 * clkdev integration
1765 */
1766
1767static struct omap_clk omap2420_clks[] = {
1768 /* external root sources */
1769 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1770 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1771 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1772 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1773 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1774 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
1775 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
1776 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1777 /* internal analog sources */
1778 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1779 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1780 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1781 /* internal prcm root sources */
1782 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1783 CLK(NULL, "core_ck", &core_ck, CK_242X),
1784 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
1785 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
1786 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1787 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1788 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1789 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1790 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1791 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1792 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1793 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1794 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1795 /* mpu domain clocks */
1796 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1797 /* dsp domain clocks */
1798 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1799 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1800 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1801 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1802 /* GFX domain clocks */
1803 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1804 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1805 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1806 /* DSS domain clocks */
1807 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1808 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1809 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1810 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1811 /* L3 domain clocks */
1812 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1813 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1814 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1815 /* L4 domain clocks */
1816 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1817 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1818 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1819 /* virtual meta-group clock */
1820 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1821 /* general l4 interface ck, multi-parent functional clk */
1822 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1823 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1824 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1825 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1826 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1827 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1828 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1829 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1830 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1831 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1832 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1833 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1834 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1835 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1836 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1837 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1838 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1839 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1840 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1841 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1842 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1843 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1847 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1848 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1849 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1850 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1851 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1852 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1853 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1854 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1855 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1856 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1857 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1858 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1859 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1860 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1861 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1862 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1863 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1864 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1865 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1866 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1867 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1868 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1869 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1870 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1871 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1872 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1873 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1874 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1875 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1876 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1877 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1878 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1879 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1880 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1881 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1882 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1883 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1884 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1885 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1886 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1887 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1888 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1889 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1890 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1891 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1892 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1893 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1894 CLK(NULL, "des_ick", &des_ick, CK_242X),
1895 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1896 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1897 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1898 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1899 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1900 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1901};
1902
1903/*
1904 * init code
1905 */
1906
1907int __init omap2420_clk_init(void)
1908{
1909 const struct prcm_config *prcm;
1910 struct omap_clk *c;
1911 u32 clkrate;
1912
1913 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1914 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1915 cpu_mask = RATE_IN_242X;
1916 rate_table = omap2420_rate_table;
1917
1918 clk_init(&omap2_clk_functions);
1919
1920 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1921 c++)
1922 clk_preinit(c->lk.clk);
1923
1924 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1925 propagate_rate(&osc_ck);
1926 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1927 propagate_rate(&sys_ck);
1928
1929 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1930 c++) {
1931 clkdev_add(&c->lk);
1932 clk_register(c->lk.clk);
1933 omap2_init_clk_clkdm(c->lk.clk);
1934 }
1935
1936 /* Disable autoidle on all clocks; let the PM code enable it later */
1937 omap_clk_disable_autoidle_all();
1938
1939 /* Check the MPU rate set by bootloader */
1940 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1941 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1942 if (!(prcm->flags & cpu_mask))
1943 continue;
1944 if (prcm->xtal_speed != sys_ck.rate)
1945 continue;
1946 if (prcm->dpll_speed <= clkrate)
1947 break;
1948 }
1949 curr_prcm_set = prcm;
1950
1951 recalculate_root_clocks();
1952
1953 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1954 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1955 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1956
1957 /*
1958 * Only enable those clocks we will need, let the drivers
1959 * enable other clocks as necessary
1960 */
1961 clk_enable_init_clocks();
1962
1963 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1964 vclk = clk_get(NULL, "virt_prcm_set");
1965 sclk = clk_get(NULL, "sys_ck");
1966 dclk = clk_get(NULL, "dpll_ck");
1967
1968 return 0;
1969}
1970
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
new file mode 100644
index 00000000000..96a942e42db
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -0,0 +1,2070 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/clkdev_omap.h>
21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx_3xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
33
34/*
35 * 2430 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56 .clkdm_name = "wkup_clkdm",
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .clkdm_name = "wkup_clkdm",
64};
65
66/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
69 .ops = &clkops_oscck,
70 .clkdm_name = "wkup_clkdm",
71 .recalc = &omap2_osc_clk_recalc,
72};
73
74/* Without modem likely 12MHz, with modem likely 13MHz */
75static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
77 .ops = &clkops_null,
78 .parent = &osc_ck,
79 .clkdm_name = "wkup_clkdm",
80 .recalc = &omap2xxx_sys_clk_recalc,
81};
82
83static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
85 .ops = &clkops_null,
86 .rate = 54000000,
87 .clkdm_name = "wkup_clkdm",
88};
89
90/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
96/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
105static struct dpll_data dpll_dd = {
106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
113 .max_multiplier = 1023,
114 .min_divider = 1,
115 .max_divider = 16,
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_omap2xxx_dpll_ops,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .dpll_data = &dpll_dd,
127 .clkdm_name = "wkup_clkdm",
128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
134 .ops = &clkops_apll96,
135 .parent = &sys_ck,
136 .rate = 96000000,
137 .flags = ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
145 .ops = &clkops_apll54,
146 .parent = &sys_ck,
147 .rate = 54000000,
148 .flags = ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
152};
153
154/*
155 * PRCM digital base sources
156 */
157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
161 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
178 .ops = &clkops_null,
179 .parent = &apll54_ck, /* can also be alt_clk */
180 .clkdm_name = "wkup_clkdm",
181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
183 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
186};
187
188static struct clk core_ck = {
189 .name = "core_ck",
190 .ops = &clkops_null,
191 .parent = &dpll_ck, /* can also be 32k */
192 .clkdm_name = "wkup_clkdm",
193 .recalc = &followparent_recalc,
194};
195
196/* func_96m_ck */
197static const struct clksel_rate func_96m_apll96_rates[] = {
198 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
199 { .div = 0 },
200};
201
202static const struct clksel_rate func_96m_alt_rates[] = {
203 { .div = 1, .val = 1, .flags = RATE_IN_243X },
204 { .div = 0 },
205};
206
207static const struct clksel func_96m_clksel[] = {
208 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
209 { .parent = &alt_ck, .rates = func_96m_alt_rates },
210 { .parent = NULL }
211};
212
213static struct clk func_96m_ck = {
214 .name = "func_96m_ck",
215 .ops = &clkops_null,
216 .parent = &apll96_ck,
217 .clkdm_name = "wkup_clkdm",
218 .init = &omap2_init_clksel_parent,
219 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
220 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
221 .clksel = func_96m_clksel,
222 .recalc = &omap2_clksel_recalc,
223};
224
225/* func_48m_ck */
226
227static const struct clksel_rate func_48m_apll96_rates[] = {
228 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
229 { .div = 0 },
230};
231
232static const struct clksel_rate func_48m_alt_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
234 { .div = 0 },
235};
236
237static const struct clksel func_48m_clksel[] = {
238 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
239 { .parent = &alt_ck, .rates = func_48m_alt_rates },
240 { .parent = NULL }
241};
242
243static struct clk func_48m_ck = {
244 .name = "func_48m_ck",
245 .ops = &clkops_null,
246 .parent = &apll96_ck, /* 96M or Alt */
247 .clkdm_name = "wkup_clkdm",
248 .init = &omap2_init_clksel_parent,
249 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
250 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
251 .clksel = func_48m_clksel,
252 .recalc = &omap2_clksel_recalc,
253 .round_rate = &omap2_clksel_round_rate,
254 .set_rate = &omap2_clksel_set_rate
255};
256
257static struct clk func_12m_ck = {
258 .name = "func_12m_ck",
259 .ops = &clkops_null,
260 .parent = &func_48m_ck,
261 .fixed_div = 4,
262 .clkdm_name = "wkup_clkdm",
263 .recalc = &omap_fixed_divisor_recalc,
264};
265
266/* Secure timer, only available in secure mode */
267static struct clk wdt1_osc_ck = {
268 .name = "ck_wdt1_osc",
269 .ops = &clkops_null, /* RMK: missing? */
270 .parent = &osc_ck,
271 .recalc = &followparent_recalc,
272};
273
274/*
275 * The common_clkout* clksel_rate structs are common to
276 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
277 * sys_clkout2_* are 2420-only, so the
278 * clksel_rate flags fields are inaccurate for those clocks. This is
279 * harmless since access to those clocks are gated by the struct clk
280 * flags fields, which mark them as 2420-only.
281 */
282static const struct clksel_rate common_clkout_src_core_rates[] = {
283 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
284 { .div = 0 }
285};
286
287static const struct clksel_rate common_clkout_src_sys_rates[] = {
288 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
289 { .div = 0 }
290};
291
292static const struct clksel_rate common_clkout_src_96m_rates[] = {
293 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
294 { .div = 0 }
295};
296
297static const struct clksel_rate common_clkout_src_54m_rates[] = {
298 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
299 { .div = 0 }
300};
301
302static const struct clksel common_clkout_src_clksel[] = {
303 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
304 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
305 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
306 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
307 { .parent = NULL }
308};
309
310static struct clk sys_clkout_src = {
311 .name = "sys_clkout_src",
312 .ops = &clkops_omap2_dflt,
313 .parent = &func_54m_ck,
314 .clkdm_name = "wkup_clkdm",
315 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
316 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
317 .init = &omap2_init_clksel_parent,
318 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
319 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
320 .clksel = common_clkout_src_clksel,
321 .recalc = &omap2_clksel_recalc,
322 .round_rate = &omap2_clksel_round_rate,
323 .set_rate = &omap2_clksel_set_rate
324};
325
326static const struct clksel_rate common_clkout_rates[] = {
327 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
328 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
329 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
330 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
331 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
332 { .div = 0 },
333};
334
335static const struct clksel sys_clkout_clksel[] = {
336 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
337 { .parent = NULL }
338};
339
340static struct clk sys_clkout = {
341 .name = "sys_clkout",
342 .ops = &clkops_null,
343 .parent = &sys_clkout_src,
344 .clkdm_name = "wkup_clkdm",
345 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
346 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
347 .clksel = sys_clkout_clksel,
348 .recalc = &omap2_clksel_recalc,
349 .round_rate = &omap2_clksel_round_rate,
350 .set_rate = &omap2_clksel_set_rate
351};
352
353static struct clk emul_ck = {
354 .name = "emul_ck",
355 .ops = &clkops_omap2_dflt,
356 .parent = &func_54m_ck,
357 .clkdm_name = "wkup_clkdm",
358 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
359 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
360 .recalc = &followparent_recalc,
361
362};
363
364/*
365 * MPU clock domain
366 * Clocks:
367 * MPU_FCLK, MPU_ICLK
368 * INT_M_FCLK, INT_M_I_CLK
369 *
370 * - Individual clocks are hardware managed.
371 * - Base divider comes from: CM_CLKSEL_MPU
372 *
373 */
374static const struct clksel_rate mpu_core_rates[] = {
375 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
376 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
377 { .div = 0 },
378};
379
380static const struct clksel mpu_clksel[] = {
381 { .parent = &core_ck, .rates = mpu_core_rates },
382 { .parent = NULL }
383};
384
385static struct clk mpu_ck = { /* Control cpu */
386 .name = "mpu_ck",
387 .ops = &clkops_null,
388 .parent = &core_ck,
389 .clkdm_name = "mpu_clkdm",
390 .init = &omap2_init_clksel_parent,
391 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
392 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
393 .clksel = mpu_clksel,
394 .recalc = &omap2_clksel_recalc,
395};
396
397/*
398 * DSP (2430-IVA2.1) clock domain
399 * Clocks:
400 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
401 *
402 * Won't be too specific here. The core clock comes into this block
403 * it is divided then tee'ed. One branch goes directly to xyz enable
404 * controls. The other branch gets further divided by 2 then possibly
405 * routed into a synchronizer and out of clocks abc.
406 */
407static const struct clksel_rate dsp_fck_core_rates[] = {
408 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
409 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
410 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
411 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
412 { .div = 0 },
413};
414
415static const struct clksel dsp_fck_clksel[] = {
416 { .parent = &core_ck, .rates = dsp_fck_core_rates },
417 { .parent = NULL }
418};
419
420static struct clk dsp_fck = {
421 .name = "dsp_fck",
422 .ops = &clkops_omap2_dflt_wait,
423 .parent = &core_ck,
424 .clkdm_name = "dsp_clkdm",
425 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
426 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
427 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
428 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
429 .clksel = dsp_fck_clksel,
430 .recalc = &omap2_clksel_recalc,
431};
432
433static const struct clksel dsp_ick_clksel[] = {
434 { .parent = &dsp_fck, .rates = dsp_ick_rates },
435 { .parent = NULL }
436};
437
438/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
439static struct clk iva2_1_ick = {
440 .name = "iva2_1_ick",
441 .ops = &clkops_omap2_dflt_wait,
442 .parent = &dsp_fck,
443 .clkdm_name = "dsp_clkdm",
444 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
445 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
446 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
447 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
448 .clksel = dsp_ick_clksel,
449 .recalc = &omap2_clksel_recalc,
450};
451
452/*
453 * L3 clock domain
454 * L3 clocks are used for both interface and functional clocks to
455 * multiple entities. Some of these clocks are completely managed
456 * by hardware, and some others allow software control. Hardware
457 * managed ones general are based on directly CLK_REQ signals and
458 * various auto idle settings. The functional spec sets many of these
459 * as 'tie-high' for their enables.
460 *
461 * I-CLOCKS:
462 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
463 * CAM, HS-USB.
464 * F-CLOCK
465 * SSI.
466 *
467 * GPMC memories and SDRC have timing and clock sensitive registers which
468 * may very well need notification when the clock changes. Currently for low
469 * operating points, these are taken care of in sleep.S.
470 */
471static const struct clksel_rate core_l3_core_rates[] = {
472 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
473 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
474 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
475 { .div = 0 }
476};
477
478static const struct clksel core_l3_clksel[] = {
479 { .parent = &core_ck, .rates = core_l3_core_rates },
480 { .parent = NULL }
481};
482
483static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
484 .name = "core_l3_ck",
485 .ops = &clkops_null,
486 .parent = &core_ck,
487 .clkdm_name = "core_l3_clkdm",
488 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
489 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
490 .clksel = core_l3_clksel,
491 .recalc = &omap2_clksel_recalc,
492};
493
494/* usb_l4_ick */
495static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
496 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
497 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
498 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
499 { .div = 0 }
500};
501
502static const struct clksel usb_l4_ick_clksel[] = {
503 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
504 { .parent = NULL },
505};
506
507/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
508static struct clk usb_l4_ick = { /* FS-USB interface clock */
509 .name = "usb_l4_ick",
510 .ops = &clkops_omap2_iclk_dflt_wait,
511 .parent = &core_l3_ck,
512 .clkdm_name = "core_l4_clkdm",
513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
514 .enable_bit = OMAP24XX_EN_USB_SHIFT,
515 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
516 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
517 .clksel = usb_l4_ick_clksel,
518 .recalc = &omap2_clksel_recalc,
519};
520
521/*
522 * L4 clock management domain
523 *
524 * This domain contains lots of interface clocks from the L4 interface, some
525 * functional clocks. Fixed APLL functional source clocks are managed in
526 * this domain.
527 */
528static const struct clksel_rate l4_core_l3_rates[] = {
529 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
530 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
531 { .div = 0 }
532};
533
534static const struct clksel l4_clksel[] = {
535 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
536 { .parent = NULL }
537};
538
539static struct clk l4_ck = { /* used both as an ick and fck */
540 .name = "l4_ck",
541 .ops = &clkops_null,
542 .parent = &core_l3_ck,
543 .clkdm_name = "core_l4_clkdm",
544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
545 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
546 .clksel = l4_clksel,
547 .recalc = &omap2_clksel_recalc,
548};
549
550/*
551 * SSI is in L3 management domain, its direct parent is core not l3,
552 * many core power domain entities are grouped into the L3 clock
553 * domain.
554 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
555 *
556 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
557 */
558static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
559 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
560 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
561 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
562 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
563 { .div = 5, .val = 5, .flags = RATE_IN_243X },
564 { .div = 0 }
565};
566
567static const struct clksel ssi_ssr_sst_fck_clksel[] = {
568 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
569 { .parent = NULL }
570};
571
572static struct clk ssi_ssr_sst_fck = {
573 .name = "ssi_fck",
574 .ops = &clkops_omap2_dflt_wait,
575 .parent = &core_ck,
576 .clkdm_name = "core_l3_clkdm",
577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
578 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
579 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
580 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
581 .clksel = ssi_ssr_sst_fck_clksel,
582 .recalc = &omap2_clksel_recalc,
583};
584
585/*
586 * Presumably this is the same as SSI_ICLK.
587 * TRM contradicts itself on what clockdomain SSI_ICLK is in
588 */
589static struct clk ssi_l4_ick = {
590 .name = "ssi_l4_ick",
591 .ops = &clkops_omap2_iclk_dflt_wait,
592 .parent = &l4_ck,
593 .clkdm_name = "core_l4_clkdm",
594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
595 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
596 .recalc = &followparent_recalc,
597};
598
599
600/*
601 * GFX clock domain
602 * Clocks:
603 * GFX_FCLK, GFX_ICLK
604 * GFX_CG1(2d), GFX_CG2(3d)
605 *
606 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
607 * The 2d and 3d clocks run at a hardware determined
608 * divided value of fclk.
609 *
610 */
611
612/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
613static const struct clksel gfx_fck_clksel[] = {
614 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
615 { .parent = NULL },
616};
617
618static struct clk gfx_3d_fck = {
619 .name = "gfx_3d_fck",
620 .ops = &clkops_omap2_dflt_wait,
621 .parent = &core_l3_ck,
622 .clkdm_name = "gfx_clkdm",
623 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
624 .enable_bit = OMAP24XX_EN_3D_SHIFT,
625 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
627 .clksel = gfx_fck_clksel,
628 .recalc = &omap2_clksel_recalc,
629 .round_rate = &omap2_clksel_round_rate,
630 .set_rate = &omap2_clksel_set_rate
631};
632
633static struct clk gfx_2d_fck = {
634 .name = "gfx_2d_fck",
635 .ops = &clkops_omap2_dflt_wait,
636 .parent = &core_l3_ck,
637 .clkdm_name = "gfx_clkdm",
638 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
639 .enable_bit = OMAP24XX_EN_2D_SHIFT,
640 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
641 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
642 .clksel = gfx_fck_clksel,
643 .recalc = &omap2_clksel_recalc,
644};
645
646/* This interface clock does not have a CM_AUTOIDLE bit */
647static struct clk gfx_ick = {
648 .name = "gfx_ick", /* From l3 */
649 .ops = &clkops_omap2_dflt_wait,
650 .parent = &core_l3_ck,
651 .clkdm_name = "gfx_clkdm",
652 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
653 .enable_bit = OMAP_EN_GFX_SHIFT,
654 .recalc = &followparent_recalc,
655};
656
657/*
658 * Modem clock domain (2430)
659 * CLOCKS:
660 * MDM_OSC_CLK
661 * MDM_ICLK
662 * These clocks are usable in chassis mode only.
663 */
664static const struct clksel_rate mdm_ick_core_rates[] = {
665 { .div = 1, .val = 1, .flags = RATE_IN_243X },
666 { .div = 4, .val = 4, .flags = RATE_IN_243X },
667 { .div = 6, .val = 6, .flags = RATE_IN_243X },
668 { .div = 9, .val = 9, .flags = RATE_IN_243X },
669 { .div = 0 }
670};
671
672static const struct clksel mdm_ick_clksel[] = {
673 { .parent = &core_ck, .rates = mdm_ick_core_rates },
674 { .parent = NULL }
675};
676
677static struct clk mdm_ick = { /* used both as a ick and fck */
678 .name = "mdm_ick",
679 .ops = &clkops_omap2_iclk_dflt_wait,
680 .parent = &core_ck,
681 .clkdm_name = "mdm_clkdm",
682 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
683 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
684 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
685 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
686 .clksel = mdm_ick_clksel,
687 .recalc = &omap2_clksel_recalc,
688};
689
690static struct clk mdm_osc_ck = {
691 .name = "mdm_osc_ck",
692 .ops = &clkops_omap2_mdmclk_dflt_wait,
693 .parent = &osc_ck,
694 .clkdm_name = "mdm_clkdm",
695 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
696 .enable_bit = OMAP2430_EN_OSC_SHIFT,
697 .recalc = &followparent_recalc,
698};
699
700/*
701 * DSS clock domain
702 * CLOCKs:
703 * DSS_L4_ICLK, DSS_L3_ICLK,
704 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
705 *
706 * DSS is both initiator and target.
707 */
708/* XXX Add RATE_NOT_VALIDATED */
709
710static const struct clksel_rate dss1_fck_sys_rates[] = {
711 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
712 { .div = 0 }
713};
714
715static const struct clksel_rate dss1_fck_core_rates[] = {
716 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
717 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
718 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
719 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
720 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
721 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
722 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
723 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
724 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
725 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
726 { .div = 0 }
727};
728
729static const struct clksel dss1_fck_clksel[] = {
730 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
731 { .parent = &core_ck, .rates = dss1_fck_core_rates },
732 { .parent = NULL },
733};
734
735static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
736 .name = "dss_ick",
737 .ops = &clkops_omap2_iclk_dflt,
738 .parent = &l4_ck, /* really both l3 and l4 */
739 .clkdm_name = "dss_clkdm",
740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
741 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
742 .recalc = &followparent_recalc,
743};
744
745static struct clk dss1_fck = {
746 .name = "dss1_fck",
747 .ops = &clkops_omap2_dflt,
748 .parent = &core_ck, /* Core or sys */
749 .clkdm_name = "dss_clkdm",
750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
751 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
754 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
755 .clksel = dss1_fck_clksel,
756 .recalc = &omap2_clksel_recalc,
757};
758
759static const struct clksel_rate dss2_fck_sys_rates[] = {
760 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
761 { .div = 0 }
762};
763
764static const struct clksel_rate dss2_fck_48m_rates[] = {
765 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
766 { .div = 0 }
767};
768
769static const struct clksel dss2_fck_clksel[] = {
770 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
771 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
772 { .parent = NULL }
773};
774
775static struct clk dss2_fck = { /* Alt clk used in power management */
776 .name = "dss2_fck",
777 .ops = &clkops_omap2_dflt,
778 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
779 .clkdm_name = "dss_clkdm",
780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
781 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
782 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
785 .clksel = dss2_fck_clksel,
786 .recalc = &omap2_clksel_recalc,
787};
788
789static struct clk dss_54m_fck = { /* Alt clk used in power management */
790 .name = "dss_54m_fck", /* 54m tv clk */
791 .ops = &clkops_omap2_dflt_wait,
792 .parent = &func_54m_ck,
793 .clkdm_name = "dss_clkdm",
794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 .enable_bit = OMAP24XX_EN_TV_SHIFT,
796 .recalc = &followparent_recalc,
797};
798
799static struct clk wu_l4_ick = {
800 .name = "wu_l4_ick",
801 .ops = &clkops_null,
802 .parent = &sys_ck,
803 .clkdm_name = "wkup_clkdm",
804 .recalc = &followparent_recalc,
805};
806
807/*
808 * CORE power domain ICLK & FCLK defines.
809 * Many of the these can have more than one possible parent. Entries
810 * here will likely have an L4 interface parent, and may have multiple
811 * functional clock parents.
812 */
813static const struct clksel_rate gpt_alt_rates[] = {
814 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
815 { .div = 0 }
816};
817
818static const struct clksel omap24xx_gpt_clksel[] = {
819 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
820 { .parent = &sys_ck, .rates = gpt_sys_rates },
821 { .parent = &alt_ck, .rates = gpt_alt_rates },
822 { .parent = NULL },
823};
824
825static struct clk gpt1_ick = {
826 .name = "gpt1_ick",
827 .ops = &clkops_omap2_iclk_dflt_wait,
828 .parent = &wu_l4_ick,
829 .clkdm_name = "wkup_clkdm",
830 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
831 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
832 .recalc = &followparent_recalc,
833};
834
835static struct clk gpt1_fck = {
836 .name = "gpt1_fck",
837 .ops = &clkops_omap2_dflt_wait,
838 .parent = &func_32k_ck,
839 .clkdm_name = "core_l4_clkdm",
840 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
841 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
842 .init = &omap2_init_clksel_parent,
843 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
844 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
845 .clksel = omap24xx_gpt_clksel,
846 .recalc = &omap2_clksel_recalc,
847 .round_rate = &omap2_clksel_round_rate,
848 .set_rate = &omap2_clksel_set_rate
849};
850
851static struct clk gpt2_ick = {
852 .name = "gpt2_ick",
853 .ops = &clkops_omap2_iclk_dflt_wait,
854 .parent = &l4_ck,
855 .clkdm_name = "core_l4_clkdm",
856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
857 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
858 .recalc = &followparent_recalc,
859};
860
861static struct clk gpt2_fck = {
862 .name = "gpt2_fck",
863 .ops = &clkops_omap2_dflt_wait,
864 .parent = &func_32k_ck,
865 .clkdm_name = "core_l4_clkdm",
866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
867 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
868 .init = &omap2_init_clksel_parent,
869 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
870 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
871 .clksel = omap24xx_gpt_clksel,
872 .recalc = &omap2_clksel_recalc,
873};
874
875static struct clk gpt3_ick = {
876 .name = "gpt3_ick",
877 .ops = &clkops_omap2_iclk_dflt_wait,
878 .parent = &l4_ck,
879 .clkdm_name = "core_l4_clkdm",
880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
881 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
882 .recalc = &followparent_recalc,
883};
884
885static struct clk gpt3_fck = {
886 .name = "gpt3_fck",
887 .ops = &clkops_omap2_dflt_wait,
888 .parent = &func_32k_ck,
889 .clkdm_name = "core_l4_clkdm",
890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
891 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
892 .init = &omap2_init_clksel_parent,
893 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
894 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
895 .clksel = omap24xx_gpt_clksel,
896 .recalc = &omap2_clksel_recalc,
897};
898
899static struct clk gpt4_ick = {
900 .name = "gpt4_ick",
901 .ops = &clkops_omap2_iclk_dflt_wait,
902 .parent = &l4_ck,
903 .clkdm_name = "core_l4_clkdm",
904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
905 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
906 .recalc = &followparent_recalc,
907};
908
909static struct clk gpt4_fck = {
910 .name = "gpt4_fck",
911 .ops = &clkops_omap2_dflt_wait,
912 .parent = &func_32k_ck,
913 .clkdm_name = "core_l4_clkdm",
914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
915 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
916 .init = &omap2_init_clksel_parent,
917 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
918 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
919 .clksel = omap24xx_gpt_clksel,
920 .recalc = &omap2_clksel_recalc,
921};
922
923static struct clk gpt5_ick = {
924 .name = "gpt5_ick",
925 .ops = &clkops_omap2_iclk_dflt_wait,
926 .parent = &l4_ck,
927 .clkdm_name = "core_l4_clkdm",
928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
929 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
930 .recalc = &followparent_recalc,
931};
932
933static struct clk gpt5_fck = {
934 .name = "gpt5_fck",
935 .ops = &clkops_omap2_dflt_wait,
936 .parent = &func_32k_ck,
937 .clkdm_name = "core_l4_clkdm",
938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
939 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
940 .init = &omap2_init_clksel_parent,
941 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
942 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
943 .clksel = omap24xx_gpt_clksel,
944 .recalc = &omap2_clksel_recalc,
945};
946
947static struct clk gpt6_ick = {
948 .name = "gpt6_ick",
949 .ops = &clkops_omap2_iclk_dflt_wait,
950 .parent = &l4_ck,
951 .clkdm_name = "core_l4_clkdm",
952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
953 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
954 .recalc = &followparent_recalc,
955};
956
957static struct clk gpt6_fck = {
958 .name = "gpt6_fck",
959 .ops = &clkops_omap2_dflt_wait,
960 .parent = &func_32k_ck,
961 .clkdm_name = "core_l4_clkdm",
962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
963 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
964 .init = &omap2_init_clksel_parent,
965 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
966 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
967 .clksel = omap24xx_gpt_clksel,
968 .recalc = &omap2_clksel_recalc,
969};
970
971static struct clk gpt7_ick = {
972 .name = "gpt7_ick",
973 .ops = &clkops_omap2_iclk_dflt_wait,
974 .parent = &l4_ck,
975 .clkdm_name = "core_l4_clkdm",
976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
977 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
978 .recalc = &followparent_recalc,
979};
980
981static struct clk gpt7_fck = {
982 .name = "gpt7_fck",
983 .ops = &clkops_omap2_dflt_wait,
984 .parent = &func_32k_ck,
985 .clkdm_name = "core_l4_clkdm",
986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
987 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
988 .init = &omap2_init_clksel_parent,
989 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
990 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
991 .clksel = omap24xx_gpt_clksel,
992 .recalc = &omap2_clksel_recalc,
993};
994
995static struct clk gpt8_ick = {
996 .name = "gpt8_ick",
997 .ops = &clkops_omap2_iclk_dflt_wait,
998 .parent = &l4_ck,
999 .clkdm_name = "core_l4_clkdm",
1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1001 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1002 .recalc = &followparent_recalc,
1003};
1004
1005static struct clk gpt8_fck = {
1006 .name = "gpt8_fck",
1007 .ops = &clkops_omap2_dflt_wait,
1008 .parent = &func_32k_ck,
1009 .clkdm_name = "core_l4_clkdm",
1010 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1011 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1012 .init = &omap2_init_clksel_parent,
1013 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1014 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1015 .clksel = omap24xx_gpt_clksel,
1016 .recalc = &omap2_clksel_recalc,
1017};
1018
1019static struct clk gpt9_ick = {
1020 .name = "gpt9_ick",
1021 .ops = &clkops_omap2_iclk_dflt_wait,
1022 .parent = &l4_ck,
1023 .clkdm_name = "core_l4_clkdm",
1024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1025 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1026 .recalc = &followparent_recalc,
1027};
1028
1029static struct clk gpt9_fck = {
1030 .name = "gpt9_fck",
1031 .ops = &clkops_omap2_dflt_wait,
1032 .parent = &func_32k_ck,
1033 .clkdm_name = "core_l4_clkdm",
1034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1035 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1036 .init = &omap2_init_clksel_parent,
1037 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1038 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1039 .clksel = omap24xx_gpt_clksel,
1040 .recalc = &omap2_clksel_recalc,
1041};
1042
1043static struct clk gpt10_ick = {
1044 .name = "gpt10_ick",
1045 .ops = &clkops_omap2_iclk_dflt_wait,
1046 .parent = &l4_ck,
1047 .clkdm_name = "core_l4_clkdm",
1048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1049 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1050 .recalc = &followparent_recalc,
1051};
1052
1053static struct clk gpt10_fck = {
1054 .name = "gpt10_fck",
1055 .ops = &clkops_omap2_dflt_wait,
1056 .parent = &func_32k_ck,
1057 .clkdm_name = "core_l4_clkdm",
1058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1059 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1060 .init = &omap2_init_clksel_parent,
1061 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1062 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1063 .clksel = omap24xx_gpt_clksel,
1064 .recalc = &omap2_clksel_recalc,
1065};
1066
1067static struct clk gpt11_ick = {
1068 .name = "gpt11_ick",
1069 .ops = &clkops_omap2_iclk_dflt_wait,
1070 .parent = &l4_ck,
1071 .clkdm_name = "core_l4_clkdm",
1072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1073 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1074 .recalc = &followparent_recalc,
1075};
1076
1077static struct clk gpt11_fck = {
1078 .name = "gpt11_fck",
1079 .ops = &clkops_omap2_dflt_wait,
1080 .parent = &func_32k_ck,
1081 .clkdm_name = "core_l4_clkdm",
1082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1083 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1084 .init = &omap2_init_clksel_parent,
1085 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1086 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1087 .clksel = omap24xx_gpt_clksel,
1088 .recalc = &omap2_clksel_recalc,
1089};
1090
1091static struct clk gpt12_ick = {
1092 .name = "gpt12_ick",
1093 .ops = &clkops_omap2_iclk_dflt_wait,
1094 .parent = &l4_ck,
1095 .clkdm_name = "core_l4_clkdm",
1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1097 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1098 .recalc = &followparent_recalc,
1099};
1100
1101static struct clk gpt12_fck = {
1102 .name = "gpt12_fck",
1103 .ops = &clkops_omap2_dflt_wait,
1104 .parent = &secure_32k_ck,
1105 .clkdm_name = "core_l4_clkdm",
1106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1107 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1108 .init = &omap2_init_clksel_parent,
1109 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1110 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1111 .clksel = omap24xx_gpt_clksel,
1112 .recalc = &omap2_clksel_recalc,
1113};
1114
1115static struct clk mcbsp1_ick = {
1116 .name = "mcbsp1_ick",
1117 .ops = &clkops_omap2_iclk_dflt_wait,
1118 .parent = &l4_ck,
1119 .clkdm_name = "core_l4_clkdm",
1120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1121 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1122 .recalc = &followparent_recalc,
1123};
1124
1125static const struct clksel_rate common_mcbsp_96m_rates[] = {
1126 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1127 { .div = 0 }
1128};
1129
1130static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1132 { .div = 0 }
1133};
1134
1135static const struct clksel mcbsp_fck_clksel[] = {
1136 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1137 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1138 { .parent = NULL }
1139};
1140
1141static struct clk mcbsp1_fck = {
1142 .name = "mcbsp1_fck",
1143 .ops = &clkops_omap2_dflt_wait,
1144 .parent = &func_96m_ck,
1145 .init = &omap2_init_clksel_parent,
1146 .clkdm_name = "core_l4_clkdm",
1147 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1148 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1149 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1150 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1151 .clksel = mcbsp_fck_clksel,
1152 .recalc = &omap2_clksel_recalc,
1153};
1154
1155static struct clk mcbsp2_ick = {
1156 .name = "mcbsp2_ick",
1157 .ops = &clkops_omap2_iclk_dflt_wait,
1158 .parent = &l4_ck,
1159 .clkdm_name = "core_l4_clkdm",
1160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1161 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1162 .recalc = &followparent_recalc,
1163};
1164
1165static struct clk mcbsp2_fck = {
1166 .name = "mcbsp2_fck",
1167 .ops = &clkops_omap2_dflt_wait,
1168 .parent = &func_96m_ck,
1169 .init = &omap2_init_clksel_parent,
1170 .clkdm_name = "core_l4_clkdm",
1171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1172 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1173 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1174 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1175 .clksel = mcbsp_fck_clksel,
1176 .recalc = &omap2_clksel_recalc,
1177};
1178
1179static struct clk mcbsp3_ick = {
1180 .name = "mcbsp3_ick",
1181 .ops = &clkops_omap2_iclk_dflt_wait,
1182 .parent = &l4_ck,
1183 .clkdm_name = "core_l4_clkdm",
1184 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1185 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1186 .recalc = &followparent_recalc,
1187};
1188
1189static struct clk mcbsp3_fck = {
1190 .name = "mcbsp3_fck",
1191 .ops = &clkops_omap2_dflt_wait,
1192 .parent = &func_96m_ck,
1193 .init = &omap2_init_clksel_parent,
1194 .clkdm_name = "core_l4_clkdm",
1195 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1196 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1197 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1198 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1199 .clksel = mcbsp_fck_clksel,
1200 .recalc = &omap2_clksel_recalc,
1201};
1202
1203static struct clk mcbsp4_ick = {
1204 .name = "mcbsp4_ick",
1205 .ops = &clkops_omap2_iclk_dflt_wait,
1206 .parent = &l4_ck,
1207 .clkdm_name = "core_l4_clkdm",
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1209 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1210 .recalc = &followparent_recalc,
1211};
1212
1213static struct clk mcbsp4_fck = {
1214 .name = "mcbsp4_fck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &func_96m_ck,
1217 .init = &omap2_init_clksel_parent,
1218 .clkdm_name = "core_l4_clkdm",
1219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1220 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1221 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1222 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1223 .clksel = mcbsp_fck_clksel,
1224 .recalc = &omap2_clksel_recalc,
1225};
1226
1227static struct clk mcbsp5_ick = {
1228 .name = "mcbsp5_ick",
1229 .ops = &clkops_omap2_iclk_dflt_wait,
1230 .parent = &l4_ck,
1231 .clkdm_name = "core_l4_clkdm",
1232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1233 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1234 .recalc = &followparent_recalc,
1235};
1236
1237static struct clk mcbsp5_fck = {
1238 .name = "mcbsp5_fck",
1239 .ops = &clkops_omap2_dflt_wait,
1240 .parent = &func_96m_ck,
1241 .init = &omap2_init_clksel_parent,
1242 .clkdm_name = "core_l4_clkdm",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1244 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1245 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1246 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1247 .clksel = mcbsp_fck_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249};
1250
1251static struct clk mcspi1_ick = {
1252 .name = "mcspi1_ick",
1253 .ops = &clkops_omap2_iclk_dflt_wait,
1254 .parent = &l4_ck,
1255 .clkdm_name = "core_l4_clkdm",
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1258 .recalc = &followparent_recalc,
1259};
1260
1261static struct clk mcspi1_fck = {
1262 .name = "mcspi1_fck",
1263 .ops = &clkops_omap2_dflt_wait,
1264 .parent = &func_48m_ck,
1265 .clkdm_name = "core_l4_clkdm",
1266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1268 .recalc = &followparent_recalc,
1269};
1270
1271static struct clk mcspi2_ick = {
1272 .name = "mcspi2_ick",
1273 .ops = &clkops_omap2_iclk_dflt_wait,
1274 .parent = &l4_ck,
1275 .clkdm_name = "core_l4_clkdm",
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1277 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1278 .recalc = &followparent_recalc,
1279};
1280
1281static struct clk mcspi2_fck = {
1282 .name = "mcspi2_fck",
1283 .ops = &clkops_omap2_dflt_wait,
1284 .parent = &func_48m_ck,
1285 .clkdm_name = "core_l4_clkdm",
1286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1287 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1288 .recalc = &followparent_recalc,
1289};
1290
1291static struct clk mcspi3_ick = {
1292 .name = "mcspi3_ick",
1293 .ops = &clkops_omap2_iclk_dflt_wait,
1294 .parent = &l4_ck,
1295 .clkdm_name = "core_l4_clkdm",
1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1297 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1298 .recalc = &followparent_recalc,
1299};
1300
1301static struct clk mcspi3_fck = {
1302 .name = "mcspi3_fck",
1303 .ops = &clkops_omap2_dflt_wait,
1304 .parent = &func_48m_ck,
1305 .clkdm_name = "core_l4_clkdm",
1306 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1307 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static struct clk uart1_ick = {
1312 .name = "uart1_ick",
1313 .ops = &clkops_omap2_iclk_dflt_wait,
1314 .parent = &l4_ck,
1315 .clkdm_name = "core_l4_clkdm",
1316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1317 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1318 .recalc = &followparent_recalc,
1319};
1320
1321static struct clk uart1_fck = {
1322 .name = "uart1_fck",
1323 .ops = &clkops_omap2_dflt_wait,
1324 .parent = &func_48m_ck,
1325 .clkdm_name = "core_l4_clkdm",
1326 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1327 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1328 .recalc = &followparent_recalc,
1329};
1330
1331static struct clk uart2_ick = {
1332 .name = "uart2_ick",
1333 .ops = &clkops_omap2_iclk_dflt_wait,
1334 .parent = &l4_ck,
1335 .clkdm_name = "core_l4_clkdm",
1336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1337 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1338 .recalc = &followparent_recalc,
1339};
1340
1341static struct clk uart2_fck = {
1342 .name = "uart2_fck",
1343 .ops = &clkops_omap2_dflt_wait,
1344 .parent = &func_48m_ck,
1345 .clkdm_name = "core_l4_clkdm",
1346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1347 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1348 .recalc = &followparent_recalc,
1349};
1350
1351static struct clk uart3_ick = {
1352 .name = "uart3_ick",
1353 .ops = &clkops_omap2_iclk_dflt_wait,
1354 .parent = &l4_ck,
1355 .clkdm_name = "core_l4_clkdm",
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1357 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1358 .recalc = &followparent_recalc,
1359};
1360
1361static struct clk uart3_fck = {
1362 .name = "uart3_fck",
1363 .ops = &clkops_omap2_dflt_wait,
1364 .parent = &func_48m_ck,
1365 .clkdm_name = "core_l4_clkdm",
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1367 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk gpios_ick = {
1372 .name = "gpios_ick",
1373 .ops = &clkops_omap2_iclk_dflt_wait,
1374 .parent = &wu_l4_ick,
1375 .clkdm_name = "wkup_clkdm",
1376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1377 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk gpios_fck = {
1382 .name = "gpios_fck",
1383 .ops = &clkops_omap2_dflt_wait,
1384 .parent = &func_32k_ck,
1385 .clkdm_name = "wkup_clkdm",
1386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1387 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk mpu_wdt_ick = {
1392 .name = "mpu_wdt_ick",
1393 .ops = &clkops_omap2_iclk_dflt_wait,
1394 .parent = &wu_l4_ick,
1395 .clkdm_name = "wkup_clkdm",
1396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1397 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1398 .recalc = &followparent_recalc,
1399};
1400
1401static struct clk mpu_wdt_fck = {
1402 .name = "mpu_wdt_fck",
1403 .ops = &clkops_omap2_dflt_wait,
1404 .parent = &func_32k_ck,
1405 .clkdm_name = "wkup_clkdm",
1406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1407 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1408 .recalc = &followparent_recalc,
1409};
1410
1411static struct clk sync_32k_ick = {
1412 .name = "sync_32k_ick",
1413 .ops = &clkops_omap2_iclk_dflt_wait,
1414 .flags = ENABLE_ON_INIT,
1415 .parent = &wu_l4_ick,
1416 .clkdm_name = "wkup_clkdm",
1417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1418 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1419 .recalc = &followparent_recalc,
1420};
1421
1422static struct clk wdt1_ick = {
1423 .name = "wdt1_ick",
1424 .ops = &clkops_omap2_iclk_dflt_wait,
1425 .parent = &wu_l4_ick,
1426 .clkdm_name = "wkup_clkdm",
1427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1428 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1429 .recalc = &followparent_recalc,
1430};
1431
1432static struct clk omapctrl_ick = {
1433 .name = "omapctrl_ick",
1434 .ops = &clkops_omap2_iclk_dflt_wait,
1435 .flags = ENABLE_ON_INIT,
1436 .parent = &wu_l4_ick,
1437 .clkdm_name = "wkup_clkdm",
1438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1439 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1440 .recalc = &followparent_recalc,
1441};
1442
1443static struct clk icr_ick = {
1444 .name = "icr_ick",
1445 .ops = &clkops_omap2_iclk_dflt_wait,
1446 .parent = &wu_l4_ick,
1447 .clkdm_name = "wkup_clkdm",
1448 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1449 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1450 .recalc = &followparent_recalc,
1451};
1452
1453static struct clk cam_ick = {
1454 .name = "cam_ick",
1455 .ops = &clkops_omap2_iclk_dflt,
1456 .parent = &l4_ck,
1457 .clkdm_name = "core_l4_clkdm",
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1459 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1460 .recalc = &followparent_recalc,
1461};
1462
1463/*
1464 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1465 * split into two separate clocks, since the parent clocks are different
1466 * and the clockdomains are also different.
1467 */
1468static struct clk cam_fck = {
1469 .name = "cam_fck",
1470 .ops = &clkops_omap2_dflt,
1471 .parent = &func_96m_ck,
1472 .clkdm_name = "core_l3_clkdm",
1473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk mailboxes_ick = {
1479 .name = "mailboxes_ick",
1480 .ops = &clkops_omap2_iclk_dflt_wait,
1481 .parent = &l4_ck,
1482 .clkdm_name = "core_l4_clkdm",
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1484 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk wdt4_ick = {
1489 .name = "wdt4_ick",
1490 .ops = &clkops_omap2_iclk_dflt_wait,
1491 .parent = &l4_ck,
1492 .clkdm_name = "core_l4_clkdm",
1493 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1494 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1495 .recalc = &followparent_recalc,
1496};
1497
1498static struct clk wdt4_fck = {
1499 .name = "wdt4_fck",
1500 .ops = &clkops_omap2_dflt_wait,
1501 .parent = &func_32k_ck,
1502 .clkdm_name = "core_l4_clkdm",
1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1505 .recalc = &followparent_recalc,
1506};
1507
1508static struct clk mspro_ick = {
1509 .name = "mspro_ick",
1510 .ops = &clkops_omap2_iclk_dflt_wait,
1511 .parent = &l4_ck,
1512 .clkdm_name = "core_l4_clkdm",
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1514 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1515 .recalc = &followparent_recalc,
1516};
1517
1518static struct clk mspro_fck = {
1519 .name = "mspro_fck",
1520 .ops = &clkops_omap2_dflt_wait,
1521 .parent = &func_96m_ck,
1522 .clkdm_name = "core_l4_clkdm",
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1525 .recalc = &followparent_recalc,
1526};
1527
1528static struct clk fac_ick = {
1529 .name = "fac_ick",
1530 .ops = &clkops_omap2_iclk_dflt_wait,
1531 .parent = &l4_ck,
1532 .clkdm_name = "core_l4_clkdm",
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1534 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1535 .recalc = &followparent_recalc,
1536};
1537
1538static struct clk fac_fck = {
1539 .name = "fac_fck",
1540 .ops = &clkops_omap2_dflt_wait,
1541 .parent = &func_12m_ck,
1542 .clkdm_name = "core_l4_clkdm",
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1545 .recalc = &followparent_recalc,
1546};
1547
1548static struct clk hdq_ick = {
1549 .name = "hdq_ick",
1550 .ops = &clkops_omap2_iclk_dflt_wait,
1551 .parent = &l4_ck,
1552 .clkdm_name = "core_l4_clkdm",
1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1554 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1555 .recalc = &followparent_recalc,
1556};
1557
1558static struct clk hdq_fck = {
1559 .name = "hdq_fck",
1560 .ops = &clkops_omap2_dflt_wait,
1561 .parent = &func_12m_ck,
1562 .clkdm_name = "core_l4_clkdm",
1563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1565 .recalc = &followparent_recalc,
1566};
1567
1568/*
1569 * XXX This is marked as a 2420-only define, but it claims to be present
1570 * on 2430 also. Double-check.
1571 */
1572static struct clk i2c2_ick = {
1573 .name = "i2c2_ick",
1574 .ops = &clkops_omap2_iclk_dflt_wait,
1575 .parent = &l4_ck,
1576 .clkdm_name = "core_l4_clkdm",
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1578 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1579 .recalc = &followparent_recalc,
1580};
1581
1582static struct clk i2chs2_fck = {
1583 .name = "i2chs2_fck",
1584 .ops = &clkops_omap2430_i2chs_wait,
1585 .parent = &func_96m_ck,
1586 .clkdm_name = "core_l4_clkdm",
1587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1588 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1589 .recalc = &followparent_recalc,
1590};
1591
1592/*
1593 * XXX This is marked as a 2420-only define, but it claims to be present
1594 * on 2430 also. Double-check.
1595 */
1596static struct clk i2c1_ick = {
1597 .name = "i2c1_ick",
1598 .ops = &clkops_omap2_iclk_dflt_wait,
1599 .parent = &l4_ck,
1600 .clkdm_name = "core_l4_clkdm",
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1602 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1603 .recalc = &followparent_recalc,
1604};
1605
1606static struct clk i2chs1_fck = {
1607 .name = "i2chs1_fck",
1608 .ops = &clkops_omap2430_i2chs_wait,
1609 .parent = &func_96m_ck,
1610 .clkdm_name = "core_l4_clkdm",
1611 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1612 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1613 .recalc = &followparent_recalc,
1614};
1615
1616/*
1617 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1618 * accesses derived from this data.
1619 */
1620static struct clk gpmc_fck = {
1621 .name = "gpmc_fck",
1622 .ops = &clkops_omap2_iclk_idle_only,
1623 .parent = &core_l3_ck,
1624 .flags = ENABLE_ON_INIT,
1625 .clkdm_name = "core_l3_clkdm",
1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1627 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1628 .recalc = &followparent_recalc,
1629};
1630
1631static struct clk sdma_fck = {
1632 .name = "sdma_fck",
1633 .ops = &clkops_null, /* RMK: missing? */
1634 .parent = &core_l3_ck,
1635 .clkdm_name = "core_l3_clkdm",
1636 .recalc = &followparent_recalc,
1637};
1638
1639/*
1640 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1641 * accesses derived from this data.
1642 */
1643static struct clk sdma_ick = {
1644 .name = "sdma_ick",
1645 .ops = &clkops_omap2_iclk_idle_only,
1646 .parent = &core_l3_ck,
1647 .clkdm_name = "core_l3_clkdm",
1648 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1649 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1650 .recalc = &followparent_recalc,
1651};
1652
1653static struct clk sdrc_ick = {
1654 .name = "sdrc_ick",
1655 .ops = &clkops_omap2_iclk_idle_only,
1656 .parent = &core_l3_ck,
1657 .flags = ENABLE_ON_INIT,
1658 .clkdm_name = "core_l3_clkdm",
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1660 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1661 .recalc = &followparent_recalc,
1662};
1663
1664static struct clk des_ick = {
1665 .name = "des_ick",
1666 .ops = &clkops_omap2_iclk_dflt_wait,
1667 .parent = &l4_ck,
1668 .clkdm_name = "core_l4_clkdm",
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1670 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1671 .recalc = &followparent_recalc,
1672};
1673
1674static struct clk sha_ick = {
1675 .name = "sha_ick",
1676 .ops = &clkops_omap2_iclk_dflt_wait,
1677 .parent = &l4_ck,
1678 .clkdm_name = "core_l4_clkdm",
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1680 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1681 .recalc = &followparent_recalc,
1682};
1683
1684static struct clk rng_ick = {
1685 .name = "rng_ick",
1686 .ops = &clkops_omap2_iclk_dflt_wait,
1687 .parent = &l4_ck,
1688 .clkdm_name = "core_l4_clkdm",
1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1690 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1691 .recalc = &followparent_recalc,
1692};
1693
1694static struct clk aes_ick = {
1695 .name = "aes_ick",
1696 .ops = &clkops_omap2_iclk_dflt_wait,
1697 .parent = &l4_ck,
1698 .clkdm_name = "core_l4_clkdm",
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1700 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1701 .recalc = &followparent_recalc,
1702};
1703
1704static struct clk pka_ick = {
1705 .name = "pka_ick",
1706 .ops = &clkops_omap2_iclk_dflt_wait,
1707 .parent = &l4_ck,
1708 .clkdm_name = "core_l4_clkdm",
1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1710 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1711 .recalc = &followparent_recalc,
1712};
1713
1714static struct clk usb_fck = {
1715 .name = "usb_fck",
1716 .ops = &clkops_omap2_dflt_wait,
1717 .parent = &func_48m_ck,
1718 .clkdm_name = "core_l3_clkdm",
1719 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1720 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1721 .recalc = &followparent_recalc,
1722};
1723
1724static struct clk usbhs_ick = {
1725 .name = "usbhs_ick",
1726 .ops = &clkops_omap2_iclk_dflt_wait,
1727 .parent = &core_l3_ck,
1728 .clkdm_name = "core_l3_clkdm",
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1730 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1731 .recalc = &followparent_recalc,
1732};
1733
1734static struct clk mmchs1_ick = {
1735 .name = "mmchs1_ick",
1736 .ops = &clkops_omap2_iclk_dflt_wait,
1737 .parent = &l4_ck,
1738 .clkdm_name = "core_l4_clkdm",
1739 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1740 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1741 .recalc = &followparent_recalc,
1742};
1743
1744static struct clk mmchs1_fck = {
1745 .name = "mmchs1_fck",
1746 .ops = &clkops_omap2_dflt_wait,
1747 .parent = &func_96m_ck,
1748 .clkdm_name = "core_l4_clkdm",
1749 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1750 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1751 .recalc = &followparent_recalc,
1752};
1753
1754static struct clk mmchs2_ick = {
1755 .name = "mmchs2_ick",
1756 .ops = &clkops_omap2_iclk_dflt_wait,
1757 .parent = &l4_ck,
1758 .clkdm_name = "core_l4_clkdm",
1759 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1760 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1761 .recalc = &followparent_recalc,
1762};
1763
1764static struct clk mmchs2_fck = {
1765 .name = "mmchs2_fck",
1766 .ops = &clkops_omap2_dflt_wait,
1767 .parent = &func_96m_ck,
1768 .clkdm_name = "core_l4_clkdm",
1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1770 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1771 .recalc = &followparent_recalc,
1772};
1773
1774static struct clk gpio5_ick = {
1775 .name = "gpio5_ick",
1776 .ops = &clkops_omap2_iclk_dflt_wait,
1777 .parent = &l4_ck,
1778 .clkdm_name = "core_l4_clkdm",
1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1780 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1781 .recalc = &followparent_recalc,
1782};
1783
1784static struct clk gpio5_fck = {
1785 .name = "gpio5_fck",
1786 .ops = &clkops_omap2_dflt_wait,
1787 .parent = &func_32k_ck,
1788 .clkdm_name = "core_l4_clkdm",
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1790 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1791 .recalc = &followparent_recalc,
1792};
1793
1794static struct clk mdm_intc_ick = {
1795 .name = "mdm_intc_ick",
1796 .ops = &clkops_omap2_iclk_dflt_wait,
1797 .parent = &l4_ck,
1798 .clkdm_name = "core_l4_clkdm",
1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1800 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1801 .recalc = &followparent_recalc,
1802};
1803
1804static struct clk mmchsdb1_fck = {
1805 .name = "mmchsdb1_fck",
1806 .ops = &clkops_omap2_dflt_wait,
1807 .parent = &func_32k_ck,
1808 .clkdm_name = "core_l4_clkdm",
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1810 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1811 .recalc = &followparent_recalc,
1812};
1813
1814static struct clk mmchsdb2_fck = {
1815 .name = "mmchsdb2_fck",
1816 .ops = &clkops_omap2_dflt_wait,
1817 .parent = &func_32k_ck,
1818 .clkdm_name = "core_l4_clkdm",
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1820 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1821 .recalc = &followparent_recalc,
1822};
1823
1824/*
1825 * This clock is a composite clock which does entire set changes then
1826 * forces a rebalance. It keys on the MPU speed, but it really could
1827 * be any key speed part of a set in the rate table.
1828 *
1829 * to really change a set, you need memory table sets which get changed
1830 * in sram, pre-notifiers & post notifiers, changing the top set, without
1831 * having low level display recalc's won't work... this is why dpm notifiers
1832 * work, isr's off, walk a list of clocks already _off_ and not messing with
1833 * the bus.
1834 *
1835 * This clock should have no parent. It embodies the entire upper level
1836 * active set. A parent will mess up some of the init also.
1837 */
1838static struct clk virt_prcm_set = {
1839 .name = "virt_prcm_set",
1840 .ops = &clkops_null,
1841 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1842 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1843 .set_rate = &omap2_select_table_rate,
1844 .round_rate = &omap2_round_to_table_rate,
1845};
1846
1847
1848/*
1849 * clkdev integration
1850 */
1851
1852static struct omap_clk omap2430_clks[] = {
1853 /* external root sources */
1854 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1855 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1856 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1857 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1858 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1859 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
1860 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
1861 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
1862 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
1863 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
1864 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1865 /* internal analog sources */
1866 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1867 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1868 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1869 /* internal prcm root sources */
1870 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1871 CLK(NULL, "core_ck", &core_ck, CK_243X),
1872 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
1873 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
1874 CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
1875 CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
1876 CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
1877 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1878 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1879 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1880 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1881 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1882 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1883 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1884 /* mpu domain clocks */
1885 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1886 /* dsp domain clocks */
1887 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1888 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1889 /* GFX domain clocks */
1890 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1891 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1892 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1893 /* Modem domain clocks */
1894 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1895 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1896 /* DSS domain clocks */
1897 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1898 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1899 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1900 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1901 /* L3 domain clocks */
1902 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1903 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1904 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1905 /* L4 domain clocks */
1906 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1907 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1908 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1909 /* virtual meta-group clock */
1910 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1911 /* general l4 interface ck, multi-parent functional clk */
1912 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1913 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1914 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1915 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1916 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1917 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1918 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1919 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1920 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1921 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1922 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1923 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1924 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1925 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1926 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1927 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1928 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1929 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1930 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1931 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1932 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1933 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1934 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1935 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1936 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1937 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1938 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1939 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1940 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1941 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1942 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1943 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1944 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1945 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1946 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1947 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1948 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1952 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1953 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1954 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1955 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1956 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1957 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1958 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1959 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1960 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1961 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1962 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1963 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1964 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1965 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1966 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1967 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1968 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1969 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1970 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1971 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1972 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1973 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1974 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1975 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1976 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1977 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1978 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1979 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1980 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1981 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1982 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1983 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1984 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1985 CLK(NULL, "des_ick", &des_ick, CK_243X),
1986 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1987 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1988 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1989 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1993 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1994 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2000 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2001};
2002
2003/*
2004 * init code
2005 */
2006
2007int __init omap2430_clk_init(void)
2008{
2009 const struct prcm_config *prcm;
2010 struct omap_clk *c;
2011 u32 clkrate;
2012
2013 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2014 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
2015 cpu_mask = RATE_IN_243X;
2016 rate_table = omap2430_rate_table;
2017
2018 clk_init(&omap2_clk_functions);
2019
2020 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2021 c++)
2022 clk_preinit(c->lk.clk);
2023
2024 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2025 propagate_rate(&osc_ck);
2026 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2027 propagate_rate(&sys_ck);
2028
2029 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2030 c++) {
2031 clkdev_add(&c->lk);
2032 clk_register(c->lk.clk);
2033 omap2_init_clk_clkdm(c->lk.clk);
2034 }
2035
2036 /* Disable autoidle on all clocks; let the PM code enable it later */
2037 omap_clk_disable_autoidle_all();
2038
2039 /* Check the MPU rate set by bootloader */
2040 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2041 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2042 if (!(prcm->flags & cpu_mask))
2043 continue;
2044 if (prcm->xtal_speed != sys_ck.rate)
2045 continue;
2046 if (prcm->dpll_speed <= clkrate)
2047 break;
2048 }
2049 curr_prcm_set = prcm;
2050
2051 recalculate_root_clocks();
2052
2053 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2054 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2055 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2056
2057 /*
2058 * Only enable those clocks we will need, let the drivers
2059 * enable other clocks as necessary
2060 */
2061 clk_enable_init_clocks();
2062
2063 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2064 vclk = clk_get(NULL, "virt_prcm_set");
2065 sclk = clk_get(NULL, "sys_ck");
2066 dclk = clk_get(NULL, "dpll_ck");
2067
2068 return 0;
2069}
2070
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
new file mode 100644
index 00000000000..b9b84468314
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -0,0 +1,3578 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/list.h>
22
23#include <plat/clkdev_omap.h>
24
25#include "clock.h"
26#include "clock3xxx.h"
27#include "clock34xx.h"
28#include "clock36xx.h"
29#include "clock3517.h"
30
31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-34xx.h"
33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h"
35#include "control.h"
36
37/*
38 * clocks
39 */
40
41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43/* Maximum DPLL multiplier, divider values for OMAP3 */
44#define OMAP3_MAX_DPLL_MULT 2047
45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46#define OMAP3_MAX_DPLL_DIV 128
47
48/*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56/* Forward declarations for DPLL bypass clocks */
57static struct clk dpll1_fck;
58static struct clk dpll2_fck;
59
60/* PRM CLOCKS */
61
62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67};
68
69static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73};
74
75/* Virtual source clocks for osc_sys_ck */
76static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80};
81
82static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92};
93
94static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
98};
99
100static struct clk virt_26m_ck = {
101 .name = "virt_26m_ck",
102 .ops = &clkops_null,
103 .rate = 26000000,
104};
105
106static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null,
109 .rate = 38400000,
110};
111
112static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 }
115};
116
117static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 }
120};
121
122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 }
125};
126
127static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 }
130};
131
132static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 }
135};
136
137static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 }
140};
141
142static const struct clksel osc_sys_clksel[] = {
143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
149 { .parent = NULL },
150};
151
152/* Oscillator clock */
153/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154static struct clk osc_sys_ck = {
155 .name = "osc_sys_ck",
156 .ops = &clkops_null,
157 .init = &omap2_init_clksel_parent,
158 .clksel_reg = OMAP3430_PRM_CLKSEL,
159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
160 .clksel = osc_sys_clksel,
161 /* REVISIT: deal with autoextclkmode? */
162 .recalc = &omap2_clksel_recalc,
163};
164
165static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 }
169};
170
171static const struct clksel sys_clksel[] = {
172 { .parent = &osc_sys_ck, .rates = div2_rates },
173 { .parent = NULL }
174};
175
176/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178static struct clk sys_ck = {
179 .name = "sys_ck",
180 .ops = &clkops_null,
181 .parent = &osc_sys_ck,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
184 .clksel_mask = OMAP_SYSCLKDIV_MASK,
185 .clksel = sys_clksel,
186 .recalc = &omap2_clksel_recalc,
187};
188
189static struct clk sys_altclk = {
190 .name = "sys_altclk",
191 .ops = &clkops_null,
192};
193
194/* Optional external clock input for some McBSPs */
195static struct clk mcbsp_clks = {
196 .name = "mcbsp_clks",
197 .ops = &clkops_null,
198};
199
200/* PRM EXTERNAL CLOCK OUTPUT */
201
202static struct clk sys_clkout1 = {
203 .name = "sys_clkout1",
204 .ops = &clkops_omap2_dflt,
205 .parent = &osc_sys_ck,
206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
208 .recalc = &followparent_recalc,
209};
210
211/* DPLLS */
212
213/* CM CLOCKS */
214
215static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 }
233};
234
235static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
269};
270
271/* DPLL1 */
272/* MPU clock source */
273/* Type: DPLL */
274static struct dpll_data dpll1_dd = {
275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
278 .clk_bypass = &dpll1_fck,
279 .clk_ref = &sys_ck,
280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV,
294};
295
296static struct clk dpll1_ck = {
297 .name = "dpll1_ck",
298 .ops = &clkops_omap3_noncore_dpll_ops,
299 .parent = &sys_ck,
300 .dpll_data = &dpll1_dd,
301 .round_rate = &omap2_dpll_round_rate,
302 .set_rate = &omap3_noncore_dpll_set_rate,
303 .clkdm_name = "dpll1_clkdm",
304 .recalc = &omap3_dpll_recalc,
305};
306
307/*
308 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
309 * DPLL isn't bypassed.
310 */
311static struct clk dpll1_x2_ck = {
312 .name = "dpll1_x2_ck",
313 .ops = &clkops_null,
314 .parent = &dpll1_ck,
315 .clkdm_name = "dpll1_clkdm",
316 .recalc = &omap3_clkoutx2_recalc,
317};
318
319/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
320static const struct clksel div16_dpll1_x2m2_clksel[] = {
321 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
322 { .parent = NULL }
323};
324
325/*
326 * Does not exist in the TRM - needed to separate the M2 divider from
327 * bypass selection in mpu_ck
328 */
329static struct clk dpll1_x2m2_ck = {
330 .name = "dpll1_x2m2_ck",
331 .ops = &clkops_null,
332 .parent = &dpll1_x2_ck,
333 .init = &omap2_init_clksel_parent,
334 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
335 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
336 .clksel = div16_dpll1_x2m2_clksel,
337 .clkdm_name = "dpll1_clkdm",
338 .recalc = &omap2_clksel_recalc,
339};
340
341/* DPLL2 */
342/* IVA2 clock source */
343/* Type: DPLL */
344
345static struct dpll_data dpll2_dd = {
346 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
347 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
348 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
349 .clk_bypass = &dpll2_fck,
350 .clk_ref = &sys_ck,
351 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
352 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
353 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
354 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
355 (1 << DPLL_LOW_POWER_BYPASS),
356 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
357 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
358 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
359 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
360 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
361 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
362 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
363 .max_multiplier = OMAP3_MAX_DPLL_MULT,
364 .min_divider = 1,
365 .max_divider = OMAP3_MAX_DPLL_DIV,
366};
367
368static struct clk dpll2_ck = {
369 .name = "dpll2_ck",
370 .ops = &clkops_omap3_noncore_dpll_ops,
371 .parent = &sys_ck,
372 .dpll_data = &dpll2_dd,
373 .round_rate = &omap2_dpll_round_rate,
374 .set_rate = &omap3_noncore_dpll_set_rate,
375 .clkdm_name = "dpll2_clkdm",
376 .recalc = &omap3_dpll_recalc,
377};
378
379static const struct clksel div16_dpll2_m2x2_clksel[] = {
380 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
381 { .parent = NULL }
382};
383
384/*
385 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
386 * or CLKOUTX2. CLKOUT seems most plausible.
387 */
388static struct clk dpll2_m2_ck = {
389 .name = "dpll2_m2_ck",
390 .ops = &clkops_null,
391 .parent = &dpll2_ck,
392 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
394 OMAP3430_CM_CLKSEL2_PLL),
395 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
396 .clksel = div16_dpll2_m2x2_clksel,
397 .clkdm_name = "dpll2_clkdm",
398 .recalc = &omap2_clksel_recalc,
399};
400
401/*
402 * DPLL3
403 * Source clock for all interfaces and for some device fclks
404 * REVISIT: Also supports fast relock bypass - not included below
405 */
406static struct dpll_data dpll3_dd = {
407 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
408 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
409 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
410 .clk_bypass = &sys_ck,
411 .clk_ref = &sys_ck,
412 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
413 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
414 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
415 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
416 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
417 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
418 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
419 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
420 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
421 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
422 .max_multiplier = OMAP3_MAX_DPLL_MULT,
423 .min_divider = 1,
424 .max_divider = OMAP3_MAX_DPLL_DIV,
425};
426
427static struct clk dpll3_ck = {
428 .name = "dpll3_ck",
429 .ops = &clkops_omap3_core_dpll_ops,
430 .parent = &sys_ck,
431 .dpll_data = &dpll3_dd,
432 .round_rate = &omap2_dpll_round_rate,
433 .clkdm_name = "dpll3_clkdm",
434 .recalc = &omap3_dpll_recalc,
435};
436
437/*
438 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
439 * DPLL isn't bypassed
440 */
441static struct clk dpll3_x2_ck = {
442 .name = "dpll3_x2_ck",
443 .ops = &clkops_null,
444 .parent = &dpll3_ck,
445 .clkdm_name = "dpll3_clkdm",
446 .recalc = &omap3_clkoutx2_recalc,
447};
448
449static const struct clksel_rate div31_dpll3_rates[] = {
450 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
451 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
452 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
453 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
454 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
455 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 0 },
482};
483
484static const struct clksel div31_dpll3m2_clksel[] = {
485 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
486 { .parent = NULL }
487};
488
489/* DPLL3 output M2 - primary control point for CORE speed */
490static struct clk dpll3_m2_ck = {
491 .name = "dpll3_m2_ck",
492 .ops = &clkops_null,
493 .parent = &dpll3_ck,
494 .init = &omap2_init_clksel_parent,
495 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
496 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
497 .clksel = div31_dpll3m2_clksel,
498 .clkdm_name = "dpll3_clkdm",
499 .round_rate = &omap2_clksel_round_rate,
500 .set_rate = &omap3_core_dpll_m2_set_rate,
501 .recalc = &omap2_clksel_recalc,
502};
503
504static struct clk core_ck = {
505 .name = "core_ck",
506 .ops = &clkops_null,
507 .parent = &dpll3_m2_ck,
508 .recalc = &followparent_recalc,
509};
510
511static struct clk dpll3_m2x2_ck = {
512 .name = "dpll3_m2x2_ck",
513 .ops = &clkops_null,
514 .parent = &dpll3_m2_ck,
515 .clkdm_name = "dpll3_clkdm",
516 .recalc = &omap3_clkoutx2_recalc,
517};
518
519/* The PWRDN bit is apparently only available on 3430ES2 and above */
520static const struct clksel div16_dpll3_clksel[] = {
521 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
522 { .parent = NULL }
523};
524
525/* This virtual clock is the source for dpll3_m3x2_ck */
526static struct clk dpll3_m3_ck = {
527 .name = "dpll3_m3_ck",
528 .ops = &clkops_null,
529 .parent = &dpll3_ck,
530 .init = &omap2_init_clksel_parent,
531 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
532 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
533 .clksel = div16_dpll3_clksel,
534 .clkdm_name = "dpll3_clkdm",
535 .recalc = &omap2_clksel_recalc,
536};
537
538/* The PWRDN bit is apparently only available on 3430ES2 and above */
539static struct clk dpll3_m3x2_ck = {
540 .name = "dpll3_m3x2_ck",
541 .ops = &clkops_omap2_dflt_wait,
542 .parent = &dpll3_m3_ck,
543 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
544 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
545 .flags = INVERT_ENABLE,
546 .clkdm_name = "dpll3_clkdm",
547 .recalc = &omap3_clkoutx2_recalc,
548};
549
550static struct clk emu_core_alwon_ck = {
551 .name = "emu_core_alwon_ck",
552 .ops = &clkops_null,
553 .parent = &dpll3_m3x2_ck,
554 .clkdm_name = "dpll3_clkdm",
555 .recalc = &followparent_recalc,
556};
557
558/* DPLL4 */
559/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
560/* Type: DPLL */
561static struct dpll_data dpll4_dd;
562
563static struct dpll_data dpll4_dd_34xx __initdata = {
564 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
565 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
566 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
567 .clk_bypass = &sys_ck,
568 .clk_ref = &sys_ck,
569 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
570 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
572 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
573 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
574 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
575 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
576 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
577 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
578 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
579 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
580 .max_multiplier = OMAP3_MAX_DPLL_MULT,
581 .min_divider = 1,
582 .max_divider = OMAP3_MAX_DPLL_DIV,
583};
584
585static struct dpll_data dpll4_dd_3630 __initdata = {
586 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
587 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
588 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
589 .clk_bypass = &sys_ck,
590 .clk_ref = &sys_ck,
591 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
592 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
593 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
594 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
595 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
596 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
597 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
598 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
599 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
600 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
601 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
602 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
604 .min_divider = 1,
605 .max_divider = OMAP3_MAX_DPLL_DIV,
606 .flags = DPLL_J_TYPE
607};
608
609static struct clk dpll4_ck = {
610 .name = "dpll4_ck",
611 .ops = &clkops_omap3_noncore_dpll_ops,
612 .parent = &sys_ck,
613 .dpll_data = &dpll4_dd,
614 .round_rate = &omap2_dpll_round_rate,
615 .set_rate = &omap3_dpll4_set_rate,
616 .clkdm_name = "dpll4_clkdm",
617 .recalc = &omap3_dpll_recalc,
618};
619
620/*
621 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
622 * DPLL isn't bypassed --
623 * XXX does this serve any downstream clocks?
624 */
625static struct clk dpll4_x2_ck = {
626 .name = "dpll4_x2_ck",
627 .ops = &clkops_null,
628 .parent = &dpll4_ck,
629 .clkdm_name = "dpll4_clkdm",
630 .recalc = &omap3_clkoutx2_recalc,
631};
632
633static const struct clksel dpll4_clksel[] = {
634 { .parent = &dpll4_ck, .rates = dpll4_rates },
635 { .parent = NULL }
636};
637
638/* This virtual clock is the source for dpll4_m2x2_ck */
639static struct clk dpll4_m2_ck = {
640 .name = "dpll4_m2_ck",
641 .ops = &clkops_null,
642 .parent = &dpll4_ck,
643 .init = &omap2_init_clksel_parent,
644 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
645 .clksel_mask = OMAP3630_DIV_96M_MASK,
646 .clksel = dpll4_clksel,
647 .clkdm_name = "dpll4_clkdm",
648 .recalc = &omap2_clksel_recalc,
649};
650
651/* The PWRDN bit is apparently only available on 3430ES2 and above */
652static struct clk dpll4_m2x2_ck = {
653 .name = "dpll4_m2x2_ck",
654 .ops = &clkops_omap2_dflt_wait,
655 .parent = &dpll4_m2_ck,
656 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
657 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
658 .flags = INVERT_ENABLE,
659 .clkdm_name = "dpll4_clkdm",
660 .recalc = &omap3_clkoutx2_recalc,
661};
662
663/*
664 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
665 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
666 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
667 * CM_96K_(F)CLK.
668 */
669
670/* Adding 192MHz Clock node needed by SGX */
671static struct clk omap_192m_alwon_fck = {
672 .name = "omap_192m_alwon_fck",
673 .ops = &clkops_null,
674 .parent = &dpll4_m2x2_ck,
675 .recalc = &followparent_recalc,
676};
677
678static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
679 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
680 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
681 { .div = 0 }
682};
683
684static const struct clksel omap_96m_alwon_fck_clksel[] = {
685 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
686 { .parent = NULL }
687};
688
689static const struct clksel_rate omap_96m_dpll_rates[] = {
690 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
691 { .div = 0 }
692};
693
694static const struct clksel_rate omap_96m_sys_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
696 { .div = 0 }
697};
698
699static struct clk omap_96m_alwon_fck = {
700 .name = "omap_96m_alwon_fck",
701 .ops = &clkops_null,
702 .parent = &dpll4_m2x2_ck,
703 .recalc = &followparent_recalc,
704};
705
706static struct clk omap_96m_alwon_fck_3630 = {
707 .name = "omap_96m_alwon_fck",
708 .parent = &omap_192m_alwon_fck,
709 .init = &omap2_init_clksel_parent,
710 .ops = &clkops_null,
711 .recalc = &omap2_clksel_recalc,
712 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
713 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
714 .clksel = omap_96m_alwon_fck_clksel
715};
716
717static struct clk cm_96m_fck = {
718 .name = "cm_96m_fck",
719 .ops = &clkops_null,
720 .parent = &omap_96m_alwon_fck,
721 .recalc = &followparent_recalc,
722};
723
724static const struct clksel omap_96m_fck_clksel[] = {
725 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
726 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
727 { .parent = NULL }
728};
729
730static struct clk omap_96m_fck = {
731 .name = "omap_96m_fck",
732 .ops = &clkops_null,
733 .parent = &sys_ck,
734 .init = &omap2_init_clksel_parent,
735 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
736 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
737 .clksel = omap_96m_fck_clksel,
738 .recalc = &omap2_clksel_recalc,
739};
740
741/* This virtual clock is the source for dpll4_m3x2_ck */
742static struct clk dpll4_m3_ck = {
743 .name = "dpll4_m3_ck",
744 .ops = &clkops_null,
745 .parent = &dpll4_ck,
746 .init = &omap2_init_clksel_parent,
747 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
748 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
749 .clksel = dpll4_clksel,
750 .clkdm_name = "dpll4_clkdm",
751 .recalc = &omap2_clksel_recalc,
752};
753
754/* The PWRDN bit is apparently only available on 3430ES2 and above */
755static struct clk dpll4_m3x2_ck = {
756 .name = "dpll4_m3x2_ck",
757 .ops = &clkops_omap2_dflt_wait,
758 .parent = &dpll4_m3_ck,
759 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
760 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
761 .flags = INVERT_ENABLE,
762 .clkdm_name = "dpll4_clkdm",
763 .recalc = &omap3_clkoutx2_recalc,
764};
765
766static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
767 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
768 { .div = 0 }
769};
770
771static const struct clksel_rate omap_54m_alt_rates[] = {
772 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
773 { .div = 0 }
774};
775
776static const struct clksel omap_54m_clksel[] = {
777 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
778 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
779 { .parent = NULL }
780};
781
782static struct clk omap_54m_fck = {
783 .name = "omap_54m_fck",
784 .ops = &clkops_null,
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
787 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
788 .clksel = omap_54m_clksel,
789 .recalc = &omap2_clksel_recalc,
790};
791
792static const struct clksel_rate omap_48m_cm96m_rates[] = {
793 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
794 { .div = 0 }
795};
796
797static const struct clksel_rate omap_48m_alt_rates[] = {
798 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
799 { .div = 0 }
800};
801
802static const struct clksel omap_48m_clksel[] = {
803 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
804 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
805 { .parent = NULL }
806};
807
808static struct clk omap_48m_fck = {
809 .name = "omap_48m_fck",
810 .ops = &clkops_null,
811 .init = &omap2_init_clksel_parent,
812 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
813 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
814 .clksel = omap_48m_clksel,
815 .recalc = &omap2_clksel_recalc,
816};
817
818static struct clk omap_12m_fck = {
819 .name = "omap_12m_fck",
820 .ops = &clkops_null,
821 .parent = &omap_48m_fck,
822 .fixed_div = 4,
823 .recalc = &omap_fixed_divisor_recalc,
824};
825
826/* This virtual clock is the source for dpll4_m4x2_ck */
827static struct clk dpll4_m4_ck = {
828 .name = "dpll4_m4_ck",
829 .ops = &clkops_null,
830 .parent = &dpll4_ck,
831 .init = &omap2_init_clksel_parent,
832 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
833 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
834 .clksel = dpll4_clksel,
835 .clkdm_name = "dpll4_clkdm",
836 .recalc = &omap2_clksel_recalc,
837 .set_rate = &omap2_clksel_set_rate,
838 .round_rate = &omap2_clksel_round_rate,
839};
840
841/* The PWRDN bit is apparently only available on 3430ES2 and above */
842static struct clk dpll4_m4x2_ck = {
843 .name = "dpll4_m4x2_ck",
844 .ops = &clkops_omap2_dflt_wait,
845 .parent = &dpll4_m4_ck,
846 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
847 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
848 .flags = INVERT_ENABLE,
849 .clkdm_name = "dpll4_clkdm",
850 .recalc = &omap3_clkoutx2_recalc,
851};
852
853/* This virtual clock is the source for dpll4_m5x2_ck */
854static struct clk dpll4_m5_ck = {
855 .name = "dpll4_m5_ck",
856 .ops = &clkops_null,
857 .parent = &dpll4_ck,
858 .init = &omap2_init_clksel_parent,
859 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
860 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
861 .clksel = dpll4_clksel,
862 .clkdm_name = "dpll4_clkdm",
863 .set_rate = &omap2_clksel_set_rate,
864 .round_rate = &omap2_clksel_round_rate,
865 .recalc = &omap2_clksel_recalc,
866};
867
868/* The PWRDN bit is apparently only available on 3430ES2 and above */
869static struct clk dpll4_m5x2_ck = {
870 .name = "dpll4_m5x2_ck",
871 .ops = &clkops_omap2_dflt_wait,
872 .parent = &dpll4_m5_ck,
873 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
874 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
875 .flags = INVERT_ENABLE,
876 .clkdm_name = "dpll4_clkdm",
877 .recalc = &omap3_clkoutx2_recalc,
878};
879
880/* This virtual clock is the source for dpll4_m6x2_ck */
881static struct clk dpll4_m6_ck = {
882 .name = "dpll4_m6_ck",
883 .ops = &clkops_null,
884 .parent = &dpll4_ck,
885 .init = &omap2_init_clksel_parent,
886 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
887 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
888 .clksel = dpll4_clksel,
889 .clkdm_name = "dpll4_clkdm",
890 .recalc = &omap2_clksel_recalc,
891};
892
893/* The PWRDN bit is apparently only available on 3430ES2 and above */
894static struct clk dpll4_m6x2_ck = {
895 .name = "dpll4_m6x2_ck",
896 .ops = &clkops_omap2_dflt_wait,
897 .parent = &dpll4_m6_ck,
898 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
899 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
900 .flags = INVERT_ENABLE,
901 .clkdm_name = "dpll4_clkdm",
902 .recalc = &omap3_clkoutx2_recalc,
903};
904
905static struct clk emu_per_alwon_ck = {
906 .name = "emu_per_alwon_ck",
907 .ops = &clkops_null,
908 .parent = &dpll4_m6x2_ck,
909 .clkdm_name = "dpll4_clkdm",
910 .recalc = &followparent_recalc,
911};
912
913/* DPLL5 */
914/* Supplies 120MHz clock, USIM source clock */
915/* Type: DPLL */
916/* 3430ES2 only */
917static struct dpll_data dpll5_dd = {
918 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
919 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
920 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
921 .clk_bypass = &sys_ck,
922 .clk_ref = &sys_ck,
923 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
924 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
925 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
926 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
927 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
928 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
929 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
930 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
931 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
932 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
933 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
934 .max_multiplier = OMAP3_MAX_DPLL_MULT,
935 .min_divider = 1,
936 .max_divider = OMAP3_MAX_DPLL_DIV,
937};
938
939static struct clk dpll5_ck = {
940 .name = "dpll5_ck",
941 .ops = &clkops_omap3_noncore_dpll_ops,
942 .parent = &sys_ck,
943 .dpll_data = &dpll5_dd,
944 .round_rate = &omap2_dpll_round_rate,
945 .set_rate = &omap3_noncore_dpll_set_rate,
946 .clkdm_name = "dpll5_clkdm",
947 .recalc = &omap3_dpll_recalc,
948};
949
950static const struct clksel div16_dpll5_clksel[] = {
951 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
952 { .parent = NULL }
953};
954
955static struct clk dpll5_m2_ck = {
956 .name = "dpll5_m2_ck",
957 .ops = &clkops_null,
958 .parent = &dpll5_ck,
959 .init = &omap2_init_clksel_parent,
960 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
961 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
962 .clksel = div16_dpll5_clksel,
963 .clkdm_name = "dpll5_clkdm",
964 .recalc = &omap2_clksel_recalc,
965};
966
967/* CM EXTERNAL CLOCK OUTPUTS */
968
969static const struct clksel_rate clkout2_src_core_rates[] = {
970 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
971 { .div = 0 }
972};
973
974static const struct clksel_rate clkout2_src_sys_rates[] = {
975 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
976 { .div = 0 }
977};
978
979static const struct clksel_rate clkout2_src_96m_rates[] = {
980 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
981 { .div = 0 }
982};
983
984static const struct clksel_rate clkout2_src_54m_rates[] = {
985 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
986 { .div = 0 }
987};
988
989static const struct clksel clkout2_src_clksel[] = {
990 { .parent = &core_ck, .rates = clkout2_src_core_rates },
991 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
992 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
993 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
994 { .parent = NULL }
995};
996
997static struct clk clkout2_src_ck = {
998 .name = "clkout2_src_ck",
999 .ops = &clkops_omap2_dflt,
1000 .init = &omap2_init_clksel_parent,
1001 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1002 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1003 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1004 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1005 .clksel = clkout2_src_clksel,
1006 .clkdm_name = "core_clkdm",
1007 .recalc = &omap2_clksel_recalc,
1008};
1009
1010static const struct clksel_rate sys_clkout2_rates[] = {
1011 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1012 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1013 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1014 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1015 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1016 { .div = 0 },
1017};
1018
1019static const struct clksel sys_clkout2_clksel[] = {
1020 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1021 { .parent = NULL },
1022};
1023
1024static struct clk sys_clkout2 = {
1025 .name = "sys_clkout2",
1026 .ops = &clkops_null,
1027 .init = &omap2_init_clksel_parent,
1028 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1029 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1030 .clksel = sys_clkout2_clksel,
1031 .recalc = &omap2_clksel_recalc,
1032 .round_rate = &omap2_clksel_round_rate,
1033 .set_rate = &omap2_clksel_set_rate
1034};
1035
1036/* CM OUTPUT CLOCKS */
1037
1038static struct clk corex2_fck = {
1039 .name = "corex2_fck",
1040 .ops = &clkops_null,
1041 .parent = &dpll3_m2x2_ck,
1042 .recalc = &followparent_recalc,
1043};
1044
1045/* DPLL power domain clock controls */
1046
1047static const struct clksel_rate div4_rates[] = {
1048 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1049 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1050 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1051 { .div = 0 }
1052};
1053
1054static const struct clksel div4_core_clksel[] = {
1055 { .parent = &core_ck, .rates = div4_rates },
1056 { .parent = NULL }
1057};
1058
1059/*
1060 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1061 * may be inconsistent here?
1062 */
1063static struct clk dpll1_fck = {
1064 .name = "dpll1_fck",
1065 .ops = &clkops_null,
1066 .parent = &core_ck,
1067 .init = &omap2_init_clksel_parent,
1068 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1069 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1070 .clksel = div4_core_clksel,
1071 .recalc = &omap2_clksel_recalc,
1072};
1073
1074static struct clk mpu_ck = {
1075 .name = "mpu_ck",
1076 .ops = &clkops_null,
1077 .parent = &dpll1_x2m2_ck,
1078 .clkdm_name = "mpu_clkdm",
1079 .recalc = &followparent_recalc,
1080};
1081
1082/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1083static const struct clksel_rate arm_fck_rates[] = {
1084 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1085 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1086 { .div = 0 },
1087};
1088
1089static const struct clksel arm_fck_clksel[] = {
1090 { .parent = &mpu_ck, .rates = arm_fck_rates },
1091 { .parent = NULL }
1092};
1093
1094static struct clk arm_fck = {
1095 .name = "arm_fck",
1096 .ops = &clkops_null,
1097 .parent = &mpu_ck,
1098 .init = &omap2_init_clksel_parent,
1099 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1100 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1101 .clksel = arm_fck_clksel,
1102 .clkdm_name = "mpu_clkdm",
1103 .recalc = &omap2_clksel_recalc,
1104};
1105
1106/* XXX What about neon_clkdm ? */
1107
1108/*
1109 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1110 * although it is referenced - so this is a guess
1111 */
1112static struct clk emu_mpu_alwon_ck = {
1113 .name = "emu_mpu_alwon_ck",
1114 .ops = &clkops_null,
1115 .parent = &mpu_ck,
1116 .recalc = &followparent_recalc,
1117};
1118
1119static struct clk dpll2_fck = {
1120 .name = "dpll2_fck",
1121 .ops = &clkops_null,
1122 .parent = &core_ck,
1123 .init = &omap2_init_clksel_parent,
1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1126 .clksel = div4_core_clksel,
1127 .recalc = &omap2_clksel_recalc,
1128};
1129
1130static struct clk iva2_ck = {
1131 .name = "iva2_ck",
1132 .ops = &clkops_omap2_dflt_wait,
1133 .parent = &dpll2_m2_ck,
1134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1135 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1136 .clkdm_name = "iva2_clkdm",
1137 .recalc = &followparent_recalc,
1138};
1139
1140/* Common interface clocks */
1141
1142static const struct clksel div2_core_clksel[] = {
1143 { .parent = &core_ck, .rates = div2_rates },
1144 { .parent = NULL }
1145};
1146
1147static struct clk l3_ick = {
1148 .name = "l3_ick",
1149 .ops = &clkops_null,
1150 .parent = &core_ck,
1151 .init = &omap2_init_clksel_parent,
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1153 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1154 .clksel = div2_core_clksel,
1155 .clkdm_name = "core_l3_clkdm",
1156 .recalc = &omap2_clksel_recalc,
1157};
1158
1159static const struct clksel div2_l3_clksel[] = {
1160 { .parent = &l3_ick, .rates = div2_rates },
1161 { .parent = NULL }
1162};
1163
1164static struct clk l4_ick = {
1165 .name = "l4_ick",
1166 .ops = &clkops_null,
1167 .parent = &l3_ick,
1168 .init = &omap2_init_clksel_parent,
1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1170 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1171 .clksel = div2_l3_clksel,
1172 .clkdm_name = "core_l4_clkdm",
1173 .recalc = &omap2_clksel_recalc,
1174
1175};
1176
1177static const struct clksel div2_l4_clksel[] = {
1178 { .parent = &l4_ick, .rates = div2_rates },
1179 { .parent = NULL }
1180};
1181
1182static struct clk rm_ick = {
1183 .name = "rm_ick",
1184 .ops = &clkops_null,
1185 .parent = &l4_ick,
1186 .init = &omap2_init_clksel_parent,
1187 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1189 .clksel = div2_l4_clksel,
1190 .recalc = &omap2_clksel_recalc,
1191};
1192
1193/* GFX power domain */
1194
1195/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1196
1197static const struct clksel gfx_l3_clksel[] = {
1198 { .parent = &l3_ick, .rates = gfx_l3_rates },
1199 { .parent = NULL }
1200};
1201
1202/*
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1205 */
1206static struct clk gfx_l3_ck = {
1207 .name = "gfx_l3_ck",
1208 .ops = &clkops_omap2_dflt_wait,
1209 .parent = &l3_ick,
1210 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1211 .enable_bit = OMAP_EN_GFX_SHIFT,
1212 .recalc = &followparent_recalc,
1213};
1214
1215static struct clk gfx_l3_fck = {
1216 .name = "gfx_l3_fck",
1217 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck,
1219 .init = &omap2_init_clksel_parent,
1220 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1221 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1222 .clksel = gfx_l3_clksel,
1223 .clkdm_name = "gfx_3430es1_clkdm",
1224 .recalc = &omap2_clksel_recalc,
1225};
1226
1227static struct clk gfx_l3_ick = {
1228 .name = "gfx_l3_ick",
1229 .ops = &clkops_null,
1230 .parent = &gfx_l3_ck,
1231 .clkdm_name = "gfx_3430es1_clkdm",
1232 .recalc = &followparent_recalc,
1233};
1234
1235static struct clk gfx_cg1_ck = {
1236 .name = "gfx_cg1_ck",
1237 .ops = &clkops_omap2_dflt_wait,
1238 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1241 .clkdm_name = "gfx_3430es1_clkdm",
1242 .recalc = &followparent_recalc,
1243};
1244
1245static struct clk gfx_cg2_ck = {
1246 .name = "gfx_cg2_ck",
1247 .ops = &clkops_omap2_dflt_wait,
1248 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1249 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1250 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1251 .clkdm_name = "gfx_3430es1_clkdm",
1252 .recalc = &followparent_recalc,
1253};
1254
1255/* SGX power domain - 3430ES2 only */
1256
1257static const struct clksel_rate sgx_core_rates[] = {
1258 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1259 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1260 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1261 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1262 { .div = 0 },
1263};
1264
1265static const struct clksel_rate sgx_192m_rates[] = {
1266 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1267 { .div = 0 },
1268};
1269
1270static const struct clksel_rate sgx_corex2_rates[] = {
1271 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1272 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1273 { .div = 0 },
1274};
1275
1276static const struct clksel_rate sgx_96m_rates[] = {
1277 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1278 { .div = 0 },
1279};
1280
1281static const struct clksel sgx_clksel[] = {
1282 { .parent = &core_ck, .rates = sgx_core_rates },
1283 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1284 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1285 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1286 { .parent = NULL }
1287};
1288
1289static struct clk sgx_fck = {
1290 .name = "sgx_fck",
1291 .ops = &clkops_omap2_dflt_wait,
1292 .init = &omap2_init_clksel_parent,
1293 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1294 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1295 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1296 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1297 .clksel = sgx_clksel,
1298 .clkdm_name = "sgx_clkdm",
1299 .recalc = &omap2_clksel_recalc,
1300 .set_rate = &omap2_clksel_set_rate,
1301 .round_rate = &omap2_clksel_round_rate
1302};
1303
1304/* This interface clock does not have a CM_AUTOIDLE bit */
1305static struct clk sgx_ick = {
1306 .name = "sgx_ick",
1307 .ops = &clkops_omap2_dflt_wait,
1308 .parent = &l3_ick,
1309 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311 .clkdm_name = "sgx_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315/* CORE power domain */
1316
1317static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1319 .ops = &clkops_omap2_dflt_wait,
1320 .parent = &sys_ck,
1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1323 .clkdm_name = "d2d_clkdm",
1324 .recalc = &followparent_recalc,
1325};
1326
1327static struct clk modem_fck = {
1328 .name = "modem_fck",
1329 .ops = &clkops_omap2_mdmclk_dflt_wait,
1330 .parent = &sys_ck,
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1333 .clkdm_name = "d2d_clkdm",
1334 .recalc = &followparent_recalc,
1335};
1336
1337static struct clk sad2d_ick = {
1338 .name = "sad2d_ick",
1339 .ops = &clkops_omap2_iclk_dflt_wait,
1340 .parent = &l3_ick,
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1343 .clkdm_name = "d2d_clkdm",
1344 .recalc = &followparent_recalc,
1345};
1346
1347static struct clk mad2d_ick = {
1348 .name = "mad2d_ick",
1349 .ops = &clkops_omap2_iclk_dflt_wait,
1350 .parent = &l3_ick,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1353 .clkdm_name = "d2d_clkdm",
1354 .recalc = &followparent_recalc,
1355};
1356
1357static const struct clksel omap343x_gpt_clksel[] = {
1358 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1359 { .parent = &sys_ck, .rates = gpt_sys_rates },
1360 { .parent = NULL}
1361};
1362
1363static struct clk gpt10_fck = {
1364 .name = "gpt10_fck",
1365 .ops = &clkops_omap2_dflt_wait,
1366 .parent = &sys_ck,
1367 .init = &omap2_init_clksel_parent,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1370 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1371 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1372 .clksel = omap343x_gpt_clksel,
1373 .clkdm_name = "core_l4_clkdm",
1374 .recalc = &omap2_clksel_recalc,
1375};
1376
1377static struct clk gpt11_fck = {
1378 .name = "gpt11_fck",
1379 .ops = &clkops_omap2_dflt_wait,
1380 .parent = &sys_ck,
1381 .init = &omap2_init_clksel_parent,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1384 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1386 .clksel = omap343x_gpt_clksel,
1387 .clkdm_name = "core_l4_clkdm",
1388 .recalc = &omap2_clksel_recalc,
1389};
1390
1391static struct clk cpefuse_fck = {
1392 .name = "cpefuse_fck",
1393 .ops = &clkops_omap2_dflt,
1394 .parent = &sys_ck,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1396 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk ts_fck = {
1401 .name = "ts_fck",
1402 .ops = &clkops_omap2_dflt,
1403 .parent = &omap_32k_fck,
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1405 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1406 .recalc = &followparent_recalc,
1407};
1408
1409static struct clk usbtll_fck = {
1410 .name = "usbtll_fck",
1411 .ops = &clkops_omap2_dflt_wait,
1412 .parent = &dpll5_m2_ck,
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1414 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1415 .recalc = &followparent_recalc,
1416};
1417
1418/* CORE 96M FCLK-derived clocks */
1419
1420static struct clk core_96m_fck = {
1421 .name = "core_96m_fck",
1422 .ops = &clkops_null,
1423 .parent = &omap_96m_fck,
1424 .clkdm_name = "core_l4_clkdm",
1425 .recalc = &followparent_recalc,
1426};
1427
1428static struct clk mmchs3_fck = {
1429 .name = "mmchs3_fck",
1430 .ops = &clkops_omap2_dflt_wait,
1431 .parent = &core_96m_fck,
1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1434 .clkdm_name = "core_l4_clkdm",
1435 .recalc = &followparent_recalc,
1436};
1437
1438static struct clk mmchs2_fck = {
1439 .name = "mmchs2_fck",
1440 .ops = &clkops_omap2_dflt_wait,
1441 .parent = &core_96m_fck,
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1444 .clkdm_name = "core_l4_clkdm",
1445 .recalc = &followparent_recalc,
1446};
1447
1448static struct clk mspro_fck = {
1449 .name = "mspro_fck",
1450 .ops = &clkops_omap2_dflt_wait,
1451 .parent = &core_96m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1454 .clkdm_name = "core_l4_clkdm",
1455 .recalc = &followparent_recalc,
1456};
1457
1458static struct clk mmchs1_fck = {
1459 .name = "mmchs1_fck",
1460 .ops = &clkops_omap2_dflt_wait,
1461 .parent = &core_96m_fck,
1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1464 .clkdm_name = "core_l4_clkdm",
1465 .recalc = &followparent_recalc,
1466};
1467
1468static struct clk i2c3_fck = {
1469 .name = "i2c3_fck",
1470 .ops = &clkops_omap2_dflt_wait,
1471 .parent = &core_96m_fck,
1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1474 .clkdm_name = "core_l4_clkdm",
1475 .recalc = &followparent_recalc,
1476};
1477
1478static struct clk i2c2_fck = {
1479 .name = "i2c2_fck",
1480 .ops = &clkops_omap2_dflt_wait,
1481 .parent = &core_96m_fck,
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1484 .clkdm_name = "core_l4_clkdm",
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk i2c1_fck = {
1489 .name = "i2c1_fck",
1490 .ops = &clkops_omap2_dflt_wait,
1491 .parent = &core_96m_fck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1494 .clkdm_name = "core_l4_clkdm",
1495 .recalc = &followparent_recalc,
1496};
1497
1498/*
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1501 */
1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1504 { .div = 0 }
1505};
1506
1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1509 { .div = 0 }
1510};
1511
1512static const struct clksel mcbsp_15_clksel[] = {
1513 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1514 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1515 { .parent = NULL }
1516};
1517
1518static struct clk mcbsp5_fck = {
1519 .name = "mcbsp5_fck",
1520 .ops = &clkops_omap2_dflt_wait,
1521 .init = &omap2_init_clksel_parent,
1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1524 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1525 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1526 .clksel = mcbsp_15_clksel,
1527 .clkdm_name = "core_l4_clkdm",
1528 .recalc = &omap2_clksel_recalc,
1529};
1530
1531static struct clk mcbsp1_fck = {
1532 .name = "mcbsp1_fck",
1533 .ops = &clkops_omap2_dflt_wait,
1534 .init = &omap2_init_clksel_parent,
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1537 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1538 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1539 .clksel = mcbsp_15_clksel,
1540 .clkdm_name = "core_l4_clkdm",
1541 .recalc = &omap2_clksel_recalc,
1542};
1543
1544/* CORE_48M_FCK-derived clocks */
1545
1546static struct clk core_48m_fck = {
1547 .name = "core_48m_fck",
1548 .ops = &clkops_null,
1549 .parent = &omap_48m_fck,
1550 .clkdm_name = "core_l4_clkdm",
1551 .recalc = &followparent_recalc,
1552};
1553
1554static struct clk mcspi4_fck = {
1555 .name = "mcspi4_fck",
1556 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &core_48m_fck,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1560 .recalc = &followparent_recalc,
1561 .clkdm_name = "core_l4_clkdm",
1562};
1563
1564static struct clk mcspi3_fck = {
1565 .name = "mcspi3_fck",
1566 .ops = &clkops_omap2_dflt_wait,
1567 .parent = &core_48m_fck,
1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1570 .recalc = &followparent_recalc,
1571 .clkdm_name = "core_l4_clkdm",
1572};
1573
1574static struct clk mcspi2_fck = {
1575 .name = "mcspi2_fck",
1576 .ops = &clkops_omap2_dflt_wait,
1577 .parent = &core_48m_fck,
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1579 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1580 .recalc = &followparent_recalc,
1581 .clkdm_name = "core_l4_clkdm",
1582};
1583
1584static struct clk mcspi1_fck = {
1585 .name = "mcspi1_fck",
1586 .ops = &clkops_omap2_dflt_wait,
1587 .parent = &core_48m_fck,
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1589 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1590 .recalc = &followparent_recalc,
1591 .clkdm_name = "core_l4_clkdm",
1592};
1593
1594static struct clk uart2_fck = {
1595 .name = "uart2_fck",
1596 .ops = &clkops_omap2_dflt_wait,
1597 .parent = &core_48m_fck,
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1600 .clkdm_name = "core_l4_clkdm",
1601 .recalc = &followparent_recalc,
1602};
1603
1604static struct clk uart1_fck = {
1605 .name = "uart1_fck",
1606 .ops = &clkops_omap2_dflt_wait,
1607 .parent = &core_48m_fck,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1610 .clkdm_name = "core_l4_clkdm",
1611 .recalc = &followparent_recalc,
1612};
1613
1614static struct clk fshostusb_fck = {
1615 .name = "fshostusb_fck",
1616 .ops = &clkops_omap2_dflt_wait,
1617 .parent = &core_48m_fck,
1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1620 .recalc = &followparent_recalc,
1621};
1622
1623/* CORE_12M_FCK based clocks */
1624
1625static struct clk core_12m_fck = {
1626 .name = "core_12m_fck",
1627 .ops = &clkops_null,
1628 .parent = &omap_12m_fck,
1629 .clkdm_name = "core_l4_clkdm",
1630 .recalc = &followparent_recalc,
1631};
1632
1633static struct clk hdq_fck = {
1634 .name = "hdq_fck",
1635 .ops = &clkops_omap2_dflt_wait,
1636 .parent = &core_12m_fck,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1639 .recalc = &followparent_recalc,
1640};
1641
1642/* DPLL3-derived clock */
1643
1644static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1645 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1646 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1647 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1648 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1649 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1650 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1651 { .div = 0 }
1652};
1653
1654static const struct clksel ssi_ssr_clksel[] = {
1655 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1656 { .parent = NULL }
1657};
1658
1659static struct clk ssi_ssr_fck_3430es1 = {
1660 .name = "ssi_ssr_fck",
1661 .ops = &clkops_omap2_dflt,
1662 .init = &omap2_init_clksel_parent,
1663 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1664 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1665 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1666 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1667 .clksel = ssi_ssr_clksel,
1668 .clkdm_name = "core_l4_clkdm",
1669 .recalc = &omap2_clksel_recalc,
1670};
1671
1672static struct clk ssi_ssr_fck_3430es2 = {
1673 .name = "ssi_ssr_fck",
1674 .ops = &clkops_omap3430es2_ssi_wait,
1675 .init = &omap2_init_clksel_parent,
1676 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1677 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1678 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1679 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1680 .clksel = ssi_ssr_clksel,
1681 .clkdm_name = "core_l4_clkdm",
1682 .recalc = &omap2_clksel_recalc,
1683};
1684
1685static struct clk ssi_sst_fck_3430es1 = {
1686 .name = "ssi_sst_fck",
1687 .ops = &clkops_null,
1688 .parent = &ssi_ssr_fck_3430es1,
1689 .fixed_div = 2,
1690 .recalc = &omap_fixed_divisor_recalc,
1691};
1692
1693static struct clk ssi_sst_fck_3430es2 = {
1694 .name = "ssi_sst_fck",
1695 .ops = &clkops_null,
1696 .parent = &ssi_ssr_fck_3430es2,
1697 .fixed_div = 2,
1698 .recalc = &omap_fixed_divisor_recalc,
1699};
1700
1701
1702
1703/* CORE_L3_ICK based clocks */
1704
1705/*
1706 * XXX must add clk_enable/clk_disable for these if standard code won't
1707 * handle it
1708 */
1709static struct clk core_l3_ick = {
1710 .name = "core_l3_ick",
1711 .ops = &clkops_null,
1712 .parent = &l3_ick,
1713 .clkdm_name = "core_l3_clkdm",
1714 .recalc = &followparent_recalc,
1715};
1716
1717static struct clk hsotgusb_ick_3430es1 = {
1718 .name = "hsotgusb_ick",
1719 .ops = &clkops_omap2_iclk_dflt,
1720 .parent = &core_l3_ick,
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1722 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1723 .clkdm_name = "core_l3_clkdm",
1724 .recalc = &followparent_recalc,
1725};
1726
1727static struct clk hsotgusb_ick_3430es2 = {
1728 .name = "hsotgusb_ick",
1729 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1730 .parent = &core_l3_ick,
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1733 .clkdm_name = "core_l3_clkdm",
1734 .recalc = &followparent_recalc,
1735};
1736
1737/* This interface clock does not have a CM_AUTOIDLE bit */
1738static struct clk sdrc_ick = {
1739 .name = "sdrc_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1741 .parent = &core_l3_ick,
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1743 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1744 .flags = ENABLE_ON_INIT,
1745 .clkdm_name = "core_l3_clkdm",
1746 .recalc = &followparent_recalc,
1747};
1748
1749static struct clk gpmc_fck = {
1750 .name = "gpmc_fck",
1751 .ops = &clkops_null,
1752 .parent = &core_l3_ick,
1753 .flags = ENABLE_ON_INIT, /* huh? */
1754 .clkdm_name = "core_l3_clkdm",
1755 .recalc = &followparent_recalc,
1756};
1757
1758/* SECURITY_L3_ICK based clocks */
1759
1760static struct clk security_l3_ick = {
1761 .name = "security_l3_ick",
1762 .ops = &clkops_null,
1763 .parent = &l3_ick,
1764 .recalc = &followparent_recalc,
1765};
1766
1767static struct clk pka_ick = {
1768 .name = "pka_ick",
1769 .ops = &clkops_omap2_iclk_dflt_wait,
1770 .parent = &security_l3_ick,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1772 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1773 .recalc = &followparent_recalc,
1774};
1775
1776/* CORE_L4_ICK based clocks */
1777
1778static struct clk core_l4_ick = {
1779 .name = "core_l4_ick",
1780 .ops = &clkops_null,
1781 .parent = &l4_ick,
1782 .clkdm_name = "core_l4_clkdm",
1783 .recalc = &followparent_recalc,
1784};
1785
1786static struct clk usbtll_ick = {
1787 .name = "usbtll_ick",
1788 .ops = &clkops_omap2_iclk_dflt_wait,
1789 .parent = &core_l4_ick,
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1791 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1792 .clkdm_name = "core_l4_clkdm",
1793 .recalc = &followparent_recalc,
1794};
1795
1796static struct clk mmchs3_ick = {
1797 .name = "mmchs3_ick",
1798 .ops = &clkops_omap2_iclk_dflt_wait,
1799 .parent = &core_l4_ick,
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1802 .clkdm_name = "core_l4_clkdm",
1803 .recalc = &followparent_recalc,
1804};
1805
1806/* Intersystem Communication Registers - chassis mode only */
1807static struct clk icr_ick = {
1808 .name = "icr_ick",
1809 .ops = &clkops_omap2_iclk_dflt_wait,
1810 .parent = &core_l4_ick,
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1813 .clkdm_name = "core_l4_clkdm",
1814 .recalc = &followparent_recalc,
1815};
1816
1817static struct clk aes2_ick = {
1818 .name = "aes2_ick",
1819 .ops = &clkops_omap2_iclk_dflt_wait,
1820 .parent = &core_l4_ick,
1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1823 .clkdm_name = "core_l4_clkdm",
1824 .recalc = &followparent_recalc,
1825};
1826
1827static struct clk sha12_ick = {
1828 .name = "sha12_ick",
1829 .ops = &clkops_omap2_iclk_dflt_wait,
1830 .parent = &core_l4_ick,
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1833 .clkdm_name = "core_l4_clkdm",
1834 .recalc = &followparent_recalc,
1835};
1836
1837static struct clk des2_ick = {
1838 .name = "des2_ick",
1839 .ops = &clkops_omap2_iclk_dflt_wait,
1840 .parent = &core_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1843 .clkdm_name = "core_l4_clkdm",
1844 .recalc = &followparent_recalc,
1845};
1846
1847static struct clk mmchs2_ick = {
1848 .name = "mmchs2_ick",
1849 .ops = &clkops_omap2_iclk_dflt_wait,
1850 .parent = &core_l4_ick,
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1853 .clkdm_name = "core_l4_clkdm",
1854 .recalc = &followparent_recalc,
1855};
1856
1857static struct clk mmchs1_ick = {
1858 .name = "mmchs1_ick",
1859 .ops = &clkops_omap2_iclk_dflt_wait,
1860 .parent = &core_l4_ick,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1863 .clkdm_name = "core_l4_clkdm",
1864 .recalc = &followparent_recalc,
1865};
1866
1867static struct clk mspro_ick = {
1868 .name = "mspro_ick",
1869 .ops = &clkops_omap2_iclk_dflt_wait,
1870 .parent = &core_l4_ick,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1873 .clkdm_name = "core_l4_clkdm",
1874 .recalc = &followparent_recalc,
1875};
1876
1877static struct clk hdq_ick = {
1878 .name = "hdq_ick",
1879 .ops = &clkops_omap2_iclk_dflt_wait,
1880 .parent = &core_l4_ick,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1883 .clkdm_name = "core_l4_clkdm",
1884 .recalc = &followparent_recalc,
1885};
1886
1887static struct clk mcspi4_ick = {
1888 .name = "mcspi4_ick",
1889 .ops = &clkops_omap2_iclk_dflt_wait,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1895};
1896
1897static struct clk mcspi3_ick = {
1898 .name = "mcspi3_ick",
1899 .ops = &clkops_omap2_iclk_dflt_wait,
1900 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1903 .clkdm_name = "core_l4_clkdm",
1904 .recalc = &followparent_recalc,
1905};
1906
1907static struct clk mcspi2_ick = {
1908 .name = "mcspi2_ick",
1909 .ops = &clkops_omap2_iclk_dflt_wait,
1910 .parent = &core_l4_ick,
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk mcspi1_ick = {
1918 .name = "mcspi1_ick",
1919 .ops = &clkops_omap2_iclk_dflt_wait,
1920 .parent = &core_l4_ick,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1923 .clkdm_name = "core_l4_clkdm",
1924 .recalc = &followparent_recalc,
1925};
1926
1927static struct clk i2c3_ick = {
1928 .name = "i2c3_ick",
1929 .ops = &clkops_omap2_iclk_dflt_wait,
1930 .parent = &core_l4_ick,
1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1933 .clkdm_name = "core_l4_clkdm",
1934 .recalc = &followparent_recalc,
1935};
1936
1937static struct clk i2c2_ick = {
1938 .name = "i2c2_ick",
1939 .ops = &clkops_omap2_iclk_dflt_wait,
1940 .parent = &core_l4_ick,
1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1942 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1943 .clkdm_name = "core_l4_clkdm",
1944 .recalc = &followparent_recalc,
1945};
1946
1947static struct clk i2c1_ick = {
1948 .name = "i2c1_ick",
1949 .ops = &clkops_omap2_iclk_dflt_wait,
1950 .parent = &core_l4_ick,
1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1952 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1953 .clkdm_name = "core_l4_clkdm",
1954 .recalc = &followparent_recalc,
1955};
1956
1957static struct clk uart2_ick = {
1958 .name = "uart2_ick",
1959 .ops = &clkops_omap2_iclk_dflt_wait,
1960 .parent = &core_l4_ick,
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1963 .clkdm_name = "core_l4_clkdm",
1964 .recalc = &followparent_recalc,
1965};
1966
1967static struct clk uart1_ick = {
1968 .name = "uart1_ick",
1969 .ops = &clkops_omap2_iclk_dflt_wait,
1970 .parent = &core_l4_ick,
1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1972 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1973 .clkdm_name = "core_l4_clkdm",
1974 .recalc = &followparent_recalc,
1975};
1976
1977static struct clk gpt11_ick = {
1978 .name = "gpt11_ick",
1979 .ops = &clkops_omap2_iclk_dflt_wait,
1980 .parent = &core_l4_ick,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1983 .clkdm_name = "core_l4_clkdm",
1984 .recalc = &followparent_recalc,
1985};
1986
1987static struct clk gpt10_ick = {
1988 .name = "gpt10_ick",
1989 .ops = &clkops_omap2_iclk_dflt_wait,
1990 .parent = &core_l4_ick,
1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1993 .clkdm_name = "core_l4_clkdm",
1994 .recalc = &followparent_recalc,
1995};
1996
1997static struct clk mcbsp5_ick = {
1998 .name = "mcbsp5_ick",
1999 .ops = &clkops_omap2_iclk_dflt_wait,
2000 .parent = &core_l4_ick,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2003 .clkdm_name = "core_l4_clkdm",
2004 .recalc = &followparent_recalc,
2005};
2006
2007static struct clk mcbsp1_ick = {
2008 .name = "mcbsp1_ick",
2009 .ops = &clkops_omap2_iclk_dflt_wait,
2010 .parent = &core_l4_ick,
2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2012 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2013 .clkdm_name = "core_l4_clkdm",
2014 .recalc = &followparent_recalc,
2015};
2016
2017static struct clk fac_ick = {
2018 .name = "fac_ick",
2019 .ops = &clkops_omap2_iclk_dflt_wait,
2020 .parent = &core_l4_ick,
2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2022 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2023 .clkdm_name = "core_l4_clkdm",
2024 .recalc = &followparent_recalc,
2025};
2026
2027static struct clk mailboxes_ick = {
2028 .name = "mailboxes_ick",
2029 .ops = &clkops_omap2_iclk_dflt_wait,
2030 .parent = &core_l4_ick,
2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2032 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2033 .clkdm_name = "core_l4_clkdm",
2034 .recalc = &followparent_recalc,
2035};
2036
2037static struct clk omapctrl_ick = {
2038 .name = "omapctrl_ick",
2039 .ops = &clkops_omap2_iclk_dflt_wait,
2040 .parent = &core_l4_ick,
2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2043 .flags = ENABLE_ON_INIT,
2044 .recalc = &followparent_recalc,
2045};
2046
2047/* SSI_L4_ICK based clocks */
2048
2049static struct clk ssi_l4_ick = {
2050 .name = "ssi_l4_ick",
2051 .ops = &clkops_null,
2052 .parent = &l4_ick,
2053 .clkdm_name = "core_l4_clkdm",
2054 .recalc = &followparent_recalc,
2055};
2056
2057static struct clk ssi_ick_3430es1 = {
2058 .name = "ssi_ick",
2059 .ops = &clkops_omap2_iclk_dflt,
2060 .parent = &ssi_l4_ick,
2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2063 .clkdm_name = "core_l4_clkdm",
2064 .recalc = &followparent_recalc,
2065};
2066
2067static struct clk ssi_ick_3430es2 = {
2068 .name = "ssi_ick",
2069 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2070 .parent = &ssi_l4_ick,
2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2072 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2073 .clkdm_name = "core_l4_clkdm",
2074 .recalc = &followparent_recalc,
2075};
2076
2077/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2078 * but l4_ick makes more sense to me */
2079
2080static const struct clksel usb_l4_clksel[] = {
2081 { .parent = &l4_ick, .rates = div2_rates },
2082 { .parent = NULL },
2083};
2084
2085static struct clk usb_l4_ick = {
2086 .name = "usb_l4_ick",
2087 .ops = &clkops_omap2_iclk_dflt_wait,
2088 .parent = &l4_ick,
2089 .init = &omap2_init_clksel_parent,
2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2092 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2093 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2094 .clksel = usb_l4_clksel,
2095 .recalc = &omap2_clksel_recalc,
2096};
2097
2098/* SECURITY_L4_ICK2 based clocks */
2099
2100static struct clk security_l4_ick2 = {
2101 .name = "security_l4_ick2",
2102 .ops = &clkops_null,
2103 .parent = &l4_ick,
2104 .recalc = &followparent_recalc,
2105};
2106
2107static struct clk aes1_ick = {
2108 .name = "aes1_ick",
2109 .ops = &clkops_omap2_iclk_dflt_wait,
2110 .parent = &security_l4_ick2,
2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk rng_ick = {
2117 .name = "rng_ick",
2118 .ops = &clkops_omap2_iclk_dflt_wait,
2119 .parent = &security_l4_ick2,
2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2122 .recalc = &followparent_recalc,
2123};
2124
2125static struct clk sha11_ick = {
2126 .name = "sha11_ick",
2127 .ops = &clkops_omap2_iclk_dflt_wait,
2128 .parent = &security_l4_ick2,
2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2131 .recalc = &followparent_recalc,
2132};
2133
2134static struct clk des1_ick = {
2135 .name = "des1_ick",
2136 .ops = &clkops_omap2_iclk_dflt_wait,
2137 .parent = &security_l4_ick2,
2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2140 .recalc = &followparent_recalc,
2141};
2142
2143/* DSS */
2144static struct clk dss1_alwon_fck_3430es1 = {
2145 .name = "dss1_alwon_fck",
2146 .ops = &clkops_omap2_dflt,
2147 .parent = &dpll4_m4x2_ck,
2148 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2149 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2150 .clkdm_name = "dss_clkdm",
2151 .recalc = &followparent_recalc,
2152};
2153
2154static struct clk dss1_alwon_fck_3430es2 = {
2155 .name = "dss1_alwon_fck",
2156 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2157 .parent = &dpll4_m4x2_ck,
2158 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2159 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2160 .clkdm_name = "dss_clkdm",
2161 .recalc = &followparent_recalc,
2162};
2163
2164static struct clk dss_tv_fck = {
2165 .name = "dss_tv_fck",
2166 .ops = &clkops_omap2_dflt,
2167 .parent = &omap_54m_fck,
2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2169 .enable_bit = OMAP3430_EN_TV_SHIFT,
2170 .clkdm_name = "dss_clkdm",
2171 .recalc = &followparent_recalc,
2172};
2173
2174static struct clk dss_96m_fck = {
2175 .name = "dss_96m_fck",
2176 .ops = &clkops_omap2_dflt,
2177 .parent = &omap_96m_fck,
2178 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2179 .enable_bit = OMAP3430_EN_TV_SHIFT,
2180 .clkdm_name = "dss_clkdm",
2181 .recalc = &followparent_recalc,
2182};
2183
2184static struct clk dss2_alwon_fck = {
2185 .name = "dss2_alwon_fck",
2186 .ops = &clkops_omap2_dflt,
2187 .parent = &sys_ck,
2188 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2189 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2190 .clkdm_name = "dss_clkdm",
2191 .recalc = &followparent_recalc,
2192};
2193
2194static struct clk dss_ick_3430es1 = {
2195 /* Handles both L3 and L4 clocks */
2196 .name = "dss_ick",
2197 .ops = &clkops_omap2_iclk_dflt,
2198 .parent = &l4_ick,
2199 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2200 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2201 .clkdm_name = "dss_clkdm",
2202 .recalc = &followparent_recalc,
2203};
2204
2205static struct clk dss_ick_3430es2 = {
2206 /* Handles both L3 and L4 clocks */
2207 .name = "dss_ick",
2208 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2209 .parent = &l4_ick,
2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2211 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2212 .clkdm_name = "dss_clkdm",
2213 .recalc = &followparent_recalc,
2214};
2215
2216/* CAM */
2217
2218static struct clk cam_mclk = {
2219 .name = "cam_mclk",
2220 .ops = &clkops_omap2_dflt,
2221 .parent = &dpll4_m5x2_ck,
2222 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2223 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2224 .clkdm_name = "cam_clkdm",
2225 .recalc = &followparent_recalc,
2226};
2227
2228static struct clk cam_ick = {
2229 /* Handles both L3 and L4 clocks */
2230 .name = "cam_ick",
2231 .ops = &clkops_omap2_iclk_dflt,
2232 .parent = &l4_ick,
2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2234 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2235 .clkdm_name = "cam_clkdm",
2236 .recalc = &followparent_recalc,
2237};
2238
2239static struct clk csi2_96m_fck = {
2240 .name = "csi2_96m_fck",
2241 .ops = &clkops_omap2_dflt,
2242 .parent = &core_96m_fck,
2243 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2244 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2245 .clkdm_name = "cam_clkdm",
2246 .recalc = &followparent_recalc,
2247};
2248
2249/* USBHOST - 3430ES2 only */
2250
2251static struct clk usbhost_120m_fck = {
2252 .name = "usbhost_120m_fck",
2253 .ops = &clkops_omap2_dflt,
2254 .parent = &dpll5_m2_ck,
2255 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2256 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2257 .clkdm_name = "usbhost_clkdm",
2258 .recalc = &followparent_recalc,
2259};
2260
2261static struct clk usbhost_48m_fck = {
2262 .name = "usbhost_48m_fck",
2263 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2264 .parent = &omap_48m_fck,
2265 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2266 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2267 .clkdm_name = "usbhost_clkdm",
2268 .recalc = &followparent_recalc,
2269};
2270
2271static struct clk usbhost_ick = {
2272 /* Handles both L3 and L4 clocks */
2273 .name = "usbhost_ick",
2274 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2275 .parent = &l4_ick,
2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2277 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2278 .clkdm_name = "usbhost_clkdm",
2279 .recalc = &followparent_recalc,
2280};
2281
2282/* WKUP */
2283
2284static const struct clksel_rate usim_96m_rates[] = {
2285 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2286 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2287 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2288 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2289 { .div = 0 },
2290};
2291
2292static const struct clksel_rate usim_120m_rates[] = {
2293 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2294 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2295 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2296 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2297 { .div = 0 },
2298};
2299
2300static const struct clksel usim_clksel[] = {
2301 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2302 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2303 { .parent = &sys_ck, .rates = div2_rates },
2304 { .parent = NULL },
2305};
2306
2307/* 3430ES2 only */
2308static struct clk usim_fck = {
2309 .name = "usim_fck",
2310 .ops = &clkops_omap2_dflt_wait,
2311 .init = &omap2_init_clksel_parent,
2312 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2313 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2314 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2315 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2316 .clksel = usim_clksel,
2317 .recalc = &omap2_clksel_recalc,
2318};
2319
2320/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2321static struct clk gpt1_fck = {
2322 .name = "gpt1_fck",
2323 .ops = &clkops_omap2_dflt_wait,
2324 .init = &omap2_init_clksel_parent,
2325 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2326 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2327 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2328 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2329 .clksel = omap343x_gpt_clksel,
2330 .clkdm_name = "wkup_clkdm",
2331 .recalc = &omap2_clksel_recalc,
2332};
2333
2334static struct clk wkup_32k_fck = {
2335 .name = "wkup_32k_fck",
2336 .ops = &clkops_null,
2337 .parent = &omap_32k_fck,
2338 .clkdm_name = "wkup_clkdm",
2339 .recalc = &followparent_recalc,
2340};
2341
2342static struct clk gpio1_dbck = {
2343 .name = "gpio1_dbck",
2344 .ops = &clkops_omap2_dflt,
2345 .parent = &wkup_32k_fck,
2346 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2348 .clkdm_name = "wkup_clkdm",
2349 .recalc = &followparent_recalc,
2350};
2351
2352static struct clk wdt2_fck = {
2353 .name = "wdt2_fck",
2354 .ops = &clkops_omap2_dflt_wait,
2355 .parent = &wkup_32k_fck,
2356 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2357 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2358 .clkdm_name = "wkup_clkdm",
2359 .recalc = &followparent_recalc,
2360};
2361
2362static struct clk wkup_l4_ick = {
2363 .name = "wkup_l4_ick",
2364 .ops = &clkops_null,
2365 .parent = &sys_ck,
2366 .clkdm_name = "wkup_clkdm",
2367 .recalc = &followparent_recalc,
2368};
2369
2370/* 3430ES2 only */
2371/* Never specifically named in the TRM, so we have to infer a likely name */
2372static struct clk usim_ick = {
2373 .name = "usim_ick",
2374 .ops = &clkops_omap2_iclk_dflt_wait,
2375 .parent = &wkup_l4_ick,
2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2377 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2378 .clkdm_name = "wkup_clkdm",
2379 .recalc = &followparent_recalc,
2380};
2381
2382static struct clk wdt2_ick = {
2383 .name = "wdt2_ick",
2384 .ops = &clkops_omap2_iclk_dflt_wait,
2385 .parent = &wkup_l4_ick,
2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2387 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2388 .clkdm_name = "wkup_clkdm",
2389 .recalc = &followparent_recalc,
2390};
2391
2392static struct clk wdt1_ick = {
2393 .name = "wdt1_ick",
2394 .ops = &clkops_omap2_iclk_dflt_wait,
2395 .parent = &wkup_l4_ick,
2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2397 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2398 .clkdm_name = "wkup_clkdm",
2399 .recalc = &followparent_recalc,
2400};
2401
2402static struct clk gpio1_ick = {
2403 .name = "gpio1_ick",
2404 .ops = &clkops_omap2_iclk_dflt_wait,
2405 .parent = &wkup_l4_ick,
2406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2407 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2408 .clkdm_name = "wkup_clkdm",
2409 .recalc = &followparent_recalc,
2410};
2411
2412static struct clk omap_32ksync_ick = {
2413 .name = "omap_32ksync_ick",
2414 .ops = &clkops_omap2_iclk_dflt_wait,
2415 .parent = &wkup_l4_ick,
2416 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2417 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2418 .clkdm_name = "wkup_clkdm",
2419 .recalc = &followparent_recalc,
2420};
2421
2422/* XXX This clock no longer exists in 3430 TRM rev F */
2423static struct clk gpt12_ick = {
2424 .name = "gpt12_ick",
2425 .ops = &clkops_omap2_iclk_dflt_wait,
2426 .parent = &wkup_l4_ick,
2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2428 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2429 .clkdm_name = "wkup_clkdm",
2430 .recalc = &followparent_recalc,
2431};
2432
2433static struct clk gpt1_ick = {
2434 .name = "gpt1_ick",
2435 .ops = &clkops_omap2_iclk_dflt_wait,
2436 .parent = &wkup_l4_ick,
2437 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2438 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2439 .clkdm_name = "wkup_clkdm",
2440 .recalc = &followparent_recalc,
2441};
2442
2443
2444
2445/* PER clock domain */
2446
2447static struct clk per_96m_fck = {
2448 .name = "per_96m_fck",
2449 .ops = &clkops_null,
2450 .parent = &omap_96m_alwon_fck,
2451 .clkdm_name = "per_clkdm",
2452 .recalc = &followparent_recalc,
2453};
2454
2455static struct clk per_48m_fck = {
2456 .name = "per_48m_fck",
2457 .ops = &clkops_null,
2458 .parent = &omap_48m_fck,
2459 .clkdm_name = "per_clkdm",
2460 .recalc = &followparent_recalc,
2461};
2462
2463static struct clk uart3_fck = {
2464 .name = "uart3_fck",
2465 .ops = &clkops_omap2_dflt_wait,
2466 .parent = &per_48m_fck,
2467 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2469 .clkdm_name = "per_clkdm",
2470 .recalc = &followparent_recalc,
2471};
2472
2473static struct clk uart4_fck = {
2474 .name = "uart4_fck",
2475 .ops = &clkops_omap2_dflt_wait,
2476 .parent = &per_48m_fck,
2477 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2478 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2479 .clkdm_name = "per_clkdm",
2480 .recalc = &followparent_recalc,
2481};
2482
2483static struct clk gpt2_fck = {
2484 .name = "gpt2_fck",
2485 .ops = &clkops_omap2_dflt_wait,
2486 .init = &omap2_init_clksel_parent,
2487 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2488 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2489 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2490 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2491 .clksel = omap343x_gpt_clksel,
2492 .clkdm_name = "per_clkdm",
2493 .recalc = &omap2_clksel_recalc,
2494};
2495
2496static struct clk gpt3_fck = {
2497 .name = "gpt3_fck",
2498 .ops = &clkops_omap2_dflt_wait,
2499 .init = &omap2_init_clksel_parent,
2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2501 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2502 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2503 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2504 .clksel = omap343x_gpt_clksel,
2505 .clkdm_name = "per_clkdm",
2506 .recalc = &omap2_clksel_recalc,
2507};
2508
2509static struct clk gpt4_fck = {
2510 .name = "gpt4_fck",
2511 .ops = &clkops_omap2_dflt_wait,
2512 .init = &omap2_init_clksel_parent,
2513 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2514 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2515 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2516 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2517 .clksel = omap343x_gpt_clksel,
2518 .clkdm_name = "per_clkdm",
2519 .recalc = &omap2_clksel_recalc,
2520};
2521
2522static struct clk gpt5_fck = {
2523 .name = "gpt5_fck",
2524 .ops = &clkops_omap2_dflt_wait,
2525 .init = &omap2_init_clksel_parent,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2528 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2530 .clksel = omap343x_gpt_clksel,
2531 .clkdm_name = "per_clkdm",
2532 .recalc = &omap2_clksel_recalc,
2533};
2534
2535static struct clk gpt6_fck = {
2536 .name = "gpt6_fck",
2537 .ops = &clkops_omap2_dflt_wait,
2538 .init = &omap2_init_clksel_parent,
2539 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2540 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2541 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2542 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2543 .clksel = omap343x_gpt_clksel,
2544 .clkdm_name = "per_clkdm",
2545 .recalc = &omap2_clksel_recalc,
2546};
2547
2548static struct clk gpt7_fck = {
2549 .name = "gpt7_fck",
2550 .ops = &clkops_omap2_dflt_wait,
2551 .init = &omap2_init_clksel_parent,
2552 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2553 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2554 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2555 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2556 .clksel = omap343x_gpt_clksel,
2557 .clkdm_name = "per_clkdm",
2558 .recalc = &omap2_clksel_recalc,
2559};
2560
2561static struct clk gpt8_fck = {
2562 .name = "gpt8_fck",
2563 .ops = &clkops_omap2_dflt_wait,
2564 .init = &omap2_init_clksel_parent,
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2567 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2568 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2569 .clksel = omap343x_gpt_clksel,
2570 .clkdm_name = "per_clkdm",
2571 .recalc = &omap2_clksel_recalc,
2572};
2573
2574static struct clk gpt9_fck = {
2575 .name = "gpt9_fck",
2576 .ops = &clkops_omap2_dflt_wait,
2577 .init = &omap2_init_clksel_parent,
2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2580 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2581 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2582 .clksel = omap343x_gpt_clksel,
2583 .clkdm_name = "per_clkdm",
2584 .recalc = &omap2_clksel_recalc,
2585};
2586
2587static struct clk per_32k_alwon_fck = {
2588 .name = "per_32k_alwon_fck",
2589 .ops = &clkops_null,
2590 .parent = &omap_32k_fck,
2591 .clkdm_name = "per_clkdm",
2592 .recalc = &followparent_recalc,
2593};
2594
2595static struct clk gpio6_dbck = {
2596 .name = "gpio6_dbck",
2597 .ops = &clkops_omap2_dflt,
2598 .parent = &per_32k_alwon_fck,
2599 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2600 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2601 .clkdm_name = "per_clkdm",
2602 .recalc = &followparent_recalc,
2603};
2604
2605static struct clk gpio5_dbck = {
2606 .name = "gpio5_dbck",
2607 .ops = &clkops_omap2_dflt,
2608 .parent = &per_32k_alwon_fck,
2609 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2610 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2611 .clkdm_name = "per_clkdm",
2612 .recalc = &followparent_recalc,
2613};
2614
2615static struct clk gpio4_dbck = {
2616 .name = "gpio4_dbck",
2617 .ops = &clkops_omap2_dflt,
2618 .parent = &per_32k_alwon_fck,
2619 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2620 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2621 .clkdm_name = "per_clkdm",
2622 .recalc = &followparent_recalc,
2623};
2624
2625static struct clk gpio3_dbck = {
2626 .name = "gpio3_dbck",
2627 .ops = &clkops_omap2_dflt,
2628 .parent = &per_32k_alwon_fck,
2629 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2630 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2631 .clkdm_name = "per_clkdm",
2632 .recalc = &followparent_recalc,
2633};
2634
2635static struct clk gpio2_dbck = {
2636 .name = "gpio2_dbck",
2637 .ops = &clkops_omap2_dflt,
2638 .parent = &per_32k_alwon_fck,
2639 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2640 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2641 .clkdm_name = "per_clkdm",
2642 .recalc = &followparent_recalc,
2643};
2644
2645static struct clk wdt3_fck = {
2646 .name = "wdt3_fck",
2647 .ops = &clkops_omap2_dflt_wait,
2648 .parent = &per_32k_alwon_fck,
2649 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2650 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2651 .clkdm_name = "per_clkdm",
2652 .recalc = &followparent_recalc,
2653};
2654
2655static struct clk per_l4_ick = {
2656 .name = "per_l4_ick",
2657 .ops = &clkops_null,
2658 .parent = &l4_ick,
2659 .clkdm_name = "per_clkdm",
2660 .recalc = &followparent_recalc,
2661};
2662
2663static struct clk gpio6_ick = {
2664 .name = "gpio6_ick",
2665 .ops = &clkops_omap2_iclk_dflt_wait,
2666 .parent = &per_l4_ick,
2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2668 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2669 .clkdm_name = "per_clkdm",
2670 .recalc = &followparent_recalc,
2671};
2672
2673static struct clk gpio5_ick = {
2674 .name = "gpio5_ick",
2675 .ops = &clkops_omap2_iclk_dflt_wait,
2676 .parent = &per_l4_ick,
2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2678 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2679 .clkdm_name = "per_clkdm",
2680 .recalc = &followparent_recalc,
2681};
2682
2683static struct clk gpio4_ick = {
2684 .name = "gpio4_ick",
2685 .ops = &clkops_omap2_iclk_dflt_wait,
2686 .parent = &per_l4_ick,
2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2688 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2689 .clkdm_name = "per_clkdm",
2690 .recalc = &followparent_recalc,
2691};
2692
2693static struct clk gpio3_ick = {
2694 .name = "gpio3_ick",
2695 .ops = &clkops_omap2_iclk_dflt_wait,
2696 .parent = &per_l4_ick,
2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2698 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2699 .clkdm_name = "per_clkdm",
2700 .recalc = &followparent_recalc,
2701};
2702
2703static struct clk gpio2_ick = {
2704 .name = "gpio2_ick",
2705 .ops = &clkops_omap2_iclk_dflt_wait,
2706 .parent = &per_l4_ick,
2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2708 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2709 .clkdm_name = "per_clkdm",
2710 .recalc = &followparent_recalc,
2711};
2712
2713static struct clk wdt3_ick = {
2714 .name = "wdt3_ick",
2715 .ops = &clkops_omap2_iclk_dflt_wait,
2716 .parent = &per_l4_ick,
2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2718 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2719 .clkdm_name = "per_clkdm",
2720 .recalc = &followparent_recalc,
2721};
2722
2723static struct clk uart3_ick = {
2724 .name = "uart3_ick",
2725 .ops = &clkops_omap2_iclk_dflt_wait,
2726 .parent = &per_l4_ick,
2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2728 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2729 .clkdm_name = "per_clkdm",
2730 .recalc = &followparent_recalc,
2731};
2732
2733static struct clk uart4_ick = {
2734 .name = "uart4_ick",
2735 .ops = &clkops_omap2_iclk_dflt_wait,
2736 .parent = &per_l4_ick,
2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2738 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2739 .clkdm_name = "per_clkdm",
2740 .recalc = &followparent_recalc,
2741};
2742
2743static struct clk gpt9_ick = {
2744 .name = "gpt9_ick",
2745 .ops = &clkops_omap2_iclk_dflt_wait,
2746 .parent = &per_l4_ick,
2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2748 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2749 .clkdm_name = "per_clkdm",
2750 .recalc = &followparent_recalc,
2751};
2752
2753static struct clk gpt8_ick = {
2754 .name = "gpt8_ick",
2755 .ops = &clkops_omap2_iclk_dflt_wait,
2756 .parent = &per_l4_ick,
2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2758 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2759 .clkdm_name = "per_clkdm",
2760 .recalc = &followparent_recalc,
2761};
2762
2763static struct clk gpt7_ick = {
2764 .name = "gpt7_ick",
2765 .ops = &clkops_omap2_iclk_dflt_wait,
2766 .parent = &per_l4_ick,
2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2768 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2769 .clkdm_name = "per_clkdm",
2770 .recalc = &followparent_recalc,
2771};
2772
2773static struct clk gpt6_ick = {
2774 .name = "gpt6_ick",
2775 .ops = &clkops_omap2_iclk_dflt_wait,
2776 .parent = &per_l4_ick,
2777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2778 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2779 .clkdm_name = "per_clkdm",
2780 .recalc = &followparent_recalc,
2781};
2782
2783static struct clk gpt5_ick = {
2784 .name = "gpt5_ick",
2785 .ops = &clkops_omap2_iclk_dflt_wait,
2786 .parent = &per_l4_ick,
2787 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2788 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2789 .clkdm_name = "per_clkdm",
2790 .recalc = &followparent_recalc,
2791};
2792
2793static struct clk gpt4_ick = {
2794 .name = "gpt4_ick",
2795 .ops = &clkops_omap2_iclk_dflt_wait,
2796 .parent = &per_l4_ick,
2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2798 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2799 .clkdm_name = "per_clkdm",
2800 .recalc = &followparent_recalc,
2801};
2802
2803static struct clk gpt3_ick = {
2804 .name = "gpt3_ick",
2805 .ops = &clkops_omap2_iclk_dflt_wait,
2806 .parent = &per_l4_ick,
2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2808 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2809 .clkdm_name = "per_clkdm",
2810 .recalc = &followparent_recalc,
2811};
2812
2813static struct clk gpt2_ick = {
2814 .name = "gpt2_ick",
2815 .ops = &clkops_omap2_iclk_dflt_wait,
2816 .parent = &per_l4_ick,
2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2818 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2819 .clkdm_name = "per_clkdm",
2820 .recalc = &followparent_recalc,
2821};
2822
2823static struct clk mcbsp2_ick = {
2824 .name = "mcbsp2_ick",
2825 .ops = &clkops_omap2_iclk_dflt_wait,
2826 .parent = &per_l4_ick,
2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2829 .clkdm_name = "per_clkdm",
2830 .recalc = &followparent_recalc,
2831};
2832
2833static struct clk mcbsp3_ick = {
2834 .name = "mcbsp3_ick",
2835 .ops = &clkops_omap2_iclk_dflt_wait,
2836 .parent = &per_l4_ick,
2837 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2838 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2839 .clkdm_name = "per_clkdm",
2840 .recalc = &followparent_recalc,
2841};
2842
2843static struct clk mcbsp4_ick = {
2844 .name = "mcbsp4_ick",
2845 .ops = &clkops_omap2_iclk_dflt_wait,
2846 .parent = &per_l4_ick,
2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2849 .clkdm_name = "per_clkdm",
2850 .recalc = &followparent_recalc,
2851};
2852
2853static const struct clksel mcbsp_234_clksel[] = {
2854 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2855 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2856 { .parent = NULL }
2857};
2858
2859static struct clk mcbsp2_fck = {
2860 .name = "mcbsp2_fck",
2861 .ops = &clkops_omap2_dflt_wait,
2862 .init = &omap2_init_clksel_parent,
2863 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2864 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2865 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2866 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2867 .clksel = mcbsp_234_clksel,
2868 .clkdm_name = "per_clkdm",
2869 .recalc = &omap2_clksel_recalc,
2870};
2871
2872static struct clk mcbsp3_fck = {
2873 .name = "mcbsp3_fck",
2874 .ops = &clkops_omap2_dflt_wait,
2875 .init = &omap2_init_clksel_parent,
2876 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2877 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2878 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2879 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2880 .clksel = mcbsp_234_clksel,
2881 .clkdm_name = "per_clkdm",
2882 .recalc = &omap2_clksel_recalc,
2883};
2884
2885static struct clk mcbsp4_fck = {
2886 .name = "mcbsp4_fck",
2887 .ops = &clkops_omap2_dflt_wait,
2888 .init = &omap2_init_clksel_parent,
2889 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2890 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2891 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2892 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2893 .clksel = mcbsp_234_clksel,
2894 .clkdm_name = "per_clkdm",
2895 .recalc = &omap2_clksel_recalc,
2896};
2897
2898/* EMU clocks */
2899
2900/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2901
2902static const struct clksel_rate emu_src_sys_rates[] = {
2903 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2904 { .div = 0 },
2905};
2906
2907static const struct clksel_rate emu_src_core_rates[] = {
2908 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2909 { .div = 0 },
2910};
2911
2912static const struct clksel_rate emu_src_per_rates[] = {
2913 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2914 { .div = 0 },
2915};
2916
2917static const struct clksel_rate emu_src_mpu_rates[] = {
2918 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2919 { .div = 0 },
2920};
2921
2922static const struct clksel emu_src_clksel[] = {
2923 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2924 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2925 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2926 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2927 { .parent = NULL },
2928};
2929
2930/*
2931 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2932 * to switch the source of some of the EMU clocks.
2933 * XXX Are there CLKEN bits for these EMU clks?
2934 */
2935static struct clk emu_src_ck = {
2936 .name = "emu_src_ck",
2937 .ops = &clkops_null,
2938 .init = &omap2_init_clksel_parent,
2939 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2940 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2941 .clksel = emu_src_clksel,
2942 .clkdm_name = "emu_clkdm",
2943 .recalc = &omap2_clksel_recalc,
2944};
2945
2946static const struct clksel_rate pclk_emu_rates[] = {
2947 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2948 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2949 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2950 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2951 { .div = 0 },
2952};
2953
2954static const struct clksel pclk_emu_clksel[] = {
2955 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2956 { .parent = NULL },
2957};
2958
2959static struct clk pclk_fck = {
2960 .name = "pclk_fck",
2961 .ops = &clkops_null,
2962 .init = &omap2_init_clksel_parent,
2963 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2964 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2965 .clksel = pclk_emu_clksel,
2966 .clkdm_name = "emu_clkdm",
2967 .recalc = &omap2_clksel_recalc,
2968};
2969
2970static const struct clksel_rate pclkx2_emu_rates[] = {
2971 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2972 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2973 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2974 { .div = 0 },
2975};
2976
2977static const struct clksel pclkx2_emu_clksel[] = {
2978 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2979 { .parent = NULL },
2980};
2981
2982static struct clk pclkx2_fck = {
2983 .name = "pclkx2_fck",
2984 .ops = &clkops_null,
2985 .init = &omap2_init_clksel_parent,
2986 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2987 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2988 .clksel = pclkx2_emu_clksel,
2989 .clkdm_name = "emu_clkdm",
2990 .recalc = &omap2_clksel_recalc,
2991};
2992
2993static const struct clksel atclk_emu_clksel[] = {
2994 { .parent = &emu_src_ck, .rates = div2_rates },
2995 { .parent = NULL },
2996};
2997
2998static struct clk atclk_fck = {
2999 .name = "atclk_fck",
3000 .ops = &clkops_null,
3001 .init = &omap2_init_clksel_parent,
3002 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3003 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3004 .clksel = atclk_emu_clksel,
3005 .clkdm_name = "emu_clkdm",
3006 .recalc = &omap2_clksel_recalc,
3007};
3008
3009static struct clk traceclk_src_fck = {
3010 .name = "traceclk_src_fck",
3011 .ops = &clkops_null,
3012 .init = &omap2_init_clksel_parent,
3013 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3014 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3015 .clksel = emu_src_clksel,
3016 .clkdm_name = "emu_clkdm",
3017 .recalc = &omap2_clksel_recalc,
3018};
3019
3020static const struct clksel_rate traceclk_rates[] = {
3021 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3022 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3023 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3024 { .div = 0 },
3025};
3026
3027static const struct clksel traceclk_clksel[] = {
3028 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3029 { .parent = NULL },
3030};
3031
3032static struct clk traceclk_fck = {
3033 .name = "traceclk_fck",
3034 .ops = &clkops_null,
3035 .init = &omap2_init_clksel_parent,
3036 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3037 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3038 .clksel = traceclk_clksel,
3039 .clkdm_name = "emu_clkdm",
3040 .recalc = &omap2_clksel_recalc,
3041};
3042
3043/* SR clocks */
3044
3045/* SmartReflex fclk (VDD1) */
3046static struct clk sr1_fck = {
3047 .name = "sr1_fck",
3048 .ops = &clkops_omap2_dflt_wait,
3049 .parent = &sys_ck,
3050 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3051 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3052 .clkdm_name = "wkup_clkdm",
3053 .recalc = &followparent_recalc,
3054};
3055
3056/* SmartReflex fclk (VDD2) */
3057static struct clk sr2_fck = {
3058 .name = "sr2_fck",
3059 .ops = &clkops_omap2_dflt_wait,
3060 .parent = &sys_ck,
3061 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3062 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3063 .clkdm_name = "wkup_clkdm",
3064 .recalc = &followparent_recalc,
3065};
3066
3067static struct clk sr_l4_ick = {
3068 .name = "sr_l4_ick",
3069 .ops = &clkops_null, /* RMK: missing? */
3070 .parent = &l4_ick,
3071 .clkdm_name = "core_l4_clkdm",
3072 .recalc = &followparent_recalc,
3073};
3074
3075/* SECURE_32K_FCK clocks */
3076
3077static struct clk gpt12_fck = {
3078 .name = "gpt12_fck",
3079 .ops = &clkops_null,
3080 .parent = &secure_32k_fck,
3081 .clkdm_name = "wkup_clkdm",
3082 .recalc = &followparent_recalc,
3083};
3084
3085static struct clk wdt1_fck = {
3086 .name = "wdt1_fck",
3087 .ops = &clkops_null,
3088 .parent = &secure_32k_fck,
3089 .clkdm_name = "wkup_clkdm",
3090 .recalc = &followparent_recalc,
3091};
3092
3093/* Clocks for AM35XX */
3094static struct clk ipss_ick = {
3095 .name = "ipss_ick",
3096 .ops = &clkops_am35xx_ipss_wait,
3097 .parent = &core_l3_ick,
3098 .clkdm_name = "core_l3_clkdm",
3099 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3100 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3101 .recalc = &followparent_recalc,
3102};
3103
3104static struct clk emac_ick = {
3105 .name = "emac_ick",
3106 .ops = &clkops_am35xx_ipss_module_wait,
3107 .parent = &ipss_ick,
3108 .clkdm_name = "core_l3_clkdm",
3109 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3110 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3111 .recalc = &followparent_recalc,
3112};
3113
3114static struct clk rmii_ck = {
3115 .name = "rmii_ck",
3116 .ops = &clkops_null,
3117 .rate = 50000000,
3118};
3119
3120static struct clk emac_fck = {
3121 .name = "emac_fck",
3122 .ops = &clkops_omap2_dflt,
3123 .parent = &rmii_ck,
3124 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3125 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3126 .recalc = &followparent_recalc,
3127};
3128
3129static struct clk hsotgusb_ick_am35xx = {
3130 .name = "hsotgusb_ick",
3131 .ops = &clkops_am35xx_ipss_module_wait,
3132 .parent = &ipss_ick,
3133 .clkdm_name = "core_l3_clkdm",
3134 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3135 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3136 .recalc = &followparent_recalc,
3137};
3138
3139static struct clk hsotgusb_fck_am35xx = {
3140 .name = "hsotgusb_fck",
3141 .ops = &clkops_omap2_dflt,
3142 .parent = &sys_ck,
3143 .clkdm_name = "core_l3_clkdm",
3144 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3145 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3146 .recalc = &followparent_recalc,
3147};
3148
3149static struct clk hecc_ck = {
3150 .name = "hecc_ck",
3151 .ops = &clkops_am35xx_ipss_module_wait,
3152 .parent = &sys_ck,
3153 .clkdm_name = "core_l3_clkdm",
3154 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3155 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3156 .recalc = &followparent_recalc,
3157};
3158
3159static struct clk vpfe_ick = {
3160 .name = "vpfe_ick",
3161 .ops = &clkops_am35xx_ipss_module_wait,
3162 .parent = &ipss_ick,
3163 .clkdm_name = "core_l3_clkdm",
3164 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3165 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3166 .recalc = &followparent_recalc,
3167};
3168
3169static struct clk pclk_ck = {
3170 .name = "pclk_ck",
3171 .ops = &clkops_null,
3172 .rate = 27000000,
3173};
3174
3175static struct clk vpfe_fck = {
3176 .name = "vpfe_fck",
3177 .ops = &clkops_omap2_dflt,
3178 .parent = &pclk_ck,
3179 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3180 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3181 .recalc = &followparent_recalc,
3182};
3183
3184/*
3185 * The UART1/2 functional clock acts as the functional
3186 * clock for UART4. No separate fclk control available.
3187 */
3188static struct clk uart4_ick_am35xx = {
3189 .name = "uart4_ick",
3190 .ops = &clkops_omap2_iclk_dflt_wait,
3191 .parent = &core_l4_ick,
3192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3193 .enable_bit = AM35XX_EN_UART4_SHIFT,
3194 .clkdm_name = "core_l4_clkdm",
3195 .recalc = &followparent_recalc,
3196};
3197
3198static struct clk dummy_apb_pclk = {
3199 .name = "apb_pclk",
3200 .ops = &clkops_null,
3201};
3202
3203/*
3204 * clkdev
3205 */
3206
3207/* XXX At some point we should rename this file to clock3xxx_data.c */
3208static struct omap_clk omap3xxx_clks[] = {
3209 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3210 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3211 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3212 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3213 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3214 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3215 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3216 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3217 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3218 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3219 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3220 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3221 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3222 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3223 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3224 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3225 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3226 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3227 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3228 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3229 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3230 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3231 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3232 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3233 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3234 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3235 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3236 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3237 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3238 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3239 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3240 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3241 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3242 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3243 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3244 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3245 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3246 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3247 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3248 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3249 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3250 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3251 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3252 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3253 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3254 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3255 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3258 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3259 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3260 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3261 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3262 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3263 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3264 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3265 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3266 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3267 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3268 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3269 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3270 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3271 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3272 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3273 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3274 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3275 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3276 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3277 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3278 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3279 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3280 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3281 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3282 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3283 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3284 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3285 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3286 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3287 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3288 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3292 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3293 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3294 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3295 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3296 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3297 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3298 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3299 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3300 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3301 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3302 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3303 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3304 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3305 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3306 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3307 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3308 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3309 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3310 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3311 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3312 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3313 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3314 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3315 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3317 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3318 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3319 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3320 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3321 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3322 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3323 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3324 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3325 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3327 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3328 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3329 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3330 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3331 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3332 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3333 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3334 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3335 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3336 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3337 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3338 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3339 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3340 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3341 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3342 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3343 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3344 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3345 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3346 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3347 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3348 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3349 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3350 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3351 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3352 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3353 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3354 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3355 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3356 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3357 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3358 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3359 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3360 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3361 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3362 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3363 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3364 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3365 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3366 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3367 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3368 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3369 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3370 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3371 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3372 CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3373 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374 CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3375 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3376 CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3377 CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3378 CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3379 CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3380 CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3381 CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3382 CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3383 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3384 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3385 CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX),
3386 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3387 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3388 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3389 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3390 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3391 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3392 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3393 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3394 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3395 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3396 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3397 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3398 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3399 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3400 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3401 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3402 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3403 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3404 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3405 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3406 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3407 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3408 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3409 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3410 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3411 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3412 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3413 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3414 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3415 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3416 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3417 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3418 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3419 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3420 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3421 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3422 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3423 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3424 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3425 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3426 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3427 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3428 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3429 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3430 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3431 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3432 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3433 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3434 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3435 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3436 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3437 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3438 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3439 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3440 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3441 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3442 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3443 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3444 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3445 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3446 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3447 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3448 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3449 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3450 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3451 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3452 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3453 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3454 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3455 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3456 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3457 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3458 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3459 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3460 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3461 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3462 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3463 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3464 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3465 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3466 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3467};
3468
3469
3470int __init omap3xxx_clk_init(void)
3471{
3472 struct omap_clk *c;
3473 u32 cpu_clkflg = 0;
3474
3475 if (cpu_is_omap3517()) {
3476 cpu_mask = RATE_IN_34XX;
3477 cpu_clkflg = CK_3517;
3478 } else if (cpu_is_omap3505()) {
3479 cpu_mask = RATE_IN_34XX;
3480 cpu_clkflg = CK_3505;
3481 } else if (cpu_is_omap3630()) {
3482 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3483 cpu_clkflg = CK_36XX;
3484 } else if (cpu_is_ti816x()) {
3485 cpu_mask = RATE_IN_TI816X;
3486 cpu_clkflg = CK_TI816X;
3487 } else if (cpu_is_omap34xx()) {
3488 if (omap_rev() == OMAP3430_REV_ES1_0) {
3489 cpu_mask = RATE_IN_3430ES1;
3490 cpu_clkflg = CK_3430ES1;
3491 } else {
3492 /*
3493 * Assume that anything that we haven't matched yet
3494 * has 3430ES2-type clocks.
3495 */
3496 cpu_mask = RATE_IN_3430ES2PLUS;
3497 cpu_clkflg = CK_3430ES2PLUS;
3498 }
3499 } else {
3500 WARN(1, "clock: could not identify OMAP3 variant\n");
3501 }
3502
3503 if (omap3_has_192mhz_clk())
3504 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3505
3506 if (cpu_is_omap3630()) {
3507 /*
3508 * XXX This type of dynamic rewriting of the clock tree is
3509 * deprecated and should be revised soon.
3510 *
3511 * For 3630: override clkops_omap2_dflt_wait for the
3512 * clocks affected from PWRDN reset Limitation
3513 */
3514 dpll3_m3x2_ck.ops =
3515 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3516 dpll4_m2x2_ck.ops =
3517 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3518 dpll4_m3x2_ck.ops =
3519 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3520 dpll4_m4x2_ck.ops =
3521 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3522 dpll4_m5x2_ck.ops =
3523 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3524 dpll4_m6x2_ck.ops =
3525 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3526 }
3527
3528 /*
3529 * XXX This type of dynamic rewriting of the clock tree is
3530 * deprecated and should be revised soon.
3531 */
3532 if (cpu_is_omap3630())
3533 dpll4_dd = dpll4_dd_3630;
3534 else
3535 dpll4_dd = dpll4_dd_34xx;
3536
3537 clk_init(&omap2_clk_functions);
3538
3539 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3540 c++)
3541 clk_preinit(c->lk.clk);
3542
3543 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3544 c++)
3545 if (c->cpu & cpu_clkflg) {
3546 clkdev_add(&c->lk);
3547 clk_register(c->lk.clk);
3548 omap2_init_clk_clkdm(c->lk.clk);
3549 }
3550
3551 /* Disable autoidle on all clocks; let the PM code enable it later */
3552 omap_clk_disable_autoidle_all();
3553
3554 recalculate_root_clocks();
3555
3556 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3557 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3558 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3559
3560 /*
3561 * Only enable those clocks we will need, let the drivers
3562 * enable other clocks as necessary
3563 */
3564 clk_enable_init_clocks();
3565
3566 /*
3567 * Lock DPLL5 -- here only until other device init code can
3568 * handle this
3569 */
3570 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3571 omap3_clk_lock_dpll5();
3572
3573 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3574 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3575 arm_fck_p = clk_get(NULL, "arm_fck");
3576
3577 return 0;
3578}
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
new file mode 100644
index 00000000000..c0b6fbda340
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -0,0 +1,3416 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
24 */
25
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/clk.h>
29#include <plat/clkdev_omap.h>
30
31#include "clock.h"
32#include "clock44xx.h"
33#include "cm1_44xx.h"
34#include "cm2_44xx.h"
35#include "cm-regbits-44xx.h"
36#include "prm44xx.h"
37#include "prm-regbits-44xx.h"
38#include "control.h"
39#include "scrm44xx.h"
40
41/* OMAP4 modulemode control */
42#define OMAP4430_MODULEMODE_HWCTRL 0
43#define OMAP4430_MODULEMODE_SWCTRL 1
44
45/* Root clocks */
46
47static struct clk extalt_clkin_ck = {
48 .name = "extalt_clkin_ck",
49 .rate = 59000000,
50 .ops = &clkops_null,
51};
52
53static struct clk pad_clks_ck = {
54 .name = "pad_clks_ck",
55 .rate = 12000000,
56 .ops = &clkops_omap2_dflt,
57 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
59};
60
61static struct clk pad_slimbus_core_clks_ck = {
62 .name = "pad_slimbus_core_clks_ck",
63 .rate = 12000000,
64 .ops = &clkops_null,
65};
66
67static struct clk secure_32k_clk_src_ck = {
68 .name = "secure_32k_clk_src_ck",
69 .rate = 32768,
70 .ops = &clkops_null,
71};
72
73static struct clk slimbus_clk = {
74 .name = "slimbus_clk",
75 .rate = 12000000,
76 .ops = &clkops_omap2_dflt,
77 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
79};
80
81static struct clk sys_32k_ck = {
82 .name = "sys_32k_ck",
83 .rate = 32768,
84 .ops = &clkops_null,
85};
86
87static struct clk virt_12000000_ck = {
88 .name = "virt_12000000_ck",
89 .ops = &clkops_null,
90 .rate = 12000000,
91};
92
93static struct clk virt_13000000_ck = {
94 .name = "virt_13000000_ck",
95 .ops = &clkops_null,
96 .rate = 13000000,
97};
98
99static struct clk virt_16800000_ck = {
100 .name = "virt_16800000_ck",
101 .ops = &clkops_null,
102 .rate = 16800000,
103};
104
105static struct clk virt_19200000_ck = {
106 .name = "virt_19200000_ck",
107 .ops = &clkops_null,
108 .rate = 19200000,
109};
110
111static struct clk virt_26000000_ck = {
112 .name = "virt_26000000_ck",
113 .ops = &clkops_null,
114 .rate = 26000000,
115};
116
117static struct clk virt_27000000_ck = {
118 .name = "virt_27000000_ck",
119 .ops = &clkops_null,
120 .rate = 27000000,
121};
122
123static struct clk virt_38400000_ck = {
124 .name = "virt_38400000_ck",
125 .ops = &clkops_null,
126 .rate = 38400000,
127};
128
129static const struct clksel_rate div_1_0_rates[] = {
130 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
131 { .div = 0 },
132};
133
134static const struct clksel_rate div_1_1_rates[] = {
135 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
136 { .div = 0 },
137};
138
139static const struct clksel_rate div_1_2_rates[] = {
140 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
141 { .div = 0 },
142};
143
144static const struct clksel_rate div_1_3_rates[] = {
145 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
146 { .div = 0 },
147};
148
149static const struct clksel_rate div_1_4_rates[] = {
150 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
151 { .div = 0 },
152};
153
154static const struct clksel_rate div_1_5_rates[] = {
155 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
156 { .div = 0 },
157};
158
159static const struct clksel_rate div_1_6_rates[] = {
160 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
161 { .div = 0 },
162};
163
164static const struct clksel_rate div_1_7_rates[] = {
165 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
166 { .div = 0 },
167};
168
169static const struct clksel sys_clkin_sel[] = {
170 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
171 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
172 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
173 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
174 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
175 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
176 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
177 { .parent = NULL },
178};
179
180static struct clk sys_clkin_ck = {
181 .name = "sys_clkin_ck",
182 .rate = 38400000,
183 .clksel = sys_clkin_sel,
184 .init = &omap2_init_clksel_parent,
185 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
186 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
187 .ops = &clkops_null,
188 .recalc = &omap2_clksel_recalc,
189};
190
191static struct clk tie_low_clock_ck = {
192 .name = "tie_low_clock_ck",
193 .rate = 0,
194 .ops = &clkops_null,
195};
196
197static struct clk utmi_phy_clkout_ck = {
198 .name = "utmi_phy_clkout_ck",
199 .rate = 60000000,
200 .ops = &clkops_null,
201};
202
203static struct clk xclk60mhsp1_ck = {
204 .name = "xclk60mhsp1_ck",
205 .rate = 60000000,
206 .ops = &clkops_null,
207};
208
209static struct clk xclk60mhsp2_ck = {
210 .name = "xclk60mhsp2_ck",
211 .rate = 60000000,
212 .ops = &clkops_null,
213};
214
215static struct clk xclk60motg_ck = {
216 .name = "xclk60motg_ck",
217 .rate = 60000000,
218 .ops = &clkops_null,
219};
220
221/* Module clocks and DPLL outputs */
222
223static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
224 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
225 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
226 { .parent = NULL },
227};
228
229static struct clk abe_dpll_bypass_clk_mux_ck = {
230 .name = "abe_dpll_bypass_clk_mux_ck",
231 .parent = &sys_clkin_ck,
232 .ops = &clkops_null,
233 .recalc = &followparent_recalc,
234};
235
236static struct clk abe_dpll_refclk_mux_ck = {
237 .name = "abe_dpll_refclk_mux_ck",
238 .parent = &sys_clkin_ck,
239 .clksel = abe_dpll_bypass_clk_mux_sel,
240 .init = &omap2_init_clksel_parent,
241 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
242 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
243 .ops = &clkops_null,
244 .recalc = &omap2_clksel_recalc,
245};
246
247/* DPLL_ABE */
248static struct dpll_data dpll_abe_dd = {
249 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
250 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
251 .clk_ref = &abe_dpll_refclk_mux_ck,
252 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
253 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
254 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
255 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
256 .mult_mask = OMAP4430_DPLL_MULT_MASK,
257 .div1_mask = OMAP4430_DPLL_DIV_MASK,
258 .enable_mask = OMAP4430_DPLL_EN_MASK,
259 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
260 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
261 .max_multiplier = 2047,
262 .max_divider = 128,
263 .min_divider = 1,
264};
265
266
267static struct clk dpll_abe_ck = {
268 .name = "dpll_abe_ck",
269 .parent = &abe_dpll_refclk_mux_ck,
270 .dpll_data = &dpll_abe_dd,
271 .init = &omap2_init_dpll_parent,
272 .ops = &clkops_omap3_noncore_dpll_ops,
273 .recalc = &omap3_dpll_recalc,
274 .round_rate = &omap2_dpll_round_rate,
275 .set_rate = &omap3_noncore_dpll_set_rate,
276};
277
278static struct clk dpll_abe_x2_ck = {
279 .name = "dpll_abe_x2_ck",
280 .parent = &dpll_abe_ck,
281 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
282 .flags = CLOCK_CLKOUTX2,
283 .ops = &clkops_omap4_dpllmx_ops,
284 .recalc = &omap3_clkoutx2_recalc,
285};
286
287static const struct clksel_rate div31_1to31_rates[] = {
288 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
289 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
290 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
291 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
292 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
293 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
294 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
295 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
296 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
297 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
298 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
299 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
300 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
301 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
302 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
303 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
304 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
305 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
306 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
307 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
308 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
309 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
310 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
311 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
312 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
313 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
314 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
315 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
316 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
317 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
318 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
319 { .div = 0 },
320};
321
322static const struct clksel dpll_abe_m2x2_div[] = {
323 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
324 { .parent = NULL },
325};
326
327static struct clk dpll_abe_m2x2_ck = {
328 .name = "dpll_abe_m2x2_ck",
329 .parent = &dpll_abe_x2_ck,
330 .clksel = dpll_abe_m2x2_div,
331 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
332 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
333 .ops = &clkops_omap4_dpllmx_ops,
334 .recalc = &omap2_clksel_recalc,
335 .round_rate = &omap2_clksel_round_rate,
336 .set_rate = &omap2_clksel_set_rate,
337};
338
339static struct clk abe_24m_fclk = {
340 .name = "abe_24m_fclk",
341 .parent = &dpll_abe_m2x2_ck,
342 .ops = &clkops_null,
343 .fixed_div = 8,
344 .recalc = &omap_fixed_divisor_recalc,
345};
346
347static const struct clksel_rate div3_1to4_rates[] = {
348 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
349 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
350 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
351 { .div = 0 },
352};
353
354static const struct clksel abe_clk_div[] = {
355 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
356 { .parent = NULL },
357};
358
359static struct clk abe_clk = {
360 .name = "abe_clk",
361 .parent = &dpll_abe_m2x2_ck,
362 .clksel = abe_clk_div,
363 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
364 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
365 .ops = &clkops_null,
366 .recalc = &omap2_clksel_recalc,
367 .round_rate = &omap2_clksel_round_rate,
368 .set_rate = &omap2_clksel_set_rate,
369};
370
371static const struct clksel_rate div2_1to2_rates[] = {
372 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
373 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
374 { .div = 0 },
375};
376
377static const struct clksel aess_fclk_div[] = {
378 { .parent = &abe_clk, .rates = div2_1to2_rates },
379 { .parent = NULL },
380};
381
382static struct clk aess_fclk = {
383 .name = "aess_fclk",
384 .parent = &abe_clk,
385 .clksel = aess_fclk_div,
386 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
387 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
388 .ops = &clkops_null,
389 .recalc = &omap2_clksel_recalc,
390 .round_rate = &omap2_clksel_round_rate,
391 .set_rate = &omap2_clksel_set_rate,
392};
393
394static struct clk dpll_abe_m3x2_ck = {
395 .name = "dpll_abe_m3x2_ck",
396 .parent = &dpll_abe_x2_ck,
397 .clksel = dpll_abe_m2x2_div,
398 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
399 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
400 .ops = &clkops_omap4_dpllmx_ops,
401 .recalc = &omap2_clksel_recalc,
402 .round_rate = &omap2_clksel_round_rate,
403 .set_rate = &omap2_clksel_set_rate,
404};
405
406static const struct clksel core_hsd_byp_clk_mux_sel[] = {
407 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
408 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
409 { .parent = NULL },
410};
411
412static struct clk core_hsd_byp_clk_mux_ck = {
413 .name = "core_hsd_byp_clk_mux_ck",
414 .parent = &sys_clkin_ck,
415 .clksel = core_hsd_byp_clk_mux_sel,
416 .init = &omap2_init_clksel_parent,
417 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
418 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
419 .ops = &clkops_null,
420 .recalc = &omap2_clksel_recalc,
421};
422
423/* DPLL_CORE */
424static struct dpll_data dpll_core_dd = {
425 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
426 .clk_bypass = &core_hsd_byp_clk_mux_ck,
427 .clk_ref = &sys_clkin_ck,
428 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
429 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
430 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
431 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
432 .mult_mask = OMAP4430_DPLL_MULT_MASK,
433 .div1_mask = OMAP4430_DPLL_DIV_MASK,
434 .enable_mask = OMAP4430_DPLL_EN_MASK,
435 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
436 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
437 .max_multiplier = 2047,
438 .max_divider = 128,
439 .min_divider = 1,
440};
441
442
443static struct clk dpll_core_ck = {
444 .name = "dpll_core_ck",
445 .parent = &sys_clkin_ck,
446 .dpll_data = &dpll_core_dd,
447 .init = &omap2_init_dpll_parent,
448 .ops = &clkops_omap3_core_dpll_ops,
449 .recalc = &omap3_dpll_recalc,
450};
451
452static struct clk dpll_core_x2_ck = {
453 .name = "dpll_core_x2_ck",
454 .parent = &dpll_core_ck,
455 .flags = CLOCK_CLKOUTX2,
456 .ops = &clkops_null,
457 .recalc = &omap3_clkoutx2_recalc,
458};
459
460static const struct clksel dpll_core_m6x2_div[] = {
461 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
462 { .parent = NULL },
463};
464
465static struct clk dpll_core_m6x2_ck = {
466 .name = "dpll_core_m6x2_ck",
467 .parent = &dpll_core_x2_ck,
468 .clksel = dpll_core_m6x2_div,
469 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
470 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
471 .ops = &clkops_omap4_dpllmx_ops,
472 .recalc = &omap2_clksel_recalc,
473 .round_rate = &omap2_clksel_round_rate,
474 .set_rate = &omap2_clksel_set_rate,
475};
476
477static const struct clksel dbgclk_mux_sel[] = {
478 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
479 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
480 { .parent = NULL },
481};
482
483static struct clk dbgclk_mux_ck = {
484 .name = "dbgclk_mux_ck",
485 .parent = &sys_clkin_ck,
486 .ops = &clkops_null,
487 .recalc = &followparent_recalc,
488};
489
490static const struct clksel dpll_core_m2_div[] = {
491 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
492 { .parent = NULL },
493};
494
495static struct clk dpll_core_m2_ck = {
496 .name = "dpll_core_m2_ck",
497 .parent = &dpll_core_ck,
498 .clksel = dpll_core_m2_div,
499 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
500 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
501 .ops = &clkops_omap4_dpllmx_ops,
502 .recalc = &omap2_clksel_recalc,
503 .round_rate = &omap2_clksel_round_rate,
504 .set_rate = &omap2_clksel_set_rate,
505};
506
507static struct clk ddrphy_ck = {
508 .name = "ddrphy_ck",
509 .parent = &dpll_core_m2_ck,
510 .ops = &clkops_null,
511 .fixed_div = 2,
512 .recalc = &omap_fixed_divisor_recalc,
513};
514
515static struct clk dpll_core_m5x2_ck = {
516 .name = "dpll_core_m5x2_ck",
517 .parent = &dpll_core_x2_ck,
518 .clksel = dpll_core_m6x2_div,
519 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
520 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
521 .ops = &clkops_omap4_dpllmx_ops,
522 .recalc = &omap2_clksel_recalc,
523 .round_rate = &omap2_clksel_round_rate,
524 .set_rate = &omap2_clksel_set_rate,
525};
526
527static const struct clksel div_core_div[] = {
528 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
529 { .parent = NULL },
530};
531
532static struct clk div_core_ck = {
533 .name = "div_core_ck",
534 .parent = &dpll_core_m5x2_ck,
535 .clksel = div_core_div,
536 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
537 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
538 .ops = &clkops_null,
539 .recalc = &omap2_clksel_recalc,
540 .round_rate = &omap2_clksel_round_rate,
541 .set_rate = &omap2_clksel_set_rate,
542};
543
544static const struct clksel_rate div4_1to8_rates[] = {
545 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
546 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
547 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
548 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
549 { .div = 0 },
550};
551
552static const struct clksel div_iva_hs_clk_div[] = {
553 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
554 { .parent = NULL },
555};
556
557static struct clk div_iva_hs_clk = {
558 .name = "div_iva_hs_clk",
559 .parent = &dpll_core_m5x2_ck,
560 .clksel = div_iva_hs_clk_div,
561 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
562 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
563 .ops = &clkops_null,
564 .recalc = &omap2_clksel_recalc,
565 .round_rate = &omap2_clksel_round_rate,
566 .set_rate = &omap2_clksel_set_rate,
567};
568
569static struct clk div_mpu_hs_clk = {
570 .name = "div_mpu_hs_clk",
571 .parent = &dpll_core_m5x2_ck,
572 .clksel = div_iva_hs_clk_div,
573 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
574 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
575 .ops = &clkops_null,
576 .recalc = &omap2_clksel_recalc,
577 .round_rate = &omap2_clksel_round_rate,
578 .set_rate = &omap2_clksel_set_rate,
579};
580
581static struct clk dpll_core_m4x2_ck = {
582 .name = "dpll_core_m4x2_ck",
583 .parent = &dpll_core_x2_ck,
584 .clksel = dpll_core_m6x2_div,
585 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
586 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
587 .ops = &clkops_omap4_dpllmx_ops,
588 .recalc = &omap2_clksel_recalc,
589 .round_rate = &omap2_clksel_round_rate,
590 .set_rate = &omap2_clksel_set_rate,
591};
592
593static struct clk dll_clk_div_ck = {
594 .name = "dll_clk_div_ck",
595 .parent = &dpll_core_m4x2_ck,
596 .ops = &clkops_null,
597 .fixed_div = 2,
598 .recalc = &omap_fixed_divisor_recalc,
599};
600
601static const struct clksel dpll_abe_m2_div[] = {
602 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
603 { .parent = NULL },
604};
605
606static struct clk dpll_abe_m2_ck = {
607 .name = "dpll_abe_m2_ck",
608 .parent = &dpll_abe_ck,
609 .clksel = dpll_abe_m2_div,
610 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
611 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
612 .ops = &clkops_omap4_dpllmx_ops,
613 .recalc = &omap2_clksel_recalc,
614 .round_rate = &omap2_clksel_round_rate,
615 .set_rate = &omap2_clksel_set_rate,
616};
617
618static struct clk dpll_core_m3x2_ck = {
619 .name = "dpll_core_m3x2_ck",
620 .parent = &dpll_core_x2_ck,
621 .clksel = dpll_core_m6x2_div,
622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
624 .ops = &clkops_omap2_dflt,
625 .recalc = &omap2_clksel_recalc,
626 .round_rate = &omap2_clksel_round_rate,
627 .set_rate = &omap2_clksel_set_rate,
628 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
629 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
630};
631
632static struct clk dpll_core_m7x2_ck = {
633 .name = "dpll_core_m7x2_ck",
634 .parent = &dpll_core_x2_ck,
635 .clksel = dpll_core_m6x2_div,
636 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
637 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
638 .ops = &clkops_omap4_dpllmx_ops,
639 .recalc = &omap2_clksel_recalc,
640 .round_rate = &omap2_clksel_round_rate,
641 .set_rate = &omap2_clksel_set_rate,
642};
643
644static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
645 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
646 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
647 { .parent = NULL },
648};
649
650static struct clk iva_hsd_byp_clk_mux_ck = {
651 .name = "iva_hsd_byp_clk_mux_ck",
652 .parent = &sys_clkin_ck,
653 .clksel = iva_hsd_byp_clk_mux_sel,
654 .init = &omap2_init_clksel_parent,
655 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
656 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
657 .ops = &clkops_null,
658 .recalc = &omap2_clksel_recalc,
659};
660
661/* DPLL_IVA */
662static struct dpll_data dpll_iva_dd = {
663 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
664 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
665 .clk_ref = &sys_clkin_ck,
666 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
667 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
668 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
669 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
670 .mult_mask = OMAP4430_DPLL_MULT_MASK,
671 .div1_mask = OMAP4430_DPLL_DIV_MASK,
672 .enable_mask = OMAP4430_DPLL_EN_MASK,
673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
675 .max_multiplier = 2047,
676 .max_divider = 128,
677 .min_divider = 1,
678};
679
680
681static struct clk dpll_iva_ck = {
682 .name = "dpll_iva_ck",
683 .parent = &sys_clkin_ck,
684 .dpll_data = &dpll_iva_dd,
685 .init = &omap2_init_dpll_parent,
686 .ops = &clkops_omap3_noncore_dpll_ops,
687 .recalc = &omap3_dpll_recalc,
688 .round_rate = &omap2_dpll_round_rate,
689 .set_rate = &omap3_noncore_dpll_set_rate,
690};
691
692static struct clk dpll_iva_x2_ck = {
693 .name = "dpll_iva_x2_ck",
694 .parent = &dpll_iva_ck,
695 .flags = CLOCK_CLKOUTX2,
696 .ops = &clkops_null,
697 .recalc = &omap3_clkoutx2_recalc,
698};
699
700static const struct clksel dpll_iva_m4x2_div[] = {
701 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
702 { .parent = NULL },
703};
704
705static struct clk dpll_iva_m4x2_ck = {
706 .name = "dpll_iva_m4x2_ck",
707 .parent = &dpll_iva_x2_ck,
708 .clksel = dpll_iva_m4x2_div,
709 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
710 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
711 .ops = &clkops_omap4_dpllmx_ops,
712 .recalc = &omap2_clksel_recalc,
713 .round_rate = &omap2_clksel_round_rate,
714 .set_rate = &omap2_clksel_set_rate,
715};
716
717static struct clk dpll_iva_m5x2_ck = {
718 .name = "dpll_iva_m5x2_ck",
719 .parent = &dpll_iva_x2_ck,
720 .clksel = dpll_iva_m4x2_div,
721 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
722 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
723 .ops = &clkops_omap4_dpllmx_ops,
724 .recalc = &omap2_clksel_recalc,
725 .round_rate = &omap2_clksel_round_rate,
726 .set_rate = &omap2_clksel_set_rate,
727};
728
729/* DPLL_MPU */
730static struct dpll_data dpll_mpu_dd = {
731 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
732 .clk_bypass = &div_mpu_hs_clk,
733 .clk_ref = &sys_clkin_ck,
734 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
735 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
736 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
737 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
738 .mult_mask = OMAP4430_DPLL_MULT_MASK,
739 .div1_mask = OMAP4430_DPLL_DIV_MASK,
740 .enable_mask = OMAP4430_DPLL_EN_MASK,
741 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
742 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
743 .max_multiplier = 2047,
744 .max_divider = 128,
745 .min_divider = 1,
746};
747
748
749static struct clk dpll_mpu_ck = {
750 .name = "dpll_mpu_ck",
751 .parent = &sys_clkin_ck,
752 .dpll_data = &dpll_mpu_dd,
753 .init = &omap2_init_dpll_parent,
754 .ops = &clkops_omap3_noncore_dpll_ops,
755 .recalc = &omap3_dpll_recalc,
756 .round_rate = &omap2_dpll_round_rate,
757 .set_rate = &omap3_noncore_dpll_set_rate,
758};
759
760static const struct clksel dpll_mpu_m2_div[] = {
761 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
762 { .parent = NULL },
763};
764
765static struct clk dpll_mpu_m2_ck = {
766 .name = "dpll_mpu_m2_ck",
767 .parent = &dpll_mpu_ck,
768 .clksel = dpll_mpu_m2_div,
769 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
770 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
771 .ops = &clkops_omap4_dpllmx_ops,
772 .recalc = &omap2_clksel_recalc,
773 .round_rate = &omap2_clksel_round_rate,
774 .set_rate = &omap2_clksel_set_rate,
775};
776
777static struct clk per_hs_clk_div_ck = {
778 .name = "per_hs_clk_div_ck",
779 .parent = &dpll_abe_m3x2_ck,
780 .ops = &clkops_null,
781 .fixed_div = 2,
782 .recalc = &omap_fixed_divisor_recalc,
783};
784
785static const struct clksel per_hsd_byp_clk_mux_sel[] = {
786 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
787 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
788 { .parent = NULL },
789};
790
791static struct clk per_hsd_byp_clk_mux_ck = {
792 .name = "per_hsd_byp_clk_mux_ck",
793 .parent = &sys_clkin_ck,
794 .clksel = per_hsd_byp_clk_mux_sel,
795 .init = &omap2_init_clksel_parent,
796 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
797 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
798 .ops = &clkops_null,
799 .recalc = &omap2_clksel_recalc,
800};
801
802/* DPLL_PER */
803static struct dpll_data dpll_per_dd = {
804 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
805 .clk_bypass = &per_hsd_byp_clk_mux_ck,
806 .clk_ref = &sys_clkin_ck,
807 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
808 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
809 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
810 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
811 .mult_mask = OMAP4430_DPLL_MULT_MASK,
812 .div1_mask = OMAP4430_DPLL_DIV_MASK,
813 .enable_mask = OMAP4430_DPLL_EN_MASK,
814 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
815 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
816 .max_multiplier = 2047,
817 .max_divider = 128,
818 .min_divider = 1,
819};
820
821
822static struct clk dpll_per_ck = {
823 .name = "dpll_per_ck",
824 .parent = &sys_clkin_ck,
825 .dpll_data = &dpll_per_dd,
826 .init = &omap2_init_dpll_parent,
827 .ops = &clkops_omap3_noncore_dpll_ops,
828 .recalc = &omap3_dpll_recalc,
829 .round_rate = &omap2_dpll_round_rate,
830 .set_rate = &omap3_noncore_dpll_set_rate,
831};
832
833static const struct clksel dpll_per_m2_div[] = {
834 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
835 { .parent = NULL },
836};
837
838static struct clk dpll_per_m2_ck = {
839 .name = "dpll_per_m2_ck",
840 .parent = &dpll_per_ck,
841 .clksel = dpll_per_m2_div,
842 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
843 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
844 .ops = &clkops_omap4_dpllmx_ops,
845 .recalc = &omap2_clksel_recalc,
846 .round_rate = &omap2_clksel_round_rate,
847 .set_rate = &omap2_clksel_set_rate,
848};
849
850static struct clk dpll_per_x2_ck = {
851 .name = "dpll_per_x2_ck",
852 .parent = &dpll_per_ck,
853 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
854 .flags = CLOCK_CLKOUTX2,
855 .ops = &clkops_omap4_dpllmx_ops,
856 .recalc = &omap3_clkoutx2_recalc,
857};
858
859static const struct clksel dpll_per_m2x2_div[] = {
860 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
861 { .parent = NULL },
862};
863
864static struct clk dpll_per_m2x2_ck = {
865 .name = "dpll_per_m2x2_ck",
866 .parent = &dpll_per_x2_ck,
867 .clksel = dpll_per_m2x2_div,
868 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
869 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
870 .ops = &clkops_omap4_dpllmx_ops,
871 .recalc = &omap2_clksel_recalc,
872 .round_rate = &omap2_clksel_round_rate,
873 .set_rate = &omap2_clksel_set_rate,
874};
875
876static struct clk dpll_per_m3x2_ck = {
877 .name = "dpll_per_m3x2_ck",
878 .parent = &dpll_per_x2_ck,
879 .clksel = dpll_per_m2x2_div,
880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
882 .ops = &clkops_omap2_dflt,
883 .recalc = &omap2_clksel_recalc,
884 .round_rate = &omap2_clksel_round_rate,
885 .set_rate = &omap2_clksel_set_rate,
886 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
887 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
888};
889
890static struct clk dpll_per_m4x2_ck = {
891 .name = "dpll_per_m4x2_ck",
892 .parent = &dpll_per_x2_ck,
893 .clksel = dpll_per_m2x2_div,
894 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
895 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
896 .ops = &clkops_omap4_dpllmx_ops,
897 .recalc = &omap2_clksel_recalc,
898 .round_rate = &omap2_clksel_round_rate,
899 .set_rate = &omap2_clksel_set_rate,
900};
901
902static struct clk dpll_per_m5x2_ck = {
903 .name = "dpll_per_m5x2_ck",
904 .parent = &dpll_per_x2_ck,
905 .clksel = dpll_per_m2x2_div,
906 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
907 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
908 .ops = &clkops_omap4_dpllmx_ops,
909 .recalc = &omap2_clksel_recalc,
910 .round_rate = &omap2_clksel_round_rate,
911 .set_rate = &omap2_clksel_set_rate,
912};
913
914static struct clk dpll_per_m6x2_ck = {
915 .name = "dpll_per_m6x2_ck",
916 .parent = &dpll_per_x2_ck,
917 .clksel = dpll_per_m2x2_div,
918 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
919 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
920 .ops = &clkops_omap4_dpllmx_ops,
921 .recalc = &omap2_clksel_recalc,
922 .round_rate = &omap2_clksel_round_rate,
923 .set_rate = &omap2_clksel_set_rate,
924};
925
926static struct clk dpll_per_m7x2_ck = {
927 .name = "dpll_per_m7x2_ck",
928 .parent = &dpll_per_x2_ck,
929 .clksel = dpll_per_m2x2_div,
930 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
931 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
932 .ops = &clkops_omap4_dpllmx_ops,
933 .recalc = &omap2_clksel_recalc,
934 .round_rate = &omap2_clksel_round_rate,
935 .set_rate = &omap2_clksel_set_rate,
936};
937
938static struct clk usb_hs_clk_div_ck = {
939 .name = "usb_hs_clk_div_ck",
940 .parent = &dpll_abe_m3x2_ck,
941 .ops = &clkops_null,
942 .fixed_div = 3,
943 .recalc = &omap_fixed_divisor_recalc,
944};
945
946/* DPLL_USB */
947static struct dpll_data dpll_usb_dd = {
948 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
949 .clk_bypass = &usb_hs_clk_div_ck,
950 .flags = DPLL_J_TYPE,
951 .clk_ref = &sys_clkin_ck,
952 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
953 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
954 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
955 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
956 .mult_mask = OMAP4430_DPLL_MULT_MASK,
957 .div1_mask = OMAP4430_DPLL_DIV_MASK,
958 .enable_mask = OMAP4430_DPLL_EN_MASK,
959 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
960 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
961 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
962 .max_multiplier = 4095,
963 .max_divider = 256,
964 .min_divider = 1,
965};
966
967
968static struct clk dpll_usb_ck = {
969 .name = "dpll_usb_ck",
970 .parent = &sys_clkin_ck,
971 .dpll_data = &dpll_usb_dd,
972 .init = &omap2_init_dpll_parent,
973 .ops = &clkops_omap3_noncore_dpll_ops,
974 .recalc = &omap3_dpll_recalc,
975 .round_rate = &omap2_dpll_round_rate,
976 .set_rate = &omap3_noncore_dpll_set_rate,
977};
978
979static struct clk dpll_usb_clkdcoldo_ck = {
980 .name = "dpll_usb_clkdcoldo_ck",
981 .parent = &dpll_usb_ck,
982 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
983 .ops = &clkops_omap4_dpllmx_ops,
984 .recalc = &followparent_recalc,
985};
986
987static const struct clksel dpll_usb_m2_div[] = {
988 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
989 { .parent = NULL },
990};
991
992static struct clk dpll_usb_m2_ck = {
993 .name = "dpll_usb_m2_ck",
994 .parent = &dpll_usb_ck,
995 .clksel = dpll_usb_m2_div,
996 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
997 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
998 .ops = &clkops_omap4_dpllmx_ops,
999 .recalc = &omap2_clksel_recalc,
1000 .round_rate = &omap2_clksel_round_rate,
1001 .set_rate = &omap2_clksel_set_rate,
1002};
1003
1004static const struct clksel ducati_clk_mux_sel[] = {
1005 { .parent = &div_core_ck, .rates = div_1_0_rates },
1006 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1007 { .parent = NULL },
1008};
1009
1010static struct clk ducati_clk_mux_ck = {
1011 .name = "ducati_clk_mux_ck",
1012 .parent = &div_core_ck,
1013 .clksel = ducati_clk_mux_sel,
1014 .init = &omap2_init_clksel_parent,
1015 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1016 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1017 .ops = &clkops_null,
1018 .recalc = &omap2_clksel_recalc,
1019};
1020
1021static struct clk func_12m_fclk = {
1022 .name = "func_12m_fclk",
1023 .parent = &dpll_per_m2x2_ck,
1024 .ops = &clkops_null,
1025 .fixed_div = 16,
1026 .recalc = &omap_fixed_divisor_recalc,
1027};
1028
1029static struct clk func_24m_clk = {
1030 .name = "func_24m_clk",
1031 .parent = &dpll_per_m2_ck,
1032 .ops = &clkops_null,
1033 .fixed_div = 4,
1034 .recalc = &omap_fixed_divisor_recalc,
1035};
1036
1037static struct clk func_24mc_fclk = {
1038 .name = "func_24mc_fclk",
1039 .parent = &dpll_per_m2x2_ck,
1040 .ops = &clkops_null,
1041 .fixed_div = 8,
1042 .recalc = &omap_fixed_divisor_recalc,
1043};
1044
1045static const struct clksel_rate div2_4to8_rates[] = {
1046 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1047 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1048 { .div = 0 },
1049};
1050
1051static const struct clksel func_48m_fclk_div[] = {
1052 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1053 { .parent = NULL },
1054};
1055
1056static struct clk func_48m_fclk = {
1057 .name = "func_48m_fclk",
1058 .parent = &dpll_per_m2x2_ck,
1059 .clksel = func_48m_fclk_div,
1060 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1061 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1062 .ops = &clkops_null,
1063 .recalc = &omap2_clksel_recalc,
1064 .round_rate = &omap2_clksel_round_rate,
1065 .set_rate = &omap2_clksel_set_rate,
1066};
1067
1068static struct clk func_48mc_fclk = {
1069 .name = "func_48mc_fclk",
1070 .parent = &dpll_per_m2x2_ck,
1071 .ops = &clkops_null,
1072 .fixed_div = 4,
1073 .recalc = &omap_fixed_divisor_recalc,
1074};
1075
1076static const struct clksel_rate div2_2to4_rates[] = {
1077 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1078 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1079 { .div = 0 },
1080};
1081
1082static const struct clksel func_64m_fclk_div[] = {
1083 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1084 { .parent = NULL },
1085};
1086
1087static struct clk func_64m_fclk = {
1088 .name = "func_64m_fclk",
1089 .parent = &dpll_per_m4x2_ck,
1090 .clksel = func_64m_fclk_div,
1091 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1092 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1093 .ops = &clkops_null,
1094 .recalc = &omap2_clksel_recalc,
1095 .round_rate = &omap2_clksel_round_rate,
1096 .set_rate = &omap2_clksel_set_rate,
1097};
1098
1099static const struct clksel func_96m_fclk_div[] = {
1100 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1101 { .parent = NULL },
1102};
1103
1104static struct clk func_96m_fclk = {
1105 .name = "func_96m_fclk",
1106 .parent = &dpll_per_m2x2_ck,
1107 .clksel = func_96m_fclk_div,
1108 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1109 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1110 .ops = &clkops_null,
1111 .recalc = &omap2_clksel_recalc,
1112 .round_rate = &omap2_clksel_round_rate,
1113 .set_rate = &omap2_clksel_set_rate,
1114};
1115
1116static const struct clksel_rate div2_1to8_rates[] = {
1117 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1118 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1119 { .div = 0 },
1120};
1121
1122static const struct clksel init_60m_fclk_div[] = {
1123 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1124 { .parent = NULL },
1125};
1126
1127static struct clk init_60m_fclk = {
1128 .name = "init_60m_fclk",
1129 .parent = &dpll_usb_m2_ck,
1130 .clksel = init_60m_fclk_div,
1131 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1132 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1133 .ops = &clkops_null,
1134 .recalc = &omap2_clksel_recalc,
1135 .round_rate = &omap2_clksel_round_rate,
1136 .set_rate = &omap2_clksel_set_rate,
1137};
1138
1139static const struct clksel l3_div_div[] = {
1140 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1141 { .parent = NULL },
1142};
1143
1144static struct clk l3_div_ck = {
1145 .name = "l3_div_ck",
1146 .parent = &div_core_ck,
1147 .clksel = l3_div_div,
1148 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1149 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1150 .ops = &clkops_null,
1151 .recalc = &omap2_clksel_recalc,
1152 .round_rate = &omap2_clksel_round_rate,
1153 .set_rate = &omap2_clksel_set_rate,
1154};
1155
1156static const struct clksel l4_div_div[] = {
1157 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1158 { .parent = NULL },
1159};
1160
1161static struct clk l4_div_ck = {
1162 .name = "l4_div_ck",
1163 .parent = &l3_div_ck,
1164 .clksel = l4_div_div,
1165 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1166 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1167 .ops = &clkops_null,
1168 .recalc = &omap2_clksel_recalc,
1169 .round_rate = &omap2_clksel_round_rate,
1170 .set_rate = &omap2_clksel_set_rate,
1171};
1172
1173static struct clk lp_clk_div_ck = {
1174 .name = "lp_clk_div_ck",
1175 .parent = &dpll_abe_m2x2_ck,
1176 .ops = &clkops_null,
1177 .fixed_div = 16,
1178 .recalc = &omap_fixed_divisor_recalc,
1179};
1180
1181static const struct clksel l4_wkup_clk_mux_sel[] = {
1182 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1183 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1184 { .parent = NULL },
1185};
1186
1187static struct clk l4_wkup_clk_mux_ck = {
1188 .name = "l4_wkup_clk_mux_ck",
1189 .parent = &sys_clkin_ck,
1190 .clksel = l4_wkup_clk_mux_sel,
1191 .init = &omap2_init_clksel_parent,
1192 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1193 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1194 .ops = &clkops_null,
1195 .recalc = &omap2_clksel_recalc,
1196};
1197
1198static struct clk ocp_abe_iclk = {
1199 .name = "ocp_abe_iclk",
1200 .parent = &aess_fclk,
1201 .ops = &clkops_null,
1202 .recalc = &followparent_recalc,
1203};
1204
1205static struct clk per_abe_24m_fclk = {
1206 .name = "per_abe_24m_fclk",
1207 .parent = &dpll_abe_m2_ck,
1208 .ops = &clkops_null,
1209 .fixed_div = 4,
1210 .recalc = &omap_fixed_divisor_recalc,
1211};
1212
1213static const struct clksel per_abe_nc_fclk_div[] = {
1214 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1215 { .parent = NULL },
1216};
1217
1218static struct clk per_abe_nc_fclk = {
1219 .name = "per_abe_nc_fclk",
1220 .parent = &dpll_abe_m2_ck,
1221 .clksel = per_abe_nc_fclk_div,
1222 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1223 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1224 .ops = &clkops_null,
1225 .recalc = &omap2_clksel_recalc,
1226 .round_rate = &omap2_clksel_round_rate,
1227 .set_rate = &omap2_clksel_set_rate,
1228};
1229
1230static const struct clksel pmd_stm_clock_mux_sel[] = {
1231 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1233 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1234 { .parent = NULL },
1235};
1236
1237static struct clk pmd_stm_clock_mux_ck = {
1238 .name = "pmd_stm_clock_mux_ck",
1239 .parent = &sys_clkin_ck,
1240 .ops = &clkops_null,
1241 .recalc = &followparent_recalc,
1242};
1243
1244static struct clk pmd_trace_clk_mux_ck = {
1245 .name = "pmd_trace_clk_mux_ck",
1246 .parent = &sys_clkin_ck,
1247 .ops = &clkops_null,
1248 .recalc = &followparent_recalc,
1249};
1250
1251static const struct clksel syc_clk_div_div[] = {
1252 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1253 { .parent = NULL },
1254};
1255
1256static struct clk syc_clk_div_ck = {
1257 .name = "syc_clk_div_ck",
1258 .parent = &sys_clkin_ck,
1259 .clksel = syc_clk_div_div,
1260 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1261 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1262 .ops = &clkops_null,
1263 .recalc = &omap2_clksel_recalc,
1264 .round_rate = &omap2_clksel_round_rate,
1265 .set_rate = &omap2_clksel_set_rate,
1266};
1267
1268/* Leaf clocks controlled by modules */
1269
1270static struct clk aes1_fck = {
1271 .name = "aes1_fck",
1272 .ops = &clkops_omap2_dflt,
1273 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1274 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1275 .clkdm_name = "l4_secure_clkdm",
1276 .parent = &l3_div_ck,
1277 .recalc = &followparent_recalc,
1278};
1279
1280static struct clk aes2_fck = {
1281 .name = "aes2_fck",
1282 .ops = &clkops_omap2_dflt,
1283 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1284 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1285 .clkdm_name = "l4_secure_clkdm",
1286 .parent = &l3_div_ck,
1287 .recalc = &followparent_recalc,
1288};
1289
1290static struct clk aess_fck = {
1291 .name = "aess_fck",
1292 .ops = &clkops_omap2_dflt,
1293 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1294 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1295 .clkdm_name = "abe_clkdm",
1296 .parent = &aess_fclk,
1297 .recalc = &followparent_recalc,
1298};
1299
1300static struct clk bandgap_fclk = {
1301 .name = "bandgap_fclk",
1302 .ops = &clkops_omap2_dflt,
1303 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1304 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1305 .clkdm_name = "l4_wkup_clkdm",
1306 .parent = &sys_32k_ck,
1307 .recalc = &followparent_recalc,
1308};
1309
1310static struct clk des3des_fck = {
1311 .name = "des3des_fck",
1312 .ops = &clkops_omap2_dflt,
1313 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1314 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1315 .clkdm_name = "l4_secure_clkdm",
1316 .parent = &l4_div_ck,
1317 .recalc = &followparent_recalc,
1318};
1319
1320static const struct clksel dmic_sync_mux_sel[] = {
1321 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1322 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1323 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1324 { .parent = NULL },
1325};
1326
1327static struct clk dmic_sync_mux_ck = {
1328 .name = "dmic_sync_mux_ck",
1329 .parent = &abe_24m_fclk,
1330 .clksel = dmic_sync_mux_sel,
1331 .init = &omap2_init_clksel_parent,
1332 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1333 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1334 .ops = &clkops_null,
1335 .recalc = &omap2_clksel_recalc,
1336};
1337
1338static const struct clksel func_dmic_abe_gfclk_sel[] = {
1339 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1340 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1341 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1342 { .parent = NULL },
1343};
1344
1345/* Merged func_dmic_abe_gfclk into dmic */
1346static struct clk dmic_fck = {
1347 .name = "dmic_fck",
1348 .parent = &dmic_sync_mux_ck,
1349 .clksel = func_dmic_abe_gfclk_sel,
1350 .init = &omap2_init_clksel_parent,
1351 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1352 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1353 .ops = &clkops_omap2_dflt,
1354 .recalc = &omap2_clksel_recalc,
1355 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1356 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1357 .clkdm_name = "abe_clkdm",
1358};
1359
1360static struct clk dsp_fck = {
1361 .name = "dsp_fck",
1362 .ops = &clkops_omap2_dflt,
1363 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1364 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1365 .clkdm_name = "tesla_clkdm",
1366 .parent = &dpll_iva_m4x2_ck,
1367 .recalc = &followparent_recalc,
1368};
1369
1370static struct clk dss_sys_clk = {
1371 .name = "dss_sys_clk",
1372 .ops = &clkops_omap2_dflt,
1373 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1374 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1375 .clkdm_name = "l3_dss_clkdm",
1376 .parent = &syc_clk_div_ck,
1377 .recalc = &followparent_recalc,
1378};
1379
1380static struct clk dss_tv_clk = {
1381 .name = "dss_tv_clk",
1382 .ops = &clkops_omap2_dflt,
1383 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1384 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1385 .clkdm_name = "l3_dss_clkdm",
1386 .parent = &extalt_clkin_ck,
1387 .recalc = &followparent_recalc,
1388};
1389
1390static struct clk dss_dss_clk = {
1391 .name = "dss_dss_clk",
1392 .ops = &clkops_omap2_dflt,
1393 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1394 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1395 .clkdm_name = "l3_dss_clkdm",
1396 .parent = &dpll_per_m5x2_ck,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static const struct clksel_rate div3_8to32_rates[] = {
1401 { .div = 8, .val = 0, .flags = RATE_IN_44XX },
1402 { .div = 16, .val = 1, .flags = RATE_IN_44XX },
1403 { .div = 32, .val = 2, .flags = RATE_IN_44XX },
1404 { .div = 0 },
1405};
1406
1407static const struct clksel div_ts_div[] = {
1408 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1409 { .parent = NULL },
1410};
1411
1412static struct clk div_ts_ck = {
1413 .name = "div_ts_ck",
1414 .parent = &l4_wkup_clk_mux_ck,
1415 .clksel = div_ts_div,
1416 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1417 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1418 .ops = &clkops_null,
1419 .recalc = &omap2_clksel_recalc,
1420 .round_rate = &omap2_clksel_round_rate,
1421 .set_rate = &omap2_clksel_set_rate,
1422};
1423
1424static struct clk bandgap_ts_fclk = {
1425 .name = "bandgap_ts_fclk",
1426 .ops = &clkops_omap2_dflt,
1427 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1428 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1429 .clkdm_name = "l4_wkup_clkdm",
1430 .parent = &div_ts_ck,
1431 .recalc = &followparent_recalc,
1432};
1433
1434static struct clk dss_48mhz_clk = {
1435 .name = "dss_48mhz_clk",
1436 .ops = &clkops_omap2_dflt,
1437 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1438 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1439 .clkdm_name = "l3_dss_clkdm",
1440 .parent = &func_48mc_fclk,
1441 .recalc = &followparent_recalc,
1442};
1443
1444static struct clk dss_fck = {
1445 .name = "dss_fck",
1446 .ops = &clkops_omap2_dflt,
1447 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1448 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1449 .clkdm_name = "l3_dss_clkdm",
1450 .parent = &l3_div_ck,
1451 .recalc = &followparent_recalc,
1452};
1453
1454static struct clk efuse_ctrl_cust_fck = {
1455 .name = "efuse_ctrl_cust_fck",
1456 .ops = &clkops_omap2_dflt,
1457 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1458 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1459 .clkdm_name = "l4_cefuse_clkdm",
1460 .parent = &sys_clkin_ck,
1461 .recalc = &followparent_recalc,
1462};
1463
1464static struct clk emif1_fck = {
1465 .name = "emif1_fck",
1466 .ops = &clkops_omap2_dflt,
1467 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1468 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1469 .flags = ENABLE_ON_INIT,
1470 .clkdm_name = "l3_emif_clkdm",
1471 .parent = &ddrphy_ck,
1472 .recalc = &followparent_recalc,
1473};
1474
1475static struct clk emif2_fck = {
1476 .name = "emif2_fck",
1477 .ops = &clkops_omap2_dflt,
1478 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1479 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1480 .flags = ENABLE_ON_INIT,
1481 .clkdm_name = "l3_emif_clkdm",
1482 .parent = &ddrphy_ck,
1483 .recalc = &followparent_recalc,
1484};
1485
1486static const struct clksel fdif_fclk_div[] = {
1487 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1488 { .parent = NULL },
1489};
1490
1491/* Merged fdif_fclk into fdif */
1492static struct clk fdif_fck = {
1493 .name = "fdif_fck",
1494 .parent = &dpll_per_m4x2_ck,
1495 .clksel = fdif_fclk_div,
1496 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1497 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1498 .ops = &clkops_omap2_dflt,
1499 .recalc = &omap2_clksel_recalc,
1500 .round_rate = &omap2_clksel_round_rate,
1501 .set_rate = &omap2_clksel_set_rate,
1502 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1503 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1504 .clkdm_name = "iss_clkdm",
1505};
1506
1507static struct clk fpka_fck = {
1508 .name = "fpka_fck",
1509 .ops = &clkops_omap2_dflt,
1510 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1511 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1512 .clkdm_name = "l4_secure_clkdm",
1513 .parent = &l4_div_ck,
1514 .recalc = &followparent_recalc,
1515};
1516
1517static struct clk gpio1_dbclk = {
1518 .name = "gpio1_dbclk",
1519 .ops = &clkops_omap2_dflt,
1520 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1521 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1522 .clkdm_name = "l4_wkup_clkdm",
1523 .parent = &sys_32k_ck,
1524 .recalc = &followparent_recalc,
1525};
1526
1527static struct clk gpio1_ick = {
1528 .name = "gpio1_ick",
1529 .ops = &clkops_omap2_dflt,
1530 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1531 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1532 .clkdm_name = "l4_wkup_clkdm",
1533 .parent = &l4_wkup_clk_mux_ck,
1534 .recalc = &followparent_recalc,
1535};
1536
1537static struct clk gpio2_dbclk = {
1538 .name = "gpio2_dbclk",
1539 .ops = &clkops_omap2_dflt,
1540 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1541 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1542 .clkdm_name = "l4_per_clkdm",
1543 .parent = &sys_32k_ck,
1544 .recalc = &followparent_recalc,
1545};
1546
1547static struct clk gpio2_ick = {
1548 .name = "gpio2_ick",
1549 .ops = &clkops_omap2_dflt,
1550 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1551 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1552 .clkdm_name = "l4_per_clkdm",
1553 .parent = &l4_div_ck,
1554 .recalc = &followparent_recalc,
1555};
1556
1557static struct clk gpio3_dbclk = {
1558 .name = "gpio3_dbclk",
1559 .ops = &clkops_omap2_dflt,
1560 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1561 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1562 .clkdm_name = "l4_per_clkdm",
1563 .parent = &sys_32k_ck,
1564 .recalc = &followparent_recalc,
1565};
1566
1567static struct clk gpio3_ick = {
1568 .name = "gpio3_ick",
1569 .ops = &clkops_omap2_dflt,
1570 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1571 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1572 .clkdm_name = "l4_per_clkdm",
1573 .parent = &l4_div_ck,
1574 .recalc = &followparent_recalc,
1575};
1576
1577static struct clk gpio4_dbclk = {
1578 .name = "gpio4_dbclk",
1579 .ops = &clkops_omap2_dflt,
1580 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1581 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1582 .clkdm_name = "l4_per_clkdm",
1583 .parent = &sys_32k_ck,
1584 .recalc = &followparent_recalc,
1585};
1586
1587static struct clk gpio4_ick = {
1588 .name = "gpio4_ick",
1589 .ops = &clkops_omap2_dflt,
1590 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1591 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1592 .clkdm_name = "l4_per_clkdm",
1593 .parent = &l4_div_ck,
1594 .recalc = &followparent_recalc,
1595};
1596
1597static struct clk gpio5_dbclk = {
1598 .name = "gpio5_dbclk",
1599 .ops = &clkops_omap2_dflt,
1600 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1601 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1602 .clkdm_name = "l4_per_clkdm",
1603 .parent = &sys_32k_ck,
1604 .recalc = &followparent_recalc,
1605};
1606
1607static struct clk gpio5_ick = {
1608 .name = "gpio5_ick",
1609 .ops = &clkops_omap2_dflt,
1610 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1611 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1612 .clkdm_name = "l4_per_clkdm",
1613 .parent = &l4_div_ck,
1614 .recalc = &followparent_recalc,
1615};
1616
1617static struct clk gpio6_dbclk = {
1618 .name = "gpio6_dbclk",
1619 .ops = &clkops_omap2_dflt,
1620 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1621 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1622 .clkdm_name = "l4_per_clkdm",
1623 .parent = &sys_32k_ck,
1624 .recalc = &followparent_recalc,
1625};
1626
1627static struct clk gpio6_ick = {
1628 .name = "gpio6_ick",
1629 .ops = &clkops_omap2_dflt,
1630 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1631 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1632 .clkdm_name = "l4_per_clkdm",
1633 .parent = &l4_div_ck,
1634 .recalc = &followparent_recalc,
1635};
1636
1637static struct clk gpmc_ick = {
1638 .name = "gpmc_ick",
1639 .ops = &clkops_omap2_dflt,
1640 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1641 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1642 .flags = ENABLE_ON_INIT,
1643 .clkdm_name = "l3_2_clkdm",
1644 .parent = &l3_div_ck,
1645 .recalc = &followparent_recalc,
1646};
1647
1648static const struct clksel sgx_clk_mux_sel[] = {
1649 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1650 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1651 { .parent = NULL },
1652};
1653
1654/* Merged sgx_clk_mux into gpu */
1655static struct clk gpu_fck = {
1656 .name = "gpu_fck",
1657 .parent = &dpll_core_m7x2_ck,
1658 .clksel = sgx_clk_mux_sel,
1659 .init = &omap2_init_clksel_parent,
1660 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1661 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1662 .ops = &clkops_omap2_dflt,
1663 .recalc = &omap2_clksel_recalc,
1664 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1665 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1666 .clkdm_name = "l3_gfx_clkdm",
1667};
1668
1669static struct clk hdq1w_fck = {
1670 .name = "hdq1w_fck",
1671 .ops = &clkops_omap2_dflt,
1672 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1673 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1674 .clkdm_name = "l4_per_clkdm",
1675 .parent = &func_12m_fclk,
1676 .recalc = &followparent_recalc,
1677};
1678
1679static const struct clksel hsi_fclk_div[] = {
1680 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1681 { .parent = NULL },
1682};
1683
1684/* Merged hsi_fclk into hsi */
1685static struct clk hsi_fck = {
1686 .name = "hsi_fck",
1687 .parent = &dpll_per_m2x2_ck,
1688 .clksel = hsi_fclk_div,
1689 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1690 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1691 .ops = &clkops_omap2_dflt,
1692 .recalc = &omap2_clksel_recalc,
1693 .round_rate = &omap2_clksel_round_rate,
1694 .set_rate = &omap2_clksel_set_rate,
1695 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1696 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1697 .clkdm_name = "l3_init_clkdm",
1698};
1699
1700static struct clk i2c1_fck = {
1701 .name = "i2c1_fck",
1702 .ops = &clkops_omap2_dflt,
1703 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1704 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1705 .clkdm_name = "l4_per_clkdm",
1706 .parent = &func_96m_fclk,
1707 .recalc = &followparent_recalc,
1708};
1709
1710static struct clk i2c2_fck = {
1711 .name = "i2c2_fck",
1712 .ops = &clkops_omap2_dflt,
1713 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1714 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1715 .clkdm_name = "l4_per_clkdm",
1716 .parent = &func_96m_fclk,
1717 .recalc = &followparent_recalc,
1718};
1719
1720static struct clk i2c3_fck = {
1721 .name = "i2c3_fck",
1722 .ops = &clkops_omap2_dflt,
1723 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1724 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1725 .clkdm_name = "l4_per_clkdm",
1726 .parent = &func_96m_fclk,
1727 .recalc = &followparent_recalc,
1728};
1729
1730static struct clk i2c4_fck = {
1731 .name = "i2c4_fck",
1732 .ops = &clkops_omap2_dflt,
1733 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1734 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1735 .clkdm_name = "l4_per_clkdm",
1736 .parent = &func_96m_fclk,
1737 .recalc = &followparent_recalc,
1738};
1739
1740static struct clk ipu_fck = {
1741 .name = "ipu_fck",
1742 .ops = &clkops_omap2_dflt,
1743 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1744 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1745 .clkdm_name = "ducati_clkdm",
1746 .parent = &ducati_clk_mux_ck,
1747 .recalc = &followparent_recalc,
1748};
1749
1750static struct clk iss_ctrlclk = {
1751 .name = "iss_ctrlclk",
1752 .ops = &clkops_omap2_dflt,
1753 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1754 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1755 .clkdm_name = "iss_clkdm",
1756 .parent = &func_96m_fclk,
1757 .recalc = &followparent_recalc,
1758};
1759
1760static struct clk iss_fck = {
1761 .name = "iss_fck",
1762 .ops = &clkops_omap2_dflt,
1763 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1764 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1765 .clkdm_name = "iss_clkdm",
1766 .parent = &ducati_clk_mux_ck,
1767 .recalc = &followparent_recalc,
1768};
1769
1770static struct clk iva_fck = {
1771 .name = "iva_fck",
1772 .ops = &clkops_omap2_dflt,
1773 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1774 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1775 .clkdm_name = "ivahd_clkdm",
1776 .parent = &dpll_iva_m5x2_ck,
1777 .recalc = &followparent_recalc,
1778};
1779
1780static struct clk kbd_fck = {
1781 .name = "kbd_fck",
1782 .ops = &clkops_omap2_dflt,
1783 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1784 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1785 .clkdm_name = "l4_wkup_clkdm",
1786 .parent = &sys_32k_ck,
1787 .recalc = &followparent_recalc,
1788};
1789
1790static struct clk l3_instr_ick = {
1791 .name = "l3_instr_ick",
1792 .ops = &clkops_omap2_dflt,
1793 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1794 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1795 .flags = ENABLE_ON_INIT,
1796 .clkdm_name = "l3_instr_clkdm",
1797 .parent = &l3_div_ck,
1798 .recalc = &followparent_recalc,
1799};
1800
1801static struct clk l3_main_3_ick = {
1802 .name = "l3_main_3_ick",
1803 .ops = &clkops_omap2_dflt,
1804 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1805 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1806 .flags = ENABLE_ON_INIT,
1807 .clkdm_name = "l3_instr_clkdm",
1808 .parent = &l3_div_ck,
1809 .recalc = &followparent_recalc,
1810};
1811
1812static struct clk mcasp_sync_mux_ck = {
1813 .name = "mcasp_sync_mux_ck",
1814 .parent = &abe_24m_fclk,
1815 .clksel = dmic_sync_mux_sel,
1816 .init = &omap2_init_clksel_parent,
1817 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1818 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1819 .ops = &clkops_null,
1820 .recalc = &omap2_clksel_recalc,
1821};
1822
1823static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1824 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1825 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1826 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1827 { .parent = NULL },
1828};
1829
1830/* Merged func_mcasp_abe_gfclk into mcasp */
1831static struct clk mcasp_fck = {
1832 .name = "mcasp_fck",
1833 .parent = &mcasp_sync_mux_ck,
1834 .clksel = func_mcasp_abe_gfclk_sel,
1835 .init = &omap2_init_clksel_parent,
1836 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1837 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1838 .ops = &clkops_omap2_dflt,
1839 .recalc = &omap2_clksel_recalc,
1840 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1841 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1842 .clkdm_name = "abe_clkdm",
1843};
1844
1845static struct clk mcbsp1_sync_mux_ck = {
1846 .name = "mcbsp1_sync_mux_ck",
1847 .parent = &abe_24m_fclk,
1848 .clksel = dmic_sync_mux_sel,
1849 .init = &omap2_init_clksel_parent,
1850 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1851 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1852 .ops = &clkops_null,
1853 .recalc = &omap2_clksel_recalc,
1854};
1855
1856static const struct clksel func_mcbsp1_gfclk_sel[] = {
1857 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1858 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1859 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1860 { .parent = NULL },
1861};
1862
1863/* Merged func_mcbsp1_gfclk into mcbsp1 */
1864static struct clk mcbsp1_fck = {
1865 .name = "mcbsp1_fck",
1866 .parent = &mcbsp1_sync_mux_ck,
1867 .clksel = func_mcbsp1_gfclk_sel,
1868 .init = &omap2_init_clksel_parent,
1869 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1870 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1871 .ops = &clkops_omap2_dflt,
1872 .recalc = &omap2_clksel_recalc,
1873 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1874 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1875 .clkdm_name = "abe_clkdm",
1876};
1877
1878static struct clk mcbsp2_sync_mux_ck = {
1879 .name = "mcbsp2_sync_mux_ck",
1880 .parent = &abe_24m_fclk,
1881 .clksel = dmic_sync_mux_sel,
1882 .init = &omap2_init_clksel_parent,
1883 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1884 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1885 .ops = &clkops_null,
1886 .recalc = &omap2_clksel_recalc,
1887};
1888
1889static const struct clksel func_mcbsp2_gfclk_sel[] = {
1890 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1891 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1892 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1893 { .parent = NULL },
1894};
1895
1896/* Merged func_mcbsp2_gfclk into mcbsp2 */
1897static struct clk mcbsp2_fck = {
1898 .name = "mcbsp2_fck",
1899 .parent = &mcbsp2_sync_mux_ck,
1900 .clksel = func_mcbsp2_gfclk_sel,
1901 .init = &omap2_init_clksel_parent,
1902 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1903 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1904 .ops = &clkops_omap2_dflt,
1905 .recalc = &omap2_clksel_recalc,
1906 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1907 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1908 .clkdm_name = "abe_clkdm",
1909};
1910
1911static struct clk mcbsp3_sync_mux_ck = {
1912 .name = "mcbsp3_sync_mux_ck",
1913 .parent = &abe_24m_fclk,
1914 .clksel = dmic_sync_mux_sel,
1915 .init = &omap2_init_clksel_parent,
1916 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1917 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1918 .ops = &clkops_null,
1919 .recalc = &omap2_clksel_recalc,
1920};
1921
1922static const struct clksel func_mcbsp3_gfclk_sel[] = {
1923 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1924 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1925 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1926 { .parent = NULL },
1927};
1928
1929/* Merged func_mcbsp3_gfclk into mcbsp3 */
1930static struct clk mcbsp3_fck = {
1931 .name = "mcbsp3_fck",
1932 .parent = &mcbsp3_sync_mux_ck,
1933 .clksel = func_mcbsp3_gfclk_sel,
1934 .init = &omap2_init_clksel_parent,
1935 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1936 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1937 .ops = &clkops_omap2_dflt,
1938 .recalc = &omap2_clksel_recalc,
1939 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1940 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1941 .clkdm_name = "abe_clkdm",
1942};
1943
1944static const struct clksel mcbsp4_sync_mux_sel[] = {
1945 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1946 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1947 { .parent = NULL },
1948};
1949
1950static struct clk mcbsp4_sync_mux_ck = {
1951 .name = "mcbsp4_sync_mux_ck",
1952 .parent = &func_96m_fclk,
1953 .clksel = mcbsp4_sync_mux_sel,
1954 .init = &omap2_init_clksel_parent,
1955 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1956 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1957 .ops = &clkops_null,
1958 .recalc = &omap2_clksel_recalc,
1959};
1960
1961static const struct clksel per_mcbsp4_gfclk_sel[] = {
1962 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1963 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1964 { .parent = NULL },
1965};
1966
1967/* Merged per_mcbsp4_gfclk into mcbsp4 */
1968static struct clk mcbsp4_fck = {
1969 .name = "mcbsp4_fck",
1970 .parent = &mcbsp4_sync_mux_ck,
1971 .clksel = per_mcbsp4_gfclk_sel,
1972 .init = &omap2_init_clksel_parent,
1973 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1974 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1975 .ops = &clkops_omap2_dflt,
1976 .recalc = &omap2_clksel_recalc,
1977 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1978 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1979 .clkdm_name = "l4_per_clkdm",
1980};
1981
1982static struct clk mcpdm_fck = {
1983 .name = "mcpdm_fck",
1984 .ops = &clkops_omap2_dflt,
1985 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1986 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1987 .clkdm_name = "abe_clkdm",
1988 .parent = &pad_clks_ck,
1989 .recalc = &followparent_recalc,
1990};
1991
1992static struct clk mcspi1_fck = {
1993 .name = "mcspi1_fck",
1994 .ops = &clkops_omap2_dflt,
1995 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1996 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1997 .clkdm_name = "l4_per_clkdm",
1998 .parent = &func_48m_fclk,
1999 .recalc = &followparent_recalc,
2000};
2001
2002static struct clk mcspi2_fck = {
2003 .name = "mcspi2_fck",
2004 .ops = &clkops_omap2_dflt,
2005 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2006 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2007 .clkdm_name = "l4_per_clkdm",
2008 .parent = &func_48m_fclk,
2009 .recalc = &followparent_recalc,
2010};
2011
2012static struct clk mcspi3_fck = {
2013 .name = "mcspi3_fck",
2014 .ops = &clkops_omap2_dflt,
2015 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2016 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2017 .clkdm_name = "l4_per_clkdm",
2018 .parent = &func_48m_fclk,
2019 .recalc = &followparent_recalc,
2020};
2021
2022static struct clk mcspi4_fck = {
2023 .name = "mcspi4_fck",
2024 .ops = &clkops_omap2_dflt,
2025 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2026 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2027 .clkdm_name = "l4_per_clkdm",
2028 .parent = &func_48m_fclk,
2029 .recalc = &followparent_recalc,
2030};
2031
2032static const struct clksel hsmmc1_fclk_sel[] = {
2033 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2034 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2035 { .parent = NULL },
2036};
2037
2038/* Merged hsmmc1_fclk into mmc1 */
2039static struct clk mmc1_fck = {
2040 .name = "mmc1_fck",
2041 .parent = &func_64m_fclk,
2042 .clksel = hsmmc1_fclk_sel,
2043 .init = &omap2_init_clksel_parent,
2044 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2045 .clksel_mask = OMAP4430_CLKSEL_MASK,
2046 .ops = &clkops_omap2_dflt,
2047 .recalc = &omap2_clksel_recalc,
2048 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2049 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2050 .clkdm_name = "l3_init_clkdm",
2051};
2052
2053/* Merged hsmmc2_fclk into mmc2 */
2054static struct clk mmc2_fck = {
2055 .name = "mmc2_fck",
2056 .parent = &func_64m_fclk,
2057 .clksel = hsmmc1_fclk_sel,
2058 .init = &omap2_init_clksel_parent,
2059 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2060 .clksel_mask = OMAP4430_CLKSEL_MASK,
2061 .ops = &clkops_omap2_dflt,
2062 .recalc = &omap2_clksel_recalc,
2063 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2064 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2065 .clkdm_name = "l3_init_clkdm",
2066};
2067
2068static struct clk mmc3_fck = {
2069 .name = "mmc3_fck",
2070 .ops = &clkops_omap2_dflt,
2071 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2072 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2073 .clkdm_name = "l4_per_clkdm",
2074 .parent = &func_48m_fclk,
2075 .recalc = &followparent_recalc,
2076};
2077
2078static struct clk mmc4_fck = {
2079 .name = "mmc4_fck",
2080 .ops = &clkops_omap2_dflt,
2081 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2082 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2083 .clkdm_name = "l4_per_clkdm",
2084 .parent = &func_48m_fclk,
2085 .recalc = &followparent_recalc,
2086};
2087
2088static struct clk mmc5_fck = {
2089 .name = "mmc5_fck",
2090 .ops = &clkops_omap2_dflt,
2091 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2092 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2093 .clkdm_name = "l4_per_clkdm",
2094 .parent = &func_48m_fclk,
2095 .recalc = &followparent_recalc,
2096};
2097
2098static struct clk ocp2scp_usb_phy_phy_48m = {
2099 .name = "ocp2scp_usb_phy_phy_48m",
2100 .ops = &clkops_omap2_dflt,
2101 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2102 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2103 .clkdm_name = "l3_init_clkdm",
2104 .parent = &func_48m_fclk,
2105 .recalc = &followparent_recalc,
2106};
2107
2108static struct clk ocp2scp_usb_phy_ick = {
2109 .name = "ocp2scp_usb_phy_ick",
2110 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2113 .clkdm_name = "l3_init_clkdm",
2114 .parent = &l4_div_ck,
2115 .recalc = &followparent_recalc,
2116};
2117
2118static struct clk ocp_wp_noc_ick = {
2119 .name = "ocp_wp_noc_ick",
2120 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2122 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2123 .flags = ENABLE_ON_INIT,
2124 .clkdm_name = "l3_instr_clkdm",
2125 .parent = &l3_div_ck,
2126 .recalc = &followparent_recalc,
2127};
2128
2129static struct clk rng_ick = {
2130 .name = "rng_ick",
2131 .ops = &clkops_omap2_dflt,
2132 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2133 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2134 .clkdm_name = "l4_secure_clkdm",
2135 .parent = &l4_div_ck,
2136 .recalc = &followparent_recalc,
2137};
2138
2139static struct clk sha2md5_fck = {
2140 .name = "sha2md5_fck",
2141 .ops = &clkops_omap2_dflt,
2142 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2143 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2144 .clkdm_name = "l4_secure_clkdm",
2145 .parent = &l3_div_ck,
2146 .recalc = &followparent_recalc,
2147};
2148
2149static struct clk sl2if_ick = {
2150 .name = "sl2if_ick",
2151 .ops = &clkops_omap2_dflt,
2152 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2153 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2154 .clkdm_name = "ivahd_clkdm",
2155 .parent = &dpll_iva_m5x2_ck,
2156 .recalc = &followparent_recalc,
2157};
2158
2159static struct clk slimbus1_fclk_1 = {
2160 .name = "slimbus1_fclk_1",
2161 .ops = &clkops_omap2_dflt,
2162 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2163 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2164 .clkdm_name = "abe_clkdm",
2165 .parent = &func_24m_clk,
2166 .recalc = &followparent_recalc,
2167};
2168
2169static struct clk slimbus1_fclk_0 = {
2170 .name = "slimbus1_fclk_0",
2171 .ops = &clkops_omap2_dflt,
2172 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2173 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2174 .clkdm_name = "abe_clkdm",
2175 .parent = &abe_24m_fclk,
2176 .recalc = &followparent_recalc,
2177};
2178
2179static struct clk slimbus1_fclk_2 = {
2180 .name = "slimbus1_fclk_2",
2181 .ops = &clkops_omap2_dflt,
2182 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2183 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2184 .clkdm_name = "abe_clkdm",
2185 .parent = &pad_clks_ck,
2186 .recalc = &followparent_recalc,
2187};
2188
2189static struct clk slimbus1_slimbus_clk = {
2190 .name = "slimbus1_slimbus_clk",
2191 .ops = &clkops_omap2_dflt,
2192 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2193 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2194 .clkdm_name = "abe_clkdm",
2195 .parent = &slimbus_clk,
2196 .recalc = &followparent_recalc,
2197};
2198
2199static struct clk slimbus1_fck = {
2200 .name = "slimbus1_fck",
2201 .ops = &clkops_omap2_dflt,
2202 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2203 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2204 .clkdm_name = "abe_clkdm",
2205 .parent = &ocp_abe_iclk,
2206 .recalc = &followparent_recalc,
2207};
2208
2209static struct clk slimbus2_fclk_1 = {
2210 .name = "slimbus2_fclk_1",
2211 .ops = &clkops_omap2_dflt,
2212 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2213 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2214 .clkdm_name = "l4_per_clkdm",
2215 .parent = &per_abe_24m_fclk,
2216 .recalc = &followparent_recalc,
2217};
2218
2219static struct clk slimbus2_fclk_0 = {
2220 .name = "slimbus2_fclk_0",
2221 .ops = &clkops_omap2_dflt,
2222 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2223 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2224 .clkdm_name = "l4_per_clkdm",
2225 .parent = &func_24mc_fclk,
2226 .recalc = &followparent_recalc,
2227};
2228
2229static struct clk slimbus2_slimbus_clk = {
2230 .name = "slimbus2_slimbus_clk",
2231 .ops = &clkops_omap2_dflt,
2232 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2233 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2234 .clkdm_name = "l4_per_clkdm",
2235 .parent = &pad_slimbus_core_clks_ck,
2236 .recalc = &followparent_recalc,
2237};
2238
2239static struct clk slimbus2_fck = {
2240 .name = "slimbus2_fck",
2241 .ops = &clkops_omap2_dflt,
2242 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2243 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2244 .clkdm_name = "l4_per_clkdm",
2245 .parent = &l4_div_ck,
2246 .recalc = &followparent_recalc,
2247};
2248
2249static struct clk smartreflex_core_fck = {
2250 .name = "smartreflex_core_fck",
2251 .ops = &clkops_omap2_dflt,
2252 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2253 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2254 .clkdm_name = "l4_ao_clkdm",
2255 .parent = &l4_wkup_clk_mux_ck,
2256 .recalc = &followparent_recalc,
2257};
2258
2259static struct clk smartreflex_iva_fck = {
2260 .name = "smartreflex_iva_fck",
2261 .ops = &clkops_omap2_dflt,
2262 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2263 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2264 .clkdm_name = "l4_ao_clkdm",
2265 .parent = &l4_wkup_clk_mux_ck,
2266 .recalc = &followparent_recalc,
2267};
2268
2269static struct clk smartreflex_mpu_fck = {
2270 .name = "smartreflex_mpu_fck",
2271 .ops = &clkops_omap2_dflt,
2272 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2273 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2274 .clkdm_name = "l4_ao_clkdm",
2275 .parent = &l4_wkup_clk_mux_ck,
2276 .recalc = &followparent_recalc,
2277};
2278
2279/* Merged dmt1_clk_mux into timer1 */
2280static struct clk timer1_fck = {
2281 .name = "timer1_fck",
2282 .parent = &sys_clkin_ck,
2283 .clksel = abe_dpll_bypass_clk_mux_sel,
2284 .init = &omap2_init_clksel_parent,
2285 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2286 .clksel_mask = OMAP4430_CLKSEL_MASK,
2287 .ops = &clkops_omap2_dflt,
2288 .recalc = &omap2_clksel_recalc,
2289 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2290 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2291 .clkdm_name = "l4_wkup_clkdm",
2292};
2293
2294/* Merged cm2_dm10_mux into timer10 */
2295static struct clk timer10_fck = {
2296 .name = "timer10_fck",
2297 .parent = &sys_clkin_ck,
2298 .clksel = abe_dpll_bypass_clk_mux_sel,
2299 .init = &omap2_init_clksel_parent,
2300 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2301 .clksel_mask = OMAP4430_CLKSEL_MASK,
2302 .ops = &clkops_omap2_dflt,
2303 .recalc = &omap2_clksel_recalc,
2304 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2305 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2306 .clkdm_name = "l4_per_clkdm",
2307};
2308
2309/* Merged cm2_dm11_mux into timer11 */
2310static struct clk timer11_fck = {
2311 .name = "timer11_fck",
2312 .parent = &sys_clkin_ck,
2313 .clksel = abe_dpll_bypass_clk_mux_sel,
2314 .init = &omap2_init_clksel_parent,
2315 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2316 .clksel_mask = OMAP4430_CLKSEL_MASK,
2317 .ops = &clkops_omap2_dflt,
2318 .recalc = &omap2_clksel_recalc,
2319 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2320 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2321 .clkdm_name = "l4_per_clkdm",
2322};
2323
2324/* Merged cm2_dm2_mux into timer2 */
2325static struct clk timer2_fck = {
2326 .name = "timer2_fck",
2327 .parent = &sys_clkin_ck,
2328 .clksel = abe_dpll_bypass_clk_mux_sel,
2329 .init = &omap2_init_clksel_parent,
2330 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2331 .clksel_mask = OMAP4430_CLKSEL_MASK,
2332 .ops = &clkops_omap2_dflt,
2333 .recalc = &omap2_clksel_recalc,
2334 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2335 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2336 .clkdm_name = "l4_per_clkdm",
2337};
2338
2339/* Merged cm2_dm3_mux into timer3 */
2340static struct clk timer3_fck = {
2341 .name = "timer3_fck",
2342 .parent = &sys_clkin_ck,
2343 .clksel = abe_dpll_bypass_clk_mux_sel,
2344 .init = &omap2_init_clksel_parent,
2345 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2346 .clksel_mask = OMAP4430_CLKSEL_MASK,
2347 .ops = &clkops_omap2_dflt,
2348 .recalc = &omap2_clksel_recalc,
2349 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2350 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2351 .clkdm_name = "l4_per_clkdm",
2352};
2353
2354/* Merged cm2_dm4_mux into timer4 */
2355static struct clk timer4_fck = {
2356 .name = "timer4_fck",
2357 .parent = &sys_clkin_ck,
2358 .clksel = abe_dpll_bypass_clk_mux_sel,
2359 .init = &omap2_init_clksel_parent,
2360 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2361 .clksel_mask = OMAP4430_CLKSEL_MASK,
2362 .ops = &clkops_omap2_dflt,
2363 .recalc = &omap2_clksel_recalc,
2364 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2365 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2366 .clkdm_name = "l4_per_clkdm",
2367};
2368
2369static const struct clksel timer5_sync_mux_sel[] = {
2370 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2371 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2372 { .parent = NULL },
2373};
2374
2375/* Merged timer5_sync_mux into timer5 */
2376static struct clk timer5_fck = {
2377 .name = "timer5_fck",
2378 .parent = &syc_clk_div_ck,
2379 .clksel = timer5_sync_mux_sel,
2380 .init = &omap2_init_clksel_parent,
2381 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2382 .clksel_mask = OMAP4430_CLKSEL_MASK,
2383 .ops = &clkops_omap2_dflt,
2384 .recalc = &omap2_clksel_recalc,
2385 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2386 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2387 .clkdm_name = "abe_clkdm",
2388};
2389
2390/* Merged timer6_sync_mux into timer6 */
2391static struct clk timer6_fck = {
2392 .name = "timer6_fck",
2393 .parent = &syc_clk_div_ck,
2394 .clksel = timer5_sync_mux_sel,
2395 .init = &omap2_init_clksel_parent,
2396 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2397 .clksel_mask = OMAP4430_CLKSEL_MASK,
2398 .ops = &clkops_omap2_dflt,
2399 .recalc = &omap2_clksel_recalc,
2400 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2401 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2402 .clkdm_name = "abe_clkdm",
2403};
2404
2405/* Merged timer7_sync_mux into timer7 */
2406static struct clk timer7_fck = {
2407 .name = "timer7_fck",
2408 .parent = &syc_clk_div_ck,
2409 .clksel = timer5_sync_mux_sel,
2410 .init = &omap2_init_clksel_parent,
2411 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2412 .clksel_mask = OMAP4430_CLKSEL_MASK,
2413 .ops = &clkops_omap2_dflt,
2414 .recalc = &omap2_clksel_recalc,
2415 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2416 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2417 .clkdm_name = "abe_clkdm",
2418};
2419
2420/* Merged timer8_sync_mux into timer8 */
2421static struct clk timer8_fck = {
2422 .name = "timer8_fck",
2423 .parent = &syc_clk_div_ck,
2424 .clksel = timer5_sync_mux_sel,
2425 .init = &omap2_init_clksel_parent,
2426 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2427 .clksel_mask = OMAP4430_CLKSEL_MASK,
2428 .ops = &clkops_omap2_dflt,
2429 .recalc = &omap2_clksel_recalc,
2430 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2431 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2432 .clkdm_name = "abe_clkdm",
2433};
2434
2435/* Merged cm2_dm9_mux into timer9 */
2436static struct clk timer9_fck = {
2437 .name = "timer9_fck",
2438 .parent = &sys_clkin_ck,
2439 .clksel = abe_dpll_bypass_clk_mux_sel,
2440 .init = &omap2_init_clksel_parent,
2441 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2442 .clksel_mask = OMAP4430_CLKSEL_MASK,
2443 .ops = &clkops_omap2_dflt,
2444 .recalc = &omap2_clksel_recalc,
2445 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2446 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2447 .clkdm_name = "l4_per_clkdm",
2448};
2449
2450static struct clk uart1_fck = {
2451 .name = "uart1_fck",
2452 .ops = &clkops_omap2_dflt,
2453 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2454 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2455 .clkdm_name = "l4_per_clkdm",
2456 .parent = &func_48m_fclk,
2457 .recalc = &followparent_recalc,
2458};
2459
2460static struct clk uart2_fck = {
2461 .name = "uart2_fck",
2462 .ops = &clkops_omap2_dflt,
2463 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2464 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2465 .clkdm_name = "l4_per_clkdm",
2466 .parent = &func_48m_fclk,
2467 .recalc = &followparent_recalc,
2468};
2469
2470static struct clk uart3_fck = {
2471 .name = "uart3_fck",
2472 .ops = &clkops_omap2_dflt,
2473 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2474 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2475 .clkdm_name = "l4_per_clkdm",
2476 .parent = &func_48m_fclk,
2477 .recalc = &followparent_recalc,
2478};
2479
2480static struct clk uart4_fck = {
2481 .name = "uart4_fck",
2482 .ops = &clkops_omap2_dflt,
2483 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2484 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2485 .clkdm_name = "l4_per_clkdm",
2486 .parent = &func_48m_fclk,
2487 .recalc = &followparent_recalc,
2488};
2489
2490static struct clk usb_host_fs_fck = {
2491 .name = "usb_host_fs_fck",
2492 .ops = &clkops_omap2_dflt,
2493 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2494 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2495 .clkdm_name = "l3_init_clkdm",
2496 .parent = &func_48mc_fclk,
2497 .recalc = &followparent_recalc,
2498};
2499
2500static const struct clksel utmi_p1_gfclk_sel[] = {
2501 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2502 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2503 { .parent = NULL },
2504};
2505
2506static struct clk utmi_p1_gfclk = {
2507 .name = "utmi_p1_gfclk",
2508 .parent = &init_60m_fclk,
2509 .clksel = utmi_p1_gfclk_sel,
2510 .init = &omap2_init_clksel_parent,
2511 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2512 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2513 .ops = &clkops_null,
2514 .recalc = &omap2_clksel_recalc,
2515};
2516
2517static struct clk usb_host_hs_utmi_p1_clk = {
2518 .name = "usb_host_hs_utmi_p1_clk",
2519 .ops = &clkops_omap2_dflt,
2520 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2521 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2522 .clkdm_name = "l3_init_clkdm",
2523 .parent = &utmi_p1_gfclk,
2524 .recalc = &followparent_recalc,
2525};
2526
2527static const struct clksel utmi_p2_gfclk_sel[] = {
2528 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2529 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2530 { .parent = NULL },
2531};
2532
2533static struct clk utmi_p2_gfclk = {
2534 .name = "utmi_p2_gfclk",
2535 .parent = &init_60m_fclk,
2536 .clksel = utmi_p2_gfclk_sel,
2537 .init = &omap2_init_clksel_parent,
2538 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2540 .ops = &clkops_null,
2541 .recalc = &omap2_clksel_recalc,
2542};
2543
2544static struct clk usb_host_hs_utmi_p2_clk = {
2545 .name = "usb_host_hs_utmi_p2_clk",
2546 .ops = &clkops_omap2_dflt,
2547 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2548 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2549 .clkdm_name = "l3_init_clkdm",
2550 .parent = &utmi_p2_gfclk,
2551 .recalc = &followparent_recalc,
2552};
2553
2554static struct clk usb_host_hs_utmi_p3_clk = {
2555 .name = "usb_host_hs_utmi_p3_clk",
2556 .ops = &clkops_omap2_dflt,
2557 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2558 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2559 .clkdm_name = "l3_init_clkdm",
2560 .parent = &init_60m_fclk,
2561 .recalc = &followparent_recalc,
2562};
2563
2564static struct clk usb_host_hs_hsic480m_p1_clk = {
2565 .name = "usb_host_hs_hsic480m_p1_clk",
2566 .ops = &clkops_omap2_dflt,
2567 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2568 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2569 .clkdm_name = "l3_init_clkdm",
2570 .parent = &dpll_usb_m2_ck,
2571 .recalc = &followparent_recalc,
2572};
2573
2574static struct clk usb_host_hs_hsic60m_p1_clk = {
2575 .name = "usb_host_hs_hsic60m_p1_clk",
2576 .ops = &clkops_omap2_dflt,
2577 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2578 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2579 .clkdm_name = "l3_init_clkdm",
2580 .parent = &init_60m_fclk,
2581 .recalc = &followparent_recalc,
2582};
2583
2584static struct clk usb_host_hs_hsic60m_p2_clk = {
2585 .name = "usb_host_hs_hsic60m_p2_clk",
2586 .ops = &clkops_omap2_dflt,
2587 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2588 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2589 .clkdm_name = "l3_init_clkdm",
2590 .parent = &init_60m_fclk,
2591 .recalc = &followparent_recalc,
2592};
2593
2594static struct clk usb_host_hs_hsic480m_p2_clk = {
2595 .name = "usb_host_hs_hsic480m_p2_clk",
2596 .ops = &clkops_omap2_dflt,
2597 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2598 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2599 .clkdm_name = "l3_init_clkdm",
2600 .parent = &dpll_usb_m2_ck,
2601 .recalc = &followparent_recalc,
2602};
2603
2604static struct clk usb_host_hs_func48mclk = {
2605 .name = "usb_host_hs_func48mclk",
2606 .ops = &clkops_omap2_dflt,
2607 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2608 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2609 .clkdm_name = "l3_init_clkdm",
2610 .parent = &func_48mc_fclk,
2611 .recalc = &followparent_recalc,
2612};
2613
2614static struct clk usb_host_hs_fck = {
2615 .name = "usb_host_hs_fck",
2616 .ops = &clkops_omap2_dflt,
2617 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2618 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2619 .clkdm_name = "l3_init_clkdm",
2620 .parent = &init_60m_fclk,
2621 .recalc = &followparent_recalc,
2622};
2623
2624static const struct clksel otg_60m_gfclk_sel[] = {
2625 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2626 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2627 { .parent = NULL },
2628};
2629
2630static struct clk otg_60m_gfclk = {
2631 .name = "otg_60m_gfclk",
2632 .parent = &utmi_phy_clkout_ck,
2633 .clksel = otg_60m_gfclk_sel,
2634 .init = &omap2_init_clksel_parent,
2635 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2636 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2637 .ops = &clkops_null,
2638 .recalc = &omap2_clksel_recalc,
2639};
2640
2641static struct clk usb_otg_hs_xclk = {
2642 .name = "usb_otg_hs_xclk",
2643 .ops = &clkops_omap2_dflt,
2644 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2645 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2646 .clkdm_name = "l3_init_clkdm",
2647 .parent = &otg_60m_gfclk,
2648 .recalc = &followparent_recalc,
2649};
2650
2651static struct clk usb_otg_hs_ick = {
2652 .name = "usb_otg_hs_ick",
2653 .ops = &clkops_omap2_dflt,
2654 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2655 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2656 .clkdm_name = "l3_init_clkdm",
2657 .parent = &l3_div_ck,
2658 .recalc = &followparent_recalc,
2659};
2660
2661static struct clk usb_phy_cm_clk32k = {
2662 .name = "usb_phy_cm_clk32k",
2663 .ops = &clkops_omap2_dflt,
2664 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2665 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2666 .clkdm_name = "l4_ao_clkdm",
2667 .parent = &sys_32k_ck,
2668 .recalc = &followparent_recalc,
2669};
2670
2671static struct clk usb_tll_hs_usb_ch2_clk = {
2672 .name = "usb_tll_hs_usb_ch2_clk",
2673 .ops = &clkops_omap2_dflt,
2674 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2675 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2676 .clkdm_name = "l3_init_clkdm",
2677 .parent = &init_60m_fclk,
2678 .recalc = &followparent_recalc,
2679};
2680
2681static struct clk usb_tll_hs_usb_ch0_clk = {
2682 .name = "usb_tll_hs_usb_ch0_clk",
2683 .ops = &clkops_omap2_dflt,
2684 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2685 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2686 .clkdm_name = "l3_init_clkdm",
2687 .parent = &init_60m_fclk,
2688 .recalc = &followparent_recalc,
2689};
2690
2691static struct clk usb_tll_hs_usb_ch1_clk = {
2692 .name = "usb_tll_hs_usb_ch1_clk",
2693 .ops = &clkops_omap2_dflt,
2694 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2695 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2696 .clkdm_name = "l3_init_clkdm",
2697 .parent = &init_60m_fclk,
2698 .recalc = &followparent_recalc,
2699};
2700
2701static struct clk usb_tll_hs_ick = {
2702 .name = "usb_tll_hs_ick",
2703 .ops = &clkops_omap2_dflt,
2704 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2705 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2706 .clkdm_name = "l3_init_clkdm",
2707 .parent = &l4_div_ck,
2708 .recalc = &followparent_recalc,
2709};
2710
2711static const struct clksel_rate div2_14to18_rates[] = {
2712 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2713 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2714 { .div = 0 },
2715};
2716
2717static const struct clksel usim_fclk_div[] = {
2718 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2719 { .parent = NULL },
2720};
2721
2722static struct clk usim_ck = {
2723 .name = "usim_ck",
2724 .parent = &dpll_per_m4x2_ck,
2725 .clksel = usim_fclk_div,
2726 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2727 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2728 .ops = &clkops_null,
2729 .recalc = &omap2_clksel_recalc,
2730 .round_rate = &omap2_clksel_round_rate,
2731 .set_rate = &omap2_clksel_set_rate,
2732};
2733
2734static struct clk usim_fclk = {
2735 .name = "usim_fclk",
2736 .ops = &clkops_omap2_dflt,
2737 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2738 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2739 .clkdm_name = "l4_wkup_clkdm",
2740 .parent = &usim_ck,
2741 .recalc = &followparent_recalc,
2742};
2743
2744static struct clk usim_fck = {
2745 .name = "usim_fck",
2746 .ops = &clkops_omap2_dflt,
2747 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2748 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2749 .clkdm_name = "l4_wkup_clkdm",
2750 .parent = &sys_32k_ck,
2751 .recalc = &followparent_recalc,
2752};
2753
2754static struct clk wd_timer2_fck = {
2755 .name = "wd_timer2_fck",
2756 .ops = &clkops_omap2_dflt,
2757 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2758 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2759 .clkdm_name = "l4_wkup_clkdm",
2760 .parent = &sys_32k_ck,
2761 .recalc = &followparent_recalc,
2762};
2763
2764static struct clk wd_timer3_fck = {
2765 .name = "wd_timer3_fck",
2766 .ops = &clkops_omap2_dflt,
2767 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2768 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2769 .clkdm_name = "abe_clkdm",
2770 .parent = &sys_32k_ck,
2771 .recalc = &followparent_recalc,
2772};
2773
2774/* Remaining optional clocks */
2775static const struct clksel stm_clk_div_div[] = {
2776 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2777 { .parent = NULL },
2778};
2779
2780static struct clk stm_clk_div_ck = {
2781 .name = "stm_clk_div_ck",
2782 .parent = &pmd_stm_clock_mux_ck,
2783 .clksel = stm_clk_div_div,
2784 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2785 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2786 .ops = &clkops_null,
2787 .recalc = &omap2_clksel_recalc,
2788 .round_rate = &omap2_clksel_round_rate,
2789 .set_rate = &omap2_clksel_set_rate,
2790};
2791
2792static const struct clksel trace_clk_div_div[] = {
2793 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2794 { .parent = NULL },
2795};
2796
2797static struct clk trace_clk_div_ck = {
2798 .name = "trace_clk_div_ck",
2799 .parent = &pmd_trace_clk_mux_ck,
2800 .clksel = trace_clk_div_div,
2801 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2802 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2803 .ops = &clkops_null,
2804 .recalc = &omap2_clksel_recalc,
2805 .round_rate = &omap2_clksel_round_rate,
2806 .set_rate = &omap2_clksel_set_rate,
2807};
2808
2809/* SCRM aux clk nodes */
2810
2811static const struct clksel auxclk_src_sel[] = {
2812 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2813 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2814 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2815 { .parent = NULL },
2816};
2817
2818static const struct clksel_rate div16_1to16_rates[] = {
2819 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2820 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2821 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2822 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2823 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2824 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2825 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2826 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2827 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2828 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2829 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2830 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2831 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2832 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2833 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2834 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2835 { .div = 0 },
2836};
2837
2838static struct clk auxclk0_src_ck = {
2839 .name = "auxclk0_src_ck",
2840 .parent = &sys_clkin_ck,
2841 .init = &omap2_init_clksel_parent,
2842 .ops = &clkops_omap2_dflt,
2843 .clksel = auxclk_src_sel,
2844 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2845 .clksel_mask = OMAP4_SRCSELECT_MASK,
2846 .recalc = &omap2_clksel_recalc,
2847 .enable_reg = OMAP4_SCRM_AUXCLK0,
2848 .enable_bit = OMAP4_ENABLE_SHIFT,
2849};
2850
2851static const struct clksel auxclk0_sel[] = {
2852 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2853 { .parent = NULL },
2854};
2855
2856static struct clk auxclk0_ck = {
2857 .name = "auxclk0_ck",
2858 .parent = &auxclk0_src_ck,
2859 .clksel = auxclk0_sel,
2860 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2861 .clksel_mask = OMAP4_CLKDIV_MASK,
2862 .ops = &clkops_null,
2863 .recalc = &omap2_clksel_recalc,
2864 .round_rate = &omap2_clksel_round_rate,
2865 .set_rate = &omap2_clksel_set_rate,
2866};
2867
2868static struct clk auxclk1_src_ck = {
2869 .name = "auxclk1_src_ck",
2870 .parent = &sys_clkin_ck,
2871 .init = &omap2_init_clksel_parent,
2872 .ops = &clkops_omap2_dflt,
2873 .clksel = auxclk_src_sel,
2874 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2875 .clksel_mask = OMAP4_SRCSELECT_MASK,
2876 .recalc = &omap2_clksel_recalc,
2877 .enable_reg = OMAP4_SCRM_AUXCLK1,
2878 .enable_bit = OMAP4_ENABLE_SHIFT,
2879};
2880
2881static const struct clksel auxclk1_sel[] = {
2882 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2883 { .parent = NULL },
2884};
2885
2886static struct clk auxclk1_ck = {
2887 .name = "auxclk1_ck",
2888 .parent = &auxclk1_src_ck,
2889 .clksel = auxclk1_sel,
2890 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2891 .clksel_mask = OMAP4_CLKDIV_MASK,
2892 .ops = &clkops_null,
2893 .recalc = &omap2_clksel_recalc,
2894 .round_rate = &omap2_clksel_round_rate,
2895 .set_rate = &omap2_clksel_set_rate,
2896};
2897
2898static struct clk auxclk2_src_ck = {
2899 .name = "auxclk2_src_ck",
2900 .parent = &sys_clkin_ck,
2901 .init = &omap2_init_clksel_parent,
2902 .ops = &clkops_omap2_dflt,
2903 .clksel = auxclk_src_sel,
2904 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2905 .clksel_mask = OMAP4_SRCSELECT_MASK,
2906 .recalc = &omap2_clksel_recalc,
2907 .enable_reg = OMAP4_SCRM_AUXCLK2,
2908 .enable_bit = OMAP4_ENABLE_SHIFT,
2909};
2910
2911static const struct clksel auxclk2_sel[] = {
2912 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2913 { .parent = NULL },
2914};
2915
2916static struct clk auxclk2_ck = {
2917 .name = "auxclk2_ck",
2918 .parent = &auxclk2_src_ck,
2919 .clksel = auxclk2_sel,
2920 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2921 .clksel_mask = OMAP4_CLKDIV_MASK,
2922 .ops = &clkops_null,
2923 .recalc = &omap2_clksel_recalc,
2924 .round_rate = &omap2_clksel_round_rate,
2925 .set_rate = &omap2_clksel_set_rate,
2926};
2927
2928static struct clk auxclk3_src_ck = {
2929 .name = "auxclk3_src_ck",
2930 .parent = &sys_clkin_ck,
2931 .init = &omap2_init_clksel_parent,
2932 .ops = &clkops_omap2_dflt,
2933 .clksel = auxclk_src_sel,
2934 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2935 .clksel_mask = OMAP4_SRCSELECT_MASK,
2936 .recalc = &omap2_clksel_recalc,
2937 .enable_reg = OMAP4_SCRM_AUXCLK3,
2938 .enable_bit = OMAP4_ENABLE_SHIFT,
2939};
2940
2941static const struct clksel auxclk3_sel[] = {
2942 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2943 { .parent = NULL },
2944};
2945
2946static struct clk auxclk3_ck = {
2947 .name = "auxclk3_ck",
2948 .parent = &auxclk3_src_ck,
2949 .clksel = auxclk3_sel,
2950 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2951 .clksel_mask = OMAP4_CLKDIV_MASK,
2952 .ops = &clkops_null,
2953 .recalc = &omap2_clksel_recalc,
2954 .round_rate = &omap2_clksel_round_rate,
2955 .set_rate = &omap2_clksel_set_rate,
2956};
2957
2958static struct clk auxclk4_src_ck = {
2959 .name = "auxclk4_src_ck",
2960 .parent = &sys_clkin_ck,
2961 .init = &omap2_init_clksel_parent,
2962 .ops = &clkops_omap2_dflt,
2963 .clksel = auxclk_src_sel,
2964 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2965 .clksel_mask = OMAP4_SRCSELECT_MASK,
2966 .recalc = &omap2_clksel_recalc,
2967 .enable_reg = OMAP4_SCRM_AUXCLK4,
2968 .enable_bit = OMAP4_ENABLE_SHIFT,
2969};
2970
2971static const struct clksel auxclk4_sel[] = {
2972 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2973 { .parent = NULL },
2974};
2975
2976static struct clk auxclk4_ck = {
2977 .name = "auxclk4_ck",
2978 .parent = &auxclk4_src_ck,
2979 .clksel = auxclk4_sel,
2980 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2981 .clksel_mask = OMAP4_CLKDIV_MASK,
2982 .ops = &clkops_null,
2983 .recalc = &omap2_clksel_recalc,
2984 .round_rate = &omap2_clksel_round_rate,
2985 .set_rate = &omap2_clksel_set_rate,
2986};
2987
2988static struct clk auxclk5_src_ck = {
2989 .name = "auxclk5_src_ck",
2990 .parent = &sys_clkin_ck,
2991 .init = &omap2_init_clksel_parent,
2992 .ops = &clkops_omap2_dflt,
2993 .clksel = auxclk_src_sel,
2994 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2995 .clksel_mask = OMAP4_SRCSELECT_MASK,
2996 .recalc = &omap2_clksel_recalc,
2997 .enable_reg = OMAP4_SCRM_AUXCLK5,
2998 .enable_bit = OMAP4_ENABLE_SHIFT,
2999};
3000
3001static const struct clksel auxclk5_sel[] = {
3002 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3003 { .parent = NULL },
3004};
3005
3006static struct clk auxclk5_ck = {
3007 .name = "auxclk5_ck",
3008 .parent = &auxclk5_src_ck,
3009 .clksel = auxclk5_sel,
3010 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3011 .clksel_mask = OMAP4_CLKDIV_MASK,
3012 .ops = &clkops_null,
3013 .recalc = &omap2_clksel_recalc,
3014 .round_rate = &omap2_clksel_round_rate,
3015 .set_rate = &omap2_clksel_set_rate,
3016};
3017
3018static const struct clksel auxclkreq_sel[] = {
3019 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
3020 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
3021 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
3022 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
3023 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
3024 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
3025 { .parent = NULL },
3026};
3027
3028static struct clk auxclkreq0_ck = {
3029 .name = "auxclkreq0_ck",
3030 .parent = &auxclk0_ck,
3031 .init = &omap2_init_clksel_parent,
3032 .ops = &clkops_null,
3033 .clksel = auxclkreq_sel,
3034 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
3035 .clksel_mask = OMAP4_MAPPING_MASK,
3036 .recalc = &omap2_clksel_recalc,
3037};
3038
3039static struct clk auxclkreq1_ck = {
3040 .name = "auxclkreq1_ck",
3041 .parent = &auxclk1_ck,
3042 .init = &omap2_init_clksel_parent,
3043 .ops = &clkops_null,
3044 .clksel = auxclkreq_sel,
3045 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
3046 .clksel_mask = OMAP4_MAPPING_MASK,
3047 .recalc = &omap2_clksel_recalc,
3048};
3049
3050static struct clk auxclkreq2_ck = {
3051 .name = "auxclkreq2_ck",
3052 .parent = &auxclk2_ck,
3053 .init = &omap2_init_clksel_parent,
3054 .ops = &clkops_null,
3055 .clksel = auxclkreq_sel,
3056 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
3057 .clksel_mask = OMAP4_MAPPING_MASK,
3058 .recalc = &omap2_clksel_recalc,
3059};
3060
3061static struct clk auxclkreq3_ck = {
3062 .name = "auxclkreq3_ck",
3063 .parent = &auxclk3_ck,
3064 .init = &omap2_init_clksel_parent,
3065 .ops = &clkops_null,
3066 .clksel = auxclkreq_sel,
3067 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
3068 .clksel_mask = OMAP4_MAPPING_MASK,
3069 .recalc = &omap2_clksel_recalc,
3070};
3071
3072static struct clk auxclkreq4_ck = {
3073 .name = "auxclkreq4_ck",
3074 .parent = &auxclk4_ck,
3075 .init = &omap2_init_clksel_parent,
3076 .ops = &clkops_null,
3077 .clksel = auxclkreq_sel,
3078 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
3079 .clksel_mask = OMAP4_MAPPING_MASK,
3080 .recalc = &omap2_clksel_recalc,
3081};
3082
3083static struct clk auxclkreq5_ck = {
3084 .name = "auxclkreq5_ck",
3085 .parent = &auxclk5_ck,
3086 .init = &omap2_init_clksel_parent,
3087 .ops = &clkops_null,
3088 .clksel = auxclkreq_sel,
3089 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3090 .clksel_mask = OMAP4_MAPPING_MASK,
3091 .recalc = &omap2_clksel_recalc,
3092};
3093
3094/*
3095 * clkdev
3096 */
3097
3098static struct omap_clk omap44xx_clks[] = {
3099 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
3100 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
3101 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
3102 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
3103 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
3104 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
3105 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
3106 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
3107 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
3108 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
3109 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
3110 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
3111 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
3112 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3113 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
3114 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
3115 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
3116 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
3117 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
3118 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
3119 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
3120 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3121 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
3122 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
3123 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
3124 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
3125 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
3126 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
3127 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
3128 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
3129 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3130 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
3131 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
3132 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
3133 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
3134 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
3135 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
3136 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
3137 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
3138 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
3139 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
3140 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
3141 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
3142 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
3143 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
3144 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
3145 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
3146 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3147 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
3148 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
3149 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
3150 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
3151 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
3152 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
3153 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3154 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
3155 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
3156 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
3157 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
3158 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3159 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3160 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3161 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3162 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3163 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
3164 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
3165 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
3166 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
3167 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
3168 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
3169 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
3170 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3171 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3172 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3173 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3174 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3175 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3176 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3177 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3178 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3179 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3180 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3181 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3182 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3183 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
3184 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
3185 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3186 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3187 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3188 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3189 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3190 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3191 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3192 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3193 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3194 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3195 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3196 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3197 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3198 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3199 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3200 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3201 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
3202 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
3203 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
3204 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
3205 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3206 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
3207 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3208 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
3209 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3210 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
3211 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3212 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
3213 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3214 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
3215 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3216 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3217 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3218 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3219 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3220 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3221 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3222 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3223 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3224 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3225 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3226 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
3227 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
3228 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
3229 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
3230 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
3231 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3232 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3233 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3234 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3235 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3236 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3237 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3238 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3239 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3240 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3241 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3242 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3243 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3244 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3245 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3246 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3247 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3248 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3249 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3250 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3251 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3252 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3253 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3254 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3255 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3256 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3257 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3258 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3259 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3260 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
3261 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3262 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3263 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3264 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
3265 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
3266 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
3267 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
3268 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
3269 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
3270 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
3271 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
3272 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
3273 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
3274 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
3275 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
3276 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
3277 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
3278 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
3279 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
3280 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
3281 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3282 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3283 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3284 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
3285 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3286 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3287 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3288 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3289 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3290 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3291 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3292 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3293 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3294 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3295 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
3296 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3297 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3298 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3299 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3300 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3301 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3302 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3303 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3304 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3305 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3306 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3307 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3308 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3309 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3310 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3311 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3312 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3313 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3314 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3315 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3316 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3317 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3318 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3319 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3320 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3321 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3322 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3323 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3324 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3325 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3326 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3327 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3328 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3329 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3330 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3331 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
3332 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
3333 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
3334 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
3335 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
3336 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
3337 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
3338 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
3339 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
3340 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
3341 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3342 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3343 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3344 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3345 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3346 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3347 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3348 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3349 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3350 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3351 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3352 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3353 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
3354 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
3355 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
3356 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
3357 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
3358 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
3359 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3360 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3361 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3362 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3363 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3364 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3365 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3366};
3367
3368int __init omap4xxx_clk_init(void)
3369{
3370 struct omap_clk *c;
3371 u32 cpu_clkflg;
3372
3373 if (cpu_is_omap44xx()) {
3374 cpu_mask = RATE_IN_4430;
3375 cpu_clkflg = CK_443X;
3376 } else if (cpu_is_omap446x()) {
3377 cpu_mask = RATE_IN_4460;
3378 cpu_clkflg = CK_446X;
3379 } else {
3380 return 0;
3381 }
3382
3383 clk_init(&omap2_clk_functions);
3384
3385 /*
3386 * Must stay commented until all OMAP SoC drivers are
3387 * converted to runtime PM, or drivers may start crashing
3388 *
3389 * omap2_clk_disable_clkdm_control();
3390 */
3391
3392 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3393 c++)
3394 clk_preinit(c->lk.clk);
3395
3396 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3397 c++)
3398 if (c->cpu & cpu_clkflg) {
3399 clkdev_add(&c->lk);
3400 clk_register(c->lk.clk);
3401 omap2_init_clk_clkdm(c->lk.clk);
3402 }
3403
3404 /* Disable autoidle on all clocks; let the PM code enable it later */
3405 omap_clk_disable_autoidle_all();
3406
3407 recalculate_root_clocks();
3408
3409 /*
3410 * Only enable those clocks we will need, let the drivers
3411 * enable other clocks as necessary
3412 */
3413 clk_enable_init_clocks();
3414
3415 return 0;
3416}
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
new file mode 100644
index 00000000000..f740edb111f
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -0,0 +1,276 @@
1/*
2 * OMAP2 and OMAP3 clockdomain control
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/types.h>
16#include <plat/prcm.h>
17#include "prm.h"
18#include "prm2xxx_3xxx.h"
19#include "cm.h"
20#include "cm2xxx_3xxx.h"
21#include "cm-regbits-24xx.h"
22#include "cm-regbits-34xx.h"
23#include "prm-regbits-24xx.h"
24#include "clockdomain.h"
25
26static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
27 struct clockdomain *clkdm2)
28{
29 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
30 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
31 return 0;
32}
33
34static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
35 struct clockdomain *clkdm2)
36{
37 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
38 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
39 return 0;
40}
41
42static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
43 struct clockdomain *clkdm2)
44{
45 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
46 PM_WKDEP, (1 << clkdm2->dep_bit));
47}
48
49static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 /* PRM accesses are slow, so minimize them */
61 mask |= 1 << cd->clkdm->dep_bit;
62 atomic_set(&cd->wkdep_usecount, 0);
63 }
64
65 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
66 PM_WKDEP);
67 return 0;
68}
69
70static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
71 struct clockdomain *clkdm2)
72{
73 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
74 clkdm1->pwrdm.ptr->prcm_offs,
75 OMAP3430_CM_SLEEPDEP);
76 return 0;
77}
78
79static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
80 struct clockdomain *clkdm2)
81{
82 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
83 clkdm1->pwrdm.ptr->prcm_offs,
84 OMAP3430_CM_SLEEPDEP);
85 return 0;
86}
87
88static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
89 struct clockdomain *clkdm2)
90{
91 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
92 OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
93}
94
95static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
96{
97 struct clkdm_dep *cd;
98 u32 mask = 0;
99
100 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
101 if (!omap_chip_is(cd->omap_chip))
102 continue;
103 if (!cd->clkdm)
104 continue; /* only happens if data is erroneous */
105
106 /* PRM accesses are slow, so minimize them */
107 mask |= 1 << cd->clkdm->dep_bit;
108 atomic_set(&cd->sleepdep_usecount, 0);
109 }
110 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
111 OMAP3430_CM_SLEEPDEP);
112 return 0;
113}
114
115static int omap2_clkdm_sleep(struct clockdomain *clkdm)
116{
117 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
118 clkdm->pwrdm.ptr->prcm_offs,
119 OMAP2_PM_PWSTCTRL);
120 return 0;
121}
122
123static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
124{
125 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
126 clkdm->pwrdm.ptr->prcm_offs,
127 OMAP2_PM_PWSTCTRL);
128 return 0;
129}
130
131static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
132{
133 if (atomic_read(&clkdm->usecount) > 0)
134 _clkdm_add_autodeps(clkdm);
135
136 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
137 clkdm->clktrctrl_mask);
138}
139
140static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
141{
142 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
143 clkdm->clktrctrl_mask);
144
145 if (atomic_read(&clkdm->usecount) > 0)
146 _clkdm_del_autodeps(clkdm);
147}
148
149static void _enable_hwsup(struct clockdomain *clkdm)
150{
151 if (cpu_is_omap24xx())
152 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
153 clkdm->clktrctrl_mask);
154 else if (cpu_is_omap34xx())
155 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
156 clkdm->clktrctrl_mask);
157}
158
159static void _disable_hwsup(struct clockdomain *clkdm)
160{
161 if (cpu_is_omap24xx())
162 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
163 clkdm->clktrctrl_mask);
164 else if (cpu_is_omap34xx())
165 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
166 clkdm->clktrctrl_mask);
167}
168
169
170static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
171{
172 bool hwsup = false;
173
174 if (!clkdm->clktrctrl_mask)
175 return 0;
176
177 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
178 clkdm->clktrctrl_mask);
179
180 if (hwsup) {
181 /* Disable HW transitions when we are changing deps */
182 _disable_hwsup(clkdm);
183 _clkdm_add_autodeps(clkdm);
184 _enable_hwsup(clkdm);
185 } else {
186 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
187 omap2_clkdm_wakeup(clkdm);
188 }
189
190 return 0;
191}
192
193static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
194{
195 bool hwsup = false;
196
197 if (!clkdm->clktrctrl_mask)
198 return 0;
199
200 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
201 clkdm->clktrctrl_mask);
202
203 if (hwsup) {
204 /* Disable HW transitions when we are changing deps */
205 _disable_hwsup(clkdm);
206 _clkdm_del_autodeps(clkdm);
207 _enable_hwsup(clkdm);
208 } else {
209 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
210 omap2_clkdm_sleep(clkdm);
211 }
212
213 return 0;
214}
215
216static int omap3_clkdm_sleep(struct clockdomain *clkdm)
217{
218 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
219 clkdm->clktrctrl_mask);
220 return 0;
221}
222
223static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
224{
225 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
226 clkdm->clktrctrl_mask);
227 return 0;
228}
229
230static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
231{
232 if (atomic_read(&clkdm->usecount) > 0)
233 _clkdm_add_autodeps(clkdm);
234
235 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
236 clkdm->clktrctrl_mask);
237}
238
239static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
240{
241 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
242 clkdm->clktrctrl_mask);
243
244 if (atomic_read(&clkdm->usecount) > 0)
245 _clkdm_del_autodeps(clkdm);
246}
247
248struct clkdm_ops omap2_clkdm_operations = {
249 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
250 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
251 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
252 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
253 .clkdm_sleep = omap2_clkdm_sleep,
254 .clkdm_wakeup = omap2_clkdm_wakeup,
255 .clkdm_allow_idle = omap2_clkdm_allow_idle,
256 .clkdm_deny_idle = omap2_clkdm_deny_idle,
257 .clkdm_clk_enable = omap2_clkdm_clk_enable,
258 .clkdm_clk_disable = omap2_clkdm_clk_disable,
259};
260
261struct clkdm_ops omap3_clkdm_operations = {
262 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
263 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
264 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
265 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
266 .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
267 .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
268 .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
269 .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
270 .clkdm_sleep = omap3_clkdm_sleep,
271 .clkdm_wakeup = omap3_clkdm_wakeup,
272 .clkdm_allow_idle = omap3_clkdm_allow_idle,
273 .clkdm_deny_idle = omap3_clkdm_deny_idle,
274 .clkdm_clk_enable = omap2_clkdm_clk_enable,
275 .clkdm_clk_disable = omap2_clkdm_clk_disable,
276};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
new file mode 100644
index 00000000000..b43706aa08b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -0,0 +1,132 @@
1/*
2 * OMAP4 clockdomain control
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include "clockdomain.h"
17#include "cminst44xx.h"
18#include "cm44xx.h"
19
20static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
21 struct clockdomain *clkdm2)
22{
23 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
24 clkdm1->prcm_partition,
25 clkdm1->cm_inst, clkdm1->clkdm_offs +
26 OMAP4_CM_STATICDEP);
27 return 0;
28}
29
30static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
31 struct clockdomain *clkdm2)
32{
33 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
34 clkdm1->prcm_partition,
35 clkdm1->cm_inst, clkdm1->clkdm_offs +
36 OMAP4_CM_STATICDEP);
37 return 0;
38}
39
40static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
41 struct clockdomain *clkdm2)
42{
43 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
44 clkdm1->cm_inst, clkdm1->clkdm_offs +
45 OMAP4_CM_STATICDEP,
46 (1 << clkdm2->dep_bit));
47}
48
49static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 mask |= 1 << cd->clkdm->dep_bit;
61 atomic_set(&cd->wkdep_usecount, 0);
62 }
63
64 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
65 clkdm->cm_inst, clkdm->clkdm_offs +
66 OMAP4_CM_STATICDEP);
67 return 0;
68}
69
70static int omap4_clkdm_sleep(struct clockdomain *clkdm)
71{
72 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
73 clkdm->cm_inst, clkdm->clkdm_offs);
74 return 0;
75}
76
77static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
78{
79 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
80 clkdm->cm_inst, clkdm->clkdm_offs);
81 return 0;
82}
83
84static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
85{
86 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
87 clkdm->cm_inst, clkdm->clkdm_offs);
88}
89
90static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
91{
92 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
93 clkdm->cm_inst, clkdm->clkdm_offs);
94}
95
96static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
97{
98 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
99 return omap4_clkdm_wakeup(clkdm);
100
101 return 0;
102}
103
104static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
105{
106 bool hwsup = false;
107
108 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
109 clkdm->cm_inst, clkdm->clkdm_offs);
110
111 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
112 omap4_clkdm_sleep(clkdm);
113
114 return 0;
115}
116
117struct clkdm_ops omap4_clkdm_operations = {
118 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
119 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
120 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
121 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
122 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
123 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
124 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
125 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
126 .clkdm_sleep = omap4_clkdm_sleep,
127 .clkdm_wakeup = omap4_clkdm_wakeup,
128 .clkdm_allow_idle = omap4_clkdm_allow_idle,
129 .clkdm_deny_idle = omap4_clkdm_deny_idle,
130 .clkdm_clk_enable = omap4_clkdm_clk_enable,
131 .clkdm_clk_disable = omap4_clkdm_clk_disable,
132};
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
new file mode 100644
index 00000000000..38830d8d478
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -0,0 +1,557 @@
1/*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/delay.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
21#include <plat/common.h>
22
23#include "cm.h"
24#include "cm2xxx_3xxx.h"
25#include "cm-regbits-24xx.h"
26#include "cm-regbits-34xx.h"
27
28/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
29#define DPLL_AUTOIDLE_DISABLE 0x0
30#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
31
32/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
33#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
34#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
35
36static const u8 cm_idlest_offs[] = {
37 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
38};
39
40u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
41{
42 return __raw_readl(cm_base + module + idx);
43}
44
45void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
46{
47 __raw_writel(val, cm_base + module + idx);
48}
49
50/* Read-modify-write a register in a CM module. Caller must lock */
51u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
52{
53 u32 v;
54
55 v = omap2_cm_read_mod_reg(module, idx);
56 v &= ~mask;
57 v |= bits;
58 omap2_cm_write_mod_reg(v, module, idx);
59
60 return v;
61}
62
63u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
64{
65 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
66}
67
68u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
69{
70 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
71}
72
73/*
74 *
75 */
76
77static void _write_clktrctrl(u8 c, s16 module, u32 mask)
78{
79 u32 v;
80
81 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
82 v &= ~mask;
83 v |= c << __ffs(mask);
84 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
85}
86
87bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
88{
89 u32 v;
90 bool ret = 0;
91
92 BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
93
94 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
95 v &= mask;
96 v >>= __ffs(mask);
97
98 if (cpu_is_omap24xx())
99 ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
100 else
101 ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
102
103 return ret;
104}
105
106void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
107{
108 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
109}
110
111void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
112{
113 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
114}
115
116void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
117{
118 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
119}
120
121void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
122{
123 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
124}
125
126void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
127{
128 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
129}
130
131void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
132{
133 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
134}
135
136/*
137 * DPLL autoidle control
138 */
139
140static void _omap2xxx_set_dpll_autoidle(u8 m)
141{
142 u32 v;
143
144 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
145 v &= ~OMAP24XX_AUTO_DPLL_MASK;
146 v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
147 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
148}
149
150void omap2xxx_cm_set_dpll_disable_autoidle(void)
151{
152 _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
153}
154
155void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
156{
157 _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
158}
159
160/*
161 * APLL autoidle control
162 */
163
164static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
165{
166 u32 v;
167
168 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
169 v &= ~mask;
170 v |= m << __ffs(mask);
171 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
172}
173
174void omap2xxx_cm_set_apll54_disable_autoidle(void)
175{
176 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
177 OMAP24XX_AUTO_54M_MASK);
178}
179
180void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
181{
182 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
183 OMAP24XX_AUTO_54M_MASK);
184}
185
186void omap2xxx_cm_set_apll96_disable_autoidle(void)
187{
188 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
189 OMAP24XX_AUTO_96M_MASK);
190}
191
192void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
193{
194 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
195 OMAP24XX_AUTO_96M_MASK);
196}
197
198/*
199 *
200 */
201
202/**
203 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
204 * @prcm_mod: PRCM module offset
205 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
206 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
207 *
208 * XXX document
209 */
210int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
211{
212 int ena = 0, i = 0;
213 u8 cm_idlest_reg;
214 u32 mask;
215
216 if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
217 return -EINVAL;
218
219 cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
220
221 mask = 1 << idlest_shift;
222
223 if (cpu_is_omap24xx())
224 ena = mask;
225 else if (cpu_is_omap34xx())
226 ena = 0;
227 else
228 BUG();
229
230 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
231 MAX_MODULE_READY_TIME, i);
232
233 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
234}
235
236/*
237 * Context save/restore code - OMAP3 only
238 */
239#ifdef CONFIG_ARCH_OMAP3
240struct omap3_cm_regs {
241 u32 iva2_cm_clksel1;
242 u32 iva2_cm_clksel2;
243 u32 cm_sysconfig;
244 u32 sgx_cm_clksel;
245 u32 dss_cm_clksel;
246 u32 cam_cm_clksel;
247 u32 per_cm_clksel;
248 u32 emu_cm_clksel;
249 u32 emu_cm_clkstctrl;
250 u32 pll_cm_autoidle;
251 u32 pll_cm_autoidle2;
252 u32 pll_cm_clksel4;
253 u32 pll_cm_clksel5;
254 u32 pll_cm_clken2;
255 u32 cm_polctrl;
256 u32 iva2_cm_fclken;
257 u32 iva2_cm_clken_pll;
258 u32 core_cm_fclken1;
259 u32 core_cm_fclken3;
260 u32 sgx_cm_fclken;
261 u32 wkup_cm_fclken;
262 u32 dss_cm_fclken;
263 u32 cam_cm_fclken;
264 u32 per_cm_fclken;
265 u32 usbhost_cm_fclken;
266 u32 core_cm_iclken1;
267 u32 core_cm_iclken2;
268 u32 core_cm_iclken3;
269 u32 sgx_cm_iclken;
270 u32 wkup_cm_iclken;
271 u32 dss_cm_iclken;
272 u32 cam_cm_iclken;
273 u32 per_cm_iclken;
274 u32 usbhost_cm_iclken;
275 u32 iva2_cm_autoidle2;
276 u32 mpu_cm_autoidle2;
277 u32 iva2_cm_clkstctrl;
278 u32 mpu_cm_clkstctrl;
279 u32 core_cm_clkstctrl;
280 u32 sgx_cm_clkstctrl;
281 u32 dss_cm_clkstctrl;
282 u32 cam_cm_clkstctrl;
283 u32 per_cm_clkstctrl;
284 u32 neon_cm_clkstctrl;
285 u32 usbhost_cm_clkstctrl;
286 u32 core_cm_autoidle1;
287 u32 core_cm_autoidle2;
288 u32 core_cm_autoidle3;
289 u32 wkup_cm_autoidle;
290 u32 dss_cm_autoidle;
291 u32 cam_cm_autoidle;
292 u32 per_cm_autoidle;
293 u32 usbhost_cm_autoidle;
294 u32 sgx_cm_sleepdep;
295 u32 dss_cm_sleepdep;
296 u32 cam_cm_sleepdep;
297 u32 per_cm_sleepdep;
298 u32 usbhost_cm_sleepdep;
299 u32 cm_clkout_ctrl;
300};
301
302static struct omap3_cm_regs cm_context;
303
304void omap3_cm_save_context(void)
305{
306 cm_context.iva2_cm_clksel1 =
307 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
308 cm_context.iva2_cm_clksel2 =
309 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
310 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
311 cm_context.sgx_cm_clksel =
312 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
313 cm_context.dss_cm_clksel =
314 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
315 cm_context.cam_cm_clksel =
316 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
317 cm_context.per_cm_clksel =
318 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
319 cm_context.emu_cm_clksel =
320 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
321 cm_context.emu_cm_clkstctrl =
322 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
323 /*
324 * As per erratum i671, ROM code does not respect the PER DPLL
325 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
326 * In this case, even though this register has been saved in
327 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
328 * by ourselves. So, we need to save it anyway.
329 */
330 cm_context.pll_cm_autoidle =
331 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
332 cm_context.pll_cm_autoidle2 =
333 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
334 cm_context.pll_cm_clksel4 =
335 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
336 cm_context.pll_cm_clksel5 =
337 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
338 cm_context.pll_cm_clken2 =
339 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
340 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
341 cm_context.iva2_cm_fclken =
342 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
343 cm_context.iva2_cm_clken_pll =
344 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
345 cm_context.core_cm_fclken1 =
346 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
347 cm_context.core_cm_fclken3 =
348 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
349 cm_context.sgx_cm_fclken =
350 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
351 cm_context.wkup_cm_fclken =
352 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
353 cm_context.dss_cm_fclken =
354 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
355 cm_context.cam_cm_fclken =
356 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
357 cm_context.per_cm_fclken =
358 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
359 cm_context.usbhost_cm_fclken =
360 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
361 cm_context.core_cm_iclken1 =
362 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
363 cm_context.core_cm_iclken2 =
364 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
365 cm_context.core_cm_iclken3 =
366 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
367 cm_context.sgx_cm_iclken =
368 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
369 cm_context.wkup_cm_iclken =
370 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
371 cm_context.dss_cm_iclken =
372 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
373 cm_context.cam_cm_iclken =
374 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
375 cm_context.per_cm_iclken =
376 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
377 cm_context.usbhost_cm_iclken =
378 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
379 cm_context.iva2_cm_autoidle2 =
380 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
381 cm_context.mpu_cm_autoidle2 =
382 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
383 cm_context.iva2_cm_clkstctrl =
384 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
385 cm_context.mpu_cm_clkstctrl =
386 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
387 cm_context.core_cm_clkstctrl =
388 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
389 cm_context.sgx_cm_clkstctrl =
390 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
391 cm_context.dss_cm_clkstctrl =
392 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
393 cm_context.cam_cm_clkstctrl =
394 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
395 cm_context.per_cm_clkstctrl =
396 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
397 cm_context.neon_cm_clkstctrl =
398 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
399 cm_context.usbhost_cm_clkstctrl =
400 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
401 OMAP2_CM_CLKSTCTRL);
402 cm_context.core_cm_autoidle1 =
403 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
404 cm_context.core_cm_autoidle2 =
405 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
406 cm_context.core_cm_autoidle3 =
407 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
408 cm_context.wkup_cm_autoidle =
409 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
410 cm_context.dss_cm_autoidle =
411 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
412 cm_context.cam_cm_autoidle =
413 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
414 cm_context.per_cm_autoidle =
415 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
416 cm_context.usbhost_cm_autoidle =
417 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
418 cm_context.sgx_cm_sleepdep =
419 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
420 OMAP3430_CM_SLEEPDEP);
421 cm_context.dss_cm_sleepdep =
422 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
423 cm_context.cam_cm_sleepdep =
424 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
425 cm_context.per_cm_sleepdep =
426 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
427 cm_context.usbhost_cm_sleepdep =
428 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
429 OMAP3430_CM_SLEEPDEP);
430 cm_context.cm_clkout_ctrl =
431 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
432 OMAP3_CM_CLKOUT_CTRL_OFFSET);
433}
434
435void omap3_cm_restore_context(void)
436{
437 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
438 CM_CLKSEL1);
439 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
440 CM_CLKSEL2);
441 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
442 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
443 CM_CLKSEL);
444 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
445 CM_CLKSEL);
446 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
447 CM_CLKSEL);
448 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
449 CM_CLKSEL);
450 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
451 CM_CLKSEL1);
452 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
453 OMAP2_CM_CLKSTCTRL);
454 /*
455 * As per erratum i671, ROM code does not respect the PER DPLL
456 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
457 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
458 */
459 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
460 CM_AUTOIDLE);
461 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
462 CM_AUTOIDLE2);
463 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
464 OMAP3430ES2_CM_CLKSEL4);
465 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
466 OMAP3430ES2_CM_CLKSEL5);
467 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
468 OMAP3430ES2_CM_CLKEN2);
469 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
470 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
471 CM_FCLKEN);
472 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
473 OMAP3430_CM_CLKEN_PLL);
474 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
475 CM_FCLKEN1);
476 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
477 OMAP3430ES2_CM_FCLKEN3);
478 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
479 CM_FCLKEN);
480 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
481 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
482 CM_FCLKEN);
483 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
484 CM_FCLKEN);
485 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
486 CM_FCLKEN);
487 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
488 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
489 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
490 CM_ICLKEN1);
491 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
492 CM_ICLKEN2);
493 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
494 CM_ICLKEN3);
495 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
496 CM_ICLKEN);
497 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
498 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
499 CM_ICLKEN);
500 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
501 CM_ICLKEN);
502 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
503 CM_ICLKEN);
504 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
505 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
506 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
507 CM_AUTOIDLE2);
508 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
509 CM_AUTOIDLE2);
510 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
511 OMAP2_CM_CLKSTCTRL);
512 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
513 OMAP2_CM_CLKSTCTRL);
514 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
515 OMAP2_CM_CLKSTCTRL);
516 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
517 OMAP2_CM_CLKSTCTRL);
518 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
519 OMAP2_CM_CLKSTCTRL);
520 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
521 OMAP2_CM_CLKSTCTRL);
522 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
523 OMAP2_CM_CLKSTCTRL);
524 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
525 OMAP2_CM_CLKSTCTRL);
526 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
527 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
528 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
529 CM_AUTOIDLE1);
530 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
531 CM_AUTOIDLE2);
532 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
533 CM_AUTOIDLE3);
534 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
535 CM_AUTOIDLE);
536 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
537 CM_AUTOIDLE);
538 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
539 CM_AUTOIDLE);
540 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
541 CM_AUTOIDLE);
542 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
543 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
544 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
545 OMAP3430_CM_SLEEPDEP);
546 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
547 OMAP3430_CM_SLEEPDEP);
548 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
549 OMAP3430_CM_SLEEPDEP);
550 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
551 OMAP3430_CM_SLEEPDEP);
552 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
553 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
554 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
555 OMAP3_CM_CLKOUT_CTRL_OFFSET);
556}
557#endif
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
new file mode 100644
index 00000000000..f1e13d1ca5e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -0,0 +1,44 @@
1/*:
2 * Address mappings and base address for AM35XX specific interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Sriramakrishnan <srk@ti.com>
8 * Vaibhav Hiremath <hvaibhav@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __ASM_ARCH_AM35XX_H
15#define __ASM_ARCH_AM35XX_H
16
17/*
18 * Base addresses
19 * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
20 */
21#define AM35XX_IPSS_EMAC_BASE 0x5C000000
22#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
23#define AM35XX_IPSS_HECC_BASE 0x5C050000
24#define AM35XX_IPSS_VPFE_BASE 0x5C060000
25
26
27/* HECC module specifc offset definitions */
28#define AM35XX_HECC_SCC_HECC_OFFSET (0x0)
29#define AM35XX_HECC_SCC_RAM_OFFSET (0x3000)
30#define AM35XX_HECC_RAM_OFFSET (0x3000)
31#define AM35XX_HECC_MBOX_OFFSET (0x2000)
32#define AM35XX_HECC_INT_LINE (0x0)
33#define AM35XX_HECC_VERSION (0x1)
34
35#define AM35XX_EMAC_CNTRL_OFFSET (0x10000)
36#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
37#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
38#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
39#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
40#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
41 AM3517_EMAC_CNTRL_RAM_OFFSET)
42#define AM35XX_EMAC_HW_RAM_ADDR (0x01E20000)
43
44#endif /* __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h
new file mode 100644
index 00000000000..b76f49e7eed
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-rx51.h
@@ -0,0 +1,11 @@
1/*
2 * Defines for rx51 boards
3 */
4
5#ifndef _OMAP_BOARD_RX51_H
6#define _OMAP_BOARD_RX51_H
7
8extern void __init rx51_peripherals_init(void);
9extern void __init rx51_video_mem_init(void);
10
11#endif
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
new file mode 100644
index 00000000000..775fdc3b000
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -0,0 +1,12 @@
1/*
2 * Defines for zoom boards
3 */
4#include <video/omapdss.h>
5
6#define ZOOM_NAND_CS 0
7
8extern int __init zoom_debugboard_init(void);
9extern void __init zoom_peripherals_init(void);
10extern void __init zoom_display_init(void);
11
12#define ZOOM2_HEADSET_EXTMUTE_GPIO 153
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 00000000000..2f7ac70a20d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
1/*
2 * OMAP44xx CTRL_MODULE_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_CORE 0x4a002000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
32#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
33#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
34#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
35#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
36#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
37#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
38#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
39#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
40#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
41#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
47#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
48#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
49#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
50#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
51#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
52#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
53#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
54#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
55#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
56#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
57#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
58#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
59#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
60#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
61#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
62#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
63#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
64#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
65#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
66#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
67#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
68#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
69#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
70#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
71#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
72#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
73#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
74#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
75#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
76#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
77#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
78#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
79#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
80#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
81#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
82#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
83#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
84#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
85#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
86#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
87#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
88#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
89#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
90#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
91#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
92#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
93#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
94#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
95#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
96#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
97#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
98#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
99#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
100
101/* Registers shifts and masks */
102
103/* IP_REVISION */
104#define OMAP4_IP_REV_SCHEME_SHIFT 30
105#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
106#define OMAP4_IP_REV_FUNC_SHIFT 16
107#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
108#define OMAP4_IP_REV_RTL_SHIFT 11
109#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
110#define OMAP4_IP_REV_MAJOR_SHIFT 8
111#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
112#define OMAP4_IP_REV_CUSTOM_SHIFT 6
113#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
114#define OMAP4_IP_REV_MINOR_SHIFT 0
115#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
116
117/* IP_HWINFO */
118#define OMAP4_IP_HWINFO_SHIFT 0
119#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
120
121/* IP_SYSCONFIG */
122#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
123#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
124
125/* STD_FUSE_DIE_ID_0 */
126#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
127#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
128
129/* ID_CODE */
130#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
131#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
132
133/* STD_FUSE_DIE_ID_1 */
134#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
135#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
136
137/* STD_FUSE_DIE_ID_2 */
138#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
139#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
140
141/* STD_FUSE_DIE_ID_3 */
142#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
143#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
144
145/* STD_FUSE_PROD_ID_0 */
146#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
147#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
148
149/* STD_FUSE_PROD_ID_1 */
150#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
151#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
152
153/* STD_FUSE_USB_CONF */
154#define OMAP4_USB_PROD_ID_SHIFT 16
155#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
156#define OMAP4_USB_VENDOR_ID_SHIFT 0
157#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
158
159/* STD_FUSE_OPP_VDD_WKUP */
160#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
161#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
162
163/* STD_FUSE_OPP_BGAP */
164#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
165#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
166
167/* STD_FUSE_OPP_DPLL_0 */
168#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
169#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
170
171/* STD_FUSE_OPP_DPLL_1 */
172#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
173#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
174
175/* STATUS */
176#define OMAP4_ATTILA_CONF_SHIFT 11
177#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
178#define OMAP4_DEVICE_TYPE_SHIFT 8
179#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
180#define OMAP4_SYS_BOOT_SHIFT 0
181#define OMAP4_SYS_BOOT_MASK (0xff << 0)
182
183/* DEV_CONF */
184#define OMAP4_DEV_CONF_SHIFT 1
185#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
186#define OMAP4_USBPHY_PD_SHIFT 0
187#define OMAP4_USBPHY_PD_MASK (1 << 0)
188
189/* LDOVBB_IVA_VOLTAGE_CTRL */
190#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
191#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
192#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
193#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
194#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
195#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
196#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
197#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
198#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
199#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
200#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
201#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
202
203/* LDOVBB_MPU_VOLTAGE_CTRL */
204#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
205#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
206#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
207#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
208#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
209#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
210#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
211#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
212#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
213#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
214#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
215#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
216
217/* LDOSRAM_IVA_VOLTAGE_CTRL */
218#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
219#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
220#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
221#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
222#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
223#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
224#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
225#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
226#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
227#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
228#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
229#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
230
231/* LDOSRAM_MPU_VOLTAGE_CTRL */
232#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
233#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
234#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
235#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
236#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
237#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
238#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
239#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
240#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
241#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
242#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
243#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
244
245/* LDOSRAM_CORE_VOLTAGE_CTRL */
246#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
247#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
248#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
249#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
250#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
251#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
252#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
253#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
254#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
255#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
256#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
257#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
258
259/* TEMP_SENSOR */
260#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
261#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
262#define OMAP4_BGAP_TSHUT_SHIFT 11
263#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
264#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
265#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
266#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
267#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
268#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
269#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
270#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
271#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
272
273/* DPLL_NWELL_TRIM_0 */
274#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
275#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
276#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
277#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
278#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
279#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
280#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
281#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
282#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
283#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
284#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
285#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
286#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
287#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
288#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
289#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
290#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
291#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
292#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
293#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
294
295/* DPLL_NWELL_TRIM_1 */
296#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
297#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
298#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
299#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
300#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
301#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
302#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
303#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
304#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
305#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
306#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
307#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
308#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
309#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
310#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
311#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
312#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
313#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
314#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
315#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
316
317/* USBOTGHS_CONTROL */
318#define OMAP4_DISCHRGVBUS_SHIFT 8
319#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
320#define OMAP4_CHRGVBUS_SHIFT 7
321#define OMAP4_CHRGVBUS_MASK (1 << 7)
322#define OMAP4_DRVVBUS_SHIFT 6
323#define OMAP4_DRVVBUS_MASK (1 << 6)
324#define OMAP4_IDPULLUP_SHIFT 5
325#define OMAP4_IDPULLUP_MASK (1 << 5)
326#define OMAP4_IDDIG_SHIFT 4
327#define OMAP4_IDDIG_MASK (1 << 4)
328#define OMAP4_SESSEND_SHIFT 3
329#define OMAP4_SESSEND_MASK (1 << 3)
330#define OMAP4_VBUSVALID_SHIFT 2
331#define OMAP4_VBUSVALID_MASK (1 << 2)
332#define OMAP4_BVALID_SHIFT 1
333#define OMAP4_BVALID_MASK (1 << 1)
334#define OMAP4_AVALID_SHIFT 0
335#define OMAP4_AVALID_MASK (1 << 0)
336
337/* DSS_CONTROL */
338#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
339#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
340
341/* HWOBS_CONTROL */
342#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
343#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
344#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
345#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
346#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
347#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
348#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
349#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
350
351/* DEBOBS_FINAL_MUX_SEL */
352#define OMAP4_SELECT_SHIFT 0
353#define OMAP4_SELECT_MASK (0xffffffff << 0)
354
355/* DEBOBS_MMR_MPU */
356#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
357#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
358
359/* CONF_SDMA_REQ_SEL0 */
360#define OMAP4_MULT_SHIFT 0
361#define OMAP4_MULT_MASK (0x7f << 0)
362
363/* CONF_CLK_SEL0 */
364#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
365#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
366
367/* CONF_CLK_SEL1 */
368#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
369#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
370
371/* CONF_CLK_SEL2 */
372#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
373#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
374
375/* CONF_DPLL_FREQLOCK_SEL */
376#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
377#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
378
379/* CONF_DPLL_TINITZ_SEL */
380#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
381#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
382
383/* CONF_DPLL_PHASELOCK_SEL */
384#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
385#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
386
387/* CONF_DEBUG_SEL_TST_0 */
388#define OMAP4_MODE_SHIFT 0
389#define OMAP4_MODE_MASK (0xf << 0)
390
391#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 00000000000..c88420de115
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
32#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
33#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
34#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
35#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
36#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
37#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
38#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
39#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
40#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
41#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
42#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
43#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
44#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
45#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
46#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
47#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
48#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
49#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
50#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
51#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
52#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
53#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
54#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
55#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
56#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
57#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
58#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
59#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
60#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
61#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
62#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
63#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
64#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
65#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
66#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
67#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
68#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
69#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
70#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
71#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
72#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
73#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
74#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
75#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
76#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
77#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
78#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
79#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
80
81/* Registers shifts and masks */
82
83/* IP_REVISION */
84#define OMAP4_IP_REV_SCHEME_SHIFT 30
85#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
86#define OMAP4_IP_REV_FUNC_SHIFT 16
87#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
88#define OMAP4_IP_REV_RTL_SHIFT 11
89#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
90#define OMAP4_IP_REV_MAJOR_SHIFT 8
91#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
92#define OMAP4_IP_REV_CUSTOM_SHIFT 6
93#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
94#define OMAP4_IP_REV_MINOR_SHIFT 0
95#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
96
97/* IP_HWINFO */
98#define OMAP4_IP_HWINFO_SHIFT 0
99#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
100
101/* IP_SYSCONFIG */
102#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
103#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
104
105/* PADCONF_WAKEUPEVENT_0 */
106#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
107#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
108#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
109#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
110#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
111#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
112#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
113#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
114#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
115#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
116#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
117#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
118#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
119#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
120#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
121#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
122#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
123#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
124#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
125#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
126#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
127#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
128#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
129#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
130#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
131#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
132#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
133#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
134#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
135#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
136#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
137#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
138#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
139#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
140#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
141#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
142#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
143#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
144#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
145#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
146#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
147#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
148#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
149#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
150#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
151#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
152#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
153#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
154#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
155#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
156#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
157#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
158#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
159#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
160#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
161#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
162#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
163#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
164#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
165#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
166#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
167#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
168#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
169#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
170
171/* PADCONF_WAKEUPEVENT_1 */
172#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
173#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
174#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
175#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
176#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
177#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
178#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
179#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
180#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
181#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
182#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
183#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
184#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
185#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
186#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
187#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
188#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
189#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
190#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
191#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
192#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
193#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
194#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
195#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
196#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
197#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
198#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
199#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
200#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
201#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
202#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
203#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
204#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
205#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
206#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
207#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
208#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
209#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
210#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
211#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
212#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
213#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
214#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
215#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
216#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
217#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
218#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
219#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
220#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
221#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
222#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
223#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
224#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
225#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
226#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
227#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
228#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
229#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
230#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
231#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
232#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
233#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
234#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
235#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
236
237/* PADCONF_WAKEUPEVENT_2 */
238#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
239#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
240#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
241#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
242#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
243#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
244#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
245#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
246#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
247#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
248#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
249#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
250#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
251#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
252#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
253#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
254#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
255#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
256#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
257#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
258#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
259#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
260#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
261#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
262#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
263#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
264#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
265#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
266#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
267#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
268#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
269#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
270#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
271#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
272#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
273#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
274#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
275#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
276#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
277#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
278#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
279#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
280#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
281#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
282#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
283#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
284#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
285#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
286#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
287#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
288#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
289#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
290#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
291#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
292#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
293#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
294#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
295#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
296#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
297#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
298#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
299#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
300#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
301#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
302
303/* PADCONF_WAKEUPEVENT_3 */
304#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
305#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
306#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
307#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
308#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
309#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
310#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
311#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
312#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
313#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
314#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
315#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
316#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
317#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
318#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
319#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
320#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
321#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
322#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
323#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
324#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
325#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
326#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
327#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
328#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
329#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
330#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
331#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
332#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
333#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
334#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
335#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
336#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
337#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
338#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
339#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
340#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
341#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
342#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
343#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
344#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
345#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
346#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
347#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
348#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
349#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
350#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
351#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
352#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
353#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
354#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
355#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
356#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
357#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
358#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
359#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
360#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
361#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
362#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
363#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
364#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
365#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
366#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
367#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
368
369/* PADCONF_WAKEUPEVENT_4 */
370#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
371#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
372#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
373#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
374#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
375#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
376#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
377#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
378#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
379#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
380#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
381#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
382#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
383#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
384#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
385#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
386#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
387#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
388#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
389#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
390#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
391#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
392#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
393#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
394#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
395#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
396#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
397#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
398#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
399#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
400#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
401#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
402#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
403#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
404#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
405#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
406#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
407#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
408#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
409#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
410#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
411#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
412#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
413#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
414#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
415#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
416#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
417#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
418#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
419#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
420#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
421#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
422#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
423#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
424#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
425#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
426#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
427#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
428#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
429#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
430#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
431#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
432#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
433#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
434
435/* PADCONF_WAKEUPEVENT_5 */
436#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
437#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
438#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
439#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
440#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
441#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
442#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
443#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
444#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
445#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
446#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
447#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
448#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
449#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
450#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
451#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
452#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
453#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
454#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
455#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
456#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
457#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
458#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
459#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
460#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
461#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
462#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
463#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
464#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
465#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
466#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
467#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
468#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
469#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
470#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
471#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
472#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
473#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
474#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
475#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
476#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
477#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
478#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
479#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
480#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
481#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
482#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
483#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
484#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
485#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
486#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
487#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
488#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
489#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
490#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
491#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
492#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
493#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
494#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
495#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
496#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
497#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
498#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
499#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
500
501/* PADCONF_WAKEUPEVENT_6 */
502#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
503#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
504#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
505#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
506#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
507#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
508#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
509#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
510#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
511#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
512#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
513#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
514#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
515#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
516#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
517#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
518
519/* CONTROL_PADCONF_GLOBAL */
520#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
521#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
522
523/* CONTROL_PADCONF_MODE */
524#define OMAP4_VDDS_DV_BANK0_SHIFT 31
525#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
526#define OMAP4_VDDS_DV_BANK1_SHIFT 30
527#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
528#define OMAP4_VDDS_DV_BANK3_SHIFT 29
529#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
530#define OMAP4_VDDS_DV_BANK4_SHIFT 28
531#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
532#define OMAP4_VDDS_DV_BANK5_SHIFT 27
533#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
534#define OMAP4_VDDS_DV_BANK6_SHIFT 26
535#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
536#define OMAP4_VDDS_DV_C2C_SHIFT 25
537#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
538#define OMAP4_VDDS_DV_CAM_SHIFT 24
539#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
540#define OMAP4_VDDS_DV_GPMC_SHIFT 23
541#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
542#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
543#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
544
545/* CONTROL_SMART1IO_PADCONF_0 */
546#define OMAP4_ABE_DR0_SC_SHIFT 30
547#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
548#define OMAP4_CAM_DR0_SC_SHIFT 28
549#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
550#define OMAP4_FREF_DR2_SC_SHIFT 26
551#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
552#define OMAP4_FREF_DR3_SC_SHIFT 24
553#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
554#define OMAP4_GPIO_DR8_SC_SHIFT 22
555#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
556#define OMAP4_GPIO_DR9_SC_SHIFT 20
557#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
558#define OMAP4_GPMC_DR2_SC_SHIFT 18
559#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
560#define OMAP4_GPMC_DR3_SC_SHIFT 16
561#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
562#define OMAP4_GPMC_DR6_SC_SHIFT 14
563#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
564#define OMAP4_HDMI_DR0_SC_SHIFT 12
565#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
566#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
567#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
568#define OMAP4_UART1_DR0_SC_SHIFT 8
569#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
570#define OMAP4_UART3_DR0_SC_SHIFT 6
571#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
572#define OMAP4_UART3_DR1_SC_SHIFT 4
573#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
574#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
575#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
576#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
577#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
578
579/* CONTROL_SMART1IO_PADCONF_1 */
580#define OMAP4_ABE_DR0_LB_SHIFT 30
581#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
582#define OMAP4_CAM_DR0_LB_SHIFT 28
583#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
584#define OMAP4_FREF_DR2_LB_SHIFT 26
585#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
586#define OMAP4_FREF_DR3_LB_SHIFT 24
587#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
588#define OMAP4_GPIO_DR8_LB_SHIFT 22
589#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
590#define OMAP4_GPIO_DR9_LB_SHIFT 20
591#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
592#define OMAP4_GPMC_DR2_LB_SHIFT 18
593#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
594#define OMAP4_GPMC_DR3_LB_SHIFT 16
595#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
596#define OMAP4_GPMC_DR6_LB_SHIFT 14
597#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
598#define OMAP4_HDMI_DR0_LB_SHIFT 12
599#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
600#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
601#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
602#define OMAP4_UART1_DR0_LB_SHIFT 8
603#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
604#define OMAP4_UART3_DR0_LB_SHIFT 6
605#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
606#define OMAP4_UART3_DR1_LB_SHIFT 4
607#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
608#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
609#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
610#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
611#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
612
613/* CONTROL_SMART2IO_PADCONF_0 */
614#define OMAP4_C2C_DR0_LB_SHIFT 31
615#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
616#define OMAP4_DPM_DR1_LB_SHIFT 30
617#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
618#define OMAP4_DPM_DR2_LB_SHIFT 29
619#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
620#define OMAP4_DPM_DR3_LB_SHIFT 28
621#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
622#define OMAP4_GPIO_DR0_LB_SHIFT 27
623#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
624#define OMAP4_GPIO_DR1_LB_SHIFT 26
625#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
626#define OMAP4_GPIO_DR10_LB_SHIFT 25
627#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
628#define OMAP4_GPIO_DR2_LB_SHIFT 24
629#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
630#define OMAP4_GPMC_DR0_LB_SHIFT 23
631#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
632#define OMAP4_GPMC_DR1_LB_SHIFT 22
633#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
634#define OMAP4_GPMC_DR4_LB_SHIFT 21
635#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
636#define OMAP4_GPMC_DR5_LB_SHIFT 20
637#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
638#define OMAP4_GPMC_DR7_LB_SHIFT 19
639#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
640#define OMAP4_HSI2_DR0_LB_SHIFT 18
641#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
642#define OMAP4_HSI2_DR1_LB_SHIFT 17
643#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
644#define OMAP4_HSI2_DR2_LB_SHIFT 16
645#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
646#define OMAP4_KPD_DR0_LB_SHIFT 15
647#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
648#define OMAP4_KPD_DR1_LB_SHIFT 14
649#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
650#define OMAP4_PDM_DR0_LB_SHIFT 13
651#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
652#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
653#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
654#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
655#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
656#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
657#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
658#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
659#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
660#define OMAP4_SPI3_DR0_LB_SHIFT 8
661#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
662#define OMAP4_SPI3_DR1_LB_SHIFT 7
663#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
664#define OMAP4_UART3_DR2_LB_SHIFT 6
665#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
666#define OMAP4_UART3_DR3_LB_SHIFT 5
667#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
668#define OMAP4_UART3_DR4_LB_SHIFT 4
669#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
670#define OMAP4_UART3_DR5_LB_SHIFT 3
671#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
672#define OMAP4_USBA0_DR1_LB_SHIFT 2
673#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
674#define OMAP4_USBA_DR2_LB_SHIFT 1
675#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
676
677/* CONTROL_SMART2IO_PADCONF_1 */
678#define OMAP4_USBB1_DR0_LB_SHIFT 31
679#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
680#define OMAP4_USBB2_DR0_LB_SHIFT 30
681#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
682#define OMAP4_USBA0_DR0_LB_SHIFT 29
683#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
684
685/* CONTROL_SMART3IO_PADCONF_0 */
686#define OMAP4_DMIC_DR0_MB_SHIFT 30
687#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
688#define OMAP4_GPIO_DR3_MB_SHIFT 28
689#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
690#define OMAP4_GPIO_DR4_MB_SHIFT 26
691#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
692#define OMAP4_GPIO_DR5_MB_SHIFT 24
693#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
694#define OMAP4_GPIO_DR6_MB_SHIFT 22
695#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
696#define OMAP4_HSI_DR1_MB_SHIFT 20
697#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
698#define OMAP4_HSI_DR2_MB_SHIFT 18
699#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
700#define OMAP4_HSI_DR3_MB_SHIFT 16
701#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
702#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
703#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
704#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
705#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
706#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
707#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
708#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
709#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
710#define OMAP4_SPI2_DR0_MB_SHIFT 0
711#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
712
713/* CONTROL_SMART3IO_PADCONF_1 */
714#define OMAP4_SPI2_DR1_MB_SHIFT 30
715#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
716#define OMAP4_SPI2_DR2_MB_SHIFT 28
717#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
718#define OMAP4_UART2_DR0_MB_SHIFT 26
719#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
720#define OMAP4_UART2_DR1_MB_SHIFT 24
721#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
722#define OMAP4_UART4_DR0_MB_SHIFT 22
723#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
724#define OMAP4_HSI_DR0_MB_SHIFT 20
725#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
726
727/* CONTROL_SMART3IO_PADCONF_2 */
728#define OMAP4_DMIC_DR0_LB_SHIFT 31
729#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
730#define OMAP4_GPIO_DR3_LB_SHIFT 30
731#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
732#define OMAP4_GPIO_DR4_LB_SHIFT 29
733#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
734#define OMAP4_GPIO_DR5_LB_SHIFT 28
735#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
736#define OMAP4_GPIO_DR6_LB_SHIFT 27
737#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
738#define OMAP4_HSI_DR1_LB_SHIFT 26
739#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
740#define OMAP4_HSI_DR2_LB_SHIFT 25
741#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
742#define OMAP4_HSI_DR3_LB_SHIFT 24
743#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
744#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
745#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
746#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
747#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
748#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
749#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
750#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
751#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
752#define OMAP4_SPI2_DR0_LB_SHIFT 16
753#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
754#define OMAP4_SPI2_DR1_LB_SHIFT 15
755#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
756#define OMAP4_SPI2_DR2_LB_SHIFT 14
757#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
758#define OMAP4_UART2_DR0_LB_SHIFT 13
759#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
760#define OMAP4_UART2_DR1_LB_SHIFT 12
761#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
762#define OMAP4_UART4_DR0_LB_SHIFT 11
763#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
764#define OMAP4_HSI_DR0_LB_SHIFT 10
765#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
766
767/* CONTROL_USBB_HSIC */
768#define OMAP4_USBB2_DR1_SR_SHIFT 30
769#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
770#define OMAP4_USBB2_DR1_I_SHIFT 27
771#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
772#define OMAP4_USBB1_DR1_SR_SHIFT 25
773#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
774#define OMAP4_USBB1_DR1_I_SHIFT 22
775#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
776#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
777#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
778#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
779#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
780#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
781#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
782#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
783#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
784#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
785#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
786#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
787#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
788#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
789#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
790#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
791#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
792#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
793#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
794#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
795#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
796#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
797#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
798#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
799#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
800
801/* CONTROL_SLIMBUS */
802#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
803#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
804#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
805#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
806#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
807#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
808#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
809#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
810#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
811#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
812#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
813#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
814#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
815#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
816#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
817#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
818
819/* CONTROL_PBIASLITE */
820#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
821#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
822#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
823#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
824#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
825#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
826#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
827#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
828#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
829#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
830#define OMAP4_MMC1_PWRDNZ_SHIFT 26
831#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
832#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
833#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
834#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
835#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
836#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
837#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
838#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
839#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
840#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
841#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
842#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
843#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
844
845/* CONTROL_I2C_0 */
846#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
847#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
848#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
849#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
850#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
851#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
852#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
853#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
854#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
855#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
856#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
857#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
858#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
859#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
860#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
861#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
862#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
863#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
864#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
865#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
866#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
867#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
868#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
869#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
870#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
871#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
872#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
873#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
874#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
875#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
876#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
877#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
878#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
879#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
880#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
881#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
882#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
883#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
884#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
885#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
886#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
887#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
888#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
889#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
890#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
891#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
892#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
893#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
894
895/* CONTROL_CAMERA_RX */
896#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
897#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
898#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
899#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
900#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
901#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
902#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
903#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
904#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
905#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
906#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
907#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
908#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
909#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
910#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
911#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
912
913/* CONTROL_AVDAC */
914#define OMAP4_AVDAC_ACEN_SHIFT 31
915#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
916#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
917#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
918#define OMAP4_AVDAC_INPUTINV_SHIFT 29
919#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
920#define OMAP4_AVDAC_CTL_SHIFT 13
921#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
922#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
923#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
924
925/* CONTROL_HDMI_TX_PHY */
926#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
927#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
928#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
929#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
930#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
931#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
932#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
933#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
934
935/* CONTROL_MMC2 */
936#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
937#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
938
939/* CONTROL_DSIPHY */
940#define OMAP4_DSI2_LANEENABLE_SHIFT 29
941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
942#define OMAP4_DSI1_LANEENABLE_SHIFT 24
943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
944#define OMAP4_DSI1_PIPD_SHIFT 19
945#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
946#define OMAP4_DSI2_PIPD_SHIFT 14
947#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
948
949/* CONTROL_MCBSPLP */
950#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
951#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
952#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
953#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
954#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
955#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
956
957/* CONTROL_USB2PHYCORE */
958#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
959#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
960#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
961#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
962#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
963#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
964#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
965#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
966#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
967#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
968#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
969#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
970#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
971#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
972#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
973#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
974#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
975#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
976#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
977#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
978#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
979#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
980#define OMAP4_USB2PHY_DATADET_SHIFT 18
981#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
982#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
983#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
984#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
985#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
986#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
987#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
988#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
989#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
990#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
991#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
992#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
993#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
994#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
995#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
996#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
997#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
998#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
999#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
1000#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
1001#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
1002#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
1003#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
1004#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
1005#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
1006#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
1007#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
1008
1009/* CONTROL_I2C_1 */
1010#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
1011#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
1012#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
1013#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
1014#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
1015#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
1016#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
1017#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
1018#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
1019#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
1020#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
1021#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
1022#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
1023#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
1024#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
1025#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
1026#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
1027#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
1028#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
1029#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
1030
1031/* CONTROL_MMC1 */
1032#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
1033#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
1034#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
1035#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
1036#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
1037#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
1038#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
1039#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
1040#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
1041#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
1042#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
1043#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
1044#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
1045#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
1046#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
1047#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
1048#define OMAP4_USB_FD_CDEN_SHIFT 23
1049#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
1050#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
1051#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
1052#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
1053#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
1054
1055/* CONTROL_HSI */
1056#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
1057#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
1058#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
1059#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
1060#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
1061#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
1062#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
1063#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
1064
1065/* CONTROL_USB */
1066#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
1067#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
1068#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
1069#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
1070
1071/* CONTROL_HDQ */
1072#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
1073#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
1074
1075/* CONTROL_LPDDR2IO1_0 */
1076#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
1077#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
1078#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
1079#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
1080#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
1081#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
1082#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
1083#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
1084#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
1085#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
1086#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
1087#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
1088#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
1089#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
1090#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
1091#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
1092#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
1093#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
1094#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
1095#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
1096#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
1097#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
1098#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
1099#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
1100
1101/* CONTROL_LPDDR2IO1_1 */
1102#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
1103#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
1104#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
1105#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
1106#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
1107#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
1108#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
1109#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
1110#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
1111#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
1112#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
1113#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
1114#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
1115#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
1116#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
1117#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
1118#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
1119#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
1120#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
1121#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
1122#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
1123#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
1124#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
1125#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
1126
1127/* CONTROL_LPDDR2IO1_2 */
1128#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
1129#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
1130#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
1131#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
1132#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
1133#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
1134#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
1135#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
1136#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
1137#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
1138#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
1139#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
1140#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
1141#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
1142#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
1143#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
1144#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
1145#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
1146
1147/* CONTROL_LPDDR2IO1_3 */
1148#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
1149#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
1150#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
1151#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
1152#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
1153#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
1154#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
1155#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
1156#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
1157#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
1158#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
1159#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
1160#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
1161#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
1162#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
1163#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
1164#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
1165#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1166#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
1167#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1168#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
1169#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1170#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
1171#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1172#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
1173#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1174#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
1175#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1176#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
1177#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1178#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
1179#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1180#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
1181#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
1182#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
1183#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
1184#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
1185#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
1186#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
1187#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
1188
1189/* CONTROL_LPDDR2IO2_0 */
1190#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
1191#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
1192#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
1193#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
1194#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
1195#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
1196#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
1197#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
1198#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
1199#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
1200#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
1201#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
1202#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
1203#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
1204#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
1205#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
1206#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
1207#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
1208#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
1209#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
1210#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
1211#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
1212#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
1213#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
1214
1215/* CONTROL_LPDDR2IO2_1 */
1216#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
1217#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
1218#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
1219#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
1220#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
1221#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
1222#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
1223#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
1224#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
1225#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
1226#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
1227#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
1228#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
1229#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
1230#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
1231#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
1232#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
1233#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
1234#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
1235#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
1236#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
1237#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
1238#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
1239#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
1240
1241/* CONTROL_LPDDR2IO2_2 */
1242#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
1243#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
1244#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
1245#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
1246#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
1247#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
1248#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
1249#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
1250#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
1251#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
1252#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
1253#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
1254#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
1255#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
1256#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
1257#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
1258#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
1259#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
1260
1261/* CONTROL_LPDDR2IO2_3 */
1262#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
1263#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
1264#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
1265#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
1266#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
1267#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
1268#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
1269#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
1270#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
1271#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
1272#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
1273#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
1274#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
1275#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
1276#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
1277#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
1278#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
1279#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1280#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
1281#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1282#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
1283#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1284#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
1285#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1286#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
1287#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1288#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
1289#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1290#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
1291#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1292#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
1293#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1294#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
1295#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
1296#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
1297#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
1298#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
1299#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
1300#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
1301#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
1302
1303/* CONTROL_BUS_HOLD */
1304#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
1305#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
1306#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
1307#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
1308
1309/* CONTROL_C2C */
1310#define OMAP4_MIRROR_MODE_EN_SHIFT 31
1311#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
1312#define OMAP4_C2C_SPARE_SHIFT 24
1313#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
1314
1315/* CORE_CONTROL_SPARE_RW */
1316#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
1317#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
1318
1319/* CORE_CONTROL_SPARE_R */
1320#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
1321#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
1322
1323/* CORE_CONTROL_SPARE_R_C0 */
1324#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
1325#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
1326#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
1327#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
1328#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
1329#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
1330#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
1331#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
1332#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
1333#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
1334#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
1335#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
1336#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
1337#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
1338#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
1339#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
1340
1341/* CONTROL_EFUSE_1 */
1342#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
1343#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
1344#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
1345#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
1346#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
1347#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
1348#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
1349#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
1350
1351/* CONTROL_EFUSE_2 */
1352#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
1353#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
1354#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
1355#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
1356#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
1357#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
1358#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
1359#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
1360#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
1361#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
1362#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
1363#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
1364#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
1365#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
1366#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
1367#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
1368#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
1369#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
1370#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
1371#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
1372#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
1373#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
1374#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
1375#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
1376#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
1377#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
1378#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
1379#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
1380#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
1381#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
1382#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
1383#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
1384#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
1385#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
1386#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
1387#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
1388
1389/* CONTROL_EFUSE_3 */
1390#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
1391#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
1392#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
1393#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
1394#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
1395#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
1396#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
1397#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
1398
1399/* CONTROL_EFUSE_4 */
1400#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
1401#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
1402#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
1403#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
1404#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
1405#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
1406#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
1407#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
1408
1409#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 00000000000..17c9b37042c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
32#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
33#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
34#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
35#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
36#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
37#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
38#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
39#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
40#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
41#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
42#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
43
44/* Registers shifts and masks */
45
46/* IP_REVISION */
47#define OMAP4_IP_REV_SCHEME_SHIFT 30
48#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
49#define OMAP4_IP_REV_FUNC_SHIFT 16
50#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
51#define OMAP4_IP_REV_RTL_SHIFT 11
52#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
53#define OMAP4_IP_REV_MAJOR_SHIFT 8
54#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
55#define OMAP4_IP_REV_CUSTOM_SHIFT 6
56#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
57#define OMAP4_IP_REV_MINOR_SHIFT 0
58#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
59
60/* IP_HWINFO */
61#define OMAP4_IP_HWINFO_SHIFT 0
62#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
63
64/* IP_SYSCONFIG */
65#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
66#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
67
68/* PADCONF_WAKEUPEVENT_0 */
69#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
70#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
71#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
72#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
73#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
74#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
75#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
76#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
77#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
78#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
79#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
80#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
81#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
82#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
83#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
84#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
85#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
86#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
87#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
88#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
89#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
90#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
91#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
92#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
93#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
94#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
95#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
96#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
97#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
98#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
99#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
100#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
101#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
102#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
103#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
104#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
105#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
106#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
107#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
108#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
109#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
110#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
111#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
112#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
113#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
114#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
115#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
116#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
117#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
118#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
119
120/* CONTROL_SMART1NOPMIO_PADCONF_0 */
121#define OMAP4_FREF_DR0_SC_SHIFT 30
122#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
123#define OMAP4_FREF_DR1_SC_SHIFT 28
124#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
125#define OMAP4_FREF_DR4_SC_SHIFT 26
126#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
127#define OMAP4_FREF_DR5_SC_SHIFT 24
128#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
129#define OMAP4_FREF_DR6_SC_SHIFT 22
130#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
131#define OMAP4_FREF_DR7_SC_SHIFT 20
132#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
133#define OMAP4_GPIO_DR7_SC_SHIFT 18
134#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
135#define OMAP4_DPM_DR0_SC_SHIFT 14
136#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
137#define OMAP4_SIM_DR0_SC_SHIFT 12
138#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
139
140/* CONTROL_SMART1NOPMIO_PADCONF_1 */
141#define OMAP4_FREF_DR0_LB_SHIFT 30
142#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
143#define OMAP4_FREF_DR1_LB_SHIFT 28
144#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
145#define OMAP4_FREF_DR4_LB_SHIFT 26
146#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
147#define OMAP4_FREF_DR5_LB_SHIFT 24
148#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
149#define OMAP4_FREF_DR6_LB_SHIFT 22
150#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
151#define OMAP4_FREF_DR7_LB_SHIFT 20
152#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
153#define OMAP4_GPIO_DR7_LB_SHIFT 18
154#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
155#define OMAP4_DPM_DR0_LB_SHIFT 14
156#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
157#define OMAP4_SIM_DR0_LB_SHIFT 12
158#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
159
160/* CONTROL_PADCONF_MODE */
161#define OMAP4_VDDS_DV_FREF_SHIFT 31
162#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
163#define OMAP4_VDDS_DV_BANK2_SHIFT 30
164#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
165
166/* CONTROL_XTAL_OSCILLATOR */
167#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
168#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
169#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
170#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
171
172/* CONTROL_USIMIO */
173#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
174#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
175#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
176#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
177#define OMAP4_USIM_PWRDNZ_SHIFT 28
178#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
179
180/* CONTROL_I2C_2 */
181#define OMAP4_SR_SDA_GLFENB_SHIFT 31
182#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
183#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
184#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
185#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
186#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
187#define OMAP4_SR_SCL_GLFENB_SHIFT 27
188#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
189#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
190#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
191#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
192#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
193
194/* CONTROL_JTAG */
195#define OMAP4_JTAG_NTRST_EN_SHIFT 31
196#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
197#define OMAP4_JTAG_TCK_EN_SHIFT 30
198#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
199#define OMAP4_JTAG_RTCK_EN_SHIFT 29
200#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
201#define OMAP4_JTAG_TDI_EN_SHIFT 28
202#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
203#define OMAP4_JTAG_TDO_EN_SHIFT 27
204#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
205
206/* CONTROL_SYS */
207#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
208#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
209
210/* WKUP_CONTROL_SPARE_RW */
211#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
212#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
213
214/* WKUP_CONTROL_SPARE_R */
215#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
216#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
217
218/* WKUP_CONTROL_SPARE_R_C0 */
219#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
220#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
221#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
222#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
223#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
224#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
225#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
226#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
227#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
228#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
229#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
230#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
231#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
232#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
233#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
234#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
235
236#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 00000000000..a0af9baec3f
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
1/*
2 * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
32#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
33#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
34#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
35#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
36#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
37#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
38#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
39#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
40#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
41#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
42#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
43#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
44#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
45#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
46#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
47#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
48#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
49#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
50#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
51#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
52#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
53#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
54#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
55#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
56#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
57#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
58#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
59#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
60#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
61#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
62#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
63
64/* Registers shifts and masks */
65
66/* IP_REVISION */
67#define OMAP4_IP_REV_SCHEME_SHIFT 30
68#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
69#define OMAP4_IP_REV_FUNC_SHIFT 16
70#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
71#define OMAP4_IP_REV_RTL_SHIFT 11
72#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
73#define OMAP4_IP_REV_MAJOR_SHIFT 8
74#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
75#define OMAP4_IP_REV_CUSTOM_SHIFT 6
76#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
77#define OMAP4_IP_REV_MINOR_SHIFT 0
78#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
79
80/* IP_HWINFO */
81#define OMAP4_IP_HWINFO_SHIFT 0
82#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
83
84/* IP_SYSCONFIG */
85#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
86#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
87
88/* CONF_DEBUG_SEL_TST_0 */
89#define OMAP4_WKUP_MODE_SHIFT 0
90#define OMAP4_WKUP_MODE_MASK (1 << 0)
91
92#endif
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
new file mode 100644
index 00000000000..ceb8b7e593d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -0,0 +1,167 @@
1/*
2 * arch/arm/plat-omap/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <mach/io.h>
15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
17
18#include <plat/omap24xx.h>
19#include <plat/omap34xx.h>
20#include <plat/omap44xx.h>
21
22#include <plat/multi.h>
23
24#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
25#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
26#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
27#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
28#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
29
30 .macro disable_fiq
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
36/*
37 * Unoptimized irq functions for multi-omap2, 3 and 4
38 */
39
40#ifdef MULTI_OMAP2
41 /*
42 * Configure the interrupt base on the first interrupt.
43 * See also omap_irq_base_init for setting omap_irq_base.
44 */
45 .macro get_irqnr_preamble, base, tmp
46 ldr \base, =omap_irq_base @ irq base address
47 ldr \base, [\base, #0] @ irq base value
48 .endm
49
50 /* Check the pending interrupts. Note that base already set */
51 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
52 tst \base, #0x100 @ gic address?
53 bne 4401f @ found gic
54
55 /* Handle omap2 and omap3 */
56 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
57 cmp \irqnr, #0x0
58 bne 9998f
59 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
60 cmp \irqnr, #0x0
61 bne 9998f
62 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
63 cmp \irqnr, #0x0
64 bne 9998f
65
66 /*
67 * ti816x has additional IRQ pending register. Checking this
68 * register on omap2 & omap3 has no effect (read as 0).
69 */
70 ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
71 cmp \irqnr, #0x0
729998:
73 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
74 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
75 b 9999f
76
77 /* Handle omap4 */
784401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
79 ldr \tmp, =1021
80 bic \irqnr, \irqstat, #0x1c00
81 cmp \irqnr, #29
82 cmpcc \irqnr, \irqnr
83 cmpne \irqnr, \tmp
84 cmpcs \irqnr, \irqnr
859999:
86 .endm
87
88#ifdef CONFIG_SMP
89 /* We assume that irqstat (the raw value of the IRQ acknowledge
90 * register) is preserved from the macro above.
91 * If there is an IPI, we immediately signal end of interrupt
92 * on the controller, since this requires the original irqstat
93 * value which we won't easily be able to recreate later.
94 */
95
96 .macro test_for_ipi, irqnr, irqstat, base, tmp
97 bic \irqnr, \irqstat, #0x1c00
98 cmp \irqnr, #16
99 it cc
100 strcc \irqstat, [\base, #GIC_CPU_EOI]
101 it cs
102 cmpcs \irqnr, \irqnr
103 .endm
104
105 /* As above, this assumes that irqstat and base are preserved */
106
107 .macro test_for_ltirq, irqnr, irqstat, base, tmp
108 bic \irqnr, \irqstat, #0x1c00
109 mov \tmp, #0
110 cmp \irqnr, #29
111 itt eq
112 moveq \tmp, #1
113 streq \irqstat, [\base, #GIC_CPU_EOI]
114 cmp \tmp, #0
115 .endm
116#endif /* CONFIG_SMP */
117
118#else /* MULTI_OMAP2 */
119
120
121/*
122 * Optimized irq functions for omap2, 3 and 4
123 */
124
125#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
126 .macro get_irqnr_preamble, base, tmp
127#ifdef CONFIG_ARCH_OMAP2
128 ldr \base, =OMAP2_IRQ_BASE
129#else
130 ldr \base, =OMAP3_IRQ_BASE
131#endif
132 .endm
133
134 /* Check the pending interrupts. Note that base already set */
135 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
136 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
137 cmp \irqnr, #0x0
138 bne 9999f
139 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
140 cmp \irqnr, #0x0
141 bne 9999f
142 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
143 cmp \irqnr, #0x0
144#ifdef CONFIG_SOC_OMAPTI816X
145 bne 9999f
146 ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
147 cmp \irqnr, #0x0
148#endif
1499999:
150 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
151 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
152
153 .endm
154#endif
155
156
157#ifdef CONFIG_ARCH_OMAP4
158#define HAVE_GET_IRQNR_PREAMBLE
159#include <asm/hardware/entry-macro-gic.S>
160
161 .macro get_irqnr_preamble, base, tmp
162 ldr \base, =OMAP4_IRQ_BASE
163 .endm
164
165#endif
166
167#endif /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
new file mode 100644
index 00000000000..be4d290d57e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/gpio.h
3 */
4
5#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h
new file mode 100644
index 00000000000..02ed3aa56f1
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/id.h
@@ -0,0 +1,22 @@
1/*
2 * OMAP2 CPU identification code
3 *
4 * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef OMAP2_ARCH_ID_H
11#define OMAP2_ARCH_ID_H
12
13struct omap_die_id {
14 u32 id_0;
15 u32 id_1;
16 u32 id_2;
17 u32 id_3;
18};
19
20void omap_get_die_id(struct omap_die_id *odi);
21
22#endif
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
new file mode 100644
index 00000000000..fd78f31aa1a
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/io.h
3 */
4
5#include <plat/io.h>
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h
new file mode 100644
index 00000000000..ca6d32a917d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/memory.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/memory.h
3 */
4
5#include <plat/memory.h>
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
new file mode 100644
index 00000000000..e4bd8761973
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -0,0 +1,43 @@
1/*
2 * omap4-common.h: OMAP4 specific common header file
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef OMAP_ARCH_OMAP4_COMMON_H
14#define OMAP_ARCH_OMAP4_COMMON_H
15
16/*
17 * wfi used in low power code. Directly opcode is used instead
18 * of instruction to avoid mulit-omap build break
19 */
20#ifdef CONFIG_THUMB2_KERNEL
21#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
22#else
23#define do_wfi() \
24 __asm__ __volatile__ (".word 0xe320f003" : : : "memory")
25#endif
26
27#ifdef CONFIG_CACHE_L2X0
28extern void __iomem *l2cache_base;
29#endif
30
31extern void __iomem *gic_dist_base_addr;
32
33extern void __init gic_init_irq(void);
34extern void omap_smc1(u32 fn, u32 arg);
35
36#ifdef CONFIG_SMP
37/* Needed for secondary core boot */
38extern void omap_secondary_startup(void);
39extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
40extern void omap_auxcoreboot_addr(u32 cpu_addr);
41extern u32 omap_read_auxcoreboot0(void);
42#endif
43#endif
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
new file mode 100644
index 00000000000..323675f21b6
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/smp.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/smp.h
3 */
4
5#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
new file mode 100644
index 00000000000..d488721ab90
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/system.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/system.h
3 */
4
5#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
new file mode 100644
index 00000000000..86631994776
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END 0xf8000000UL
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
new file mode 100644
index 00000000000..fd230c6cded
--- /dev/null
+++ b/arch/arm/mach-omap2/io.h
@@ -0,0 +1,7 @@
1
2#ifndef __MACH_OMAP2_IO_H__
3#define __MACH_OMAP2_IO_H__
4
5extern int __init omap_sram_init(void);
6
7#endif /* __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
new file mode 100644
index 00000000000..eefc37912ef
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -0,0 +1,361 @@
1/*
2 * omap iommu: omap2/3 architecture specific functions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/device.h>
16#include <linux/jiffies.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/stringify.h>
20
21#include <plat/iommu.h>
22
23/*
24 * omap2 architecture specific register bit definitions
25 */
26#define IOMMU_ARCH_VERSION 0x00000011
27
28/* SYSCONF */
29#define MMU_SYS_IDLE_SHIFT 3
30#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
31#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
32#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
33#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
34
35#define MMU_SYS_SOFTRESET (1 << 1)
36#define MMU_SYS_AUTOIDLE 1
37
38/* SYSSTATUS */
39#define MMU_SYS_RESETDONE 1
40
41/* IRQSTATUS & IRQENABLE */
42#define MMU_IRQ_MULTIHITFAULT (1 << 4)
43#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
44#define MMU_IRQ_EMUMISS (1 << 2)
45#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
46#define MMU_IRQ_TLBMISS (1 << 0)
47
48#define __MMU_IRQ_FAULT \
49 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
50#define MMU_IRQ_MASK \
51 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
52#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
53#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
54
55/* MMU_CNTL */
56#define MMU_CNTL_SHIFT 1
57#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
58#define MMU_CNTL_EML_TLB (1 << 3)
59#define MMU_CNTL_TWL_EN (1 << 2)
60#define MMU_CNTL_MMU_EN (1 << 1)
61
62#define get_cam_va_mask(pgsz) \
63 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
64 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
65 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
66 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
67
68
69static void __iommu_set_twl(struct omap_iommu *obj, bool on)
70{
71 u32 l = iommu_read_reg(obj, MMU_CNTL);
72
73 if (on)
74 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
75 else
76 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
77
78 l &= ~MMU_CNTL_MASK;
79 if (on)
80 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
81 else
82 l |= (MMU_CNTL_MMU_EN);
83
84 iommu_write_reg(obj, l, MMU_CNTL);
85}
86
87
88static int omap2_iommu_enable(struct omap_iommu *obj)
89{
90 u32 l, pa;
91 unsigned long timeout;
92
93 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
94 return -EINVAL;
95
96 pa = virt_to_phys(obj->iopgd);
97 if (!IS_ALIGNED(pa, SZ_16K))
98 return -EINVAL;
99
100 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
101
102 timeout = jiffies + msecs_to_jiffies(20);
103 do {
104 l = iommu_read_reg(obj, MMU_SYSSTATUS);
105 if (l & MMU_SYS_RESETDONE)
106 break;
107 } while (!time_after(jiffies, timeout));
108
109 if (!(l & MMU_SYS_RESETDONE)) {
110 dev_err(obj->dev, "can't take mmu out of reset\n");
111 return -ENODEV;
112 }
113
114 l = iommu_read_reg(obj, MMU_REVISION);
115 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
116 (l >> 4) & 0xf, l & 0xf);
117
118 l = iommu_read_reg(obj, MMU_SYSCONFIG);
119 l &= ~MMU_SYS_IDLE_MASK;
120 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
121 iommu_write_reg(obj, l, MMU_SYSCONFIG);
122
123 iommu_write_reg(obj, pa, MMU_TTB);
124
125 __iommu_set_twl(obj, true);
126
127 return 0;
128}
129
130static void omap2_iommu_disable(struct omap_iommu *obj)
131{
132 u32 l = iommu_read_reg(obj, MMU_CNTL);
133
134 l &= ~MMU_CNTL_MASK;
135 iommu_write_reg(obj, l, MMU_CNTL);
136 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
137
138 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
139}
140
141static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
142{
143 __iommu_set_twl(obj, false);
144}
145
146static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
147{
148 u32 stat, da;
149 u32 errs = 0;
150
151 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
152 stat &= MMU_IRQ_MASK;
153 if (!stat) {
154 *ra = 0;
155 return 0;
156 }
157
158 da = iommu_read_reg(obj, MMU_FAULT_AD);
159 *ra = da;
160
161 if (stat & MMU_IRQ_TLBMISS)
162 errs |= OMAP_IOMMU_ERR_TLB_MISS;
163 if (stat & MMU_IRQ_TRANSLATIONFAULT)
164 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
165 if (stat & MMU_IRQ_EMUMISS)
166 errs |= OMAP_IOMMU_ERR_EMU_MISS;
167 if (stat & MMU_IRQ_TABLEWALKFAULT)
168 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
169 if (stat & MMU_IRQ_MULTIHITFAULT)
170 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
171 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
172
173 return errs;
174}
175
176static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
177{
178 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
179 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
180}
181
182static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
183{
184 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
185 iommu_write_reg(obj, cr->ram, MMU_RAM);
186}
187
188static u32 omap2_cr_to_virt(struct cr_regs *cr)
189{
190 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
191 u32 mask = get_cam_va_mask(cr->cam & page_size);
192
193 return cr->cam & mask;
194}
195
196static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
197 struct iotlb_entry *e)
198{
199 struct cr_regs *cr;
200
201 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
202 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
203 e->da);
204 return ERR_PTR(-EINVAL);
205 }
206
207 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
208 if (!cr)
209 return ERR_PTR(-ENOMEM);
210
211 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
212 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
213
214 return cr;
215}
216
217static inline int omap2_cr_valid(struct cr_regs *cr)
218{
219 return cr->cam & MMU_CAM_V;
220}
221
222static u32 omap2_get_pte_attr(struct iotlb_entry *e)
223{
224 u32 attr;
225
226 attr = e->mixed << 5;
227 attr |= e->endian;
228 attr |= e->elsz >> 3;
229 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
230 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
231 return attr;
232}
233
234static ssize_t
235omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
236{
237 char *p = buf;
238
239 /* FIXME: Need more detail analysis of cam/ram */
240 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
241 (cr->cam & MMU_CAM_P) ? 1 : 0);
242
243 return p - buf;
244}
245
246#define pr_reg(name) \
247 do { \
248 ssize_t bytes; \
249 const char *str = "%20s: %08x\n"; \
250 const int maxcol = 32; \
251 bytes = snprintf(p, maxcol, str, __stringify(name), \
252 iommu_read_reg(obj, MMU_##name)); \
253 p += bytes; \
254 len -= bytes; \
255 if (len < maxcol) \
256 goto out; \
257 } while (0)
258
259static ssize_t
260omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
261{
262 char *p = buf;
263
264 pr_reg(REVISION);
265 pr_reg(SYSCONFIG);
266 pr_reg(SYSSTATUS);
267 pr_reg(IRQSTATUS);
268 pr_reg(IRQENABLE);
269 pr_reg(WALKING_ST);
270 pr_reg(CNTL);
271 pr_reg(FAULT_AD);
272 pr_reg(TTB);
273 pr_reg(LOCK);
274 pr_reg(LD_TLB);
275 pr_reg(CAM);
276 pr_reg(RAM);
277 pr_reg(GFLUSH);
278 pr_reg(FLUSH_ENTRY);
279 pr_reg(READ_CAM);
280 pr_reg(READ_RAM);
281 pr_reg(EMU_FAULT_AD);
282out:
283 return p - buf;
284}
285
286static void omap2_iommu_save_ctx(struct omap_iommu *obj)
287{
288 int i;
289 u32 *p = obj->ctx;
290
291 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
292 p[i] = iommu_read_reg(obj, i * sizeof(u32));
293 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
294 }
295
296 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
297}
298
299static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
300{
301 int i;
302 u32 *p = obj->ctx;
303
304 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
305 iommu_write_reg(obj, p[i], i * sizeof(u32));
306 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
307 }
308
309 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
310}
311
312static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
313{
314 e->da = cr->cam & MMU_CAM_VATAG_MASK;
315 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
316 e->valid = cr->cam & MMU_CAM_V;
317 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
318 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
319 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
320 e->mixed = cr->ram & MMU_RAM_MIXED;
321}
322
323static const struct iommu_functions omap2_iommu_ops = {
324 .version = IOMMU_ARCH_VERSION,
325
326 .enable = omap2_iommu_enable,
327 .disable = omap2_iommu_disable,
328 .set_twl = omap2_iommu_set_twl,
329 .fault_isr = omap2_iommu_fault_isr,
330
331 .tlb_read_cr = omap2_tlb_read_cr,
332 .tlb_load_cr = omap2_tlb_load_cr,
333
334 .cr_to_e = omap2_cr_to_e,
335 .cr_to_virt = omap2_cr_to_virt,
336 .alloc_cr = omap2_alloc_cr,
337 .cr_valid = omap2_cr_valid,
338 .dump_cr = omap2_dump_cr,
339
340 .get_pte_attr = omap2_get_pte_attr,
341
342 .save_ctx = omap2_iommu_save_ctx,
343 .restore_ctx = omap2_iommu_restore_ctx,
344 .dump_ctx = omap2_iommu_dump_ctx,
345};
346
347static int __init omap2_iommu_init(void)
348{
349 return omap_install_iommu_arch(&omap2_iommu_ops);
350}
351module_init(omap2_iommu_init);
352
353static void __exit omap2_iommu_exit(void)
354{
355 omap_uninstall_iommu_arch(&omap2_iommu_ops);
356}
357module_exit(omap2_iommu_exit);
358
359MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
360MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
361MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
new file mode 100644
index 00000000000..e69d37d9520
--- /dev/null
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -0,0 +1,57 @@
1/*
2 * OMAP44xx secure APIs file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 *
8 * This program is free software,you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14
15/*
16 * This is common routine to manage secure monitor API
17 * used to modify the PL310 secure registers.
18 * 'r0' contains the value to be modified and 'r12' contains
19 * the monitor API number. It uses few CPU registers
20 * internally and hence they need be backed up including
21 * link register "lr".
22 * Function signature : void omap_smc1(u32 fn, u32 arg)
23 */
24
25ENTRY(omap_smc1)
26 stmfd sp!, {r2-r12, lr}
27 mov r12, r0
28 mov r0, r1
29 dsb
30 smc #0
31 ldmfd sp!, {r2-r12, pc}
32ENDPROC(omap_smc1)
33
34ENTRY(omap_modify_auxcoreboot0)
35 stmfd sp!, {r1-r12, lr}
36 ldr r12, =0x104
37 dsb
38 smc #0
39 ldmfd sp!, {r1-r12, pc}
40ENDPROC(omap_modify_auxcoreboot0)
41
42ENTRY(omap_auxcoreboot_addr)
43 stmfd sp!, {r2-r12, lr}
44 ldr r12, =0x105
45 dsb
46 smc #0
47 ldmfd sp!, {r2-r12, pc}
48ENDPROC(omap_auxcoreboot_addr)
49
50ENTRY(omap_read_auxcoreboot0)
51 stmfd sp!, {r2-r12, lr}
52 ldr r12, =0x103
53 dsb
54 smc #0
55 mov r0, r0, lsr #9
56 ldmfd sp!, {r2-r12, pc}
57ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 00000000000..7b9f1909ddb
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,248 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29
30#include "omap_l3_noc.h"
31
32/*
33 * Interrupt Handler for L3 error detection.
34 * 1) Identify the L3 clockdomain partition to which the error belongs to.
35 * 2) Identify the slave where the error information is logged
36 * 3) Print the logged information.
37 * 4) Add dump stack to provide kernel trace.
38 *
39 * Two Types of errors :
40 * 1) Custom errors in L3 :
41 * Target like DMM/FW/EMIF generates SRESP=ERR error
42 * 2) Standard L3 error:
43 * - Unsupported CMD.
44 * L3 tries to access target while it is idle
45 * - OCP disconnect.
46 * - Address hole error:
47 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
48 * do not have connectivity, the error is logged in
49 * their default target which is DMM2.
50 *
51 * On High Secure devices, firewall errors are possible and those
52 * can be trapped as well. But the trapping is implemented as part
53 * secure software and hence need not be implemented here.
54 */
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{
57
58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j;
60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg;
62 u32 base, slave_addr, clear;
63 char *source_name;
64
65 /* Get the Type of interrupt */
66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
67
68 for (i = 0; i < L3_MODULES; i++) {
69 /*
70 * Read the regerr register of the clock domain
71 * to determine the source
72 */
73 base = (u32)l3->l3_base[i];
74 err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
75
76 /* Get the corresponding error and analyse */
77 if (err_reg) {
78 /* Identify the source from control status register */
79 for (j = 0; !(err_reg & (1 << j)); j++)
80 ;
81
82 err_src = j;
83 /* Read the stderrlog_main_source from clk domain */
84 std_err_main_addr = base + *(l3_targ[i] + err_src);
85 std_err_main = readl(std_err_main_addr);
86
87 switch (std_err_main & CUSTOM_ERROR) {
88 case STANDARD_ERROR:
89 source_name =
90 l3_targ_stderrlog_main_name[i][err_src];
91
92 slave_addr = std_err_main_addr +
93 L3_SLAVE_ADDRESS_OFFSET;
94 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
95 source_name, readl(slave_addr));
96 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG;
98 writel(clear, std_err_main_addr);
99 break;
100
101 case CUSTOM_ERROR:
102 source_name =
103 l3_targ_stderrlog_main_name[i][err_src];
104
105 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
106 source_name);
107 /* clear the std error log*/
108 clear = std_err_main | CLEAR_STDERR_LOG;
109 writel(clear, std_err_main_addr);
110 break;
111
112 default:
113 /* Nothing to be handled here as of now */
114 break;
115 }
116 /* Error found so break the for loop */
117 break;
118 }
119 }
120 return IRQ_HANDLED;
121}
122
123static int __init omap4_l3_probe(struct platform_device *pdev)
124{
125 static struct omap4_l3 *l3;
126 struct resource *res;
127 int ret;
128 int irq;
129
130 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
131 if (!l3)
132 return -ENOMEM;
133
134 platform_set_drvdata(pdev, l3);
135 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
136 if (!res) {
137 dev_err(&pdev->dev, "couldn't find resource 0\n");
138 ret = -ENODEV;
139 goto err0;
140 }
141
142 l3->l3_base[0] = ioremap(res->start, resource_size(res));
143 if (!l3->l3_base[0]) {
144 dev_err(&pdev->dev, "ioremap failed\n");
145 ret = -ENOMEM;
146 goto err0;
147 }
148
149 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
150 if (!res) {
151 dev_err(&pdev->dev, "couldn't find resource 1\n");
152 ret = -ENODEV;
153 goto err1;
154 }
155
156 l3->l3_base[1] = ioremap(res->start, resource_size(res));
157 if (!l3->l3_base[1]) {
158 dev_err(&pdev->dev, "ioremap failed\n");
159 ret = -ENOMEM;
160 goto err1;
161 }
162
163 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
164 if (!res) {
165 dev_err(&pdev->dev, "couldn't find resource 2\n");
166 ret = -ENODEV;
167 goto err2;
168 }
169
170 l3->l3_base[2] = ioremap(res->start, resource_size(res));
171 if (!l3->l3_base[2]) {
172 dev_err(&pdev->dev, "ioremap failed\n");
173 ret = -ENOMEM;
174 goto err2;
175 }
176
177 /*
178 * Setup interrupt Handlers
179 */
180 irq = platform_get_irq(pdev, 0);
181 ret = request_irq(irq,
182 l3_interrupt_handler,
183 IRQF_DISABLED, "l3-dbg-irq", l3);
184 if (ret) {
185 pr_crit("L3: request_irq failed to register for 0x%x\n",
186 OMAP44XX_IRQ_L3_DBG);
187 goto err3;
188 }
189 l3->debug_irq = irq;
190
191 irq = platform_get_irq(pdev, 1);
192 ret = request_irq(irq,
193 l3_interrupt_handler,
194 IRQF_DISABLED, "l3-app-irq", l3);
195 if (ret) {
196 pr_crit("L3: request_irq failed to register for 0x%x\n",
197 OMAP44XX_IRQ_L3_APP);
198 goto err4;
199 }
200 l3->app_irq = irq;
201
202 return 0;
203
204err4:
205 free_irq(l3->debug_irq, l3);
206err3:
207 iounmap(l3->l3_base[2]);
208err2:
209 iounmap(l3->l3_base[1]);
210err1:
211 iounmap(l3->l3_base[0]);
212err0:
213 kfree(l3);
214 return ret;
215}
216
217static int __exit omap4_l3_remove(struct platform_device *pdev)
218{
219 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
220
221 free_irq(l3->app_irq, l3);
222 free_irq(l3->debug_irq, l3);
223 iounmap(l3->l3_base[0]);
224 iounmap(l3->l3_base[1]);
225 iounmap(l3->l3_base[2]);
226 kfree(l3);
227
228 return 0;
229}
230
231static struct platform_driver omap4_l3_driver = {
232 .remove = __exit_p(omap4_l3_remove),
233 .driver = {
234 .name = "omap_l3_noc",
235 },
236};
237
238static int __init omap4_l3_init(void)
239{
240 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
241}
242postcore_initcall_sync(omap4_l3_init);
243
244static void __exit omap4_l3_exit(void)
245{
246 platform_driver_unregister(&omap4_l3_driver);
247}
248module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 00000000000..359b83348ae
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
1 /*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1
39
40u32 l3_flagmux[L3_MODULES] = {
41 0x50C,
42 0x100C,
43 0X020C
44};
45
46/*
47 * L3 Target standard Error register offsets
48 */
49u32 l3_targ_stderrlog_main_clk1[] = {
50 0x148, /* DMM1 */
51 0x248, /* DMM2 */
52 0x348, /* ABE */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55};
56
57u32 l3_targ_stderrlog_main_clk2[] = {
58 0x548, /* CORTEX M3 */
59 0x348, /* DSS */
60 0x148, /* GPMC */
61 0x448, /* ISS */
62 0x748, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/
65 0x248, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */
68 0x848, /* SL2 */
69 0x1648, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */
74 0xA48, /* L4 PER1*/
75 0xB48 /* L4 PER2*/
76};
77
78u32 l3_targ_stderrlog_main_clk3[] = {
79 0x0148 /* EMUSS */
80};
81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 {
84 "DMM1",
85 "DMM2",
86 "ABE",
87 "L4CFG",
88 "CLK2 PWR DISC",
89 },
90 {
91 "CORTEX M3" ,
92 "DSS ",
93 "GPMC ",
94 "ISS ",
95 "IVAHD ",
96 "AES1",
97 "L4 PER0",
98 "OCMRAM ",
99 "GPMC sERROR",
100 "SGX ",
101 "SL2 ",
102 "C2C ",
103 "PWR DISC CLK1",
104 "SHA1",
105 "AES2",
106 "L4 PER3",
107 "L4 PER1",
108 "L4 PER2",
109 },
110 {
111 "EMUSS",
112 },
113};
114
115u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1,
117 l3_targ_stderrlog_main_clk2,
118 l3_targ_stderrlog_main_clk3,
119};
120
121struct omap4_l3 {
122 struct device *dev;
123 struct clk *ick;
124
125 /* memory base */
126 void __iomem *l3_base[4];
127
128 int debug_irq;
129 int app_irq;
130};
131
132#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 00000000000..873c0e33b51
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,299 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include "omap_l3_smx.h"
31
32static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
33{
34 return __raw_readll(base + reg);
35}
36
37static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
38{
39 __raw_writell(value, base + reg);
40}
41
42static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
43{
44 return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
45}
46
47static inline u32 omap3_l3_decode_addr(u64 error_addr)
48{
49 return error_addr & 0xffffffff;
50}
51
52static inline unsigned omap3_l3_decode_cmd(u64 error)
53{
54 return (error & 0x07) >> L3_ERROR_LOG_CMD;
55}
56
57static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
58{
59 return (error & 0xff00) >> L3_ERROR_LOG_INITID;
60}
61
62static inline unsigned omap3_l3_decode_req_info(u64 error)
63{
64 return (error >> 32) & 0xffff;
65}
66
67static char *omap3_l3_code_string(u8 code)
68{
69 switch (code) {
70 case OMAP_L3_CODE_NOERROR:
71 return "No Error";
72 case OMAP_L3_CODE_UNSUP_CMD:
73 return "Unsupported Command";
74 case OMAP_L3_CODE_ADDR_HOLE:
75 return "Address Hole";
76 case OMAP_L3_CODE_PROTECT_VIOLATION:
77 return "Protection Violation";
78 case OMAP_L3_CODE_IN_BAND_ERR:
79 return "In-band Error";
80 case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
81 return "Request Timeout Not Accepted";
82 case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
83 return "Request Timeout, no response";
84 default:
85 return "UNKNOWN error";
86 }
87}
88
89static char *omap3_l3_initiator_string(u8 initid)
90{
91 switch (initid) {
92 case OMAP_L3_LCD:
93 return "LCD";
94 case OMAP_L3_SAD2D:
95 return "SAD2D";
96 case OMAP_L3_IA_MPU_SS_1:
97 case OMAP_L3_IA_MPU_SS_2:
98 case OMAP_L3_IA_MPU_SS_3:
99 case OMAP_L3_IA_MPU_SS_4:
100 case OMAP_L3_IA_MPU_SS_5:
101 return "MPU";
102 case OMAP_L3_IA_IVA_SS_1:
103 case OMAP_L3_IA_IVA_SS_2:
104 case OMAP_L3_IA_IVA_SS_3:
105 return "IVA_SS";
106 case OMAP_L3_IA_IVA_SS_DMA_1:
107 case OMAP_L3_IA_IVA_SS_DMA_2:
108 case OMAP_L3_IA_IVA_SS_DMA_3:
109 case OMAP_L3_IA_IVA_SS_DMA_4:
110 case OMAP_L3_IA_IVA_SS_DMA_5:
111 case OMAP_L3_IA_IVA_SS_DMA_6:
112 return "IVA_SS_DMA";
113 case OMAP_L3_IA_SGX:
114 return "SGX";
115 case OMAP_L3_IA_CAM_1:
116 case OMAP_L3_IA_CAM_2:
117 case OMAP_L3_IA_CAM_3:
118 return "CAM";
119 case OMAP_L3_IA_DAP:
120 return "DAP";
121 case OMAP_L3_SDMA_WR_1:
122 case OMAP_L3_SDMA_WR_2:
123 return "SDMA_WR";
124 case OMAP_L3_SDMA_RD_1:
125 case OMAP_L3_SDMA_RD_2:
126 case OMAP_L3_SDMA_RD_3:
127 case OMAP_L3_SDMA_RD_4:
128 return "SDMA_RD";
129 case OMAP_L3_USBOTG:
130 return "USB_OTG";
131 case OMAP_L3_USBHOST:
132 return "USB_HOST";
133 default:
134 return "UNKNOWN Initiator";
135 }
136}
137
138/**
139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 *
141 * @base: register block base address
142 * @error: L3_ERROR_LOG register of our block
143 *
144 * Called in hard-irq context. Caller should take care of locking
145 *
146 * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
147 * Analysis Sequence, we are following that sequence here, please
148 * refer to that Figure for more information on the subject.
149 */
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr)
152{
153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr);
157
158 WARN(true, "%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "",
162 address);
163
164 return IRQ_HANDLED;
165}
166
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{
169 struct omap3_l3 *l3 = _l3;
170 u64 status, clear;
171 u64 error;
172 u64 error_addr;
173 u64 err_source = 0;
174 void __iomem *base;
175 int int_type;
176 irqreturn_t ret = IRQ_NONE;
177
178 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
179 if (!int_type) {
180 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
181 /*
182 * if we have a timeout error, there's nothing we can
183 * do besides rebooting the board. So let's BUG on any
184 * of such errors and handle the others. timeout error
185 * is severe and not expected to occur.
186 */
187 BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
188 } else {
189 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
190 /* No timeout error for debug sources */
191 }
192
193 /* identify the error source */
194 for (err_source = 0; !(status & (1 << err_source)); err_source++)
195 ;
196
197 base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
198 error = omap3_l3_readll(base, L3_ERROR_LOG);
199 if (error) {
200 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
201
202 ret |= omap3_l3_block_irq(l3, error, error_addr);
203 }
204
205 /* Clear the status register */
206 clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
207 L3_AGENT_STATUS_CLEAR_TA;
208 omap3_l3_writell(base, L3_AGENT_STATUS, clear);
209
210 /* clear the error log register */
211 omap3_l3_writell(base, L3_ERROR_LOG, error);
212
213 return ret;
214}
215
216static int __init omap3_l3_probe(struct platform_device *pdev)
217{
218 struct omap3_l3 *l3;
219 struct resource *res;
220 int ret;
221
222 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
223 if (!l3)
224 return -ENOMEM;
225
226 platform_set_drvdata(pdev, l3);
227
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 if (!res) {
230 dev_err(&pdev->dev, "couldn't find resource\n");
231 ret = -ENODEV;
232 goto err0;
233 }
234 l3->rt = ioremap(res->start, resource_size(res));
235 if (!l3->rt) {
236 dev_err(&pdev->dev, "ioremap failed\n");
237 ret = -ENOMEM;
238 goto err0;
239 }
240
241 l3->debug_irq = platform_get_irq(pdev, 0);
242 ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
243 IRQF_DISABLED | IRQF_TRIGGER_RISING,
244 "l3-debug-irq", l3);
245 if (ret) {
246 dev_err(&pdev->dev, "couldn't request debug irq\n");
247 goto err1;
248 }
249
250 l3->app_irq = platform_get_irq(pdev, 1);
251 ret = request_irq(l3->app_irq, omap3_l3_app_irq,
252 IRQF_DISABLED | IRQF_TRIGGER_RISING,
253 "l3-app-irq", l3);
254 if (ret) {
255 dev_err(&pdev->dev, "couldn't request app irq\n");
256 goto err2;
257 }
258
259 return 0;
260
261err2:
262 free_irq(l3->debug_irq, l3);
263err1:
264 iounmap(l3->rt);
265err0:
266 kfree(l3);
267 return ret;
268}
269
270static int __exit omap3_l3_remove(struct platform_device *pdev)
271{
272 struct omap3_l3 *l3 = platform_get_drvdata(pdev);
273
274 free_irq(l3->app_irq, l3);
275 free_irq(l3->debug_irq, l3);
276 iounmap(l3->rt);
277 kfree(l3);
278
279 return 0;
280}
281
282static struct platform_driver omap3_l3_driver = {
283 .remove = __exit_p(omap3_l3_remove),
284 .driver = {
285 .name = "omap_l3_smx",
286 },
287};
288
289static int __init omap3_l3_init(void)
290{
291 return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
292}
293postcore_initcall_sync(omap3_l3_init);
294
295static void __exit omap3_l3_exit(void)
296{
297 platform_driver_unregister(&omap3_l3_driver);
298}
299module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 00000000000..ba2ed9a850c
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26
27/* Register definitions. All 64-bit wide */
28#define L3_COMPONENT 0x000
29#define L3_CORE 0x018
30#define L3_AGENT_CONTROL 0x020
31#define L3_AGENT_STATUS 0x028
32#define L3_ERROR_LOG 0x058
33
34#define L3_ERROR_LOG_MULTI (1 << 31)
35#define L3_ERROR_LOG_SECONDARY (1 << 30)
36
37#define L3_ERROR_LOG_ADDR 0x060
38
39/* Register definitions for Sideband Interconnect */
40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510
42
43const u64 shift = 1;
44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
47#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48#define L3_STATUS_0_IVAIA_BRST (shift << 6)
49#define L3_STATUS_0_IVAIA_RSP (shift << 7)
50#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51#define L3_STATUS_0_SGXIA_BRST (shift << 9)
52#define L3_STATUS_0_SGXIA_RSP (shift << 10)
53#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
54#define L3_STATUS_0_CAMIA_BRST (shift << 12)
55#define L3_STATUS_0_CAMIA_RSP (shift << 13)
56#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
57#define L3_STATUS_0_DISPIA_BRST (shift << 15)
58#define L3_STATUS_0_DISPIA_RSP (shift << 16)
59#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
60#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
61#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
62#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
63#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
64#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
65#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
66#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
67#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
68#define L3_STATUS_0_SMSTA_REQ (shift << 48)
69#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
70#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
71#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
72#define L3_STATUS_0_IVATA_REQ (shift << 54)
73#define L3_STATUS_0_SGXTA_REQ (shift << 55)
74#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
75#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
76#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
77#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ)
108
109#define L3_SI_FLAG_STATUS_1 0x530
110
111#define L3_STATUS_1_MPU_DATAIA (1 << 0)
112#define L3_STATUS_1_DAPIA0 (1 << 3)
113#define L3_STATUS_1_DAPIA1 (1 << 4)
114#define L3_STATUS_1_IVAIA (1 << 6)
115
116#define L3_PM_ERROR_LOG 0x020
117#define L3_PM_CONTROL 0x028
118#define L3_PM_ERROR_CLEAR_SINGLE 0x030
119#define L3_PM_ERROR_CLEAR_MULTI 0x038
120#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
121#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
122#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
123#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
124
125/* L3 error log bit fields. Common for IA and TA */
126#define L3_ERROR_LOG_CODE 24
127#define L3_ERROR_LOG_INITID 8
128#define L3_ERROR_LOG_CMD 0
129
130/* L3 agent status bit fields. */
131#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
132#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
133
134#define OMAP34xx_IRQ_L3_APP 10
135#define L3_APPLICATION_ERROR 0x0
136#define L3_DEBUG_ERROR 0x1
137
138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
156 OMAP_L3_IA_IVA_SS_DMA_3 = 17,
157 OMAP_L3_IA_IVA_SS_DMA_4 = 16,
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1,
180};
181
182enum omap3_l3_code {
183 OMAP_L3_CODE_NOERROR = 0,
184 OMAP_L3_CODE_UNSUP_CMD = 1,
185 OMAP_L3_CODE_ADDR_HOLE = 2,
186 OMAP_L3_CODE_PROTECT_VIOLATION = 3,
187 OMAP_L3_CODE_IN_BAND_ERR = 4,
188 /* codes 5 and 6 are reserved */
189 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
190 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
191 /* codes 9 - 15 are also reserved */
192};
193
194struct omap3_l3 {
195 struct device *dev;
196 struct clk *ick;
197
198 /* memory base*/
199 void __iomem *rt;
200
201 int debug_irq;
202 int app_irq;
203
204 /* true when and inband functional error occurs */
205 unsigned inband:1;
206};
207
208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = {
210 /* MPU IA */
211 0x1400,
212 0x1400,
213 0x1400,
214 /* RESERVED */
215 0,
216 0,
217 0,
218 /* IVA 2.2 IA */
219 0x1800,
220 0x1800,
221 0x1800,
222 /* SGX IA */
223 0x1c00,
224 0x1c00,
225 /* RESERVED */
226 0,
227 /* CAMERA IA */
228 0x5800,
229 0x5800,
230 0x5800,
231 /* DISPLAY IA */
232 0x5400,
233 0x5400,
234 /* RESERVED */
235 0,
236 /*SDMA RD IA */
237 0x4c00,
238 0x4c00,
239 /* RESERVED */
240 0,
241 /* SDMA WR IA */
242 0x5000,
243 0x5000,
244 /* RESERVED */
245 0,
246 /* USB OTG IA */
247 0x4400,
248 0x4400,
249 0x4400,
250 /* USB HOST IA */
251 0x4000,
252 0x4000,
253 /* RESERVED */
254 0,
255 0,
256 0,
257 0,
258 /* SAD2D IA */
259 0x3000,
260 0x3000,
261 0x3000,
262 /* RESERVED */
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 /* SMA TA */
276 0x2000,
277 /* GPMC TA */
278 0x2400,
279 /* OCM RAM TA */
280 0x2800,
281 /* OCM ROM TA */
282 0x2C00,
283 /* L4 CORE TA */
284 0x6800,
285 /* L4 PER TA */
286 0x6c00,
287 /* IVA 2.2 TA */
288 0x6000,
289 /* SGX TA */
290 0x6400,
291 /* L4 EMU TA */
292 0x7000,
293 /* GPMC TA */
294 0x2400,
295 /* L4 CORE TA */
296 0x6800,
297 /* L4 PER TA */
298 0x6c00,
299 /* L4 EMU TA */
300 0x7000,
301 /* MAD2D TA */
302 0x3400,
303 /* RESERVED */
304 0,
305 0,
306};
307
308unsigned int __iomem omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */
310 0x1400,
311 /* RESERVED */
312 0,
313 0,
314 /* DAP IA */
315 0x5c00,
316 0x5c00,
317 /* RESERVED */
318 0,
319 /* IVA 2.2 IA */
320 0x1800,
321 /* REST RESERVED */
322};
323
324u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases,
326 omap3_l3_debug_bases,
327};
328
329/*
330 * REVISIT define __raw_readll/__raw_writell here, but move them to
331 * <asm/io.h> at some point
332 */
333#define __raw_writell(v, a) (__chk_io_ptr(a), \
334 *(volatile u64 __force *)(a) = (v))
335#define __raw_readll(a) (__chk_io_ptr(a), \
336 *(volatile u64 __force *)(a))
337
338#endif
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
new file mode 100644
index 00000000000..cf600e22bf8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -0,0 +1,241 @@
1/*
2 * OMAP2 and OMAP3 powerdomain control
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/io.h>
16#include <linux/errno.h>
17#include <linux/delay.h>
18
19#include <plat/prcm.h>
20
21#include "powerdomain.h"
22#include "prm.h"
23#include "prm-regbits-24xx.h"
24#include "prm-regbits-34xx.h"
25
26
27/* Common functions across OMAP2 and OMAP3 */
28static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
29{
30 omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
31 (pwrst << OMAP_POWERSTATE_SHIFT),
32 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
33 return 0;
34}
35
36static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
37{
38 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
39 OMAP2_PM_PWSTCTRL,
40 OMAP_POWERSTATE_MASK);
41}
42
43static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
44{
45 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
46 OMAP2_PM_PWSTST,
47 OMAP_POWERSTATEST_MASK);
48}
49
50static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
51 u8 pwrst)
52{
53 u32 m;
54
55 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
56
57 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
58 OMAP2_PM_PWSTCTRL);
59
60 return 0;
61}
62
63static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
64 u8 pwrst)
65{
66 u32 m;
67
68 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
69
70 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
71 OMAP2_PM_PWSTCTRL);
72
73 return 0;
74}
75
76static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
77{
78 u32 m;
79
80 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
81
82 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
83 m);
84}
85
86static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
87{
88 u32 m;
89
90 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
91
92 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
93 OMAP2_PM_PWSTCTRL, m);
94}
95
96static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
97{
98 u32 v;
99
100 v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
101 omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
102 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
103
104 return 0;
105}
106
107static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
108{
109 u32 c = 0;
110
111 /*
112 * REVISIT: pwrdm_wait_transition() may be better implemented
113 * via a callback and a periodic timer check -- how long do we expect
114 * powerdomain transitions to take?
115 */
116
117 /* XXX Is this udelay() value meaningful? */
118 while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
119 OMAP_INTRANSITION_MASK) &&
120 (c++ < PWRDM_TRANSITION_BAILOUT))
121 udelay(1);
122
123 if (c > PWRDM_TRANSITION_BAILOUT) {
124 printk(KERN_ERR "powerdomain: waited too long for "
125 "powerdomain %s to complete transition\n", pwrdm->name);
126 return -EAGAIN;
127 }
128
129 pr_debug("powerdomain: completed transition in %d loops\n", c);
130
131 return 0;
132}
133
134/* Applicable only for OMAP3. Not supported on OMAP2 */
135static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
136{
137 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
138 OMAP3430_PM_PREPWSTST,
139 OMAP3430_LASTPOWERSTATEENTERED_MASK);
140}
141
142static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
143{
144 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
145 OMAP2_PM_PWSTST,
146 OMAP3430_LOGICSTATEST_MASK);
147}
148
149static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
150{
151 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
152 OMAP2_PM_PWSTCTRL,
153 OMAP3430_LOGICSTATEST_MASK);
154}
155
156static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
157{
158 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
159 OMAP3430_PM_PREPWSTST,
160 OMAP3430_LASTLOGICSTATEENTERED_MASK);
161}
162
163static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
164{
165 switch (bank) {
166 case 0:
167 return OMAP3430_LASTMEM1STATEENTERED_MASK;
168 case 1:
169 return OMAP3430_LASTMEM2STATEENTERED_MASK;
170 case 2:
171 return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
172 case 3:
173 return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
174 default:
175 WARN_ON(1); /* should never happen */
176 return -EEXIST;
177 }
178 return 0;
179}
180
181static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
182{
183 u32 m;
184
185 m = omap3_get_mem_bank_lastmemst_mask(bank);
186
187 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
188 OMAP3430_PM_PREPWSTST, m);
189}
190
191static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
192{
193 omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
194 return 0;
195}
196
197static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
198{
199 return omap2_prm_rmw_mod_reg_bits(0,
200 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
201 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
202}
203
204static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
205{
206 return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
207 0, pwrdm->prcm_offs,
208 OMAP2_PM_PWSTCTRL);
209}
210
211struct pwrdm_ops omap2_pwrdm_operations = {
212 .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
213 .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
214 .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
215 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
216 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
217 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
218 .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
219 .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
220 .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
221};
222
223struct pwrdm_ops omap3_pwrdm_operations = {
224 .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
225 .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
226 .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
227 .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
228 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
229 .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
230 .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
231 .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
232 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
233 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
234 .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
235 .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
236 .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
237 .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
238 .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
239 .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
240 .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
241};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
new file mode 100644
index 00000000000..a7880af4b3d
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -0,0 +1,225 @@
1/*
2 * OMAP4 powerdomain control
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/io.h>
16#include <linux/errno.h>
17#include <linux/delay.h>
18
19#include "powerdomain.h"
20#include <plat/prcm.h>
21#include "prm2xxx_3xxx.h"
22#include "prm44xx.h"
23#include "prminst44xx.h"
24#include "prm-regbits-44xx.h"
25
26static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
27{
28 omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
29 (pwrst << OMAP_POWERSTATE_SHIFT),
30 pwrdm->prcm_partition,
31 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
32 return 0;
33}
34
35static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
36{
37 u32 v;
38
39 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
40 OMAP4_PM_PWSTCTRL);
41 v &= OMAP_POWERSTATE_MASK;
42 v >>= OMAP_POWERSTATE_SHIFT;
43
44 return v;
45}
46
47static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
48{
49 u32 v;
50
51 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
52 OMAP4_PM_PWSTST);
53 v &= OMAP_POWERSTATEST_MASK;
54 v >>= OMAP_POWERSTATEST_SHIFT;
55
56 return v;
57}
58
59static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
60{
61 u32 v;
62
63 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
64 OMAP4_PM_PWSTST);
65 v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
66 v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
67
68 return v;
69}
70
71static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
72{
73 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
74 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
75 pwrdm->prcm_partition,
76 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
77 return 0;
78}
79
80static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
81{
82 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
83 OMAP4430_LASTPOWERSTATEENTERED_MASK,
84 pwrdm->prcm_partition,
85 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
86 return 0;
87}
88
89static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
90{
91 u32 v;
92
93 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
94 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
95 pwrdm->prcm_partition, pwrdm->prcm_offs,
96 OMAP4_PM_PWSTCTRL);
97
98 return 0;
99}
100
101static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
102 u8 pwrst)
103{
104 u32 m;
105
106 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
107
108 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
109 pwrdm->prcm_partition, pwrdm->prcm_offs,
110 OMAP4_PM_PWSTCTRL);
111
112 return 0;
113}
114
115static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
116 u8 pwrst)
117{
118 u32 m;
119
120 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
121
122 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
123 pwrdm->prcm_partition, pwrdm->prcm_offs,
124 OMAP4_PM_PWSTCTRL);
125
126 return 0;
127}
128
129static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
130{
131 u32 v;
132
133 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
134 OMAP4_PM_PWSTST);
135 v &= OMAP4430_LOGICSTATEST_MASK;
136 v >>= OMAP4430_LOGICSTATEST_SHIFT;
137
138 return v;
139}
140
141static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
142{
143 u32 v;
144
145 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
146 OMAP4_PM_PWSTCTRL);
147 v &= OMAP4430_LOGICRETSTATE_MASK;
148 v >>= OMAP4430_LOGICRETSTATE_SHIFT;
149
150 return v;
151}
152
153static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
154{
155 u32 m, v;
156
157 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
158
159 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
160 OMAP4_PM_PWSTST);
161 v &= m;
162 v >>= __ffs(m);
163
164 return v;
165}
166
167static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
168{
169 u32 m, v;
170
171 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
172
173 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
174 OMAP4_PM_PWSTCTRL);
175 v &= m;
176 v >>= __ffs(m);
177
178 return v;
179}
180
181static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
182{
183 u32 c = 0;
184
185 /*
186 * REVISIT: pwrdm_wait_transition() may be better implemented
187 * via a callback and a periodic timer check -- how long do we expect
188 * powerdomain transitions to take?
189 */
190
191 /* XXX Is this udelay() value meaningful? */
192 while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
193 pwrdm->prcm_offs,
194 OMAP4_PM_PWSTST) &
195 OMAP_INTRANSITION_MASK) &&
196 (c++ < PWRDM_TRANSITION_BAILOUT))
197 udelay(1);
198
199 if (c > PWRDM_TRANSITION_BAILOUT) {
200 printk(KERN_ERR "powerdomain: waited too long for "
201 "powerdomain %s to complete transition\n", pwrdm->name);
202 return -EAGAIN;
203 }
204
205 pr_debug("powerdomain: completed transition in %d loops\n", c);
206
207 return 0;
208}
209
210struct pwrdm_ops omap4_pwrdm_operations = {
211 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
212 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
213 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
214 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
215 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
216 .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
217 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
218 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
219 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
220 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
221 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
222 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
223 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
224 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
225};
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
new file mode 100644
index 00000000000..2e40a5cf016
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm.c
@@ -0,0 +1,167 @@
1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/delay.h>
26
27#include <mach/system.h>
28#include <plat/common.h>
29#include <plat/prcm.h>
30#include <plat/irqs.h>
31
32#include "clock.h"
33#include "clock2xxx.h"
34#include "cm2xxx_3xxx.h"
35#include "prm2xxx_3xxx.h"
36#include "prm44xx.h"
37#include "prminst44xx.h"
38#include "prm-regbits-24xx.h"
39#include "prm-regbits-44xx.h"
40#include "control.h"
41
42void __iomem *prm_base;
43void __iomem *cm_base;
44void __iomem *cm2_base;
45
46#define MAX_MODULE_ENABLE_WAIT 100000
47
48u32 omap_prcm_get_reset_sources(void)
49{
50 /* XXX This presumably needs modification for 34XX */
51 if (cpu_is_omap24xx() || cpu_is_omap34xx())
52 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
53 if (cpu_is_omap44xx())
54 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
55
56 return 0;
57}
58EXPORT_SYMBOL(omap_prcm_get_reset_sources);
59
60/* Resets clock rates and reboots the system. Only called from system.h */
61static void omap_prcm_arch_reset(char mode, const char *cmd)
62{
63 s16 prcm_offs = 0;
64
65 if (cpu_is_omap24xx()) {
66 omap2xxx_clk_prepare_for_reboot();
67
68 prcm_offs = WKUP_MOD;
69 } else if (cpu_is_omap34xx()) {
70 prcm_offs = OMAP3430_GR_MOD;
71 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
72 } else if (cpu_is_omap44xx()) {
73 omap4_prminst_global_warm_sw_reset(); /* never returns */
74 } else {
75 WARN_ON(1);
76 }
77
78 /*
79 * As per Errata i520, in some cases, user will not be able to
80 * access DDR memory after warm-reset.
81 * This situation occurs while the warm-reset happens during a read
82 * access to DDR memory. In that particular condition, DDR memory
83 * does not respond to a corrupted read command due to the warm
84 * reset occurrence but SDRC is waiting for read completion.
85 * SDRC is not sensitive to the warm reset, but the interconnect is
86 * reset on the fly, thus causing a misalignment between SDRC logic,
87 * interconnect logic and DDR memory state.
88 * WORKAROUND:
89 * Steps to perform before a Warm reset is trigged:
90 * 1. enable self-refresh on idle request
91 * 2. put SDRC in idle
92 * 3. wait until SDRC goes to idle
93 * 4. generate SW reset (Global SW reset)
94 *
95 * Steps to be performed after warm reset occurs (in bootloader):
96 * if HW warm reset is the source, apply below steps before any
97 * accesses to SDRAM:
98 * 1. Reset SMS and SDRC and wait till reset is complete
99 * 2. Re-initialize SMS, SDRC and memory
100 *
101 * NOTE: Above work around is required only if arch reset is implemented
102 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
103 * the WA since it resets SDRC as well as part of cold reset.
104 */
105
106 /* XXX should be moved to some OMAP2/3 specific code */
107 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
108 OMAP2_RM_RSTCTRL);
109 omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
110}
111
112void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
113
114/**
115 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
116 * @reg: physical address of module IDLEST register
117 * @mask: value to mask against to determine if the module is active
118 * @idlest: idle state indicator (0 or 1) for the clock
119 * @name: name of the clock (for printk)
120 *
121 * Returns 1 if the module indicated readiness in time, or 0 if it
122 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
123 *
124 * XXX This function is deprecated. It should be removed once the
125 * hwmod conversion is complete.
126 */
127int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
128 const char *name)
129{
130 int i = 0;
131 int ena = 0;
132
133 if (idlest)
134 ena = 0;
135 else
136 ena = mask;
137
138 /* Wait for lock */
139 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
140 MAX_MODULE_ENABLE_WAIT, i);
141
142 if (i < MAX_MODULE_ENABLE_WAIT)
143 pr_debug("cm: Module associated with clock %s ready after %d "
144 "loops\n", name, i);
145 else
146 pr_err("cm: Module associated with clock %s didn't enable in "
147 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
148
149 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
150};
151
152void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
153{
154 /* Static mapping, never released */
155 if (omap2_globals->prm) {
156 prm_base = ioremap(omap2_globals->prm, SZ_8K);
157 WARN_ON(!prm_base);
158 }
159 if (omap2_globals->cm) {
160 cm_base = ioremap(omap2_globals->cm, SZ_8K);
161 WARN_ON(!cm_base);
162 }
163 if (omap2_globals->cm2) {
164 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
165 WARN_ON(!cm2_base);
166 }
167}
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 00000000000..19ff0104374
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,1046 @@
1/*
2 * OMAP SmartReflex Voltage Control
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008 Nokia Corporation
10 * Kalle Jokiniemi
11 *
12 * Copyright (C) 2007 Texas Instruments, Inc.
13 * Lesly A M <x0080970@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/interrupt.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/debugfs.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/pm_runtime.h>
27
28#include <plat/common.h>
29
30#include "pm.h"
31#include "smartreflex.h"
32
33#define SMARTREFLEX_NAME_LEN 16
34#define NVALUE_NAME_LEN 40
35#define SR_DISABLE_TIMEOUT 200
36
37struct omap_sr {
38 int srid;
39 int ip_type;
40 int nvalue_count;
41 bool autocomp_active;
42 u32 clk_length;
43 u32 err_weight;
44 u32 err_minlimit;
45 u32 err_maxlimit;
46 u32 accum_data;
47 u32 senn_avgweight;
48 u32 senp_avgweight;
49 u32 senp_mod;
50 u32 senn_mod;
51 unsigned int irq;
52 void __iomem *base;
53 struct platform_device *pdev;
54 struct list_head node;
55 struct omap_sr_nvalue_table *nvalue_table;
56 struct voltagedomain *voltdm;
57 struct dentry *dbg_dir;
58};
59
60/* sr_list contains all the instances of smartreflex module */
61static LIST_HEAD(sr_list);
62
63static struct omap_sr_class_data *sr_class;
64static struct omap_sr_pmic_data *sr_pmic_data;
65
66static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
67{
68 __raw_writel(value, (sr->base + offset));
69}
70
71static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
72 u32 value)
73{
74 u32 reg_val;
75 u32 errconfig_offs = 0, errconfig_mask = 0;
76
77 reg_val = __raw_readl(sr->base + offset);
78 reg_val &= ~mask;
79
80 /*
81 * Smartreflex error config register is special as it contains
82 * certain status bits which if written a 1 into means a clear
83 * of those bits. So in order to make sure no accidental write of
84 * 1 happens to those status bits, do a clear of them in the read
85 * value. This mean this API doesn't rewrite values in these bits
86 * if they are currently set, but does allow the caller to write
87 * those bits.
88 */
89 if (sr->ip_type == SR_TYPE_V1) {
90 errconfig_offs = ERRCONFIG_V1;
91 errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
92 } else if (sr->ip_type == SR_TYPE_V2) {
93 errconfig_offs = ERRCONFIG_V2;
94 errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
95 }
96
97 if (offset == errconfig_offs)
98 reg_val &= ~errconfig_mask;
99
100 reg_val |= value;
101
102 __raw_writel(reg_val, (sr->base + offset));
103}
104
105static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
106{
107 return __raw_readl(sr->base + offset);
108}
109
110static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
111{
112 struct omap_sr *sr_info;
113
114 if (!voltdm) {
115 pr_err("%s: Null voltage domain passed!\n", __func__);
116 return ERR_PTR(-EINVAL);
117 }
118
119 list_for_each_entry(sr_info, &sr_list, node) {
120 if (voltdm == sr_info->voltdm)
121 return sr_info;
122 }
123
124 return ERR_PTR(-ENODATA);
125}
126
127static irqreturn_t sr_interrupt(int irq, void *data)
128{
129 struct omap_sr *sr_info = (struct omap_sr *)data;
130 u32 status = 0;
131
132 if (sr_info->ip_type == SR_TYPE_V1) {
133 /* Read the status bits */
134 status = sr_read_reg(sr_info, ERRCONFIG_V1);
135
136 /* Clear them by writing back */
137 sr_write_reg(sr_info, ERRCONFIG_V1, status);
138 } else if (sr_info->ip_type == SR_TYPE_V2) {
139 /* Read the status bits */
140 status = sr_read_reg(sr_info, IRQSTATUS);
141
142 /* Clear them by writing back */
143 sr_write_reg(sr_info, IRQSTATUS, status);
144 }
145
146 if (sr_class->notify)
147 sr_class->notify(sr_info->voltdm, status);
148
149 return IRQ_HANDLED;
150}
151
152static void sr_set_clk_length(struct omap_sr *sr)
153{
154 struct clk *sys_ck;
155 u32 sys_clk_speed;
156
157 if (cpu_is_omap34xx())
158 sys_ck = clk_get(NULL, "sys_ck");
159 else
160 sys_ck = clk_get(NULL, "sys_clkin_ck");
161
162 if (IS_ERR(sys_ck)) {
163 dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
164 __func__);
165 return;
166 }
167 sys_clk_speed = clk_get_rate(sys_ck);
168 clk_put(sys_ck);
169
170 switch (sys_clk_speed) {
171 case 12000000:
172 sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
173 break;
174 case 13000000:
175 sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
176 break;
177 case 19200000:
178 sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
179 break;
180 case 26000000:
181 sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
182 break;
183 case 38400000:
184 sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
185 break;
186 default:
187 dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
188 __func__, sys_clk_speed);
189 break;
190 }
191}
192
193static void sr_set_regfields(struct omap_sr *sr)
194{
195 /*
196 * For time being these values are defined in smartreflex.h
197 * and populated during init. May be they can be moved to board
198 * file or pmic specific data structure. In that case these structure
199 * fields will have to be populated using the pdata or pmic structure.
200 */
201 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
202 sr->err_weight = OMAP3430_SR_ERRWEIGHT;
203 sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
204 sr->accum_data = OMAP3430_SR_ACCUMDATA;
205 if (!(strcmp(sr->voltdm->name, "mpu"))) {
206 sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
207 sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
208 } else {
209 sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
210 sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
211 }
212 }
213}
214
215static void sr_start_vddautocomp(struct omap_sr *sr)
216{
217 if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
218 dev_warn(&sr->pdev->dev,
219 "%s: smartreflex class driver not registered\n",
220 __func__);
221 return;
222 }
223
224 if (!sr_class->enable(sr->voltdm))
225 sr->autocomp_active = true;
226}
227
228static void sr_stop_vddautocomp(struct omap_sr *sr)
229{
230 if (!sr_class || !(sr_class->disable)) {
231 dev_warn(&sr->pdev->dev,
232 "%s: smartreflex class driver not registered\n",
233 __func__);
234 return;
235 }
236
237 if (sr->autocomp_active) {
238 sr_class->disable(sr->voltdm, 1);
239 sr->autocomp_active = false;
240 }
241}
242
243/*
244 * This function handles the intializations which have to be done
245 * only when both sr device and class driver regiter has
246 * completed. This will be attempted to be called from both sr class
247 * driver register and sr device intializtion API's. Only one call
248 * will ultimately succeed.
249 *
250 * Currently this function registers interrrupt handler for a particular SR
251 * if smartreflex class driver is already registered and has
252 * requested for interrupts and the SR interrupt line in present.
253 */
254static int sr_late_init(struct omap_sr *sr_info)
255{
256 char *name;
257 struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
258 struct resource *mem;
259 int ret = 0;
260
261 if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
262 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
263 if (name == NULL) {
264 ret = -ENOMEM;
265 goto error;
266 }
267 ret = request_irq(sr_info->irq, sr_interrupt,
268 0, name, (void *)sr_info);
269 if (ret)
270 goto error;
271 disable_irq(sr_info->irq);
272 }
273
274 if (pdata && pdata->enable_on_init)
275 sr_start_vddautocomp(sr_info);
276
277 return ret;
278
279error:
280 iounmap(sr_info->base);
281 mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
282 release_mem_region(mem->start, resource_size(mem));
283 list_del(&sr_info->node);
284 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
285 "interrupt handler. Smartreflex will"
286 "not function as desired\n", __func__);
287 kfree(name);
288 kfree(sr_info);
289 return ret;
290}
291
292static void sr_v1_disable(struct omap_sr *sr)
293{
294 int timeout = 0;
295
296 /* Enable MCUDisableAcknowledge interrupt */
297 sr_modify_reg(sr, ERRCONFIG_V1,
298 ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
299
300 /* SRCONFIG - disable SR */
301 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
302
303 /* Disable all other SR interrupts and clear the status */
304 sr_modify_reg(sr, ERRCONFIG_V1,
305 (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
306 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
307 (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
308 ERRCONFIG_MCUBOUNDINTST |
309 ERRCONFIG_VPBOUNDINTST_V1));
310
311 /*
312 * Wait for SR to be disabled.
313 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
314 */
315 omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
316 ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
317 timeout);
318
319 if (timeout >= SR_DISABLE_TIMEOUT)
320 dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
321 __func__);
322
323 /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
324 sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
325 ERRCONFIG_MCUDISACKINTST);
326}
327
328static void sr_v2_disable(struct omap_sr *sr)
329{
330 int timeout = 0;
331
332 /* Enable MCUDisableAcknowledge interrupt */
333 sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
334
335 /* SRCONFIG - disable SR */
336 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
337
338 /* Disable all other SR interrupts and clear the status */
339 sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
340 ERRCONFIG_VPBOUNDINTST_V2);
341 sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
342 IRQENABLE_MCUVALIDINT |
343 IRQENABLE_MCUBOUNDSINT));
344 sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
345 IRQSTATUS_MCVALIDINT |
346 IRQSTATUS_MCBOUNDSINT));
347
348 /*
349 * Wait for SR to be disabled.
350 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
351 */
352 omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
353 IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
354 timeout);
355
356 if (timeout >= SR_DISABLE_TIMEOUT)
357 dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
358 __func__);
359
360 /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
361 sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
362 sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
363}
364
365static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
366{
367 int i;
368
369 if (!sr->nvalue_table) {
370 dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
371 __func__);
372 return 0;
373 }
374
375 for (i = 0; i < sr->nvalue_count; i++) {
376 if (sr->nvalue_table[i].efuse_offs == efuse_offs)
377 return sr->nvalue_table[i].nvalue;
378 }
379
380 return 0;
381}
382
383/* Public Functions */
384
385/**
386 * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
387 * error generator module.
388 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
389 *
390 * This API is to be called from the smartreflex class driver to
391 * configure the error generator module inside the smartreflex module.
392 * SR settings if using the ERROR module inside Smartreflex.
393 * SR CLASS 3 by default uses only the ERROR module where as
394 * SR CLASS 2 can choose between ERROR module and MINMAXAVG
395 * module. Returns 0 on success and error value in case of failure.
396 */
397int sr_configure_errgen(struct voltagedomain *voltdm)
398{
399 u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
400 u32 vpboundint_st, senp_en = 0, senn_en = 0;
401 u8 senp_shift, senn_shift;
402 struct omap_sr *sr = _sr_lookup(voltdm);
403
404 if (IS_ERR(sr)) {
405 pr_warning("%s: omap_sr struct for sr_%s not found\n",
406 __func__, voltdm->name);
407 return -EINVAL;
408 }
409
410 if (!sr->clk_length)
411 sr_set_clk_length(sr);
412
413 senp_en = sr->senp_mod;
414 senn_en = sr->senn_mod;
415
416 sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
417 SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
418
419 if (sr->ip_type == SR_TYPE_V1) {
420 sr_config |= SRCONFIG_DELAYCTRL;
421 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
422 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
423 errconfig_offs = ERRCONFIG_V1;
424 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
425 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
426 } else if (sr->ip_type == SR_TYPE_V2) {
427 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
428 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
429 errconfig_offs = ERRCONFIG_V2;
430 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
431 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
432 } else {
433 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
434 "module without specifying the ip\n", __func__);
435 return -EINVAL;
436 }
437
438 sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
439 sr_write_reg(sr, SRCONFIG, sr_config);
440 sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
441 (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
442 (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT);
443 sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
444 SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
445 sr_errconfig);
446
447 /* Enabling the interrupts if the ERROR module is used */
448 sr_modify_reg(sr, errconfig_offs,
449 vpboundint_en, (vpboundint_en | vpboundint_st));
450
451 return 0;
452}
453
454/**
455 * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
456 * minmaxavg module.
457 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
458 *
459 * This API is to be called from the smartreflex class driver to
460 * configure the minmaxavg module inside the smartreflex module.
461 * SR settings if using the ERROR module inside Smartreflex.
462 * SR CLASS 3 by default uses only the ERROR module where as
463 * SR CLASS 2 can choose between ERROR module and MINMAXAVG
464 * module. Returns 0 on success and error value in case of failure.
465 */
466int sr_configure_minmax(struct voltagedomain *voltdm)
467{
468 u32 sr_config, sr_avgwt;
469 u32 senp_en = 0, senn_en = 0;
470 u8 senp_shift, senn_shift;
471 struct omap_sr *sr = _sr_lookup(voltdm);
472
473 if (IS_ERR(sr)) {
474 pr_warning("%s: omap_sr struct for sr_%s not found\n",
475 __func__, voltdm->name);
476 return -EINVAL;
477 }
478
479 if (!sr->clk_length)
480 sr_set_clk_length(sr);
481
482 senp_en = sr->senp_mod;
483 senn_en = sr->senn_mod;
484
485 sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
486 SRCONFIG_SENENABLE |
487 (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
488
489 if (sr->ip_type == SR_TYPE_V1) {
490 sr_config |= SRCONFIG_DELAYCTRL;
491 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
492 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
493 } else if (sr->ip_type == SR_TYPE_V2) {
494 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
495 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
496 } else {
497 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
498 "module without specifying the ip\n", __func__);
499 return -EINVAL;
500 }
501
502 sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
503 sr_write_reg(sr, SRCONFIG, sr_config);
504 sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
505 (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
506 sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
507
508 /*
509 * Enabling the interrupts if MINMAXAVG module is used.
510 * TODO: check if all the interrupts are mandatory
511 */
512 if (sr->ip_type == SR_TYPE_V1) {
513 sr_modify_reg(sr, ERRCONFIG_V1,
514 (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
515 ERRCONFIG_MCUBOUNDINTEN),
516 (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
517 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
518 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
519 } else if (sr->ip_type == SR_TYPE_V2) {
520 sr_write_reg(sr, IRQSTATUS,
521 IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
522 IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
523 sr_write_reg(sr, IRQENABLE_SET,
524 IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
525 IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
526 }
527
528 return 0;
529}
530
531/**
532 * sr_enable() - Enables the smartreflex module.
533 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
534 * @volt: The voltage at which the Voltage domain associated with
535 * the smartreflex module is operating at.
536 * This is required only to program the correct Ntarget value.
537 *
538 * This API is to be called from the smartreflex class driver to
539 * enable a smartreflex module. Returns 0 on success. Returns error
540 * value if the voltage passed is wrong or if ntarget value is wrong.
541 */
542int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
543{
544 u32 nvalue_reciprocal;
545 struct omap_volt_data *volt_data;
546 struct omap_sr *sr = _sr_lookup(voltdm);
547 int ret;
548
549 if (IS_ERR(sr)) {
550 pr_warning("%s: omap_sr struct for sr_%s not found\n",
551 __func__, voltdm->name);
552 return -EINVAL;
553 }
554
555 volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
556
557 if (IS_ERR(volt_data)) {
558 dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
559 "for nominal voltage %ld\n", __func__, volt);
560 return -ENODATA;
561 }
562
563 nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
564
565 if (!nvalue_reciprocal) {
566 dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
567 __func__, volt);
568 return -ENODATA;
569 }
570
571 /* errminlimit is opp dependent and hence linked to voltage */
572 sr->err_minlimit = volt_data->sr_errminlimit;
573
574 pm_runtime_get_sync(&sr->pdev->dev);
575
576 /* Check if SR is already enabled. If yes do nothing */
577 if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
578 return 0;
579
580 /* Configure SR */
581 ret = sr_class->configure(voltdm);
582 if (ret)
583 return ret;
584
585 sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
586
587 /* SRCONFIG - enable SR */
588 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
589 return 0;
590}
591
592/**
593 * sr_disable() - Disables the smartreflex module.
594 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
595 *
596 * This API is to be called from the smartreflex class driver to
597 * disable a smartreflex module.
598 */
599void sr_disable(struct voltagedomain *voltdm)
600{
601 struct omap_sr *sr = _sr_lookup(voltdm);
602
603 if (IS_ERR(sr)) {
604 pr_warning("%s: omap_sr struct for sr_%s not found\n",
605 __func__, voltdm->name);
606 return;
607 }
608
609 /* Check if SR clocks are already disabled. If yes do nothing */
610 if (pm_runtime_suspended(&sr->pdev->dev))
611 return;
612
613 /*
614 * Disable SR if only it is indeed enabled. Else just
615 * disable the clocks.
616 */
617 if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
618 if (sr->ip_type == SR_TYPE_V1)
619 sr_v1_disable(sr);
620 else if (sr->ip_type == SR_TYPE_V2)
621 sr_v2_disable(sr);
622 }
623
624 pm_runtime_put_sync_suspend(&sr->pdev->dev);
625}
626
627/**
628 * sr_register_class() - API to register a smartreflex class parameters.
629 * @class_data: The structure containing various sr class specific data.
630 *
631 * This API is to be called by the smartreflex class driver to register itself
632 * with the smartreflex driver during init. Returns 0 on success else the
633 * error value.
634 */
635int sr_register_class(struct omap_sr_class_data *class_data)
636{
637 struct omap_sr *sr_info;
638
639 if (!class_data) {
640 pr_warning("%s:, Smartreflex class data passed is NULL\n",
641 __func__);
642 return -EINVAL;
643 }
644
645 if (sr_class) {
646 pr_warning("%s: Smartreflex class driver already registered\n",
647 __func__);
648 return -EBUSY;
649 }
650
651 sr_class = class_data;
652
653 /*
654 * Call into late init to do intializations that require
655 * both sr driver and sr class driver to be initiallized.
656 */
657 list_for_each_entry(sr_info, &sr_list, node)
658 sr_late_init(sr_info);
659
660 return 0;
661}
662
663/**
664 * omap_sr_enable() - API to enable SR clocks and to call into the
665 * registered smartreflex class enable API.
666 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
667 *
668 * This API is to be called from the kernel in order to enable
669 * a particular smartreflex module. This API will do the initial
670 * configurations to turn on the smartreflex module and in turn call
671 * into the registered smartreflex class enable API.
672 */
673void omap_sr_enable(struct voltagedomain *voltdm)
674{
675 struct omap_sr *sr = _sr_lookup(voltdm);
676
677 if (IS_ERR(sr)) {
678 pr_warning("%s: omap_sr struct for sr_%s not found\n",
679 __func__, voltdm->name);
680 return;
681 }
682
683 if (!sr->autocomp_active)
684 return;
685
686 if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
687 dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
688 "registered\n", __func__);
689 return;
690 }
691
692 sr_class->enable(voltdm);
693}
694
695/**
696 * omap_sr_disable() - API to disable SR without resetting the voltage
697 * processor voltage
698 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
699 *
700 * This API is to be called from the kernel in order to disable
701 * a particular smartreflex module. This API will in turn call
702 * into the registered smartreflex class disable API. This API will tell
703 * the smartreflex class disable not to reset the VP voltage after
704 * disabling smartreflex.
705 */
706void omap_sr_disable(struct voltagedomain *voltdm)
707{
708 struct omap_sr *sr = _sr_lookup(voltdm);
709
710 if (IS_ERR(sr)) {
711 pr_warning("%s: omap_sr struct for sr_%s not found\n",
712 __func__, voltdm->name);
713 return;
714 }
715
716 if (!sr->autocomp_active)
717 return;
718
719 if (!sr_class || !(sr_class->disable)) {
720 dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
721 "registered\n", __func__);
722 return;
723 }
724
725 sr_class->disable(voltdm, 0);
726}
727
728/**
729 * omap_sr_disable_reset_volt() - API to disable SR and reset the
730 * voltage processor voltage
731 * @voltdm: VDD pointer to which the SR module to be configured belongs to.
732 *
733 * This API is to be called from the kernel in order to disable
734 * a particular smartreflex module. This API will in turn call
735 * into the registered smartreflex class disable API. This API will tell
736 * the smartreflex class disable to reset the VP voltage after
737 * disabling smartreflex.
738 */
739void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
740{
741 struct omap_sr *sr = _sr_lookup(voltdm);
742
743 if (IS_ERR(sr)) {
744 pr_warning("%s: omap_sr struct for sr_%s not found\n",
745 __func__, voltdm->name);
746 return;
747 }
748
749 if (!sr->autocomp_active)
750 return;
751
752 if (!sr_class || !(sr_class->disable)) {
753 dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
754 "registered\n", __func__);
755 return;
756 }
757
758 sr_class->disable(voltdm, 1);
759}
760
761/**
762 * omap_sr_register_pmic() - API to register pmic specific info.
763 * @pmic_data: The structure containing pmic specific data.
764 *
765 * This API is to be called from the PMIC specific code to register with
766 * smartreflex driver pmic specific info. Currently the only info required
767 * is the smartreflex init on the PMIC side.
768 */
769void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
770{
771 if (!pmic_data) {
772 pr_warning("%s: Trying to register NULL PMIC data structure"
773 "with smartreflex\n", __func__);
774 return;
775 }
776
777 sr_pmic_data = pmic_data;
778}
779
780/* PM Debug Fs enteries to enable disable smartreflex. */
781static int omap_sr_autocomp_show(void *data, u64 *val)
782{
783 struct omap_sr *sr_info = (struct omap_sr *) data;
784
785 if (!sr_info) {
786 pr_warning("%s: omap_sr struct not found\n", __func__);
787 return -EINVAL;
788 }
789
790 *val = sr_info->autocomp_active;
791
792 return 0;
793}
794
795static int omap_sr_autocomp_store(void *data, u64 val)
796{
797 struct omap_sr *sr_info = (struct omap_sr *) data;
798
799 if (!sr_info) {
800 pr_warning("%s: omap_sr struct not found\n", __func__);
801 return -EINVAL;
802 }
803
804 /* Sanity check */
805 if (val && (val != 1)) {
806 pr_warning("%s: Invalid argument %lld\n", __func__, val);
807 return -EINVAL;
808 }
809
810 /* control enable/disable only if there is a delta in value */
811 if (sr_info->autocomp_active != val) {
812 if (!val)
813 sr_stop_vddautocomp(sr_info);
814 else
815 sr_start_vddautocomp(sr_info);
816 }
817
818 return 0;
819}
820
821DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
822 omap_sr_autocomp_store, "%llu\n");
823
824static int __init omap_sr_probe(struct platform_device *pdev)
825{
826 struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
827 struct omap_sr_data *pdata = pdev->dev.platform_data;
828 struct resource *mem, *irq;
829 struct dentry *vdd_dbg_dir, *nvalue_dir;
830 struct omap_volt_data *volt_data;
831 int i, ret = 0;
832
833 if (!sr_info) {
834 dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
835 __func__);
836 return -ENOMEM;
837 }
838
839 if (!pdata) {
840 dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
841 ret = -EINVAL;
842 goto err_free_devinfo;
843 }
844
845 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 if (!mem) {
847 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
848 ret = -ENODEV;
849 goto err_free_devinfo;
850 }
851
852 mem = request_mem_region(mem->start, resource_size(mem),
853 dev_name(&pdev->dev));
854 if (!mem) {
855 dev_err(&pdev->dev, "%s: no mem region\n", __func__);
856 ret = -EBUSY;
857 goto err_free_devinfo;
858 }
859
860 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
861
862 pm_runtime_enable(&pdev->dev);
863 pm_runtime_irq_safe(&pdev->dev);
864
865 sr_info->pdev = pdev;
866 sr_info->srid = pdev->id;
867 sr_info->voltdm = pdata->voltdm;
868 sr_info->nvalue_table = pdata->nvalue_table;
869 sr_info->nvalue_count = pdata->nvalue_count;
870 sr_info->senn_mod = pdata->senn_mod;
871 sr_info->senp_mod = pdata->senp_mod;
872 sr_info->autocomp_active = false;
873 sr_info->ip_type = pdata->ip_type;
874 sr_info->base = ioremap(mem->start, resource_size(mem));
875 if (!sr_info->base) {
876 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
877 ret = -ENOMEM;
878 goto err_release_region;
879 }
880
881 if (irq)
882 sr_info->irq = irq->start;
883
884 sr_set_clk_length(sr_info);
885 sr_set_regfields(sr_info);
886
887 list_add(&sr_info->node, &sr_list);
888
889 /*
890 * Call into late init to do intializations that require
891 * both sr driver and sr class driver to be initiallized.
892 */
893 if (sr_class) {
894 ret = sr_late_init(sr_info);
895 if (ret) {
896 pr_warning("%s: Error in SR late init\n", __func__);
897 return ret;
898 }
899 }
900
901 dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
902
903 /*
904 * If the voltage domain debugfs directory is not created, do
905 * not try to create rest of the debugfs entries.
906 */
907 vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
908 if (!vdd_dbg_dir) {
909 ret = -EINVAL;
910 goto err_iounmap;
911 }
912
913 sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
914 if (IS_ERR(sr_info->dbg_dir)) {
915 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
916 __func__);
917 ret = PTR_ERR(sr_info->dbg_dir);
918 goto err_iounmap;
919 }
920
921 (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
922 sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
923 (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
924 &sr_info->err_weight);
925 (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
926 &sr_info->err_maxlimit);
927 (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
928 &sr_info->err_minlimit);
929
930 nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
931 if (IS_ERR(nvalue_dir)) {
932 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
933 "for n-values\n", __func__);
934 ret = PTR_ERR(nvalue_dir);
935 goto err_debugfs;
936 }
937
938 omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
939 if (!volt_data) {
940 dev_warn(&pdev->dev, "%s: No Voltage table for the"
941 " corresponding vdd vdd_%s. Cannot create debugfs"
942 "entries for n-values\n",
943 __func__, sr_info->voltdm->name);
944 ret = -ENODATA;
945 goto err_debugfs;
946 }
947
948 for (i = 0; i < sr_info->nvalue_count; i++) {
949 char name[NVALUE_NAME_LEN + 1];
950
951 snprintf(name, sizeof(name), "volt_%d",
952 volt_data[i].volt_nominal);
953 (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
954 &(sr_info->nvalue_table[i].nvalue));
955 }
956
957 return ret;
958
959err_debugfs:
960 debugfs_remove_recursive(sr_info->dbg_dir);
961err_iounmap:
962 list_del(&sr_info->node);
963 iounmap(sr_info->base);
964err_release_region:
965 release_mem_region(mem->start, resource_size(mem));
966err_free_devinfo:
967 kfree(sr_info);
968
969 return ret;
970}
971
972static int __devexit omap_sr_remove(struct platform_device *pdev)
973{
974 struct omap_sr_data *pdata = pdev->dev.platform_data;
975 struct omap_sr *sr_info;
976 struct resource *mem;
977
978 if (!pdata) {
979 dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
980 return -EINVAL;
981 }
982
983 sr_info = _sr_lookup(pdata->voltdm);
984 if (IS_ERR(sr_info)) {
985 dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
986 __func__);
987 return -EINVAL;
988 }
989
990 if (sr_info->autocomp_active)
991 sr_stop_vddautocomp(sr_info);
992 if (sr_info->dbg_dir)
993 debugfs_remove_recursive(sr_info->dbg_dir);
994
995 list_del(&sr_info->node);
996 iounmap(sr_info->base);
997 kfree(sr_info);
998 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
999 release_mem_region(mem->start, resource_size(mem));
1000
1001 return 0;
1002}
1003
1004static struct platform_driver smartreflex_driver = {
1005 .remove = omap_sr_remove,
1006 .driver = {
1007 .name = "smartreflex",
1008 },
1009};
1010
1011static int __init sr_init(void)
1012{
1013 int ret = 0;
1014
1015 /*
1016 * sr_init is a late init. If by then a pmic specific API is not
1017 * registered either there is no need for anything to be done on
1018 * the PMIC side or somebody has forgotten to register a PMIC
1019 * handler. Warn for the second condition.
1020 */
1021 if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
1022 sr_pmic_data->sr_pmic_init();
1023 else
1024 pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
1025
1026 ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
1027 if (ret) {
1028 pr_err("%s: platform driver register failed for SR\n",
1029 __func__);
1030 return ret;
1031 }
1032
1033 return 0;
1034}
1035
1036static void __exit sr_exit(void)
1037{
1038 platform_driver_unregister(&smartreflex_driver);
1039}
1040late_initcall(sr_init);
1041module_exit(sr_exit);
1042
1043MODULE_DESCRIPTION("OMAP Smartreflex Driver");
1044MODULE_LICENSE("GPL");
1045MODULE_ALIAS("platform:" DRIVER_NAME);
1046MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
new file mode 100644
index 00000000000..5f35b9e2555
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -0,0 +1,246 @@
1/*
2 * OMAP Smartreflex Defines and Routines
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008 Nokia Corporation
10 * Kalle Jokiniemi
11 *
12 * Copyright (C) 2007 Texas Instruments, Inc.
13 * Lesly A M <x0080970@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
21#define __ASM_ARM_OMAP_SMARTREFLEX_H
22
23#include <linux/platform_device.h>
24
25#include "voltage.h"
26
27/*
28 * Different Smartreflex IPs version. The v1 is the 65nm version used in
29 * OMAP3430. The v2 is the update for the 45nm version of the IP
30 * used in OMAP3630 and OMAP4430
31 */
32#define SR_TYPE_V1 1
33#define SR_TYPE_V2 2
34
35/* SMART REFLEX REG ADDRESS OFFSET */
36#define SRCONFIG 0x00
37#define SRSTATUS 0x04
38#define SENVAL 0x08
39#define SENMIN 0x0C
40#define SENMAX 0x10
41#define SENAVG 0x14
42#define AVGWEIGHT 0x18
43#define NVALUERECIPROCAL 0x1c
44#define SENERROR_V1 0x20
45#define ERRCONFIG_V1 0x24
46#define IRQ_EOI 0x20
47#define IRQSTATUS_RAW 0x24
48#define IRQSTATUS 0x28
49#define IRQENABLE_SET 0x2C
50#define IRQENABLE_CLR 0x30
51#define SENERROR_V2 0x34
52#define ERRCONFIG_V2 0x38
53
54/* Bit/Shift Positions */
55
56/* SRCONFIG */
57#define SRCONFIG_ACCUMDATA_SHIFT 22
58#define SRCONFIG_SRCLKLENGTH_SHIFT 12
59#define SRCONFIG_SENNENABLE_V1_SHIFT 5
60#define SRCONFIG_SENPENABLE_V1_SHIFT 3
61#define SRCONFIG_SENNENABLE_V2_SHIFT 1
62#define SRCONFIG_SENPENABLE_V2_SHIFT 0
63#define SRCONFIG_CLKCTRL_SHIFT 0
64
65#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
66
67#define SRCONFIG_SRENABLE BIT(11)
68#define SRCONFIG_SENENABLE BIT(10)
69#define SRCONFIG_ERRGEN_EN BIT(9)
70#define SRCONFIG_MINMAXAVG_EN BIT(8)
71#define SRCONFIG_DELAYCTRL BIT(2)
72
73/* AVGWEIGHT */
74#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
75#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
76
77/* NVALUERECIPROCAL */
78#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
79#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
80#define NVALUERECIPROCAL_RNSENP_SHIFT 8
81#define NVALUERECIPROCAL_RNSENN_SHIFT 0
82
83/* ERRCONFIG */
84#define ERRCONFIG_ERRWEIGHT_SHIFT 16
85#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
86#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
87
88#define SR_ERRWEIGHT_MASK (0x07 << 16)
89#define SR_ERRMAXLIMIT_MASK (0xff << 8)
90#define SR_ERRMINLIMIT_MASK (0xff << 0)
91
92#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
93#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
94#define ERRCONFIG_MCUACCUMINTEN BIT(29)
95#define ERRCONFIG_MCUACCUMINTST BIT(28)
96#define ERRCONFIG_MCUVALIDINTEN BIT(27)
97#define ERRCONFIG_MCUVALIDINTST BIT(26)
98#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
99#define ERRCONFIG_MCUBOUNDINTST BIT(24)
100#define ERRCONFIG_MCUDISACKINTEN BIT(23)
101#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
102#define ERRCONFIG_MCUDISACKINTST BIT(22)
103#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
104
105#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
106 ERRCONFIG_MCUACCUMINTST | \
107 ERRCONFIG_MCUVALIDINTST | \
108 ERRCONFIG_MCUBOUNDINTST | \
109 ERRCONFIG_MCUDISACKINTST)
110/* IRQSTATUS */
111#define IRQSTATUS_MCUACCUMINT BIT(3)
112#define IRQSTATUS_MCVALIDINT BIT(2)
113#define IRQSTATUS_MCBOUNDSINT BIT(1)
114#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
115
116/* IRQENABLE_SET and IRQENABLE_CLEAR */
117#define IRQENABLE_MCUACCUMINT BIT(3)
118#define IRQENABLE_MCUVALIDINT BIT(2)
119#define IRQENABLE_MCUBOUNDSINT BIT(1)
120#define IRQENABLE_MCUDISABLEACKINT BIT(0)
121
122/* Common Bit values */
123
124#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
125#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
126#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
127#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
128#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
129
130/*
131 * 3430 specific values. Maybe these should be passed from board file or
132 * pmic structures.
133 */
134#define OMAP3430_SR_ACCUMDATA 0x1f4
135
136#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
137#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
138
139#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
140#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
141
142#define OMAP3430_SR_ERRWEIGHT 0x04
143#define OMAP3430_SR_ERRMAXLIMIT 0x02
144
145/**
146 * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
147 * pmic specific info to smartreflex driver
148 *
149 * @sr_pmic_init: API to initialize smartreflex on the PMIC side.
150 */
151struct omap_sr_pmic_data {
152 void (*sr_pmic_init) (void);
153};
154
155#ifdef CONFIG_OMAP_SMARTREFLEX
156/*
157 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
158 * The smartreflex class driver should pass the class type.
159 * Should be used to populate the class_type field of the
160 * omap_smartreflex_class_data structure.
161 */
162#define SR_CLASS1 0x1
163#define SR_CLASS2 0x2
164#define SR_CLASS3 0x3
165
166/**
167 * struct omap_sr_class_data - Smartreflex class driver info
168 *
169 * @enable: API to enable a particular class smaartreflex.
170 * @disable: API to disable a particular class smartreflex.
171 * @configure: API to configure a particular class smartreflex.
172 * @notify: API to notify the class driver about an event in SR.
173 * Not needed for class3.
174 * @notify_flags: specify the events to be notified to the class driver
175 * @class_type: specify which smartreflex class.
176 * Can be used by the SR driver to take any class
177 * based decisions.
178 */
179struct omap_sr_class_data {
180 int (*enable)(struct voltagedomain *voltdm);
181 int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
182 int (*configure)(struct voltagedomain *voltdm);
183 int (*notify)(struct voltagedomain *voltdm, u32 status);
184 u8 notify_flags;
185 u8 class_type;
186};
187
188/**
189 * struct omap_sr_nvalue_table - Smartreflex n-target value info
190 *
191 * @efuse_offs: The offset of the efuse where n-target values are stored.
192 * @nvalue: The n-target value.
193 */
194struct omap_sr_nvalue_table {
195 u32 efuse_offs;
196 u32 nvalue;
197};
198
199/**
200 * struct omap_sr_data - Smartreflex platform data.
201 *
202 * @ip_type: Smartreflex IP type.
203 * @senp_mod: SENPENABLE value for the sr
204 * @senn_mod: SENNENABLE value for sr
205 * @nvalue_count: Number of distinct nvalues in the nvalue table
206 * @enable_on_init: whether this sr module needs to enabled at
207 * boot up or not.
208 * @nvalue_table: table containing the efuse offsets and nvalues
209 * corresponding to them.
210 * @voltdm: Pointer to the voltage domain associated with the SR
211 */
212struct omap_sr_data {
213 int ip_type;
214 u32 senp_mod;
215 u32 senn_mod;
216 int nvalue_count;
217 bool enable_on_init;
218 struct omap_sr_nvalue_table *nvalue_table;
219 struct voltagedomain *voltdm;
220};
221
222/* Smartreflex module enable/disable interface */
223void omap_sr_enable(struct voltagedomain *voltdm);
224void omap_sr_disable(struct voltagedomain *voltdm);
225void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
226
227/* API to register the pmic specific data with the smartreflex driver. */
228void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
229
230/* Smartreflex driver hooks to be called from Smartreflex class driver */
231int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
232void sr_disable(struct voltagedomain *voltdm);
233int sr_configure_errgen(struct voltagedomain *voltdm);
234int sr_configure_minmax(struct voltagedomain *voltdm);
235
236/* API to register the smartreflex class driver with the smartreflex driver */
237int sr_register_class(struct omap_sr_class_data *class_data);
238#else
239static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
240static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
241static inline void omap_sr_disable_reset_volt(
242 struct voltagedomain *voltdm) {}
243static inline void omap_sr_register_pmic(
244 struct omap_sr_pmic_data *pmic_data) {}
245#endif
246#endif
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
new file mode 100644
index 00000000000..31c0ac4cd66
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -0,0 +1,39 @@
1/*
2 * The MPU local timer source file. In OMAP4, both cortex-a9 cores have
3 * own timer in it's MPU domain. These timers will be driving the
4 * linux kernel SMP tick framework when active. These timers are not
5 * part of the wake up domain.
6 *
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Author:
10 * Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This file is based on arm realview smp platform file.
13 * Copyright (C) 2002 ARM Ltd.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19#include <linux/init.h>
20#include <linux/smp.h>
21#include <linux/clockchips.h>
22#include <asm/irq.h>
23#include <asm/smp_twd.h>
24#include <asm/localtimer.h>
25
26/*
27 * Setup the local clock events for a CPU.
28 */
29int __cpuinit local_timer_setup(struct clock_event_device *evt)
30{
31 /* Local timers are not supprted on OMAP4430 ES1.0 */
32 if (omap_rev() == OMAP4430_REV_ES1_0)
33 return -ENXIO;
34
35 evt->irq = OMAP44XX_IRQ_LOCALTIMER;
36 twd_timer_setup(evt);
37 return 0;
38}
39
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
new file mode 100644
index 00000000000..1481078763b
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -0,0 +1,359 @@
1/*
2 * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29
30#include <asm/irq.h>
31
32#include <plat/usb.h>
33#include <plat/board.h>
34
35#include "control.h"
36#include "mux.h"
37
38#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
39#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
40#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
41#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
42#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
43
44#if defined(CONFIG_ARCH_OMAP2)
45
46#ifdef CONFIG_USB_GADGET_OMAP
47
48static struct resource udc_resources[] = {
49 /* order is significant! */
50 { /* registers */
51 .start = UDC_BASE,
52 .end = UDC_BASE + 0xff,
53 .flags = IORESOURCE_MEM,
54 }, { /* general IRQ */
55 .start = INT_USB_IRQ_GEN,
56 .flags = IORESOURCE_IRQ,
57 }, { /* PIO IRQ */
58 .start = INT_USB_IRQ_NISO,
59 .flags = IORESOURCE_IRQ,
60 }, { /* SOF IRQ */
61 .start = INT_USB_IRQ_ISO,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66static u64 udc_dmamask = ~(u32)0;
67
68static struct platform_device udc_device = {
69 .name = "omap_udc",
70 .id = -1,
71 .dev = {
72 .dma_mask = &udc_dmamask,
73 .coherent_dma_mask = 0xffffffff,
74 },
75 .num_resources = ARRAY_SIZE(udc_resources),
76 .resource = udc_resources,
77};
78
79static inline void udc_device_init(struct omap_usb_config *pdata)
80{
81 pdata->udc_device = &udc_device;
82}
83
84#else
85
86static inline void udc_device_init(struct omap_usb_config *pdata)
87{
88}
89
90#endif
91
92#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
93
94/* The dmamask must be set for OHCI to work */
95static u64 ohci_dmamask = ~(u32)0;
96
97static struct resource ohci_resources[] = {
98 {
99 .start = OMAP_OHCI_BASE,
100 .end = OMAP_OHCI_BASE + 0xff,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .start = INT_USB_IRQ_HGEN,
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct platform_device ohci_device = {
110 .name = "ohci",
111 .id = -1,
112 .dev = {
113 .dma_mask = &ohci_dmamask,
114 .coherent_dma_mask = 0xffffffff,
115 },
116 .num_resources = ARRAY_SIZE(ohci_resources),
117 .resource = ohci_resources,
118};
119
120static inline void ohci_device_init(struct omap_usb_config *pdata)
121{
122 pdata->ohci_device = &ohci_device;
123}
124
125#else
126
127static inline void ohci_device_init(struct omap_usb_config *pdata)
128{
129}
130
131#endif
132
133#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
134
135static struct resource otg_resources[] = {
136 /* order is significant! */
137 {
138 .start = OTG_BASE,
139 .end = OTG_BASE + 0xff,
140 .flags = IORESOURCE_MEM,
141 }, {
142 .start = INT_USB_IRQ_OTG,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct platform_device otg_device = {
148 .name = "omap_otg",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(otg_resources),
151 .resource = otg_resources,
152};
153
154static inline void otg_device_init(struct omap_usb_config *pdata)
155{
156 pdata->otg_device = &otg_device;
157}
158
159#else
160
161static inline void otg_device_init(struct omap_usb_config *pdata)
162{
163}
164
165#endif
166
167static void omap2_usb_devconf_clear(u8 port, u32 mask)
168{
169 u32 r;
170
171 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
172 r &= ~USBTXWRMODEI(port, mask);
173 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
174}
175
176static void omap2_usb_devconf_set(u8 port, u32 mask)
177{
178 u32 r;
179
180 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
181 r |= USBTXWRMODEI(port, mask);
182 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
183}
184
185static void omap2_usb2_disable_5pinbitll(void)
186{
187 u32 r;
188
189 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
190 r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
191 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
192}
193
194static void omap2_usb2_enable_5pinunitll(void)
195{
196 u32 r;
197
198 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
199 r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
200 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
201}
202
203static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
204{
205 u32 syscon1 = 0;
206
207 omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
208
209 if (nwires == 0)
210 return 0;
211
212 if (is_device)
213 omap_mux_init_signal("usb0_puen", 0);
214
215 omap_mux_init_signal("usb0_dat", 0);
216 omap_mux_init_signal("usb0_txen", 0);
217 omap_mux_init_signal("usb0_se0", 0);
218 if (nwires != 3)
219 omap_mux_init_signal("usb0_rcv", 0);
220
221 switch (nwires) {
222 case 3:
223 syscon1 = 2;
224 omap2_usb_devconf_set(0, USB_BIDIR);
225 break;
226 case 4:
227 syscon1 = 1;
228 omap2_usb_devconf_set(0, USB_BIDIR);
229 break;
230 case 6:
231 syscon1 = 3;
232 omap_mux_init_signal("usb0_vp", 0);
233 omap_mux_init_signal("usb0_vm", 0);
234 omap2_usb_devconf_set(0, USB_UNIDIR);
235 break;
236 default:
237 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
238 0, nwires);
239 }
240
241 return syscon1 << 16;
242}
243
244static u32 __init omap2_usb1_init(unsigned nwires)
245{
246 u32 syscon1 = 0;
247
248 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
249
250 if (nwires == 0)
251 return 0;
252
253 /* NOTE: board-specific code must set up pin muxing for usb1,
254 * since each signal could come out on either of two balls.
255 */
256
257 switch (nwires) {
258 case 2:
259 /* NOTE: board-specific code must override this setting if
260 * this TLL link is not using DP/DM
261 */
262 syscon1 = 1;
263 omap2_usb_devconf_set(1, USB_BIDIR_TLL);
264 break;
265 case 3:
266 syscon1 = 2;
267 omap2_usb_devconf_set(1, USB_BIDIR);
268 break;
269 case 4:
270 syscon1 = 1;
271 omap2_usb_devconf_set(1, USB_BIDIR);
272 break;
273 case 6:
274 default:
275 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
276 1, nwires);
277 }
278
279 return syscon1 << 20;
280}
281
282static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
283{
284 u32 syscon1 = 0;
285
286 omap2_usb2_disable_5pinbitll();
287 alt_pingroup = 0;
288
289 /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
290 if (alt_pingroup || nwires == 0)
291 return 0;
292
293 omap_mux_init_signal("usb2_dat", 0);
294 omap_mux_init_signal("usb2_se0", 0);
295 if (nwires > 2)
296 omap_mux_init_signal("usb2_txen", 0);
297 if (nwires > 3)
298 omap_mux_init_signal("usb2_rcv", 0);
299
300 switch (nwires) {
301 case 2:
302 /* NOTE: board-specific code must override this setting if
303 * this TLL link is not using DP/DM
304 */
305 syscon1 = 1;
306 omap2_usb_devconf_set(2, USB_BIDIR_TLL);
307 break;
308 case 3:
309 syscon1 = 2;
310 omap2_usb_devconf_set(2, USB_BIDIR);
311 break;
312 case 4:
313 syscon1 = 1;
314 omap2_usb_devconf_set(2, USB_BIDIR);
315 break;
316 case 5:
317 /* NOTE: board-specific code must mux this setting depending
318 * on TLL link using DP/DM. Something must also
319 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
320 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
321 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
322 */
323
324 syscon1 = 3;
325 omap2_usb2_enable_5pinunitll();
326 break;
327 case 6:
328 default:
329 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
330 2, nwires);
331 }
332
333 return syscon1 << 24;
334}
335
336void __init omap2_usbfs_init(struct omap_usb_config *pdata)
337{
338 struct clk *ick;
339
340 if (!cpu_is_omap24xx())
341 return;
342
343 ick = clk_get(NULL, "usb_l4_ick");
344 if (IS_ERR(ick))
345 return;
346
347 clk_enable(ick);
348 pdata->usb0_init = omap2_usb0_init;
349 pdata->usb1_init = omap2_usb1_init;
350 pdata->usb2_init = omap2_usb2_init;
351 udc_device_init(pdata);
352 ohci_device_init(pdata);
353 otg_device_init(pdata);
354 omap_otg_init(pdata);
355 clk_disable(ick);
356 clk_put(ick);
357}
358
359#endif