37 files changed, 18236 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
new file mode 100644
index 00000000000..debc040872f
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -0,0 +1,1970 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <plat/clkdev_omap.h>
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most peripherals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ */
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+        .name           = "func_32k_ck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .clkdm_name     = "wkup_clkdm",
+};
+static struct clk secure_32k_ck = {
+        .name           = "secure_32k_ck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .clkdm_name     = "wkup_clkdm",
+};
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
+        .name           = "osc_ck",
+        .ops            = &clkops_oscck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_osc_clk_recalc,
+};
+/* Without modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
+        .name           = "sys_ck",             /* ~ ref_clk also */
+        .ops            = &clkops_null,
+        .parent         = &osc_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2xxx_sys_clk_recalc,
+};
+static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
+        .name           = "alt_ck",
+        .ops            = &clkops_null,
+        .rate           = 54000000,
+        .clkdm_name     = "wkup_clkdm",
+};
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+/*
+ * Analog domain root source clocks
+ */
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
+ * deal with this
+ */
+static struct dpll_data dpll_dd = {
+        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+        .clk_bypass             = &sys_ck,
+        .clk_ref                = &sys_ck,
+        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
+        .max_multiplier         = 1023,
+        .min_divider            = 1,
+        .max_divider            = 16,
+};
+/*
+ * XXX Cannot add round_rate here yet, as this is still a composite clock,
+ * not just a DPLL
+ */
+static struct clk dpll_ck = {
+        .name           = "dpll_ck",
+        .ops            = &clkops_omap2xxx_dpll_ops,
+        .parent         = &sys_ck,              /* Can be func_32k also */
+        .dpll_data      = &dpll_dd,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_dpllcore_recalc,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+static struct clk apll96_ck = {
+        .name           = "apll96_ck",
+        .ops            = &clkops_apll96,
+        .parent         = &sys_ck,
+        .rate           = 96000000,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+};
+static struct clk apll54_ck = {
+        .name           = "apll54_ck",
+        .ops            = &clkops_apll54,
+        .parent         = &sys_ck,
+        .rate           = 54000000,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+};
+/*
+ * PRCM digital base sources
+ */
+/* func_54m_ck */
+static const struct clksel_rate func_54m_apll54_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel_rate func_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel func_54m_clksel[] = {
+        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
+        { .parent = NULL },
+};
+static struct clk func_54m_ck = {
+        .name           = "func_54m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll54_ck,   /* can also be alt_clk */
+        .clkdm_name     = "wkup_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
+        .clksel         = func_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll_ck,             /* can also be 32k */
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk func_96m_ck = {
+        .name           = "func_96m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll96_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* func_48m_ck */
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL }
+};
+static struct clk func_48m_ck = {
+        .name           = "func_48m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll96_ck,    /* 96M or Alt */
+        .clkdm_name     = "wkup_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+        .clksel         = func_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk func_12m_ck = {
+        .name           = "func_12m_ck",
+        .ops            = &clkops_null,
+        .parent         = &func_48m_ck,
+        .fixed_div      = 4,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+        .name           = "ck_wdt1_osc",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &osc_ck,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL }
+};
+static struct clk sys_clkout_src = {
+        .name           = "sys_clkout_src",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static const struct clksel_rate common_clkout_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel sys_clkout_clksel[] = {
+        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+static struct clk sys_clkout = {
+        .name           = "sys_clkout",
+        .ops            = &clkops_null,
+        .parent         = &sys_clkout_src,
+        .clkdm_name     = "wkup_clkdm",
+        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
+        .clksel         = sys_clkout_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+        .name           = "sys_clkout2_src",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .ops            = &clkops_null,
+        .parent         = &sys_clkout2_src,
+        .clkdm_name     = "wkup_clkdm",
+        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk emul_ck = {
+        .name           = "emul_ck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * MPU clock domain
+ *      Clocks:
+ *              MPU_FCLK, MPU_ICLK
+ *              INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+static const struct clksel mpu_clksel[] = {
+        { .parent = &core_ck, .rates = mpu_core_rates },
+        { .parent = NULL }
+};
+static struct clk mpu_ck = {    /* Control cpu */
+        .name           = "mpu_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .clkdm_name     = "mpu_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
+        .clksel         = mpu_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * DSP (2420-UMA+IVA1) clock domain
+ * Clocks:
+ *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL }
+};
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "dsp_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
+        { .parent = NULL }
+};
+static struct clk dsp_ick = {
+        .name           = "dsp_ick",     /* apparently ipi and isp */
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
+ * the C54x, but which is contained in the DSP powerdomain.  Does not
+ * exist on later OMAPs.
+ */
+static struct clk iva1_ifck = {
+        .name           = "iva1_ifck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "iva1_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+        .name           = "iva1_mpu_int_ifck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &iva1_ifck,
+        .clkdm_name     = "iva1_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ *      CAM, HS-USB.
+ * F-CLOCK
+ *      SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel core_l3_clksel[] = {
+        { .parent = &core_ck, .rates = core_l3_core_rates },
+        { .parent = NULL }
+};
+static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
+        .name           = "core_l3_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
+        .clksel         = core_l3_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
+static struct clk usb_l4_ick = {        /* FS-USB interface clock */
+        .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
+        .clksel         = usb_l4_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks.   Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel l4_clksel[] = {
+        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+        { .parent = NULL }
+};
+static struct clk l4_ck = {             /* used both as an ick and fck */
+        .name           = "l4_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
+        .clksel         = l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL }
+};
+static struct clk ssi_ssr_sst_fck = {
+        .name           = "ssi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_sst_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * GFX clock domain
+ *      Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+static struct clk gfx_3d_fck = {
+        .name           = "gfx_3d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk gfx_2d_fck = {
+        .name           = "gfx_2d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* This interface clock does not have a CM_AUTOIDLE bit */
+static struct clk gfx_ick = {
+        .name           = "gfx_ick",            /* From l3 */
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ck,       /* really both l3 and l4 */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss1_fck = {
+        .name           = "dss1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_ck,             /* Core or sys */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
+        .clksel         = dss1_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL }
+};
+static struct clk dss2_fck = {          /* Alt clk used in power management */
+        .name           = "dss2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
+        .clksel         = dss2_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk dss_54m_fck = {       /* Alt clk used in power management */
+        .name           = "dss_54m_fck",        /* 54m tv clk */
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,      .rates = gpt_sys_rates },
+        { .parent = &alt_ck,      .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &secure_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcspi1_ick = {
+        .name           = "mcspi1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi1_fck = {
+        .name           = "mcspi1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_ick = {
+        .name           = "mcspi2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_fck = {
+        .name           = "mcspi2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpios_ick = {
+        .name           = "gpios_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpios_fck = {
+        .name           = "gpios_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mpu_wdt_ick = {
+        .name           = "mpu_wdt_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mpu_wdt_fck = {
+        .name           = "mpu_wdt_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sync_32k_ick = {
+        .name           = "sync_32k_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk cam_ick = {
+        .name           = "cam_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
+ * split into two separate clocks, since the parent clocks are different
+ * and the clockdomains are also different.
+ */
+static struct clk cam_fck = {
+        .name           = "cam_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt4_ick = {
+        .name           = "wdt4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt4_fck = {
+        .name           = "wdt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmc_ick = {
+        .name           = "mmc_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmc_fck = {
+        .name           = "mmc_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk fac_fck = {
+        .name           = "fac_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk eac_ick = {
+        .name           = "eac_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk eac_fck = {
+        .name           = "eac_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c2_ick = {
+        .name           = "i2c2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c2_fck = {
+        .name           = "i2c2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c1_ick = {
+        .name           = "i2c1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c1_fck = {
+        .name           = "i2c1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sdma_fck = {
+        .name           = "sdma_fck",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdma_ick = {
+        .name           = "sdma_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk vlynq_ick = {
+        .name           = "vlynq_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_242X },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 3, .val = 3, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 9, .val = 9, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 18, .val = 18, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel vlynq_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+        { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
+        { .parent = NULL }
+};
+static struct clk vlynq_fck = {
+        .name           = "vlynq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
+        .clksel         = vlynq_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk des_ick = {
+        .name           = "des_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sha_ick = {
+        .name           = "sha_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk aes_ick = {
+        .name           = "aes_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_fck = {
+        .name           = "usb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+        .name           = "virt_prcm_set",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
+        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+/*
+ * clkdev integration
+ */
+static struct omap_clk omap2420_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
+        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
+        /* DSS domain clocks */
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
+        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
+        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
+        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
+        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
+};
+/*
+ * init code
+ */
+int __init omap2420_clk_init(void)
+{
+        const struct prcm_config *prcm;
+        struct omap_clk *c;
+        u32 clkrate;
+        prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+        cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+        cpu_mask = RATE_IN_242X;
+        rate_table = omap2420_rate_table;
+        clk_init(&omap2_clk_functions);
+        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+             c++)
+                clk_preinit(c->lk.clk);
+        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+        propagate_rate(&osc_ck);
+        sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
+        propagate_rate(&sys_ck);
+        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+             c++) {
+                clkdev_add(&c->lk);
+                clk_register(c->lk.clk);
+                omap2_init_clk_clkdm(c->lk.clk);
+        }
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+        recalculate_root_clocks();
+        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+        dclk = clk_get(NULL, "dpll_ck");
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
new file mode 100644
index 00000000000..96a942e42db
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -0,0 +1,2070 @@
+/*
+ * OMAP2430 clock data
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <plat/clkdev_omap.h>
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
+/*
+ * 2430 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most peripherals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ */
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+        .name           = "func_32k_ck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .clkdm_name     = "wkup_clkdm",
+};
+static struct clk secure_32k_ck = {
+        .name           = "secure_32k_ck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .clkdm_name     = "wkup_clkdm",
+};
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
+        .name           = "osc_ck",
+        .ops            = &clkops_oscck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_osc_clk_recalc,
+};
+/* Without modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
+        .name           = "sys_ck",             /* ~ ref_clk also */
+        .ops            = &clkops_null,
+        .parent         = &osc_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2xxx_sys_clk_recalc,
+};
+static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
+        .name           = "alt_ck",
+        .ops            = &clkops_null,
+        .rate           = 54000000,
+        .clkdm_name     = "wkup_clkdm",
+};
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+/*
+ * Analog domain root source clocks
+ */
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
+ * deal with this
+ */
+static struct dpll_data dpll_dd = {
+        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+        .clk_bypass             = &sys_ck,
+        .clk_ref                = &sys_ck,
+        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
+        .max_multiplier         = 1023,
+        .min_divider            = 1,
+        .max_divider            = 16,
+};
+/*
+ * XXX Cannot add round_rate here yet, as this is still a composite clock,
+ * not just a DPLL
+ */
+static struct clk dpll_ck = {
+        .name           = "dpll_ck",
+        .ops            = &clkops_omap2xxx_dpll_ops,
+        .parent         = &sys_ck,              /* Can be func_32k also */
+        .dpll_data      = &dpll_dd,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_dpllcore_recalc,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+static struct clk apll96_ck = {
+        .name           = "apll96_ck",
+        .ops            = &clkops_apll96,
+        .parent         = &sys_ck,
+        .rate           = 96000000,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+};
+static struct clk apll54_ck = {
+        .name           = "apll54_ck",
+        .ops            = &clkops_apll54,
+        .parent         = &sys_ck,
+        .rate           = 54000000,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+};
+/*
+ * PRCM digital base sources
+ */
+/* func_54m_ck */
+static const struct clksel_rate func_54m_apll54_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel_rate func_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel func_54m_clksel[] = {
+        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
+        { .parent = NULL },
+};
+static struct clk func_54m_ck = {
+        .name           = "func_54m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll54_ck,   /* can also be alt_clk */
+        .clkdm_name     = "wkup_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
+        .clksel         = func_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll_ck,             /* can also be 32k */
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* func_96m_ck */
+static const struct clksel_rate func_96m_apll96_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel_rate func_96m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
+static const struct clksel func_96m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
+        { .parent = &alt_ck,    .rates = func_96m_alt_rates },
+        { .parent = NULL }
+};
+static struct clk func_96m_ck = {
+        .name           = "func_96m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll96_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2430_96M_SOURCE_MASK,
+        .clksel         = func_96m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* func_48m_ck */
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL }
+};
+static struct clk func_48m_ck = {
+        .name           = "func_48m_ck",
+        .ops            = &clkops_null,
+        .parent         = &apll96_ck,    /* 96M or Alt */
+        .clkdm_name     = "wkup_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+        .clksel         = func_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk func_12m_ck = {
+        .name           = "func_12m_ck",
+        .ops            = &clkops_null,
+        .parent         = &func_48m_ck,
+        .fixed_div      = 4,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+        .name           = "ck_wdt1_osc",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &osc_ck,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL }
+};
+static struct clk sys_clkout_src = {
+        .name           = "sys_clkout_src",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static const struct clksel_rate common_clkout_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel sys_clkout_clksel[] = {
+        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+static struct clk sys_clkout = {
+        .name           = "sys_clkout",
+        .ops            = &clkops_null,
+        .parent         = &sys_clkout_src,
+        .clkdm_name     = "wkup_clkdm",
+        .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
+        .clksel         = sys_clkout_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk emul_ck = {
+        .name           = "emul_ck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * MPU clock domain
+ *      Clocks:
+ *              MPU_FCLK, MPU_ICLK
+ *              INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel mpu_clksel[] = {
+        { .parent = &core_ck, .rates = mpu_core_rates },
+        { .parent = NULL }
+};
+static struct clk mpu_ck = {    /* Control cpu */
+        .name           = "mpu_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .clkdm_name     = "mpu_clkdm",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
+        .clksel         = mpu_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * DSP (2430-IVA2.1) clock domain
+ * Clocks:
+ *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL }
+};
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "dsp_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
+        { .parent = NULL }
+};
+/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+static struct clk iva2_1_ick = {
+        .name           = "iva2_1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ *      CAM, HS-USB.
+ * F-CLOCK
+ *      SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel core_l3_clksel[] = {
+        { .parent = &core_ck, .rates = core_l3_core_rates },
+        { .parent = NULL }
+};
+static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
+        .name           = "core_l3_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
+        .clksel         = core_l3_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
+static struct clk usb_l4_ick = {        /* FS-USB interface clock */
+        .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
+        .clksel         = usb_l4_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks.   Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel l4_clksel[] = {
+        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+        { .parent = NULL }
+};
+static struct clk l4_ck = {             /* used both as an ick and fck */
+        .name           = "l4_ck",
+        .ops            = &clkops_null,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
+        .clksel         = l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL }
+};
+static struct clk ssi_ssr_sst_fck = {
+        .name           = "ssi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_sst_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * GFX clock domain
+ *      Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+static struct clk gfx_3d_fck = {
+        .name           = "gfx_3d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk gfx_2d_fck = {
+        .name           = "gfx_2d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* This interface clock does not have a CM_AUTOIDLE bit */
+static struct clk gfx_ick = {
+        .name           = "gfx_ick",            /* From l3 */
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "gfx_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * Modem clock domain (2430)
+ *      CLOCKS:
+ *              MDM_OSC_CLK
+ *              MDM_ICLK
+ * These clocks are usable in chassis mode only.
+ */
+static const struct clksel_rate mdm_ick_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X },
+        { .div = 6, .val = 6, .flags = RATE_IN_243X },
+        { .div = 9, .val = 9, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+static const struct clksel mdm_ick_clksel[] = {
+        { .parent = &core_ck, .rates = mdm_ick_core_rates },
+        { .parent = NULL }
+};
+static struct clk mdm_ick = {           /* used both as a ick and fck */
+        .name           = "mdm_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_ck,
+        .clkdm_name     = "mdm_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
+        .clksel         = mdm_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mdm_osc_ck = {
+        .name           = "mdm_osc_ck",
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
+        .parent         = &osc_ck,
+        .clkdm_name     = "mdm_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ck,       /* really both l3 and l4 */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss1_fck = {
+        .name           = "dss1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_ck,             /* Core or sys */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
+        .clksel         = dss1_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL }
+};
+static struct clk dss2_fck = {          /* Alt clk used in power management */
+        .name           = "dss2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
+        .clksel         = dss2_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk dss_54m_fck = {       /* Alt clk used in power management */
+        .name           = "dss_54m_fck",        /* 54m tv clk */
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_54m_ck,
+        .clkdm_name     = "dss_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,      .rates = gpt_sys_rates },
+        { .parent = &alt_ck,      .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &secure_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcspi1_ick = {
+        .name           = "mcspi1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi1_fck = {
+        .name           = "mcspi1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_ick = {
+        .name           = "mcspi2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_fck = {
+        .name           = "mcspi2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi3_ick = {
+        .name           = "mcspi3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi3_fck = {
+        .name           = "mcspi3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpios_ick = {
+        .name           = "gpios_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpios_fck = {
+        .name           = "gpios_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mpu_wdt_ick = {
+        .name           = "mpu_wdt_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mpu_wdt_fck = {
+        .name           = "mpu_wdt_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sync_32k_ick = {
+        .name           = "sync_32k_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .flags          = ENABLE_ON_INIT,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .flags          = ENABLE_ON_INIT,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk cam_ick = {
+        .name           = "cam_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
+ * split into two separate clocks, since the parent clocks are different
+ * and the clockdomains are also different.
+ */
+static struct clk cam_fck = {
+        .name           = "cam_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt4_ick = {
+        .name           = "wdt4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt4_fck = {
+        .name           = "wdt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk fac_fck = {
+        .name           = "fac_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_12m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * XXX This is marked as a 2420-only define, but it claims to be present
+ * on 2430 also.  Double-check.
+ */
+static struct clk i2c2_ick = {
+        .name           = "i2c2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2chs2_fck = {
+        .name           = "i2chs2_fck",
+        .ops            = &clkops_omap2430_i2chs_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * XXX This is marked as a 2420-only define, but it claims to be present
+ * on 2430 also.  Double-check.
+ */
+static struct clk i2c1_ick = {
+        .name           = "i2c1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2chs1_fck = {
+        .name           = "i2chs1_fck",
+        .ops            = &clkops_omap2430_i2chs_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sdma_fck = {
+        .name           = "sdma_fck",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdma_ick = {
+        .name           = "sdma_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk des_ick = {
+        .name           = "des_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sha_ick = {
+        .name           = "sha_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk aes_ick = {
+        .name           = "aes_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_fck = {
+        .name           = "usb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_48m_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usbhs_ick = {
+        .name           = "usbhs_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs1_ick = {
+        .name           = "mmchs1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs1_fck = {
+        .name           = "mmchs1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs2_ick = {
+        .name           = "mmchs2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs2_fck = {
+        .name           = "mmchs2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mdm_intc_ick = {
+        .name           = "mdm_intc_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchsdb1_fck = {
+        .name           = "mmchsdb1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchsdb2_fck = {
+        .name           = "mmchsdb2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &func_32k_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+        .name           = "virt_prcm_set",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
+        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+/*
+ * clkdev integration
+ */
+static struct omap_clk omap2430_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
+        /* Modem domain clocks */
+        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        /* DSS domain clocks */
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
+        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+};
+/*
+ * init code
+ */
+int __init omap2430_clk_init(void)
+{
+        const struct prcm_config *prcm;
+        struct omap_clk *c;
+        u32 clkrate;
+        prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+        cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+        cpu_mask = RATE_IN_243X;
+        rate_table = omap2430_rate_table;
+        clk_init(&omap2_clk_functions);
+        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+             c++)
+                clk_preinit(c->lk.clk);
+        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+        propagate_rate(&osc_ck);
+        sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
+        propagate_rate(&sys_ck);
+        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+             c++) {
+                clkdev_add(&c->lk);
+                clk_register(c->lk.clk);
+                omap2_init_clk_clkdm(c->lk.clk);
+        }
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+        recalculate_root_clocks();
+        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+        dclk = clk_get(NULL, "dpll_ck");
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
new file mode 100644
index 00000000000..b9b84468314
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -0,0 +1,3578 @@
+/*
+ * OMAP3 clock data
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <plat/clkdev_omap.h>
+#include "clock.h"
+#include "clock3xxx.h"
+#include "clock34xx.h"
+#include "clock36xx.h"
+#include "clock3517.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-34xx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm-regbits-34xx.h"
+#include "control.h"
+/*
+ * clocks
+ */
+#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2047
+#define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
+#define OMAP3_MAX_DPLL_DIV              128
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+/* Forward declarations for DPLL bypass clocks */
+static struct clk dpll1_fck;
+static struct clk dpll2_fck;
+/* PRM CLOCKS */
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+};
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+};
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+};
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+};
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+};
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+};
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+};
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 0 }
+};
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .ops            = &clkops_null,
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .ops            = &clkops_null,
+};
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+/* PRM EXTERNAL CLOCK OUTPUT */
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* DPLLS */
+/* CM CLOCKS */
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate dpll4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
+        { .div = 17, .val = 17, .flags = RATE_IN_36XX },
+        { .div = 18, .val = 18, .flags = RATE_IN_36XX },
+        { .div = 19, .val = 19, .flags = RATE_IN_36XX },
+        { .div = 20, .val = 20, .flags = RATE_IN_36XX },
+        { .div = 21, .val = 21, .flags = RATE_IN_36XX },
+        { .div = 22, .val = 22, .flags = RATE_IN_36XX },
+        { .div = 23, .val = 23, .flags = RATE_IN_36XX },
+        { .div = 24, .val = 24, .flags = RATE_IN_36XX },
+        { .div = 25, .val = 25, .flags = RATE_IN_36XX },
+        { .div = 26, .val = 26, .flags = RATE_IN_36XX },
+        { .div = 27, .val = 27, .flags = RATE_IN_36XX },
+        { .div = 28, .val = 28, .flags = RATE_IN_36XX },
+        { .div = 29, .val = 29, .flags = RATE_IN_36XX },
+        { .div = 30, .val = 30, .flags = RATE_IN_36XX },
+        { .div = 31, .val = 31, .flags = RATE_IN_36XX },
+        { .div = 32, .val = 32, .flags = RATE_IN_36XX },
+        { .div = 0 }
+};
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll1_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_ck,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+static struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll2_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
+static struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .ops            = &clkops_omap3_core_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 0 },
+};
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+/* DPLL3 output M2 - primary control point for CORE speed */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap3_core_dpll_m2_set_rate,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m3x2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static struct dpll_data dpll4_dd;
+static struct dpll_data dpll4_dd_34xx __initdata = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct dpll_data dpll4_dd_3630 __initdata = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
+        .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
+        .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .flags          = DPLL_J_TYPE
+};
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_dpll4_set_rate,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = dpll4_rates },
+        { .parent = NULL }
+};
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3630_DIV_96M_MASK,
+        .clksel         = dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
+/* Adding 192MHz Clock node needed by SGX */
+static struct clk omap_192m_alwon_fck = {
+        .name           = "omap_192m_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_36XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_36XX },
+        { .div = 0 }
+};
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
+        { .parent = NULL }
+};
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate omap_96m_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omap_96m_alwon_fck_3630 = {
+        .name           = "omap_96m_alwon_fck",
+        .parent         = &omap_192m_alwon_fck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
+        .clksel         = omap_96m_alwon_fck_clksel
+};
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel omap_96m_fck_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
+        { .parent = NULL }
+};
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
+        .clksel         = omap_96m_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
+        .clksel         = omap_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
+        .clksel         = omap_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/* This virtual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m6_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m6x2_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* CM EXTERNAL CLOCK OUTPUTS */
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
+        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .clkdm_name     = "core_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+/* CM OUTPUT CLOCKS */
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+/* DPLL power domain clock controls */
+static const struct clksel_rate div4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel div4_core_clksel[] = {
+        { .parent = &core_ck, .rates = div4_rates },
+        { .parent = NULL }
+};
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2m2_ck,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* XXX What about neon_clkdm ? */
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll2_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+        .clkdm_name     = "iva2_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* Common interface clocks */
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* GFX power domain */
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+/*
+ * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
+ * This interface clock does not have a CM_AUTOIDLE bit
+ */
+static struct clk gfx_l3_ck = {
+        .name           = "gfx_l3_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* SGX power domain - 3430ES2 only */
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 2, .val = 5, .flags = RATE_IN_36XX },
+        { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate sgx_192m_rates[] = {
+        { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
+        { .div = 0 },
+};
+static const struct clksel_rate sgx_corex2_rates[] = {
+        { .div = 3, .val = 6, .flags = RATE_IN_36XX },
+        { .div = 5, .val = 7, .flags = RATE_IN_36XX },
+        { .div = 0 },
+};
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
+        { .parent = &corex2_fck, .rates = sgx_corex2_rates },
+        { .parent = NULL }
+};
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate
+};
+/* This interface clock does not have a CM_AUTOIDLE bit */
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* CORE power domain */
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk modem_fck = {
+        .name           = "modem_fck",
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk sad2d_ick = {
+        .name           = "sad2d_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mad2d_ick = {
+        .name           = "mad2d_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* CORE 96M FCLK-derived clocks */
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs3_fck = {
+        .name           = "mmchs3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs2_fck = {
+        .name           = "mmchs2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs1_fck = {
+        .name           = "mmchs1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c3_fck = {
+        .name           = "i2c3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c2_fck = {
+        .name           = "i2c2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c1_fck = {
+        .name           = "i2c1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* CORE_48M_FCK-derived clocks */
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi4_fck = {
+        .name           = "mcspi4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
+};
+static struct clk mcspi3_fck = {
+        .name           = "mcspi3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
+};
+static struct clk mcspi2_fck = {
+        .name           = "mcspi2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
+};
+static struct clk mcspi1_fck = {
+        .name           = "mcspi1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
+};
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* CORE_12M_FCK based clocks */
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* DPLL3-derived clock */
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+static struct clk ssi_ssr_fck_3430es1 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk ssi_sst_fck_3430es1 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/* CORE_L3_ICK based clocks */
+/*
+ * XXX must add clk_enable/clk_disable for these if standard code won't
+ * handle it
+ */
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk hsotgusb_ick_3430es1 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* This interface clock does not have a CM_AUTOIDLE bit */
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_l3_ick,
+        .flags          = ENABLE_ON_INIT, /* huh? */
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* SECURITY_L3_ICK based clocks */
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .recalc         = &followparent_recalc,
+};
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* CORE_L4_ICK based clocks */
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs3_ick = {
+        .name           = "mmchs3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs2_ick = {
+        .name           = "mmchs2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmchs1_ick = {
+        .name           = "mmchs1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi4_ick = {
+        .name           = "mcspi4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi3_ick = {
+        .name           = "mcspi3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_ick = {
+        .name           = "mcspi2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi1_ick = {
+        .name           = "mcspi1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c3_ick = {
+        .name           = "i2c3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c2_ick = {
+        .name           = "i2c2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c1_ick = {
+        .name           = "i2c1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+/* SSI_L4_ICK based clocks */
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk ssi_ick_3430es1 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_iclk_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* SECURITY_L4_ICK2 based clocks */
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .recalc         = &followparent_recalc,
+};
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/* DSS */
+static struct clk dss1_alwon_fck_3430es1 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_ick_3430es1 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* CAM */
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m5x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk cam_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "cam_ick",
+        .ops            = &clkops_omap2_iclk_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk csi2_96m_fck = {
+        .name           = "csi2_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* USBHOST - 3430ES2 only */
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk usbhost_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "usbhost_ick",
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* WKUP */
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
+        { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio1_dbck = {
+        .name           = "gpio1_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* XXX This clock no longer exists in 3430 TRM rev F */
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* PER clock domain */
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart4_fck = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio6_dbck = {
+        .name           = "gpio6_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_dbck = {
+        .name           = "gpio5_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio4_dbck = {
+        .name           = "gpio4_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio3_dbck = {
+        .name           = "gpio3_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio2_dbck = {
+        .name           = "gpio2_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart4_ick = {
+        .name           = "uart4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* EMU clocks */
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+/* SR clocks */
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* SECURE_32K_FCK clocks */
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+/* Clocks for AM35XX */
+static struct clk ipss_ick = {
+        .name           = "ipss_ick",
+        .ops            = &clkops_am35xx_ipss_wait,
+        .parent         = &core_l3_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = AM35XX_EN_IPSS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk emac_ick = {
+        .name           = "emac_ick",
+        .ops            = &clkops_am35xx_ipss_module_wait,
+        .parent         = &ipss_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk rmii_ck = {
+        .name           = "rmii_ck",
+        .ops            = &clkops_null,
+        .rate           = 50000000,
+};
+static struct clk emac_fck = {
+        .name           = "emac_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &rmii_ck,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hsotgusb_ick_am35xx = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_am35xx_ipss_module_wait,
+        .parent         = &ipss_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hsotgusb_fck_am35xx = {
+        .name           = "hsotgusb_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk hecc_ck = {
+        .name           = "hecc_ck",
+        .ops            = &clkops_am35xx_ipss_module_wait,
+        .parent         = &sys_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk vpfe_ick = {
+        .name           = "vpfe_ick",
+        .ops            = &clkops_am35xx_ipss_module_wait,
+        .parent         = &ipss_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk pclk_ck = {
+        .name           = "pclk_ck",
+        .ops            = &clkops_null,
+        .rate           = 27000000,
+};
+static struct clk vpfe_fck = {
+        .name           = "vpfe_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &pclk_ck,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+/*
+ * The UART1/2 functional clock acts as the functional
+ * clock for UART4. No separate fclk control available.
+ */
+static struct clk uart4_ick_am35xx = {
+        .name           = "uart4_ick",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = AM35XX_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .ops            = &clkops_null,
+};
+/*
+ * clkdev
+ */
+/* XXX At some point we should rename this file to clock3xxx_data.c */
+static struct omap_clk omap3xxx_clks[] = {
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
+        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
+        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
+        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
+        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
+        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
+        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
+        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
+        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
+        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
+        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs-omap.0",     "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs-omap.0",     "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
+        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
+        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
+        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
+        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK("davinci_emac",     "emac_clk",     &emac_ick,      CK_AM35XX),
+        CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
+        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
+        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
+        CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
+};
+int __init omap3xxx_clk_init(void)
+{
+        struct omap_clk *c;
+        u32 cpu_clkflg = 0;
+        if (cpu_is_omap3517()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3517;
+        } else if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3630()) {
+                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+                cpu_clkflg = CK_36XX;
+        } else if (cpu_is_ti816x()) {
+                cpu_mask = RATE_IN_TI816X;
+                cpu_clkflg = CK_TI816X;
+        } else if (cpu_is_omap34xx()) {
+                if (omap_rev() == OMAP3430_REV_ES1_0) {
+                        cpu_mask = RATE_IN_3430ES1;
+                        cpu_clkflg = CK_3430ES1;
+                } else {
+                        /*
+                         * Assume that anything that we haven't matched yet
+                         * has 3430ES2-type clocks.
+                         */
+                        cpu_mask = RATE_IN_3430ES2PLUS;
+                        cpu_clkflg = CK_3430ES2PLUS;
+                }
+        } else {
+                WARN(1, "clock: could not identify OMAP3 variant\n");
+        }
+        if (omap3_has_192mhz_clk())
+                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
+        if (cpu_is_omap3630()) {
+                /*
+                 * XXX This type of dynamic rewriting of the clock tree is
+                 * deprecated and should be revised soon.
+                 *
+                 * For 3630: override clkops_omap2_dflt_wait for the
+                 * clocks affected from PWRDN reset Limitation
+                 */
+                dpll3_m3x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+                dpll4_m2x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+                dpll4_m3x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+                dpll4_m4x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+                dpll4_m5x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+                dpll4_m6x2_ck.ops =
+                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+        }
+        /*
+         * XXX This type of dynamic rewriting of the clock tree is
+         * deprecated and should be revised soon.
+         */
+        if (cpu_is_omap3630())
+                dpll4_dd = dpll4_dd_3630;
+        else
+                dpll4_dd = dpll4_dd_34xx;
+        clk_init(&omap2_clk_functions);
+        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
+             c++)
+                clk_preinit(c->lk.clk);
+        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
+             c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+        recalculate_root_clocks();
+        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+        /*
+         * Lock DPLL5 -- here only until other device init code can
+         * handle this
+         */
+        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+                omap3_clk_lock_dpll5();
+        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
+        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
+        arm_fck_p = clk_get(NULL, "arm_fck");
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
new file mode 100644
index 00000000000..c0b6fbda340
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -0,0 +1,3416 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <plat/clkdev_omap.h>
+#include "clock.h"
+#include "clock44xx.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
+#include "scrm44xx.h"
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
+/* Root clocks */
+static struct clk extalt_clkin_ck = {
+        .name           = "extalt_clkin_ck",
+        .rate           = 59000000,
+        .ops            = &clkops_null,
+};
+static struct clk pad_clks_ck = {
+        .name           = "pad_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
+};
+static struct clk pad_slimbus_core_clks_ck = {
+        .name           = "pad_slimbus_core_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+};
+static struct clk secure_32k_clk_src_ck = {
+        .name           = "secure_32k_clk_src_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+};
+static struct clk slimbus_clk = {
+        .name           = "slimbus_clk",
+        .rate           = 12000000,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+};
+static struct clk sys_32k_ck = {
+        .name           = "sys_32k_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+};
+static struct clk virt_12000000_ck = {
+        .name           = "virt_12000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+static struct clk virt_13000000_ck = {
+        .name           = "virt_13000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+};
+static struct clk virt_16800000_ck = {
+        .name           = "virt_16800000_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+};
+static struct clk virt_19200000_ck = {
+        .name           = "virt_19200000_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+};
+static struct clk virt_26000000_ck = {
+        .name           = "virt_26000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+};
+static struct clk virt_27000000_ck = {
+        .name           = "virt_27000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 27000000,
+};
+static struct clk virt_38400000_ck = {
+        .name           = "virt_38400000_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+};
+static const struct clksel_rate div_1_0_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_1_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_2_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_3_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_4_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_5_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_6_rates[] = {
+        { .div = 1, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel_rate div_1_7_rates[] = {
+        { .div = 1, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel sys_clkin_sel[] = {
+        { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
+        { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
+        { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
+        { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
+        { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
+        { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
+        { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
+        { .parent = NULL },
+};
+static struct clk sys_clkin_ck = {
+        .name           = "sys_clkin_ck",
+        .rate           = 38400000,
+        .clksel         = sys_clkin_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk tie_low_clock_ck = {
+        .name           = "tie_low_clock_ck",
+        .rate           = 0,
+        .ops            = &clkops_null,
+};
+static struct clk utmi_phy_clkout_ck = {
+        .name           = "utmi_phy_clkout_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+};
+static struct clk xclk60mhsp1_ck = {
+        .name           = "xclk60mhsp1_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+};
+static struct clk xclk60mhsp2_ck = {
+        .name           = "xclk60mhsp2_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+};
+static struct clk xclk60motg_ck = {
+        .name           = "xclk60motg_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+};
+/* Module clocks and DPLL outputs */
+static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk abe_dpll_bypass_clk_mux_ck = {
+        .name           = "abe_dpll_bypass_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+static struct clk abe_dpll_refclk_mux_ck = {
+        .name           = "abe_dpll_refclk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
+        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
+        .clk_ref        = &abe_dpll_refclk_mux_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_abe_ck = {
+        .name           = "dpll_abe_ck",
+        .parent         = &abe_dpll_refclk_mux_ck,
+        .dpll_data      = &dpll_abe_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static struct clk dpll_abe_x2_ck = {
+        .name           = "dpll_abe_x2_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel dpll_abe_m2x2_div[] = {
+        { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_abe_m2x2_ck = {
+        .name           = "dpll_abe_m2x2_ck",
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk abe_24m_fclk = {
+        .name           = "abe_24m_fclk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel_rate div3_1to4_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel abe_clk_div[] = {
+        { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+static struct clk abe_clk = {
+        .name           = "abe_clk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .clksel         = abe_clk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel aess_fclk_div[] = {
+        { .parent = &abe_clk, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk aess_fclk = {
+        .name           = "aess_fclk",
+        .parent         = &abe_clk,
+        .clksel         = aess_fclk_div,
+        .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_abe_m3x2_ck = {
+        .name           = "dpll_abe_m3x2_ck",
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel core_hsd_byp_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk core_hsd_byp_clk_mux_ck = {
+        .name           = "core_hsd_byp_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = core_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_core_ck = {
+        .name           = "dpll_core_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_core_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_core_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+};
+static struct clk dpll_core_x2_ck = {
+        .name           = "dpll_core_x2_ck",
+        .parent         = &dpll_core_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel dpll_core_m6x2_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_core_m6x2_ck = {
+        .name           = "dpll_core_m6x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel dbgclk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk dbgclk_mux_ck = {
+        .name           = "dbgclk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel dpll_core_m2_div[] = {
+        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_core_m2_ck = {
+        .name           = "dpll_core_m2_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk ddrphy_ck = {
+        .name           = "ddrphy_ck",
+        .parent         = &dpll_core_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static struct clk dpll_core_m5x2_ck = {
+        .name           = "dpll_core_m5x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel div_core_div[] = {
+        { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk div_core_ck = {
+        .name           = "div_core_ck",
+        .parent         = &dpll_core_m5x2_ck,
+        .clksel         = div_core_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel_rate div4_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel div_iva_hs_clk_div[] = {
+        { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
+        { .parent = NULL },
+};
+static struct clk div_iva_hs_clk = {
+        .name           = "div_iva_hs_clk",
+        .parent         = &dpll_core_m5x2_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk div_mpu_hs_clk = {
+        .name           = "div_mpu_hs_clk",
+        .parent         = &dpll_core_m5x2_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_core_m4x2_ck = {
+        .name           = "dpll_core_m4x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dll_clk_div_ck = {
+        .name           = "dll_clk_div_ck",
+        .parent         = &dpll_core_m4x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel dpll_abe_m2_div[] = {
+        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_abe_m2_ck = {
+        .name           = "dpll_abe_m2_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel         = dpll_abe_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_core_m3x2_ck = {
+        .name           = "dpll_core_m3x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+};
+static struct clk dpll_core_m7x2_ck = {
+        .name           = "dpll_core_m7x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk iva_hsd_byp_clk_mux_ck = {
+        .name           = "iva_hsd_byp_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = iva_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_iva_ck = {
+        .name           = "dpll_iva_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_iva_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static struct clk dpll_iva_x2_ck = {
+        .name           = "dpll_iva_x2_ck",
+        .parent         = &dpll_iva_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel dpll_iva_m4x2_div[] = {
+        { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_iva_m4x2_ck = {
+        .name           = "dpll_iva_m4x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_iva_m5x2_ck = {
+        .name           = "dpll_iva_m5x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &div_mpu_hs_clk,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_mpu_ck = {
+        .name           = "dpll_mpu_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_mpu_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static const struct clksel dpll_mpu_m2_div[] = {
+        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_mpu_m2_ck = {
+        .name           = "dpll_mpu_m2_ck",
+        .parent         = &dpll_mpu_ck,
+        .clksel         = dpll_mpu_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk per_hs_clk_div_ck = {
+        .name           = "per_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel per_hsd_byp_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk per_hsd_byp_clk_mux_ck = {
+        .name           = "per_hsd_byp_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = per_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_per_ck = {
+        .name           = "dpll_per_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_per_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static const struct clksel dpll_per_m2_div[] = {
+        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_per_m2_ck = {
+        .name           = "dpll_per_m2_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_per_x2_ck = {
+        .name           = "dpll_per_x2_ck",
+        .parent         = &dpll_per_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+static const struct clksel dpll_per_m2x2_div[] = {
+        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_per_m2x2_ck = {
+        .name           = "dpll_per_m2x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_per_m3x2_ck = {
+        .name           = "dpll_per_m3x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
+};
+static struct clk dpll_per_m4x2_ck = {
+        .name           = "dpll_per_m4x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_per_m5x2_ck = {
+        .name           = "dpll_per_m5x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_per_m6x2_ck = {
+        .name           = "dpll_per_m6x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk dpll_per_m7x2_ck = {
+        .name           = "dpll_per_m7x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk usb_hs_clk_div_ck = {
+        .name           = "usb_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 3,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
+        .clk_bypass     = &usb_hs_clk_div_ck,
+        .flags          = DPLL_J_TYPE,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
+        .max_multiplier = 4095,
+        .max_divider    = 256,
+        .min_divider    = 1,
+};
+static struct clk dpll_usb_ck = {
+        .name           = "dpll_usb_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_usb_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static struct clk dpll_usb_clkdcoldo_ck = {
+        .name           = "dpll_usb_clkdcoldo_ck",
+        .parent         = &dpll_usb_ck,
+        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel dpll_usb_m2_div[] = {
+        { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+static struct clk dpll_usb_m2_ck = {
+        .name           = "dpll_usb_m2_ck",
+        .parent         = &dpll_usb_ck,
+        .clksel         = dpll_usb_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel ducati_clk_mux_sel[] = {
+        { .parent = &div_core_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk ducati_clk_mux_ck = {
+        .name           = "ducati_clk_mux_ck",
+        .parent         = &div_core_ck,
+        .clksel         = ducati_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk func_12m_fclk = {
+        .name           = "func_12m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static struct clk func_24m_clk = {
+        .name           = "func_24m_clk",
+        .parent         = &dpll_per_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static struct clk func_24mc_fclk = {
+        .name           = "func_24mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel_rate div2_4to8_rates[] = {
+        { .div = 4, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel func_48m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
+        { .parent = NULL },
+};
+static struct clk func_48m_fclk = {
+        .name           = "func_48m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_48m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk func_48mc_fclk = {
+        .name           = "func_48mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel_rate div2_2to4_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel func_64m_fclk_div[] = {
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+static struct clk func_64m_fclk = {
+        .name           = "func_64m_fclk",
+        .parent         = &dpll_per_m4x2_ck,
+        .clksel         = func_64m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel func_96m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+static struct clk func_96m_fclk = {
+        .name           = "func_96m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_96m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel_rate div2_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel init_60m_fclk_div[] = {
+        { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
+        { .parent = NULL },
+};
+static struct clk init_60m_fclk = {
+        .name           = "init_60m_fclk",
+        .parent         = &dpll_usb_m2_ck,
+        .clksel         = init_60m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel l3_div_div[] = {
+        { .parent = &div_core_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk l3_div_ck = {
+        .name           = "l3_div_ck",
+        .parent         = &div_core_ck,
+        .clksel         = l3_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel l4_div_div[] = {
+        { .parent = &l3_div_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk l4_div_ck = {
+        .name           = "l4_div_ck",
+        .parent         = &l3_div_ck,
+        .clksel         = l4_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk lp_clk_div_ck = {
+        .name           = "lp_clk_div_ck",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel l4_wkup_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk l4_wkup_clk_mux_ck = {
+        .name           = "l4_wkup_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = l4_wkup_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk ocp_abe_iclk = {
+        .name           = "ocp_abe_iclk",
+        .parent         = &aess_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+static struct clk per_abe_24m_fclk = {
+        .name           = "per_abe_24m_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+static const struct clksel per_abe_nc_fclk_div[] = {
+        { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk per_abe_nc_fclk = {
+        .name           = "per_abe_nc_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .clksel         = per_abe_nc_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel pmd_stm_clock_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
+        { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static struct clk pmd_stm_clock_mux_ck = {
+        .name           = "pmd_stm_clock_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+static struct clk pmd_trace_clk_mux_ck = {
+        .name           = "pmd_trace_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel syc_clk_div_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+static struct clk syc_clk_div_ck = {
+        .name           = "syc_clk_div_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = syc_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+/* Leaf clocks controlled by modules */
+static struct clk aes1_fck = {
+        .name           = "aes1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk aes2_fck = {
+        .name           = "aes2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk aess_fck = {
+        .name           = "aess_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &aess_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk bandgap_fclk = {
+        .name           = "bandgap_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk des3des_fck = {
+        .name           = "des3des_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel dmic_sync_mux_sel[] = {
+        { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
+        { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = &func_24m_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static struct clk dmic_sync_mux_ck = {
+        .name           = "dmic_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel func_dmic_abe_gfclk_sel[] = {
+        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+/* Merged func_dmic_abe_gfclk into dmic */
+static struct clk dmic_fck = {
+        .name           = "dmic_fck",
+        .parent         = &dmic_sync_mux_ck,
+        .clksel         = func_dmic_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_sys_clk = {
+        .name           = "dss_sys_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &syc_clk_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_tv_clk = {
+        .name           = "dss_tv_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &extalt_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_dss_clk = {
+        .name           = "dss_dss_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &dpll_per_m5x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate div3_8to32_rates[] = {
+        { .div = 8, .val = 0, .flags = RATE_IN_44XX },
+        { .div = 16, .val = 1, .flags = RATE_IN_44XX },
+        { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+        { .div = 0 },
+};
+static const struct clksel div_ts_div[] = {
+        { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+        { .parent = NULL },
+};
+static struct clk div_ts_ck = {
+        .name           = "div_ts_ck",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .clksel         = div_ts_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk bandgap_ts_fclk = {
+        .name           = "bandgap_ts_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &div_ts_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_48mhz_clk = {
+        .name           = "dss_48mhz_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk dss_fck = {
+        .name           = "dss_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk efuse_ctrl_cust_fck = {
+        .name           = "efuse_ctrl_cust_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk emif1_fck = {
+        .name           = "emif1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk emif2_fck = {
+        .name           = "emif2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel fdif_fclk_div[] = {
+        { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+/* Merged fdif_fclk into fdif */
+static struct clk fdif_fck = {
+        .name           = "fdif_fck",
+        .parent         = &dpll_per_m4x2_ck,
+        .clksel         = fdif_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+};
+static struct clk fpka_fck = {
+        .name           = "fpka_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio1_dbclk = {
+        .name           = "gpio1_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio2_dbclk = {
+        .name           = "gpio2_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio3_dbclk = {
+        .name           = "gpio3_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio4_dbclk = {
+        .name           = "gpio4_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_dbclk = {
+        .name           = "gpio5_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio6_dbclk = {
+        .name           = "gpio6_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk gpmc_ick = {
+        .name           = "gpmc_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_2_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+/* Merged sgx_clk_mux into gpu */
+static struct clk gpu_fck = {
+        .name           = "gpu_fck",
+        .parent         = &dpll_core_m7x2_ck,
+        .clksel         = sgx_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_gfx_clkdm",
+};
+static struct clk hdq1w_fck = {
+        .name           = "hdq1w_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_12m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel hsi_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+/* Merged hsi_fclk into hsi */
+static struct clk hsi_fck = {
+        .name           = "hsi_fck",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = hsi_fclk_div,
+        .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+static struct clk i2c1_fck = {
+        .name           = "i2c1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c2_fck = {
+        .name           = "i2c2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c3_fck = {
+        .name           = "i2c3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk i2c4_fck = {
+        .name           = "i2c4_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk ipu_fck = {
+        .name           = "ipu_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk iss_ctrlclk = {
+        .name           = "iss_ctrlclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk iss_fck = {
+        .name           = "iss_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk iva_fck = {
+        .name           = "iva_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk kbd_fck = {
+        .name           = "kbd_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk l3_instr_ick = {
+        .name           = "l3_instr_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk l3_main_3_ick = {
+        .name           = "l3_main_3_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcasp_sync_mux_ck = {
+        .name           = "mcasp_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel func_mcasp_abe_gfclk_sel[] = {
+        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+/* Merged func_mcasp_abe_gfclk into mcasp */
+static struct clk mcasp_fck = {
+        .name           = "mcasp_fck",
+        .parent         = &mcasp_sync_mux_ck,
+        .clksel         = func_mcasp_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+static struct clk mcbsp1_sync_mux_ck = {
+        .name           = "mcbsp1_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel func_mcbsp1_gfclk_sel[] = {
+        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+/* Merged func_mcbsp1_gfclk into mcbsp1 */
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .parent         = &mcbsp1_sync_mux_ck,
+        .clksel         = func_mcbsp1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+static struct clk mcbsp2_sync_mux_ck = {
+        .name           = "mcbsp2_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel func_mcbsp2_gfclk_sel[] = {
+        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+/* Merged func_mcbsp2_gfclk into mcbsp2 */
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .parent         = &mcbsp2_sync_mux_ck,
+        .clksel         = func_mcbsp2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+static struct clk mcbsp3_sync_mux_ck = {
+        .name           = "mcbsp3_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel func_mcbsp3_gfclk_sel[] = {
+        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+/* Merged func_mcbsp3_gfclk into mcbsp3 */
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .parent         = &mcbsp3_sync_mux_ck,
+        .clksel         = func_mcbsp3_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+static const struct clksel mcbsp4_sync_mux_sel[] = {
+        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk mcbsp4_sync_mux_ck = {
+        .name           = "mcbsp4_sync_mux_ck",
+        .parent         = &func_96m_fclk,
+        .clksel         = mcbsp4_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static const struct clksel per_mcbsp4_gfclk_sel[] = {
+        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+/* Merged per_mcbsp4_gfclk into mcbsp4 */
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .parent         = &mcbsp4_sync_mux_ck,
+        .clksel         = per_mcbsp4_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+static struct clk mcpdm_fck = {
+        .name           = "mcpdm_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi1_fck = {
+        .name           = "mcspi1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi2_fck = {
+        .name           = "mcspi2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi3_fck = {
+        .name           = "mcspi3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mcspi4_fck = {
+        .name           = "mcspi4_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel hsmmc1_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+/* Merged hsmmc1_fclk into mmc1 */
+static struct clk mmc1_fck = {
+        .name           = "mmc1_fck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc1_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+/* Merged hsmmc2_fclk into mmc2 */
+static struct clk mmc2_fck = {
+        .name           = "mmc2_fck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc1_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+static struct clk mmc3_fck = {
+        .name           = "mmc3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmc4_fck = {
+        .name           = "mmc4_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk mmc5_fck = {
+        .name           = "mmc5_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk ocp2scp_usb_phy_phy_48m = {
+        .name           = "ocp2scp_usb_phy_phy_48m",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk ocp2scp_usb_phy_ick = {
+        .name           = "ocp2scp_usb_phy_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk ocp_wp_noc_ick = {
+        .name           = "ocp_wp_noc_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sha2md5_fck = {
+        .name           = "sha2md5_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk sl2if_ick = {
+        .name           = "sl2if_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5x2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus1_fclk_1 = {
+        .name           = "slimbus1_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &func_24m_clk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus1_fclk_0 = {
+        .name           = "slimbus1_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus1_fclk_2 = {
+        .name           = "slimbus1_fclk_2",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus1_slimbus_clk = {
+        .name           = "slimbus1_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &slimbus_clk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus1_fck = {
+        .name           = "slimbus1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &ocp_abe_iclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus2_fclk_1 = {
+        .name           = "slimbus2_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &per_abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus2_fclk_0 = {
+        .name           = "slimbus2_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_24mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus2_slimbus_clk = {
+        .name           = "slimbus2_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &pad_slimbus_core_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk slimbus2_fck = {
+        .name           = "slimbus2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk smartreflex_core_fck = {
+        .name           = "smartreflex_core_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk smartreflex_iva_fck = {
+        .name           = "smartreflex_iva_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk smartreflex_mpu_fck = {
+        .name           = "smartreflex_mpu_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+/* Merged dmt1_clk_mux into timer1 */
+static struct clk timer1_fck = {
+        .name           = "timer1_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/* Merged cm2_dm10_mux into timer10 */
+static struct clk timer10_fck = {
+        .name           = "timer10_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+/* Merged cm2_dm11_mux into timer11 */
+static struct clk timer11_fck = {
+        .name           = "timer11_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+/* Merged cm2_dm2_mux into timer2 */
+static struct clk timer2_fck = {
+        .name           = "timer2_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+/* Merged cm2_dm3_mux into timer3 */
+static struct clk timer3_fck = {
+        .name           = "timer3_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+/* Merged cm2_dm4_mux into timer4 */
+static struct clk timer4_fck = {
+        .name           = "timer4_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+/* Merged timer5_sync_mux into timer5 */
+static struct clk timer5_fck = {
+        .name           = "timer5_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+/* Merged timer6_sync_mux into timer6 */
+static struct clk timer6_fck = {
+        .name           = "timer6_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+/* Merged timer7_sync_mux into timer7 */
+static struct clk timer7_fck = {
+        .name           = "timer7_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+/* Merged timer8_sync_mux into timer8 */
+static struct clk timer8_fck = {
+        .name           = "timer8_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+/* Merged cm2_dm9_mux into timer9 */
+static struct clk timer9_fck = {
+        .name           = "timer9_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk uart4_fck = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_fs_fck = {
+        .name           = "usb_host_fs_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk utmi_p1_gfclk = {
+        .name           = "utmi_p1_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk usb_host_hs_utmi_p1_clk = {
+        .name           = "usb_host_hs_utmi_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &utmi_p1_gfclk,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk utmi_p2_gfclk = {
+        .name           = "utmi_p2_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk usb_host_hs_utmi_p2_clk = {
+        .name           = "usb_host_hs_utmi_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &utmi_p2_gfclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_utmi_p3_clk = {
+        .name           = "usb_host_hs_utmi_p3_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_hsic480m_p1_clk = {
+        .name           = "usb_host_hs_hsic480m_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+        .name           = "usb_host_hs_hsic60m_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+        .name           = "usb_host_hs_hsic60m_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_hsic480m_p2_clk = {
+        .name           = "usb_host_hs_hsic480m_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_func48mclk = {
+        .name           = "usb_host_hs_func48mclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_host_hs_fck = {
+        .name           = "usb_host_hs_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel otg_60m_gfclk_sel[] = {
+        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
+        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk otg_60m_gfclk = {
+        .name           = "otg_60m_gfclk",
+        .parent         = &utmi_phy_clkout_ck,
+        .clksel         = otg_60m_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk usb_otg_hs_xclk = {
+        .name           = "usb_otg_hs_xclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &otg_60m_gfclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_otg_hs_ick = {
+        .name           = "usb_otg_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_phy_cm_clk32k = {
+        .name           = "usb_phy_cm_clk32k",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_tll_hs_usb_ch2_clk = {
+        .name           = "usb_tll_hs_usb_ch2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_tll_hs_usb_ch0_clk = {
+        .name           = "usb_tll_hs_usb_ch0_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_tll_hs_usb_ch1_clk = {
+        .name           = "usb_tll_hs_usb_ch1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usb_tll_hs_ick = {
+        .name           = "usb_tll_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+static const struct clksel_rate div2_14to18_rates[] = {
+        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static const struct clksel usim_fclk_div[] = {
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
+        { .parent = NULL },
+};
+static struct clk usim_ck = {
+        .name           = "usim_ck",
+        .parent         = &dpll_per_m4x2_ck,
+        .clksel         = usim_fclk_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &usim_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wd_timer2_fck = {
+        .name           = "wd_timer2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wd_timer3_fck = {
+        .name           = "wd_timer3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+/* Remaining optional clocks */
+static const struct clksel stm_clk_div_div[] = {
+        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+static struct clk stm_clk_div_ck = {
+        .name           = "stm_clk_div_ck",
+        .parent         = &pmd_stm_clock_mux_ck,
+        .clksel         = stm_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+static struct clk trace_clk_div_ck = {
+        .name           = "trace_clk_div_ck",
+        .parent         = &pmd_trace_clk_mux_ck,
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+/* SCRM aux clk nodes */
+static const struct clksel auxclk_src_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const struct clksel_rate div16_1to16_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+static struct clk auxclk0_src_ck = {
+        .name           = "auxclk0_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK0,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk0_sel[] = {
+        { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk0_ck = {
+        .name           = "auxclk0_ck",
+        .parent         = &auxclk0_src_ck,
+        .clksel         = auxclk0_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk auxclk1_src_ck = {
+        .name           = "auxclk1_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK1,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk1_sel[] = {
+        { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk1_ck = {
+        .name           = "auxclk1_ck",
+        .parent         = &auxclk1_src_ck,
+        .clksel         = auxclk1_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk auxclk2_src_ck = {
+        .name           = "auxclk2_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK2,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk2_sel[] = {
+        { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk2_ck = {
+        .name           = "auxclk2_ck",
+        .parent         = &auxclk2_src_ck,
+        .clksel         = auxclk2_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk auxclk3_src_ck = {
+        .name           = "auxclk3_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK3,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk3_sel[] = {
+        { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk3_ck = {
+        .name           = "auxclk3_ck",
+        .parent         = &auxclk3_src_ck,
+        .clksel         = auxclk3_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk auxclk4_src_ck = {
+        .name           = "auxclk4_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK4,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk4_sel[] = {
+        { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk4_ck = {
+        .name           = "auxclk4_ck",
+        .parent         = &auxclk4_src_ck,
+        .clksel         = auxclk4_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static struct clk auxclk5_src_ck = {
+        .name           = "auxclk5_src_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_src_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK5,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static const struct clksel auxclk5_sel[] = {
+        { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+static struct clk auxclk5_ck = {
+        .name           = "auxclk5_ck",
+        .parent         = &auxclk5_src_ck,
+        .clksel         = auxclk5_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+static const struct clksel auxclkreq_sel[] = {
+        { .parent = &auxclk0_ck, .rates = div_1_0_rates },
+        { .parent = &auxclk1_ck, .rates = div_1_1_rates },
+        { .parent = &auxclk2_ck, .rates = div_1_2_rates },
+        { .parent = &auxclk3_ck, .rates = div_1_3_rates },
+        { .parent = &auxclk4_ck, .rates = div_1_4_rates },
+        { .parent = &auxclk5_ck, .rates = div_1_5_rates },
+        { .parent = NULL },
+};
+static struct clk auxclkreq0_ck = {
+        .name           = "auxclkreq0_ck",
+        .parent         = &auxclk0_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk auxclkreq1_ck = {
+        .name           = "auxclkreq1_ck",
+        .parent         = &auxclk1_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk auxclkreq2_ck = {
+        .name           = "auxclkreq2_ck",
+        .parent         = &auxclk2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk auxclkreq3_ck = {
+        .name           = "auxclkreq3_ck",
+        .parent         = &auxclk3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk auxclkreq4_ck = {
+        .name           = "auxclkreq4_ck",
+        .parent         = &auxclk4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+static struct clk auxclkreq5_ck = {
+        .name           = "auxclkreq5_ck",
+        .parent         = &auxclk5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+/*
+ * clkdev
+ */
+static struct omap_clk omap44xx_clks[] = {
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
+        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
+        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
+        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
+        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
+        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
+        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
+        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
+        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
+        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
+        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
+        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
+        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
+        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
+        CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
+        CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
+        CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
+        CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
+        CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
+        CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
+        CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
+        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
+        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
+        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
+        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
+        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
+        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
+        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
+        CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
+        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
+        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
+        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
+        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
+        CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
+        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
+        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
+        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
+        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
+        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
+        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
+        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
+        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
+        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
+        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
+        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
+        CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
+        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+        CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
+        CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
+        CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
+        CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
+        CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
+        CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
+        CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
+        CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
+        CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
+        CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
+        CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
+        CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
+        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
+        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
+        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
+        CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
+        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
+        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
+        CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
+        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
+        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+};
+int __init omap4xxx_clk_init(void)
+{
+        struct omap_clk *c;
+        u32 cpu_clkflg;
+        if (cpu_is_omap44xx()) {
+                cpu_mask = RATE_IN_4430;
+                cpu_clkflg = CK_443X;
+        } else if (cpu_is_omap446x()) {
+                cpu_mask = RATE_IN_4460;
+                cpu_clkflg = CK_446X;
+        } else {
+                return 0;
+        }
+        clk_init(&omap2_clk_functions);
+        /*
+         * Must stay commented until all OMAP SoC drivers are
+         * converted to runtime PM, or drivers may start crashing
+         *
+         * omap2_clk_disable_clkdm_control();
+         */
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                clk_preinit(c->lk.clk);
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+        recalculate_root_clocks();
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
new file mode 100644
index 00000000000..f740edb111f
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -0,0 +1,276 @@
+/*
+ * OMAP2 and OMAP3 clockdomain control
+ *
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <plat/prcm.h>
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-24xx.h"
+#include "clockdomain.h"
+static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+                                                struct clockdomain *clkdm2)
+{
+        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                PM_WKDEP, (1 << clkdm2->dep_bit));
+}
+static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                 PM_WKDEP);
+        return 0;
+}
+static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
+                                                 struct clockdomain *clkdm2)
+{
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
+}
+static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->sleepdep_usecount, 0);
+        }
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
+static int omap2_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                clkdm->pwrdm.ptr->prcm_offs,
+                                OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+}
+static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+static void _enable_hwsup(struct clockdomain *clkdm)
+{
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+}
+static void _disable_hwsup(struct clockdomain *clkdm)
+{
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+}
+static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_add_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2_clkdm_wakeup(clkdm);
+        }
+        return 0;
+}
+static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_del_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap2_clkdm_sleep(clkdm);
+        }
+        return 0;
+}
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+}
+static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+struct clkdm_ops omap2_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_sleep            = omap2_clkdm_sleep,
+        .clkdm_wakeup           = omap2_clkdm_wakeup,
+        .clkdm_allow_idle       = omap2_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap2_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+};
+struct clkdm_ops omap3_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_add_sleepdep     = omap3_clkdm_add_sleepdep,
+        .clkdm_del_sleepdep     = omap3_clkdm_del_sleepdep,
+        .clkdm_read_sleepdep    = omap3_clkdm_read_sleepdep,
+        .clkdm_clear_all_sleepdeps      = omap3_clkdm_clear_all_sleepdeps,
+        .clkdm_sleep            = omap3_clkdm_sleep,
+        .clkdm_wakeup           = omap3_clkdm_wakeup,
+        .clkdm_allow_idle       = omap3_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap3_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
new file mode 100644
index 00000000000..b43706aa08b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -0,0 +1,132 @@
+/*
+ * OMAP4 clockdomain control
+ *
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include "clockdomain.h"
+#include "cminst44xx.h"
+#include "cm44xx.h"
+static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
+                                        clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
+                                        clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
+                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                        OMAP4_CM_STATICDEP,
+                                        (1 << clkdm2->dep_bit));
+}
+static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs +
+                                        OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return omap4_clkdm_wakeup(clkdm);
+        return 0;
+}
+static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                omap4_clkdm_sleep(clkdm);
+        return 0;
+}
+struct clkdm_ops omap4_clkdm_operations = {
+        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_sleep            = omap4_clkdm_sleep,
+        .clkdm_wakeup           = omap4_clkdm_wakeup,
+        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
new file mode 100644
index 00000000000..38830d8d478
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -0,0 +1,557 @@
+/*
+ * OMAP2/3 CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <plat/common.h>
+#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+#define DPLL_AUTOIDLE_DISABLE                           0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
+static const u8 cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+};
+u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(cm_base + module + idx);
+}
+void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, cm_base + module + idx);
+}
+/* Read-modify-write a register in a CM module. Caller must lock */
+u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_cm_write_mod_reg(v, module, idx);
+        return v;
+}
+u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+/*
+ *
+ */
+static void _write_clktrctrl(u8 c, s16 module, u32 mask)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= ~mask;
+        v |= c << __ffs(mask);
+        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
+}
+bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+{
+        u32 v;
+        bool ret = 0;
+        BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= mask;
+        v >>= __ffs(mask);
+        if (cpu_is_omap24xx())
+                ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+        else
+                ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+        return ret;
+}
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
+}
+void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
+}
+/*
+ * DPLL autoidle control
+ */
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
+/*
+ * APLL autoidle control
+ */
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~mask;
+        v |= m << __ffs(mask);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+/*
+ *
+ */
+/**
+ * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * XXX document
+ */
+int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
+                return -EINVAL;
+        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+        mask = 1 << idlest_shift;
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+                          MAX_MODULE_READY_TIME, i);
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+/*
+ * Context save/restore code - OMAP3 only
+ */
+#ifdef CONFIG_ARCH_OMAP3
+struct omap3_cm_regs {
+        u32 iva2_cm_clksel1;
+        u32 iva2_cm_clksel2;
+        u32 cm_sysconfig;
+        u32 sgx_cm_clksel;
+        u32 dss_cm_clksel;
+        u32 cam_cm_clksel;
+        u32 per_cm_clksel;
+        u32 emu_cm_clksel;
+        u32 emu_cm_clkstctrl;
+        u32 pll_cm_autoidle;
+        u32 pll_cm_autoidle2;
+        u32 pll_cm_clksel4;
+        u32 pll_cm_clksel5;
+        u32 pll_cm_clken2;
+        u32 cm_polctrl;
+        u32 iva2_cm_fclken;
+        u32 iva2_cm_clken_pll;
+        u32 core_cm_fclken1;
+        u32 core_cm_fclken3;
+        u32 sgx_cm_fclken;
+        u32 wkup_cm_fclken;
+        u32 dss_cm_fclken;
+        u32 cam_cm_fclken;
+        u32 per_cm_fclken;
+        u32 usbhost_cm_fclken;
+        u32 core_cm_iclken1;
+        u32 core_cm_iclken2;
+        u32 core_cm_iclken3;
+        u32 sgx_cm_iclken;
+        u32 wkup_cm_iclken;
+        u32 dss_cm_iclken;
+        u32 cam_cm_iclken;
+        u32 per_cm_iclken;
+        u32 usbhost_cm_iclken;
+        u32 iva2_cm_autoidle2;
+        u32 mpu_cm_autoidle2;
+        u32 iva2_cm_clkstctrl;
+        u32 mpu_cm_clkstctrl;
+        u32 core_cm_clkstctrl;
+        u32 sgx_cm_clkstctrl;
+        u32 dss_cm_clkstctrl;
+        u32 cam_cm_clkstctrl;
+        u32 per_cm_clkstctrl;
+        u32 neon_cm_clkstctrl;
+        u32 usbhost_cm_clkstctrl;
+        u32 core_cm_autoidle1;
+        u32 core_cm_autoidle2;
+        u32 core_cm_autoidle3;
+        u32 wkup_cm_autoidle;
+        u32 dss_cm_autoidle;
+        u32 cam_cm_autoidle;
+        u32 per_cm_autoidle;
+        u32 usbhost_cm_autoidle;
+        u32 sgx_cm_sleepdep;
+        u32 dss_cm_sleepdep;
+        u32 cam_cm_sleepdep;
+        u32 per_cm_sleepdep;
+        u32 usbhost_cm_sleepdep;
+        u32 cm_clkout_ctrl;
+};
+static struct omap3_cm_regs cm_context;
+void omap3_cm_save_context(void)
+{
+        cm_context.iva2_cm_clksel1 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
+        cm_context.iva2_cm_clksel2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+        cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+        cm_context.sgx_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+        cm_context.dss_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+        cm_context.cam_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+        cm_context.per_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+        cm_context.emu_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+        cm_context.emu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, even though this register has been saved in
+         * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
+         * by ourselves. So, we need to save it anyway.
+         */
+        cm_context.pll_cm_autoidle =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        cm_context.pll_cm_autoidle2 =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+        cm_context.pll_cm_clksel4 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
+        cm_context.pll_cm_clksel5 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+        cm_context.pll_cm_clken2 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
+        cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+        cm_context.iva2_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
+        cm_context.iva2_cm_clken_pll =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
+        cm_context.core_cm_fclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        cm_context.core_cm_fclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+        cm_context.sgx_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+        cm_context.wkup_cm_fclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+        cm_context.dss_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
+        cm_context.cam_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
+        cm_context.per_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+        cm_context.usbhost_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        cm_context.core_cm_iclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+        cm_context.core_cm_iclken2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
+        cm_context.core_cm_iclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+        cm_context.sgx_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+        cm_context.wkup_cm_iclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+        cm_context.dss_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
+        cm_context.cam_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
+        cm_context.per_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+        cm_context.usbhost_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        cm_context.iva2_cm_autoidle2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+        cm_context.mpu_cm_autoidle2 =
+                omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
+        cm_context.iva2_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.mpu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_clkstctrl =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.sgx_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.dss_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.cam_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.per_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.neon_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.usbhost_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_autoidle1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
+        cm_context.core_cm_autoidle2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
+        cm_context.core_cm_autoidle3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
+        cm_context.wkup_cm_autoidle =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
+        cm_context.dss_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
+        cm_context.cam_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
+        cm_context.per_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        cm_context.usbhost_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        cm_context.sgx_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.dss_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.cam_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.per_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.usbhost_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.cm_clkout_ctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
+                                      OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+void omap3_cm_restore_context(void)
+{
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL2);
+        __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
+         */
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL4);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL5);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
+                               OMAP3430ES2_CM_CLKEN2);
+        __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
+                               OMAP3430_CM_CLKEN_PLL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
+                               CM_FCLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
+                               OMAP3430ES2_CM_FCLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
+                               CM_ICLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
+                               CM_ICLKEN2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
+                               CM_ICLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
+                               OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
+                               CM_AUTOIDLE1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
+                               CM_AUTOIDLE3);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
+                               OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
+                               OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
+                               OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
new file mode 100644
index 00000000000..f1e13d1ca5e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -0,0 +1,44 @@
+/*:
+ * Address mappings and base address for AM35XX specific interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Sriramakrishnan <srk@ti.com>
+ *         Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AM35XX_H
+#define __ASM_ARCH_AM35XX_H
+/*
+ * Base addresses
+ *      Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
+ */
+#define AM35XX_IPSS_EMAC_BASE           0x5C000000
+#define AM35XX_IPSS_USBOTGSS_BASE       0x5C040000
+#define AM35XX_IPSS_HECC_BASE           0x5C050000
+#define AM35XX_IPSS_VPFE_BASE           0x5C060000
+/* HECC module specifc offset definitions */
+#define AM35XX_HECC_SCC_HECC_OFFSET     (0x0)
+#define AM35XX_HECC_SCC_RAM_OFFSET      (0x3000)
+#define AM35XX_HECC_RAM_OFFSET          (0x3000)
+#define AM35XX_HECC_MBOX_OFFSET         (0x2000)
+#define AM35XX_HECC_INT_LINE            (0x0)
+#define AM35XX_HECC_VERSION             (0x1)
+#define AM35XX_EMAC_CNTRL_OFFSET        (0x10000)
+#define AM35XX_EMAC_CNTRL_MOD_OFFSET    (0x0)
+#define AM35XX_EMAC_CNTRL_RAM_OFFSET    (0x20000)
+#define AM35XX_EMAC_MDIO_OFFSET         (0x30000)
+#define AM35XX_EMAC_CNTRL_RAM_SIZE      (0x2000)
+#define AM35XX_EMAC_RAM_ADDR            (AM3517_EMAC_BASE + \
+                                                AM3517_EMAC_CNTRL_RAM_OFFSET)
+#define AM35XX_EMAC_HW_RAM_ADDR         (0x01E20000)
+#endif  /*  __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h
new file mode 100644
index 00000000000..b76f49e7eed
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-rx51.h
@@ -0,0 +1,11 @@
+/*
+ * Defines for rx51 boards
+ */
+#ifndef _OMAP_BOARD_RX51_H
+#define _OMAP_BOARD_RX51_H
+extern void __init rx51_peripherals_init(void);
+extern void __init rx51_video_mem_init(void);
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
new file mode 100644
index 00000000000..775fdc3b000
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -0,0 +1,12 @@
+/*
+ * Defines for zoom boards
+ */
+#include <video/omapdss.h>
+#define ZOOM_NAND_CS    0
+extern int __init zoom_debugboard_init(void);
+extern void __init zoom_peripherals_init(void);
+extern void __init zoom_display_init(void);
+#define ZOOM2_HEADSET_EXTMUTE_GPIO      153
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 00000000000..2f7ac70a20d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
+/*
+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+/* Base address */
+#define OMAP4_CTRL_MODULE_CORE                                  0x4a002000
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION                      0x0000
+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO                        0x0004
+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG                     0x0010
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0                0x0200
+#define OMAP4_CTRL_MODULE_CORE_ID_CODE                          0x0204
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1                0x0208
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2                0x020c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3                0x0210
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0               0x0214
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1               0x0218
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF                0x021c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP            0x0228
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP                0x0260
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0              0x0264
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
+#define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL         0x0324
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL        0x0328
+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR                      0x032c
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0                0x0330
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1                0x0334
+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL                 0x033c
+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL                      0x0340
+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL                    0x0350
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL             0x0400
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU                   0x0408
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0               0x042c
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1               0x0430
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2               0x0434
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3               0x0438
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0                    0x0440
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1                    0x0444
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2                    0x0448
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL           0x044c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL             0x0450
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL          0x0454
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0             0x0480
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1             0x0484
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2             0x0488
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3             0x048c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4             0x0490
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5             0x0494
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6             0x0498
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7             0x049c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8             0x04a0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9             0x04a4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10            0x04a8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11            0x04ac
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12            0x04b0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13            0x04b4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14            0x04b8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15            0x04bc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16            0x04c0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17            0x04c4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18            0x04c8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19            0x04cc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20            0x04d0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21            0x04d4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22            0x04d8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23            0x04dc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24            0x04e0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25            0x04e4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26            0x04e8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27            0x04ec
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28            0x04f0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29            0x04f4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30            0x04f8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31            0x04fc
+/* Registers shifts and masks */
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                       30
+#define OMAP4_IP_REV_SCHEME_MASK                        (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                         16
+#define OMAP4_IP_REV_FUNC_MASK                          (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                          11
+#define OMAP4_IP_REV_RTL_MASK                           (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                        8
+#define OMAP4_IP_REV_MAJOR_MASK                         (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                       6
+#define OMAP4_IP_REV_CUSTOM_MASK                        (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                        0
+#define OMAP4_IP_REV_MINOR_MASK                         (0x3f << 0)
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                           0
+#define OMAP4_IP_HWINFO_MASK                            (0xffffffff << 0)
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT               2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                (0x3 << 2)
+/* STD_FUSE_DIE_ID_0 */
+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_0_MASK                    (0xffffffff << 0)
+/* ID_CODE */
+#define OMAP4_STD_FUSE_IDCODE_SHIFT                     0
+#define OMAP4_STD_FUSE_IDCODE_MASK                      (0xffffffff << 0)
+/* STD_FUSE_DIE_ID_1 */
+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_1_MASK                    (0xffffffff << 0)
+/* STD_FUSE_DIE_ID_2 */
+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_2_MASK                    (0xffffffff << 0)
+/* STD_FUSE_DIE_ID_3 */
+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_3_MASK                    (0xffffffff << 0)
+/* STD_FUSE_PROD_ID_0 */
+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_0_MASK                   (0xffffffff << 0)
+/* STD_FUSE_PROD_ID_1 */
+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_1_MASK                   (0xffffffff << 0)
+/* STD_FUSE_USB_CONF */
+#define OMAP4_USB_PROD_ID_SHIFT                         16
+#define OMAP4_USB_PROD_ID_MASK                          (0xffff << 16)
+#define OMAP4_USB_VENDOR_ID_SHIFT                       0
+#define OMAP4_USB_VENDOR_ID_MASK                        (0xffff << 0)
+/* STD_FUSE_OPP_VDD_WKUP */
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT               0
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK                (0xffffffff << 0)
+/* STD_FUSE_OPP_BGAP */
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT                   0
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK                    (0xffffffff << 0)
+/* STD_FUSE_OPP_DPLL_0 */
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK                  (0xffffffff << 0)
+/* STD_FUSE_OPP_DPLL_1 */
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK                  (0xffffffff << 0)
+/* STATUS */
+#define OMAP4_ATTILA_CONF_SHIFT                         11
+#define OMAP4_ATTILA_CONF_MASK                          (0x3 << 11)
+#define OMAP4_DEVICE_TYPE_SHIFT                         8
+#define OMAP4_DEVICE_TYPE_MASK                          (0x7 << 8)
+#define OMAP4_SYS_BOOT_SHIFT                            0
+#define OMAP4_SYS_BOOT_MASK                             (0xff << 0)
+/* DEV_CONF */
+#define OMAP4_DEV_CONF_SHIFT                            1
+#define OMAP4_DEV_CONF_MASK                             (0x7fffffff << 1)
+#define OMAP4_USBPHY_PD_SHIFT                           0
+#define OMAP4_USBPHY_PD_MASK                            (1 << 0)
+/* LDOVBB_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK               (0x1f << 0)
+/* LDOVBB_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK               (0x1f << 0)
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT        26
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK         (1 << 26)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT         21
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK          (0x1f << 21)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT        16
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK         (0x1f << 16)
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT        10
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK         (1 << 10)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT         5
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK          (0x1f << 5)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT        0
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK         (0x1f << 0)
+/* TEMP_SENSOR */
+#define OMAP4_BGAP_TEMPSOFF_SHIFT                       12
+#define OMAP4_BGAP_TEMPSOFF_MASK                        (1 << 12)
+#define OMAP4_BGAP_TSHUT_SHIFT                          11
+#define OMAP4_BGAP_TSHUT_MASK                           (1 << 11)
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT           10
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK            (1 << 10)
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT                9
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK                 (1 << 9)
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT               8
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK                (1 << 8)
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT              0
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK               (0xff << 0)
+/* DPLL_NWELL_TRIM_0 */
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT        29
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK         (1 << 29)
+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT                 24
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK                  (0x1f << 24)
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT        11
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK         (1 << 11)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT                 6
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK                  (0x1f << 6)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT        5
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK         (1 << 5)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT                 0
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK                  (0x1f << 0)
+/* DPLL_NWELL_TRIM_1 */
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT     29
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK      (1 << 29)
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT              24
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK               (0x1f << 24)
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT       11
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK        (1 << 11)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT                6
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK                 (0x1f << 6)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT       5
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK        (1 << 5)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT                0
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK                 (0x1f << 0)
+/* USBOTGHS_CONTROL */
+#define OMAP4_DISCHRGVBUS_SHIFT                         8
+#define OMAP4_DISCHRGVBUS_MASK                          (1 << 8)
+#define OMAP4_CHRGVBUS_SHIFT                            7
+#define OMAP4_CHRGVBUS_MASK                             (1 << 7)
+#define OMAP4_DRVVBUS_SHIFT                             6
+#define OMAP4_DRVVBUS_MASK                              (1 << 6)
+#define OMAP4_IDPULLUP_SHIFT                            5
+#define OMAP4_IDPULLUP_MASK                             (1 << 5)
+#define OMAP4_IDDIG_SHIFT                               4
+#define OMAP4_IDDIG_MASK                                (1 << 4)
+#define OMAP4_SESSEND_SHIFT                             3
+#define OMAP4_SESSEND_MASK                              (1 << 3)
+#define OMAP4_VBUSVALID_SHIFT                           2
+#define OMAP4_VBUSVALID_MASK                            (1 << 2)
+#define OMAP4_BVALID_SHIFT                              1
+#define OMAP4_BVALID_MASK                               (1 << 1)
+#define OMAP4_AVALID_SHIFT                              0
+#define OMAP4_AVALID_MASK                               (1 << 0)
+/* DSS_CONTROL */
+#define OMAP4_DSS_MUX6_SELECT_SHIFT                     0
+#define OMAP4_DSS_MUX6_SELECT_MASK                      (1 << 0)
+/* HWOBS_CONTROL */
+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT                    3
+#define OMAP4_HWOBS_CLKDIV_SEL_MASK                     (0x1f << 3)
+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT                 2
+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK                  (1 << 2)
+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT                  1
+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK                   (1 << 1)
+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT                  0
+#define OMAP4_HWOBS_MACRO_ENABLE_MASK                   (1 << 0)
+/* DEBOBS_FINAL_MUX_SEL */
+#define OMAP4_SELECT_SHIFT                              0
+#define OMAP4_SELECT_MASK                               (0xffffffff << 0)
+/* DEBOBS_MMR_MPU */
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT               0
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK                (0xf << 0)
+/* CONF_SDMA_REQ_SEL0 */
+#define OMAP4_MULT_SHIFT                                0
+#define OMAP4_MULT_MASK                                 (0x7f << 0)
+/* CONF_CLK_SEL0 */
+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL0_MASK                   (0x7 << 0)
+/* CONF_CLK_SEL1 */
+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL1_MASK                   (0x7 << 0)
+/* CONF_CLK_SEL2 */
+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL2_MASK                   (0x7 << 0)
+/* CONF_DPLL_FREQLOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT         0
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK          (0x7 << 0)
+/* CONF_DPLL_TINITZ_SEL */
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT           0
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK            (0x7 << 0)
+/* CONF_DPLL_PHASELOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT        0
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK         (0x7 << 0)
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_MODE_SHIFT                                0
+#define OMAP4_MODE_MASK                                 (0xf << 0)
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 00000000000..c88420de115
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE                              0x4a100000
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION                  0x0000
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO                    0x0004
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG                 0x0010
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0        0x01d8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1        0x01dc
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2        0x01e0
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3        0x01e4
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4        0x01e8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5        0x01ec
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6        0x01f0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE         0x05a4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC            0x05c4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS              0x05c8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE            0x0600
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0                0x0604
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX            0x0608
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC                0x060c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY          0x0610
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2                 0x0614
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY               0x0618
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP              0x061c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE          0x0620
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1                0x0624
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1                 0x0628
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI                  0x062c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB                  0x0630
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ                  0x0634
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0          0x0638
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1          0x063c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2          0x0640
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3          0x0644
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0          0x0648
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1          0x064c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2          0x0650
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3          0x0654
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD             0x0658
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C                  0x065c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW        0x0660
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R         0x0664
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0      0x0668
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1              0x0700
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2              0x0704
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3              0x0708
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4              0x070c
+/* Registers shifts and masks */
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT               31
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK                (1 << 31)
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT               30
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK                (1 << 30)
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT               16
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK                (1 << 16)
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT              11
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK               (1 << 11)
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT              10
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK               (1 << 10)
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT               9
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK                (1 << 9)
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT               8
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK                (1 << 8)
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT               6
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK                (1 << 6)
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT               5
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK                (1 << 5)
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT               4
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK                (1 << 4)
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT               3
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK                (1 << 3)
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT               0
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK                (1 << 0)
+/* PADCONF_WAKEUPEVENT_1 */
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT            30
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK             (1 << 30)
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT              25
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK               (1 << 25)
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT              24
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK               (1 << 24)
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT              23
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK               (1 << 23)
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT              22
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK               (1 << 22)
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT              20
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK               (1 << 20)
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT           15
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK            (1 << 15)
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT               13
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK                (1 << 13)
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT               12
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK                (1 << 12)
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT             11
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK              (1 << 11)
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+/* PADCONF_WAKEUPEVENT_2 */
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        31
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 31)
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT         30
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 30)
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT          29
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 29)
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT          28
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 28)
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        27
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 27)
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT            25
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK             (1 << 25)
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT            24
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK             (1 << 24)
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT            23
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK             (1 << 23)
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            22
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 22)
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            21
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 21)
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            20
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 20)
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            19
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 19)
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT             18
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 18)
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             17
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 17)
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT         16
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK          (1 << 16)
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT         15
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK          (1 << 15)
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      14
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        13
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 13)
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     12
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 12)
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     11
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     10
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     9
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     8
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     7
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     6
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     5
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      4
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      3
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      2
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      1
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT        0
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK         (1 << 0)
+/* PADCONF_WAKEUPEVENT_3 */
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT             29
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK              (1 << 29)
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT             28
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 28)
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            27
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 27)
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             25
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 25)
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT                16
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK                 (1 << 16)
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT         6
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK          (1 << 6)
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT          5
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK           (1 << 5)
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        4
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 4)
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        3
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 3)
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT         2
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 2)
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT          1
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 1)
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+/* PADCONF_WAKEUPEVENT_4 */
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      29
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        28
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 28)
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     27
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 27)
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     26
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 26)
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     25
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     24
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 24)
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     23
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 23)
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     22
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 22)
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     21
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 21)
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     20
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 20)
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      19
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      18
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      17
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      16
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT             13
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 13)
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            12
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 12)
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            11
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 11)
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            9
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 9)
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            8
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 8)
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            7
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 7)
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            6
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 6)
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT          2
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK           (1 << 2)
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT           1
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK            (1 << 1)
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT         0
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK          (1 << 0)
+/* PADCONF_WAKEUPEVENT_5 */
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT              31
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK               (1 << 31)
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT              30
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK               (1 << 30)
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT               29
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK                (1 << 29)
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT               28
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK                (1 << 28)
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT               27
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK                (1 << 27)
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT               26
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK                (1 << 26)
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT             3
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 3)
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT             2
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 2)
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT             1
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 1)
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT             0
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 0)
+/* PADCONF_WAKEUPEVENT_6 */
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT              7
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK               (1 << 7)
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT              6
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK               (1 << 6)
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT              5
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK               (1 << 5)
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT              3
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK               (1 << 3)
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT              1
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK               (1 << 1)
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT              0
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK               (1 << 0)
+/* CONTROL_PADCONF_GLOBAL */
+#define OMAP4_FORCE_OFFMODE_EN_SHIFT                            31
+#define OMAP4_FORCE_OFFMODE_EN_MASK                             (1 << 31)
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_BANK0_SHIFT                               31
+#define OMAP4_VDDS_DV_BANK0_MASK                                (1 << 31)
+#define OMAP4_VDDS_DV_BANK1_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK1_MASK                                (1 << 30)
+#define OMAP4_VDDS_DV_BANK3_SHIFT                               29
+#define OMAP4_VDDS_DV_BANK3_MASK                                (1 << 29)
+#define OMAP4_VDDS_DV_BANK4_SHIFT                               28
+#define OMAP4_VDDS_DV_BANK4_MASK                                (1 << 28)
+#define OMAP4_VDDS_DV_BANK5_SHIFT                               27
+#define OMAP4_VDDS_DV_BANK5_MASK                                (1 << 27)
+#define OMAP4_VDDS_DV_BANK6_SHIFT                               26
+#define OMAP4_VDDS_DV_BANK6_MASK                                (1 << 26)
+#define OMAP4_VDDS_DV_C2C_SHIFT                                 25
+#define OMAP4_VDDS_DV_C2C_MASK                                  (1 << 25)
+#define OMAP4_VDDS_DV_CAM_SHIFT                                 24
+#define OMAP4_VDDS_DV_CAM_MASK                                  (1 << 24)
+#define OMAP4_VDDS_DV_GPMC_SHIFT                                23
+#define OMAP4_VDDS_DV_GPMC_MASK                                 (1 << 23)
+#define OMAP4_VDDS_DV_SDMMC2_SHIFT                              22
+#define OMAP4_VDDS_DV_SDMMC2_MASK                               (1 << 22)
+/* CONTROL_SMART1IO_PADCONF_0 */
+#define OMAP4_ABE_DR0_SC_SHIFT                                  30
+#define OMAP4_ABE_DR0_SC_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_SC_SHIFT                                  28
+#define OMAP4_CAM_DR0_SC_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_SC_SHIFT                                 26
+#define OMAP4_FREF_DR2_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_SC_SHIFT                                 24
+#define OMAP4_FREF_DR3_SC_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_SC_SHIFT                                 22
+#define OMAP4_GPIO_DR8_SC_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_SC_SHIFT                                 20
+#define OMAP4_GPIO_DR9_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_SC_SHIFT                                 18
+#define OMAP4_GPMC_DR2_SC_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_SC_SHIFT                                 16
+#define OMAP4_GPMC_DR3_SC_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_SC_SHIFT                                 14
+#define OMAP4_GPMC_DR6_SC_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_SC_SHIFT                                 12
+#define OMAP4_HDMI_DR0_SC_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_SC_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_SC_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_SC_SHIFT                                8
+#define OMAP4_UART1_DR0_SC_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_SC_SHIFT                                6
+#define OMAP4_UART3_DR0_SC_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_SC_SHIFT                                4
+#define OMAP4_UART3_DR1_SC_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_SC_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_SC_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_SC_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_SC_MASK                                (0x3 << 0)
+/* CONTROL_SMART1IO_PADCONF_1 */
+#define OMAP4_ABE_DR0_LB_SHIFT                                  30
+#define OMAP4_ABE_DR0_LB_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_LB_SHIFT                                  28
+#define OMAP4_CAM_DR0_LB_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_LB_SHIFT                                 26
+#define OMAP4_FREF_DR2_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_LB_SHIFT                                 24
+#define OMAP4_FREF_DR3_LB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_LB_SHIFT                                 22
+#define OMAP4_GPIO_DR8_LB_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_LB_SHIFT                                 20
+#define OMAP4_GPIO_DR9_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_LB_SHIFT                                 18
+#define OMAP4_GPMC_DR2_LB_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_LB_SHIFT                                 16
+#define OMAP4_GPMC_DR3_LB_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_LB_SHIFT                                 14
+#define OMAP4_GPMC_DR6_LB_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_LB_SHIFT                                 12
+#define OMAP4_HDMI_DR0_LB_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_LB_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_LB_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_LB_SHIFT                                8
+#define OMAP4_UART1_DR0_LB_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_LB_SHIFT                                6
+#define OMAP4_UART3_DR0_LB_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_LB_SHIFT                                4
+#define OMAP4_UART3_DR1_LB_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_LB_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_LB_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_LB_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_LB_MASK                                (0x3 << 0)
+/* CONTROL_SMART2IO_PADCONF_0 */
+#define OMAP4_C2C_DR0_LB_SHIFT                                  31
+#define OMAP4_C2C_DR0_LB_MASK                                   (1 << 31)
+#define OMAP4_DPM_DR1_LB_SHIFT                                  30
+#define OMAP4_DPM_DR1_LB_MASK                                   (1 << 30)
+#define OMAP4_DPM_DR2_LB_SHIFT                                  29
+#define OMAP4_DPM_DR2_LB_MASK                                   (1 << 29)
+#define OMAP4_DPM_DR3_LB_SHIFT                                  28
+#define OMAP4_DPM_DR3_LB_MASK                                   (1 << 28)
+#define OMAP4_GPIO_DR0_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR0_LB_MASK                                  (1 << 27)
+#define OMAP4_GPIO_DR1_LB_SHIFT                                 26
+#define OMAP4_GPIO_DR1_LB_MASK                                  (1 << 26)
+#define OMAP4_GPIO_DR10_LB_SHIFT                                25
+#define OMAP4_GPIO_DR10_LB_MASK                                 (1 << 25)
+#define OMAP4_GPIO_DR2_LB_SHIFT                                 24
+#define OMAP4_GPIO_DR2_LB_MASK                                  (1 << 24)
+#define OMAP4_GPMC_DR0_LB_SHIFT                                 23
+#define OMAP4_GPMC_DR0_LB_MASK                                  (1 << 23)
+#define OMAP4_GPMC_DR1_LB_SHIFT                                 22
+#define OMAP4_GPMC_DR1_LB_MASK                                  (1 << 22)
+#define OMAP4_GPMC_DR4_LB_SHIFT                                 21
+#define OMAP4_GPMC_DR4_LB_MASK                                  (1 << 21)
+#define OMAP4_GPMC_DR5_LB_SHIFT                                 20
+#define OMAP4_GPMC_DR5_LB_MASK                                  (1 << 20)
+#define OMAP4_GPMC_DR7_LB_SHIFT                                 19
+#define OMAP4_GPMC_DR7_LB_MASK                                  (1 << 19)
+#define OMAP4_HSI2_DR0_LB_SHIFT                                 18
+#define OMAP4_HSI2_DR0_LB_MASK                                  (1 << 18)
+#define OMAP4_HSI2_DR1_LB_SHIFT                                 17
+#define OMAP4_HSI2_DR1_LB_MASK                                  (1 << 17)
+#define OMAP4_HSI2_DR2_LB_SHIFT                                 16
+#define OMAP4_HSI2_DR2_LB_MASK                                  (1 << 16)
+#define OMAP4_KPD_DR0_LB_SHIFT                                  15
+#define OMAP4_KPD_DR0_LB_MASK                                   (1 << 15)
+#define OMAP4_KPD_DR1_LB_SHIFT                                  14
+#define OMAP4_KPD_DR1_LB_MASK                                   (1 << 14)
+#define OMAP4_PDM_DR0_LB_SHIFT                                  13
+#define OMAP4_PDM_DR0_LB_MASK                                   (1 << 13)
+#define OMAP4_SDMMC2_DR0_LB_SHIFT                               12
+#define OMAP4_SDMMC2_DR0_LB_MASK                                (1 << 12)
+#define OMAP4_SDMMC3_DR0_LB_SHIFT                               11
+#define OMAP4_SDMMC3_DR0_LB_MASK                                (1 << 11)
+#define OMAP4_SDMMC4_DR0_LB_SHIFT                               10
+#define OMAP4_SDMMC4_DR0_LB_MASK                                (1 << 10)
+#define OMAP4_SDMMC4_DR1_LB_SHIFT                               9
+#define OMAP4_SDMMC4_DR1_LB_MASK                                (1 << 9)
+#define OMAP4_SPI3_DR0_LB_SHIFT                                 8
+#define OMAP4_SPI3_DR0_LB_MASK                                  (1 << 8)
+#define OMAP4_SPI3_DR1_LB_SHIFT                                 7
+#define OMAP4_SPI3_DR1_LB_MASK                                  (1 << 7)
+#define OMAP4_UART3_DR2_LB_SHIFT                                6
+#define OMAP4_UART3_DR2_LB_MASK                                 (1 << 6)
+#define OMAP4_UART3_DR3_LB_SHIFT                                5
+#define OMAP4_UART3_DR3_LB_MASK                                 (1 << 5)
+#define OMAP4_UART3_DR4_LB_SHIFT                                4
+#define OMAP4_UART3_DR4_LB_MASK                                 (1 << 4)
+#define OMAP4_UART3_DR5_LB_SHIFT                                3
+#define OMAP4_UART3_DR5_LB_MASK                                 (1 << 3)
+#define OMAP4_USBA0_DR1_LB_SHIFT                                2
+#define OMAP4_USBA0_DR1_LB_MASK                                 (1 << 2)
+#define OMAP4_USBA_DR2_LB_SHIFT                                 1
+#define OMAP4_USBA_DR2_LB_MASK                                  (1 << 1)
+/* CONTROL_SMART2IO_PADCONF_1 */
+#define OMAP4_USBB1_DR0_LB_SHIFT                                31
+#define OMAP4_USBB1_DR0_LB_MASK                                 (1 << 31)
+#define OMAP4_USBB2_DR0_LB_SHIFT                                30
+#define OMAP4_USBB2_DR0_LB_MASK                                 (1 << 30)
+#define OMAP4_USBA0_DR0_LB_SHIFT                                29
+#define OMAP4_USBA0_DR0_LB_MASK                                 (1 << 29)
+/* CONTROL_SMART3IO_PADCONF_0 */
+#define OMAP4_DMIC_DR0_MB_SHIFT                                 30
+#define OMAP4_DMIC_DR0_MB_MASK                                  (0x3 << 30)
+#define OMAP4_GPIO_DR3_MB_SHIFT                                 28
+#define OMAP4_GPIO_DR3_MB_MASK                                  (0x3 << 28)
+#define OMAP4_GPIO_DR4_MB_SHIFT                                 26
+#define OMAP4_GPIO_DR4_MB_MASK                                  (0x3 << 26)
+#define OMAP4_GPIO_DR5_MB_SHIFT                                 24
+#define OMAP4_GPIO_DR5_MB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR6_MB_SHIFT                                 22
+#define OMAP4_GPIO_DR6_MB_MASK                                  (0x3 << 22)
+#define OMAP4_HSI_DR1_MB_SHIFT                                  20
+#define OMAP4_HSI_DR1_MB_MASK                                   (0x3 << 20)
+#define OMAP4_HSI_DR2_MB_SHIFT                                  18
+#define OMAP4_HSI_DR2_MB_MASK                                   (0x3 << 18)
+#define OMAP4_HSI_DR3_MB_SHIFT                                  16
+#define OMAP4_HSI_DR3_MB_MASK                                   (0x3 << 16)
+#define OMAP4_MCBSP2_DR0_MB_SHIFT                               14
+#define OMAP4_MCBSP2_DR0_MB_MASK                                (0x3 << 14)
+#define OMAP4_MCSPI4_DR0_MB_SHIFT                               12
+#define OMAP4_MCSPI4_DR0_MB_MASK                                (0x3 << 12)
+#define OMAP4_MCSPI4_DR1_MB_SHIFT                               10
+#define OMAP4_MCSPI4_DR1_MB_MASK                                (0x3 << 10)
+#define OMAP4_SDMMC3_DR0_MB_SHIFT                               8
+#define OMAP4_SDMMC3_DR0_MB_MASK                                (0x3 << 8)
+#define OMAP4_SPI2_DR0_MB_SHIFT                                 0
+#define OMAP4_SPI2_DR0_MB_MASK                                  (0x3 << 0)
+/* CONTROL_SMART3IO_PADCONF_1 */
+#define OMAP4_SPI2_DR1_MB_SHIFT                                 30
+#define OMAP4_SPI2_DR1_MB_MASK                                  (0x3 << 30)
+#define OMAP4_SPI2_DR2_MB_SHIFT                                 28
+#define OMAP4_SPI2_DR2_MB_MASK                                  (0x3 << 28)
+#define OMAP4_UART2_DR0_MB_SHIFT                                26
+#define OMAP4_UART2_DR0_MB_MASK                                 (0x3 << 26)
+#define OMAP4_UART2_DR1_MB_SHIFT                                24
+#define OMAP4_UART2_DR1_MB_MASK                                 (0x3 << 24)
+#define OMAP4_UART4_DR0_MB_SHIFT                                22
+#define OMAP4_UART4_DR0_MB_MASK                                 (0x3 << 22)
+#define OMAP4_HSI_DR0_MB_SHIFT                                  20
+#define OMAP4_HSI_DR0_MB_MASK                                   (0x3 << 20)
+/* CONTROL_SMART3IO_PADCONF_2 */
+#define OMAP4_DMIC_DR0_LB_SHIFT                                 31
+#define OMAP4_DMIC_DR0_LB_MASK                                  (1 << 31)
+#define OMAP4_GPIO_DR3_LB_SHIFT                                 30
+#define OMAP4_GPIO_DR3_LB_MASK                                  (1 << 30)
+#define OMAP4_GPIO_DR4_LB_SHIFT                                 29
+#define OMAP4_GPIO_DR4_LB_MASK                                  (1 << 29)
+#define OMAP4_GPIO_DR5_LB_SHIFT                                 28
+#define OMAP4_GPIO_DR5_LB_MASK                                  (1 << 28)
+#define OMAP4_GPIO_DR6_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR6_LB_MASK                                  (1 << 27)
+#define OMAP4_HSI_DR1_LB_SHIFT                                  26
+#define OMAP4_HSI_DR1_LB_MASK                                   (1 << 26)
+#define OMAP4_HSI_DR2_LB_SHIFT                                  25
+#define OMAP4_HSI_DR2_LB_MASK                                   (1 << 25)
+#define OMAP4_HSI_DR3_LB_SHIFT                                  24
+#define OMAP4_HSI_DR3_LB_MASK                                   (1 << 24)
+#define OMAP4_MCBSP2_DR0_LB_SHIFT                               23
+#define OMAP4_MCBSP2_DR0_LB_MASK                                (1 << 23)
+#define OMAP4_MCSPI4_DR0_LB_SHIFT                               22
+#define OMAP4_MCSPI4_DR0_LB_MASK                                (1 << 22)
+#define OMAP4_MCSPI4_DR1_LB_SHIFT                               21
+#define OMAP4_MCSPI4_DR1_LB_MASK                                (1 << 21)
+#define OMAP4_SLIMBUS2_DR0_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR0_LB_MASK                              (1 << 18)
+#define OMAP4_SPI2_DR0_LB_SHIFT                                 16
+#define OMAP4_SPI2_DR0_LB_MASK                                  (1 << 16)
+#define OMAP4_SPI2_DR1_LB_SHIFT                                 15
+#define OMAP4_SPI2_DR1_LB_MASK                                  (1 << 15)
+#define OMAP4_SPI2_DR2_LB_SHIFT                                 14
+#define OMAP4_SPI2_DR2_LB_MASK                                  (1 << 14)
+#define OMAP4_UART2_DR0_LB_SHIFT                                13
+#define OMAP4_UART2_DR0_LB_MASK                                 (1 << 13)
+#define OMAP4_UART2_DR1_LB_SHIFT                                12
+#define OMAP4_UART2_DR1_LB_MASK                                 (1 << 12)
+#define OMAP4_UART4_DR0_LB_SHIFT                                11
+#define OMAP4_UART4_DR0_LB_MASK                                 (1 << 11)
+#define OMAP4_HSI_DR0_LB_SHIFT                                  10
+#define OMAP4_HSI_DR0_LB_MASK                                   (1 << 10)
+/* CONTROL_USBB_HSIC */
+#define OMAP4_USBB2_DR1_SR_SHIFT                                30
+#define OMAP4_USBB2_DR1_SR_MASK                                 (0x3 << 30)
+#define OMAP4_USBB2_DR1_I_SHIFT                                 27
+#define OMAP4_USBB2_DR1_I_MASK                                  (0x7 << 27)
+#define OMAP4_USBB1_DR1_SR_SHIFT                                25
+#define OMAP4_USBB1_DR1_SR_MASK                                 (0x3 << 25)
+#define OMAP4_USBB1_DR1_I_SHIFT                                 22
+#define OMAP4_USBB1_DR1_I_MASK                                  (0x7 << 22)
+#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT                          20
+#define OMAP4_USBB1_HSIC_DATA_WD_MASK                           (0x3 << 20)
+#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT                        18
+#define OMAP4_USBB1_HSIC_STROBE_WD_MASK                         (0x3 << 18)
+#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT                          16
+#define OMAP4_USBB2_HSIC_DATA_WD_MASK                           (0x3 << 16)
+#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT                        14
+#define OMAP4_USBB2_HSIC_STROBE_WD_MASK                         (0x3 << 14)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           13
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 13)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT                  11
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 11)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         10
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 10)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT                8
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 8)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           7
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 7)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT                  5
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 5)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         4
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 4)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT                2
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 2)
+/* CONTROL_SLIMBUS */
+#define OMAP4_SLIMBUS1_DR0_MB_SHIFT                             30
+#define OMAP4_SLIMBUS1_DR0_MB_MASK                              (0x3 << 30)
+#define OMAP4_SLIMBUS1_DR1_MB_SHIFT                             28
+#define OMAP4_SLIMBUS1_DR1_MB_MASK                              (0x3 << 28)
+#define OMAP4_SLIMBUS2_DR0_MB_SHIFT                             26
+#define OMAP4_SLIMBUS2_DR0_MB_MASK                              (0x3 << 26)
+#define OMAP4_SLIMBUS2_DR1_MB_SHIFT                             24
+#define OMAP4_SLIMBUS2_DR1_MB_MASK                              (0x3 << 24)
+#define OMAP4_SLIMBUS2_DR2_MB_SHIFT                             22
+#define OMAP4_SLIMBUS2_DR2_MB_MASK                              (0x3 << 22)
+#define OMAP4_SLIMBUS2_DR3_MB_SHIFT                             20
+#define OMAP4_SLIMBUS2_DR3_MB_MASK                              (0x3 << 20)
+#define OMAP4_SLIMBUS1_DR0_LB_SHIFT                             19
+#define OMAP4_SLIMBUS1_DR0_LB_MASK                              (1 << 19)
+#define OMAP4_SLIMBUS2_DR1_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR1_LB_MASK                              (1 << 18)
+/* CONTROL_PBIASLITE */
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT                     31
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK                      (1 << 31)
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT                30
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 30)
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT                  29
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK                   (1 << 29)
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT                       28
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK                        (1 << 28)
+#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT                        27
+#define OMAP4_USIM_PBIASLITE_VMODE_MASK                         (1 << 27)
+#define OMAP4_MMC1_PWRDNZ_SHIFT                                 26
+#define OMAP4_MMC1_PWRDNZ_MASK                                  (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT                     25
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK                      (1 << 25)
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT                24
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 24)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT                  23
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK                   (1 << 23)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT                       22
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK                        (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT                        21
+#define OMAP4_MMC1_PBIASLITE_VMODE_MASK                         (1 << 21)
+#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT                          20
+#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK                           (1 << 20)
+/* CONTROL_I2C_0 */
+#define OMAP4_I2C4_SDA_GLFENB_SHIFT                             31
+#define OMAP4_I2C4_SDA_GLFENB_MASK                              (1 << 31)
+#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT                          29
+#define OMAP4_I2C4_SDA_LOAD_BITS_MASK                           (0x3 << 29)
+#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT                         28
+#define OMAP4_I2C4_SDA_PULLUPRESX_MASK                          (1 << 28)
+#define OMAP4_I2C3_SDA_GLFENB_SHIFT                             27
+#define OMAP4_I2C3_SDA_GLFENB_MASK                              (1 << 27)
+#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT                          25
+#define OMAP4_I2C3_SDA_LOAD_BITS_MASK                           (0x3 << 25)
+#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT                         24
+#define OMAP4_I2C3_SDA_PULLUPRESX_MASK                          (1 << 24)
+#define OMAP4_I2C2_SDA_GLFENB_SHIFT                             23
+#define OMAP4_I2C2_SDA_GLFENB_MASK                              (1 << 23)
+#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT                          21
+#define OMAP4_I2C2_SDA_LOAD_BITS_MASK                           (0x3 << 21)
+#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT                         20
+#define OMAP4_I2C2_SDA_PULLUPRESX_MASK                          (1 << 20)
+#define OMAP4_I2C1_SDA_GLFENB_SHIFT                             19
+#define OMAP4_I2C1_SDA_GLFENB_MASK                              (1 << 19)
+#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT                          17
+#define OMAP4_I2C1_SDA_LOAD_BITS_MASK                           (0x3 << 17)
+#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT                         16
+#define OMAP4_I2C1_SDA_PULLUPRESX_MASK                          (1 << 16)
+#define OMAP4_I2C4_SCL_GLFENB_SHIFT                             15
+#define OMAP4_I2C4_SCL_GLFENB_MASK                              (1 << 15)
+#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT                          13
+#define OMAP4_I2C4_SCL_LOAD_BITS_MASK                           (0x3 << 13)
+#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT                         12
+#define OMAP4_I2C4_SCL_PULLUPRESX_MASK                          (1 << 12)
+#define OMAP4_I2C3_SCL_GLFENB_SHIFT                             11
+#define OMAP4_I2C3_SCL_GLFENB_MASK                              (1 << 11)
+#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT                          9
+#define OMAP4_I2C3_SCL_LOAD_BITS_MASK                           (0x3 << 9)
+#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT                         8
+#define OMAP4_I2C3_SCL_PULLUPRESX_MASK                          (1 << 8)
+#define OMAP4_I2C2_SCL_GLFENB_SHIFT                             7
+#define OMAP4_I2C2_SCL_GLFENB_MASK                              (1 << 7)
+#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT                          5
+#define OMAP4_I2C2_SCL_LOAD_BITS_MASK                           (0x3 << 5)
+#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT                         4
+#define OMAP4_I2C2_SCL_PULLUPRESX_MASK                          (1 << 4)
+#define OMAP4_I2C1_SCL_GLFENB_SHIFT                             3
+#define OMAP4_I2C1_SCL_GLFENB_MASK                              (1 << 3)
+#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT                          1
+#define OMAP4_I2C1_SCL_LOAD_BITS_MASK                           (0x3 << 1)
+#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT                         0
+#define OMAP4_I2C1_SCL_PULLUPRESX_MASK                          (1 << 0)
+/* CONTROL_CAMERA_RX */
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT                   31
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK                    (1 << 31)
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT                   29
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK                    (0x3 << 29)
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT                   24
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK                    (0x1f << 24)
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT                     22
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK                      (0x3 << 22)
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT                    21
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK                     (1 << 21)
+#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT                      19
+#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK                       (0x3 << 19)
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT                    18
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK                     (1 << 18)
+#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT                      16
+#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK                       (0x3 << 16)
+/* CONTROL_AVDAC */
+#define OMAP4_AVDAC_ACEN_SHIFT                                  31
+#define OMAP4_AVDAC_ACEN_MASK                                   (1 << 31)
+#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT                           30
+#define OMAP4_AVDAC_TVOUTBYPASS_MASK                            (1 << 30)
+#define OMAP4_AVDAC_INPUTINV_SHIFT                              29
+#define OMAP4_AVDAC_INPUTINV_MASK                               (1 << 29)
+#define OMAP4_AVDAC_CTL_SHIFT                                   13
+#define OMAP4_AVDAC_CTL_MASK                                    (0xffff << 13)
+#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                            12
+#define OMAP4_AVDAC_CTL_WR_ACK_MASK                             (1 << 12)
+/* CONTROL_HDMI_TX_PHY */
+#define OMAP4_HDMITXPHY_PADORDER_SHIFT                          31
+#define OMAP4_HDMITXPHY_PADORDER_MASK                           (1 << 31)
+#define OMAP4_HDMITXPHY_TXVALID_SHIFT                           30
+#define OMAP4_HDMITXPHY_TXVALID_MASK                            (1 << 30)
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT                       29
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK                        (1 << 29)
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT                      28
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK                       (1 << 28)
+/* CONTROL_MMC2 */
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT                       31
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK                        (1 << 31)
+/* CONTROL_DSIPHY */
+#define OMAP4_DSI2_LANEENABLE_SHIFT                             29
+#define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT                             24
+#define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
+/* CONTROL_MCBSPLP */
+#define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
+#define OMAP4_ALBCTRLRX_FSX_MASK                                (1 << 31)
+#define OMAP4_ALBCTRLRX_CLKX_SHIFT                              30
+#define OMAP4_ALBCTRLRX_CLKX_MASK                               (1 << 30)
+#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                            29
+#define OMAP4_ABE_MCBSP1_DR_EN_MASK                             (1 << 29)
+/* CONTROL_USB2PHYCORE */
+#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT                       31
+#define OMAP4_USB2PHY_AUTORESUME_EN_MASK                        (1 << 31)
+#define OMAP4_USB2PHY_DISCHGDET_SHIFT                           30
+#define OMAP4_USB2PHY_DISCHGDET_MASK                            (1 << 30)
+#define OMAP4_USB2PHY_GPIOMODE_SHIFT                            29
+#define OMAP4_USB2PHY_GPIOMODE_MASK                             (1 << 29)
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT                     28
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK                      (1 << 28)
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT                    27
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK                     (1 << 27)
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT                    26
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK                     (1 << 26)
+#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT                         25
+#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK                          (1 << 25)
+#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT                        24
+#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK                         (1 << 24)
+#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT                      21
+#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK                       (0x7 << 21)
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT                     20
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK                      (1 << 20)
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT                     19
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK                      (1 << 19)
+#define OMAP4_USB2PHY_DATADET_SHIFT                             18
+#define OMAP4_USB2PHY_DATADET_MASK                              (1 << 18)
+#define OMAP4_USB2PHY_SINKONDP_SHIFT                            17
+#define OMAP4_USB2PHY_SINKONDP_MASK                             (1 << 17)
+#define OMAP4_USB2PHY_SRCONDM_SHIFT                             16
+#define OMAP4_USB2PHY_SRCONDM_MASK                              (1 << 16)
+#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT                       15
+#define OMAP4_USB2PHY_RESTARTCHGDET_MASK                        (1 << 15)
+#define OMAP4_USB2PHY_CHGDETDONE_SHIFT                          14
+#define OMAP4_USB2PHY_CHGDETDONE_MASK                           (1 << 14)
+#define OMAP4_USB2PHY_CHGDETECTED_SHIFT                         13
+#define OMAP4_USB2PHY_CHGDETECTED_MASK                          (1 << 13)
+#define OMAP4_USB2PHY_MCPCPUEN_SHIFT                            12
+#define OMAP4_USB2PHY_MCPCPUEN_MASK                             (1 << 12)
+#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT                          11
+#define OMAP4_USB2PHY_MCPCMODEEN_MASK                           (1 << 11)
+#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT                       10
+#define OMAP4_USB2PHY_RESETDONEMCLK_MASK                        (1 << 10)
+#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT                       9
+#define OMAP4_USB2PHY_UTMIRESETDONE_MASK                        (1 << 9)
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT                    8
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK                     (1 << 8)
+#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT                       7
+#define OMAP4_USB2PHY_DATAPOLARITYN_MASK                        (1 << 7)
+#define OMAP4_USBDPLL_FREQLOCK_SHIFT                            6
+#define OMAP4_USBDPLL_FREQLOCK_MASK                             (1 << 6)
+#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT                       5
+#define OMAP4_USB2PHY_RESETDONETCLK_MASK                        (1 << 5)
+/* CONTROL_I2C_1 */
+#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT                         31
+#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK                          (1 << 31)
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT                      29
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK                       (0x3 << 29)
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT                     28
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK                      (1 << 28)
+#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT                         27
+#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK                          (1 << 27)
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT                      25
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK                       (0x3 << 25)
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT                     24
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK                      (1 << 24)
+#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT                         23
+#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK                          (1 << 23)
+#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT                          22
+#define OMAP4_HDMI_DDC_SDA_NMODE_MASK                           (1 << 22)
+#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT                         21
+#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK                          (1 << 21)
+#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT                          20
+#define OMAP4_HDMI_DDC_SCL_NMODE_MASK                           (1 << 20)
+/* CONTROL_MMC1 */
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT                      31
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK                       (1 << 31)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT                      30
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK                       (1 << 30)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT                      29
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK                       (1 << 29)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT                      28
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK                       (1 << 28)
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT                        27
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK                         (1 << 27)
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT                        26
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK                         (1 << 26)
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT                        25
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK                         (1 << 25)
+#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT                         24
+#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK                          (1 << 24)
+#define OMAP4_USB_FD_CDEN_SHIFT                                 23
+#define OMAP4_USB_FD_CDEN_MASK                                  (1 << 23)
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT                        22
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK                         (1 << 22)
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT                        21
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK                         (1 << 21)
+/* CONTROL_HSI */
+#define OMAP4_HSI1_CALLOOP_SEL_SHIFT                            31
+#define OMAP4_HSI1_CALLOOP_SEL_MASK                             (1 << 31)
+#define OMAP4_HSI1_CALMUX_SEL_SHIFT                             30
+#define OMAP4_HSI1_CALMUX_SEL_MASK                              (1 << 30)
+#define OMAP4_HSI2_CALLOOP_SEL_SHIFT                            29
+#define OMAP4_HSI2_CALLOOP_SEL_MASK                             (1 << 29)
+#define OMAP4_HSI2_CALMUX_SEL_SHIFT                             28
+#define OMAP4_HSI2_CALMUX_SEL_MASK                              (1 << 28)
+/* CONTROL_USB */
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT           31
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK            (1 << 31)
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT           30
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK            (1 << 30)
+/* CONTROL_HDQ */
+#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT                              31
+#define OMAP4_HDQ_SIO_PWRDNZ_MASK                               (1 << 31)
+/* CONTROL_LPDDR2IO1_0 */
+#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR1_WD_MASK                             (0x3 << 1)
+/* CONTROL_LPDDR2IO1_1 */
+#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR5_WD_MASK                             (0x3 << 1)
+/* CONTROL_LPDDR2IO1_2 */
+#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO1_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO1_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO1_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO1_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO1_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO1_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR9_WD_MASK                             (0x3 << 9)
+/* CONTROL_LPDDR2IO1_3 */
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK                         (1 << 12)
+/* CONTROL_LPDDR2IO2_0 */
+#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR1_WD_MASK                             (0x3 << 1)
+/* CONTROL_LPDDR2IO2_1 */
+#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR5_WD_MASK                             (0x3 << 1)
+/* CONTROL_LPDDR2IO2_2 */
+#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO2_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO2_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO2_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO2_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO2_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO2_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR9_WD_MASK                             (0x3 << 9)
+/* CONTROL_LPDDR2IO2_3 */
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK                         (1 << 12)
+/* CONTROL_BUS_HOLD */
+#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                            31
+#define OMAP4_ABE_DMIC_DIN3_EN_MASK                             (1 << 31)
+#define OMAP4_MCSPI1_CS3_EN_SHIFT                               30
+#define OMAP4_MCSPI1_CS3_EN_MASK                                (1 << 30)
+/* CONTROL_C2C */
+#define OMAP4_MIRROR_MODE_EN_SHIFT                              31
+#define OMAP4_MIRROR_MODE_EN_MASK                               (1 << 31)
+#define OMAP4_C2C_SPARE_SHIFT                                   24
+#define OMAP4_C2C_SPARE_MASK                                    (0x7f << 24)
+/* CORE_CONTROL_SPARE_RW */
+#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_CORE_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+/* CORE_CONTROL_SPARE_R */
+#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_CORE_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+/* CORE_CONTROL_SPARE_R_C0 */
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+/* CONTROL_EFUSE_1 */
+#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                            24
+#define OMAP4_AVDAC_TRIM_BYTE3_MASK                             (0x7f << 24)
+#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                            16
+#define OMAP4_AVDAC_TRIM_BYTE2_MASK                             (0xff << 16)
+#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                            8
+#define OMAP4_AVDAC_TRIM_BYTE1_MASK                             (0xff << 8)
+#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                            0
+#define OMAP4_AVDAC_TRIM_BYTE0_MASK                             (0xff << 0)
+/* CONTROL_EFUSE_2 */
+#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT                         31
+#define OMAP4_EFUSE_SMART2TEST_P0_MASK                          (1 << 31)
+#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT                         30
+#define OMAP4_EFUSE_SMART2TEST_P1_MASK                          (1 << 30)
+#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT                         29
+#define OMAP4_EFUSE_SMART2TEST_P2_MASK                          (1 << 29)
+#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT                         28
+#define OMAP4_EFUSE_SMART2TEST_P3_MASK                          (1 << 28)
+#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT                         27
+#define OMAP4_EFUSE_SMART2TEST_N0_MASK                          (1 << 27)
+#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT                         26
+#define OMAP4_EFUSE_SMART2TEST_N1_MASK                          (1 << 26)
+#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT                         25
+#define OMAP4_EFUSE_SMART2TEST_N2_MASK                          (1 << 25)
+#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT                         24
+#define OMAP4_EFUSE_SMART2TEST_N3_MASK                          (1 << 24)
+#define OMAP4_LPDDR2_PTV_N1_SHIFT                               23
+#define OMAP4_LPDDR2_PTV_N1_MASK                                (1 << 23)
+#define OMAP4_LPDDR2_PTV_N2_SHIFT                               22
+#define OMAP4_LPDDR2_PTV_N2_MASK                                (1 << 22)
+#define OMAP4_LPDDR2_PTV_N3_SHIFT                               21
+#define OMAP4_LPDDR2_PTV_N3_MASK                                (1 << 21)
+#define OMAP4_LPDDR2_PTV_N4_SHIFT                               20
+#define OMAP4_LPDDR2_PTV_N4_MASK                                (1 << 20)
+#define OMAP4_LPDDR2_PTV_N5_SHIFT                               19
+#define OMAP4_LPDDR2_PTV_N5_MASK                                (1 << 19)
+#define OMAP4_LPDDR2_PTV_P1_SHIFT                               18
+#define OMAP4_LPDDR2_PTV_P1_MASK                                (1 << 18)
+#define OMAP4_LPDDR2_PTV_P2_SHIFT                               17
+#define OMAP4_LPDDR2_PTV_P2_MASK                                (1 << 17)
+#define OMAP4_LPDDR2_PTV_P3_SHIFT                               16
+#define OMAP4_LPDDR2_PTV_P3_MASK                                (1 << 16)
+#define OMAP4_LPDDR2_PTV_P4_SHIFT                               15
+#define OMAP4_LPDDR2_PTV_P4_MASK                                (1 << 15)
+#define OMAP4_LPDDR2_PTV_P5_SHIFT                               14
+#define OMAP4_LPDDR2_PTV_P5_MASK                                (1 << 14)
+/* CONTROL_EFUSE_3 */
+#define OMAP4_STD_FUSE_SPARE_1_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_1_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_2_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_2_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_3_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_3_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_4_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_4_MASK                             (0xff << 0)
+/* CONTROL_EFUSE_4 */
+#define OMAP4_STD_FUSE_SPARE_5_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_5_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_6_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_6_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_7_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_7_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_8_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_8_MASK                             (0xff << 0)
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 00000000000..17c9b37042c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP                                      0x4a31e000
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION                          0x0000
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO                            0x0004
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG                         0x0010
+#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0                0x007c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1       0x05a4
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE                 0x05a8
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR              0x05ac
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO                       0x0600
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2                        0x0604
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG                         0x0608
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS                          0x060c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW                0x0614
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R                 0x0618
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0              0x061c
+/* Registers shifts and masks */
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT          22
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK           (1 << 22)
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT             19
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK              (1 << 19)
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT    16
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK     (1 << 16)
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT            15
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK             (1 << 15)
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT                13
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK                 (1 << 13)
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT          12
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 12)
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT         7
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK          (1 << 7)
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT                 6
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK                  (1 << 6)
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT                 5
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK                  (1 << 5)
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT            4
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK             (1 << 4)
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT                 3
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK                  (1 << 3)
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT                1
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK                 (1 << 1)
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT                 0
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK                  (1 << 0)
+/* CONTROL_SMART1NOPMIO_PADCONF_0 */
+#define OMAP4_FREF_DR0_SC_SHIFT                                 30
+#define OMAP4_FREF_DR0_SC_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_SC_SHIFT                                 28
+#define OMAP4_FREF_DR1_SC_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_SC_SHIFT                                 26
+#define OMAP4_FREF_DR4_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_SC_SHIFT                                 24
+#define OMAP4_FREF_DR5_SC_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_SC_SHIFT                                 22
+#define OMAP4_FREF_DR6_SC_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_SC_SHIFT                                 20
+#define OMAP4_FREF_DR7_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_SC_SHIFT                                 18
+#define OMAP4_GPIO_DR7_SC_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_SC_SHIFT                                  14
+#define OMAP4_DPM_DR0_SC_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_SC_SHIFT                                  12
+#define OMAP4_SIM_DR0_SC_MASK                                   (0x3 << 12)
+/* CONTROL_SMART1NOPMIO_PADCONF_1 */
+#define OMAP4_FREF_DR0_LB_SHIFT                                 30
+#define OMAP4_FREF_DR0_LB_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_LB_SHIFT                                 28
+#define OMAP4_FREF_DR1_LB_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_LB_SHIFT                                 26
+#define OMAP4_FREF_DR4_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_LB_SHIFT                                 24
+#define OMAP4_FREF_DR5_LB_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_LB_SHIFT                                 22
+#define OMAP4_FREF_DR6_LB_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_LB_SHIFT                                 20
+#define OMAP4_FREF_DR7_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_LB_SHIFT                                 18
+#define OMAP4_GPIO_DR7_LB_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_LB_SHIFT                                  14
+#define OMAP4_DPM_DR0_LB_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_LB_SHIFT                                  12
+#define OMAP4_SIM_DR0_LB_MASK                                   (0x3 << 12)
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_FREF_SHIFT                                31
+#define OMAP4_VDDS_DV_FREF_MASK                                 (1 << 31)
+#define OMAP4_VDDS_DV_BANK2_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK2_MASK                                (1 << 30)
+/* CONTROL_XTAL_OSCILLATOR */
+#define OMAP4_OSCILLATOR_BOOST_SHIFT                            31
+#define OMAP4_OSCILLATOR_BOOST_MASK                             (1 << 31)
+#define OMAP4_OSCILLATOR_OS_OUT_SHIFT                           30
+#define OMAP4_OSCILLATOR_OS_OUT_MASK                            (1 << 30)
+/* CONTROL_USIMIO */
+#define OMAP4_PAD_USIM_CLK_LOW_SHIFT                            31
+#define OMAP4_PAD_USIM_CLK_LOW_MASK                             (1 << 31)
+#define OMAP4_PAD_USIM_RST_LOW_SHIFT                            29
+#define OMAP4_PAD_USIM_RST_LOW_MASK                             (1 << 29)
+#define OMAP4_USIM_PWRDNZ_SHIFT                                 28
+#define OMAP4_USIM_PWRDNZ_MASK                                  (1 << 28)
+/* CONTROL_I2C_2 */
+#define OMAP4_SR_SDA_GLFENB_SHIFT                               31
+#define OMAP4_SR_SDA_GLFENB_MASK                                (1 << 31)
+#define OMAP4_SR_SDA_LOAD_BITS_SHIFT                            29
+#define OMAP4_SR_SDA_LOAD_BITS_MASK                             (0x3 << 29)
+#define OMAP4_SR_SDA_PULLUPRESX_SHIFT                           28
+#define OMAP4_SR_SDA_PULLUPRESX_MASK                            (1 << 28)
+#define OMAP4_SR_SCL_GLFENB_SHIFT                               27
+#define OMAP4_SR_SCL_GLFENB_MASK                                (1 << 27)
+#define OMAP4_SR_SCL_LOAD_BITS_SHIFT                            25
+#define OMAP4_SR_SCL_LOAD_BITS_MASK                             (0x3 << 25)
+#define OMAP4_SR_SCL_PULLUPRESX_SHIFT                           24
+#define OMAP4_SR_SCL_PULLUPRESX_MASK                            (1 << 24)
+/* CONTROL_JTAG */
+#define OMAP4_JTAG_NTRST_EN_SHIFT                               31
+#define OMAP4_JTAG_NTRST_EN_MASK                                (1 << 31)
+#define OMAP4_JTAG_TCK_EN_SHIFT                                 30
+#define OMAP4_JTAG_TCK_EN_MASK                                  (1 << 30)
+#define OMAP4_JTAG_RTCK_EN_SHIFT                                29
+#define OMAP4_JTAG_RTCK_EN_MASK                                 (1 << 29)
+#define OMAP4_JTAG_TDI_EN_SHIFT                                 28
+#define OMAP4_JTAG_TDI_EN_MASK                                  (1 << 28)
+#define OMAP4_JTAG_TDO_EN_SHIFT                                 27
+#define OMAP4_JTAG_TDO_EN_MASK                                  (1 << 27)
+/* CONTROL_SYS */
+#define OMAP4_SYS_NRESWARM_PIPU_SHIFT                           31
+#define OMAP4_SYS_NRESWARM_PIPU_MASK                            (1 << 31)
+/* WKUP_CONTROL_SPARE_RW */
+#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+/* WKUP_CONTROL_SPARE_R */
+#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_WKUP_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+/* WKUP_CONTROL_SPARE_R_C0 */
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 00000000000..a0af9baec3f
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
+/*
+ * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+/* Base address */
+#define OMAP4_CTRL_MODULE_WKUP                          0x4a30c000
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION              0x0000
+#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO                0x0004
+#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG             0x0010
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0     0x0460
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1     0x0464
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2     0x0468
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3     0x046c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4     0x0470
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5     0x0474
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6     0x0478
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7     0x047c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8     0x0480
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9     0x0484
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10    0x0488
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11    0x048c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12    0x0490
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13    0x0494
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14    0x0498
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15    0x049c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16    0x04a0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17    0x04a4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18    0x04a8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19    0x04ac
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20    0x04b0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21    0x04b4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22    0x04b8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23    0x04bc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24    0x04c0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25    0x04c4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26    0x04c8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27    0x04cc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28    0x04d0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29    0x04d4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30    0x04d8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31    0x04dc
+/* Registers shifts and masks */
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT               30
+#define OMAP4_IP_REV_SCHEME_MASK                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                 16
+#define OMAP4_IP_REV_FUNC_MASK                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                  11
+#define OMAP4_IP_REV_RTL_MASK                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                8
+#define OMAP4_IP_REV_MAJOR_MASK                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT               6
+#define OMAP4_IP_REV_CUSTOM_MASK                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                0
+#define OMAP4_IP_REV_MINOR_MASK                 (0x3f << 0)
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                   0
+#define OMAP4_IP_HWINFO_MASK                    (0xffffffff << 0)
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK        (0x3 << 2)
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_WKUP_MODE_SHIFT                   0
+#define OMAP4_WKUP_MODE_MASK                            (1 << 0)
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
new file mode 100644
index 00000000000..ceb8b7e593d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -0,0 +1,167 @@
+/*
+ * arch/arm/plat-omap/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for OMAP-based platforms
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/irqs.h>
+#include <asm/hardware/gic.h>
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
+#include <plat/multi.h>
+#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
+                .macro  disable_fiq
+                .endm
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+/*
+ * Unoptimized irq functions for multi-omap2, 3 and 4
+ */
+#ifdef MULTI_OMAP2
+                /*
+                 * Configure the interrupt base on the first interrupt.
+                 * See also omap_irq_base_init for setting omap_irq_base.
+                 */
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =omap_irq_base   @ irq base address
+                ldr     \base, [\base, #0]      @ irq base value
+                .endm
+                /* Check the pending interrupts. Note that base already set */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                tst     \base, #0x100           @ gic address?
+                bne     4401f                   @ found gic
+                /* Handle omap2 and omap3 */
+                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+                cmp     \irqnr, #0x0
+                bne     9998f
+                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+                cmp     \irqnr, #0x0
+                bne     9998f
+                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+                cmp     \irqnr, #0x0
+                bne     9998f
+                /*
+                 * ti816x has additional IRQ pending register. Checking this
+                 * register on omap2 & omap3 has no effect (read as 0).
+                 */
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
+9998:
+                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+                b       9999f
+                /* Handle omap4 */
+4401:           ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+9999:
+                .endm
+#ifdef CONFIG_SMP
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt
+                 * on the controller, since this requires the original irqstat
+                 * value which we won't easily be able to recreate later.
+                 */
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                it      cc
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                it      cs
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* As above, this assumes that irqstat and base are preserved */
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                itt     eq
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
+#endif  /* CONFIG_SMP */
+#else   /* MULTI_OMAP2 */
+/*
+ * Optimized irq functions for omap2, 3 and 4
+ */
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+                .macro  get_irqnr_preamble, base, tmp
+#ifdef CONFIG_ARCH_OMAP2
+                ldr     \base, =OMAP2_IRQ_BASE
+#else
+                ldr     \base, =OMAP3_IRQ_BASE
+#endif
+                .endm
+                /* Check the pending interrupts. Note that base already set */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+                cmp     \irqnr, #0x0
+                bne     9999f
+                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+                cmp     \irqnr, #0x0
+                bne     9999f
+                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+                cmp     \irqnr, #0x0
+#ifdef CONFIG_SOC_OMAPTI816X
+                bne     9999f
+                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+                cmp     \irqnr, #0x0
+#endif
+9999:
+                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+                .endm
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =OMAP4_IRQ_BASE
+                .endm
+#endif
+#endif  /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
new file mode 100644
index 00000000000..be4d290d57e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-omap2/include/mach/gpio.h
+ */
+#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h
new file mode 100644
index 00000000000..02ed3aa56f1
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/id.h
@@ -0,0 +1,22 @@
+/*
+ * OMAP2 CPU identification code
+ *
+ * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP2_ARCH_ID_H
+#define OMAP2_ARCH_ID_H
+struct omap_die_id {
+        u32 id_0;
+        u32 id_1;
+        u32 id_2;
+        u32 id_3;
+};
+void omap_get_die_id(struct omap_die_id *odi);
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
new file mode 100644
index 00000000000..fd78f31aa1a
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-omap2/include/mach/io.h
+ */
+#include <plat/io.h>
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h
new file mode 100644
index 00000000000..ca6d32a917d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/memory.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-omap2/include/mach/memory.h
+ */
+#include <plat/memory.h>
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
new file mode 100644
index 00000000000..e4bd8761973
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -0,0 +1,43 @@
+/*
+ * omap4-common.h: OMAP4 specific common header file
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_COMMON_H
+#define OMAP_ARCH_OMAP4_COMMON_H
+/*
+ * wfi used in low power code. Directly opcode is used instead
+ * of instruction to avoid mulit-omap build break
+ */
+#ifdef CONFIG_THUMB2_KERNEL
+#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define do_wfi()                        \
+                __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
+#endif
+#ifdef CONFIG_CACHE_L2X0
+extern void __iomem *l2cache_base;
+#endif
+extern void __iomem *gic_dist_base_addr;
+extern void __init gic_init_irq(void);
+extern void omap_smc1(u32 fn, u32 arg);
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
new file mode 100644
index 00000000000..323675f21b6
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/smp.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-omap2/include/mach/smp.h
+ */
+#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
new file mode 100644
index 00000000000..d488721ab90
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/system.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-omap2/include/mach/system.h
+ */
+#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
new file mode 100644
index 00000000000..86631994776
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/plat-omap/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END       0xf8000000UL
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
new file mode 100644
index 00000000000..fd230c6cded
--- /dev/null
+++ b/arch/arm/mach-omap2/io.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_OMAP2_IO_H__
+#define __MACH_OMAP2_IO_H__
+extern int __init omap_sram_init(void);
+#endif /*  __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
new file mode 100644
index 00000000000..eefc37912ef
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -0,0 +1,361 @@
+/*
+ * omap iommu: omap2/3 architecture specific functions
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
+ *              Paul Mundt and Toshihiro Kobayashi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/stringify.h>
+#include <plat/iommu.h>
+/*
+ * omap2 architecture specific register bit definitions
+ */
+#define IOMMU_ARCH_VERSION      0x00000011
+/* SYSCONF */
+#define MMU_SYS_IDLE_SHIFT      3
+#define MMU_SYS_IDLE_FORCE      (0 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_NONE       (1 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_SMART      (2 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_MASK       (3 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_SOFTRESET       (1 << 1)
+#define MMU_SYS_AUTOIDLE        1
+/* SYSSTATUS */
+#define MMU_SYS_RESETDONE       1
+/* IRQSTATUS & IRQENABLE */
+#define MMU_IRQ_MULTIHITFAULT   (1 << 4)
+#define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
+#define MMU_IRQ_EMUMISS         (1 << 2)
+#define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
+#define MMU_IRQ_TLBMISS         (1 << 0)
+#define __MMU_IRQ_FAULT         \
+        (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
+#define MMU_IRQ_MASK            \
+        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
+#define MMU_IRQ_TWL_MASK        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
+#define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
+/* MMU_CNTL */
+#define MMU_CNTL_SHIFT          1
+#define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
+#define MMU_CNTL_EML_TLB        (1 << 3)
+#define MMU_CNTL_TWL_EN         (1 << 2)
+#define MMU_CNTL_MMU_EN         (1 << 1)
+#define get_cam_va_mask(pgsz)                           \
+        (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
+static void __iommu_set_twl(struct omap_iommu *obj, bool on)
+{
+        u32 l = iommu_read_reg(obj, MMU_CNTL);
+        if (on)
+                iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
+        else
+                iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+        l &= ~MMU_CNTL_MASK;
+        if (on)
+                l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+        else
+                l |= (MMU_CNTL_MMU_EN);
+        iommu_write_reg(obj, l, MMU_CNTL);
+}
+static int omap2_iommu_enable(struct omap_iommu *obj)
+{
+        u32 l, pa;
+        unsigned long timeout;
+        if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
+                return -EINVAL;
+        pa = virt_to_phys(obj->iopgd);
+        if (!IS_ALIGNED(pa, SZ_16K))
+                return -EINVAL;
+        iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
+        timeout = jiffies + msecs_to_jiffies(20);
+        do {
+                l = iommu_read_reg(obj, MMU_SYSSTATUS);
+                if (l & MMU_SYS_RESETDONE)
+                        break;
+        } while (!time_after(jiffies, timeout));
+        if (!(l & MMU_SYS_RESETDONE)) {
+                dev_err(obj->dev, "can't take mmu out of reset\n");
+                return -ENODEV;
+        }
+        l = iommu_read_reg(obj, MMU_REVISION);
+        dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
+                 (l >> 4) & 0xf, l & 0xf);
+        l = iommu_read_reg(obj, MMU_SYSCONFIG);
+        l &= ~MMU_SYS_IDLE_MASK;
+        l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
+        iommu_write_reg(obj, l, MMU_SYSCONFIG);
+        iommu_write_reg(obj, pa, MMU_TTB);
+        __iommu_set_twl(obj, true);
+        return 0;
+}
+static void omap2_iommu_disable(struct omap_iommu *obj)
+{
+        u32 l = iommu_read_reg(obj, MMU_CNTL);
+        l &= ~MMU_CNTL_MASK;
+        iommu_write_reg(obj, l, MMU_CNTL);
+        iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
+        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
+}
+static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
+{
+        __iommu_set_twl(obj, false);
+}
+static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
+{
+        u32 stat, da;
+        u32 errs = 0;
+        stat = iommu_read_reg(obj, MMU_IRQSTATUS);
+        stat &= MMU_IRQ_MASK;
+        if (!stat) {
+                *ra = 0;
+                return 0;
+        }
+        da = iommu_read_reg(obj, MMU_FAULT_AD);
+        *ra = da;
+        if (stat & MMU_IRQ_TLBMISS)
+                errs |= OMAP_IOMMU_ERR_TLB_MISS;
+        if (stat & MMU_IRQ_TRANSLATIONFAULT)
+                errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
+        if (stat & MMU_IRQ_EMUMISS)
+                errs |= OMAP_IOMMU_ERR_EMU_MISS;
+        if (stat & MMU_IRQ_TABLEWALKFAULT)
+                errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
+        if (stat & MMU_IRQ_MULTIHITFAULT)
+                errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
+        iommu_write_reg(obj, stat, MMU_IRQSTATUS);
+        return errs;
+}
+static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
+{
+        cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
+        cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
+}
+static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
+{
+        iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
+        iommu_write_reg(obj, cr->ram, MMU_RAM);
+}
+static u32 omap2_cr_to_virt(struct cr_regs *cr)
+{
+        u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
+        u32 mask = get_cam_va_mask(cr->cam & page_size);
+        return cr->cam & mask;
+}
+static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
+                                                struct iotlb_entry *e)
+{
+        struct cr_regs *cr;
+        if (e->da & ~(get_cam_va_mask(e->pgsz))) {
+                dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
+                        e->da);
+                return ERR_PTR(-EINVAL);
+        }
+        cr = kmalloc(sizeof(*cr), GFP_KERNEL);
+        if (!cr)
+                return ERR_PTR(-ENOMEM);
+        cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
+        cr->ram = e->pa | e->endian | e->elsz | e->mixed;
+        return cr;
+}
+static inline int omap2_cr_valid(struct cr_regs *cr)
+{
+        return cr->cam & MMU_CAM_V;
+}
+static u32 omap2_get_pte_attr(struct iotlb_entry *e)
+{
+        u32 attr;
+        attr = e->mixed << 5;
+        attr |= e->endian;
+        attr |= e->elsz >> 3;
+        attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
+                        (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
+        return attr;
+}
+static ssize_t
+omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
+{
+        char *p = buf;
+        /* FIXME: Need more detail analysis of cam/ram */
+        p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
+                                        (cr->cam & MMU_CAM_P) ? 1 : 0);
+        return p - buf;
+}
+#define pr_reg(name)                                                    \
+        do {                                                            \
+                ssize_t bytes;                                          \
+                const char *str = "%20s: %08x\n";                       \
+                const int maxcol = 32;                                  \
+                bytes = snprintf(p, maxcol, str, __stringify(name),     \
+                                 iommu_read_reg(obj, MMU_##name));      \
+                p += bytes;                                             \
+                len -= bytes;                                           \
+                if (len < maxcol)                                       \
+                        goto out;                                       \
+        } while (0)
+static ssize_t
+omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
+{
+        char *p = buf;
+        pr_reg(REVISION);
+        pr_reg(SYSCONFIG);
+        pr_reg(SYSSTATUS);
+        pr_reg(IRQSTATUS);
+        pr_reg(IRQENABLE);
+        pr_reg(WALKING_ST);
+        pr_reg(CNTL);
+        pr_reg(FAULT_AD);
+        pr_reg(TTB);
+        pr_reg(LOCK);
+        pr_reg(LD_TLB);
+        pr_reg(CAM);
+        pr_reg(RAM);
+        pr_reg(GFLUSH);
+        pr_reg(FLUSH_ENTRY);
+        pr_reg(READ_CAM);
+        pr_reg(READ_RAM);
+        pr_reg(EMU_FAULT_AD);
+out:
+        return p - buf;
+}
+static void omap2_iommu_save_ctx(struct omap_iommu *obj)
+{
+        int i;
+        u32 *p = obj->ctx;
+        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
+                p[i] = iommu_read_reg(obj, i * sizeof(u32));
+                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
+        }
+        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
+}
+static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
+{
+        int i;
+        u32 *p = obj->ctx;
+        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
+                iommu_write_reg(obj, p[i], i * sizeof(u32));
+                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
+        }
+        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
+}
+static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
+{
+        e->da           = cr->cam & MMU_CAM_VATAG_MASK;
+        e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
+        e->valid        = cr->cam & MMU_CAM_V;
+        e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
+        e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
+        e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
+        e->mixed        = cr->ram & MMU_RAM_MIXED;
+}
+static const struct iommu_functions omap2_iommu_ops = {
+        .version        = IOMMU_ARCH_VERSION,
+        .enable         = omap2_iommu_enable,
+        .disable        = omap2_iommu_disable,
+        .set_twl        = omap2_iommu_set_twl,
+        .fault_isr      = omap2_iommu_fault_isr,
+        .tlb_read_cr    = omap2_tlb_read_cr,
+        .tlb_load_cr    = omap2_tlb_load_cr,
+        .cr_to_e        = omap2_cr_to_e,
+        .cr_to_virt     = omap2_cr_to_virt,
+        .alloc_cr       = omap2_alloc_cr,
+        .cr_valid       = omap2_cr_valid,
+        .dump_cr        = omap2_dump_cr,
+        .get_pte_attr   = omap2_get_pte_attr,
+        .save_ctx       = omap2_iommu_save_ctx,
+        .restore_ctx    = omap2_iommu_restore_ctx,
+        .dump_ctx       = omap2_iommu_dump_ctx,
+};
+static int __init omap2_iommu_init(void)
+{
+        return omap_install_iommu_arch(&omap2_iommu_ops);
+}
+module_init(omap2_iommu_init);
+static void __exit omap2_iommu_exit(void)
+{
+        omap_uninstall_iommu_arch(&omap2_iommu_ops);
+}
+module_exit(omap2_iommu_exit);
+MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
+MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
new file mode 100644
index 00000000000..e69d37d9520
--- /dev/null
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -0,0 +1,57 @@
+/*
+ * OMAP44xx secure APIs file.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+/*
+ * This is common routine to manage secure monitor API
+ * used to modify the PL310 secure registers.
+ * 'r0' contains the value to be modified and 'r12' contains
+ * the monitor API number. It uses few CPU registers
+ * internally and hence they need be backed up including
+ * link register "lr".
+ * Function signature : void omap_smc1(u32 fn, u32 arg)
+ */
+ENTRY(omap_smc1)
+        stmfd   sp!, {r2-r12, lr}
+        mov     r12, r0
+        mov     r0, r1
+        dsb
+        smc     #0
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_smc1)
+ENTRY(omap_modify_auxcoreboot0)
+        stmfd   sp!, {r1-r12, lr}
+        ldr     r12, =0x104
+        dsb
+        smc     #0
+        ldmfd   sp!, {r1-r12, pc}
+ENDPROC(omap_modify_auxcoreboot0)
+ENTRY(omap_auxcoreboot_addr)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x105
+        dsb
+        smc     #0
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_auxcoreboot_addr)
+ENTRY(omap_read_auxcoreboot0)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x103
+        dsb
+        smc     #0
+        mov     r0, r0, lsr #9
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 00000000000..7b9f1909ddb
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,248 @@
+/*
+  * OMAP4XXX L3 Interconnect error handling driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include "omap_l3_noc.h"
+/*
+ * Interrupt Handler for L3 error detection.
+ *      1) Identify the L3 clockdomain partition to which the error belongs to.
+ *      2) Identify the slave where the error information is logged
+ *      3) Print the logged information.
+ *      4) Add dump stack to provide kernel trace.
+ *
+ * Two Types of errors :
+ *      1) Custom errors in L3 :
+ *              Target like DMM/FW/EMIF generates SRESP=ERR error
+ *      2) Standard L3 error:
+ *              - Unsupported CMD.
+ *                      L3 tries to access target while it is idle
+ *              - OCP disconnect.
+ *              - Address hole error:
+ *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
+ *                      do not have connectivity, the error is logged in
+ *                      their default target which is DMM2.
+ *
+ *      On High Secure devices, firewall errors are possible and those
+ *      can be trapped as well. But the trapping is implemented as part
+ *      secure software and hence need not be implemented here.
+ */
+static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
+{
+        struct omap4_l3         *l3 = _l3;
+        int inttype, i, j;
+        int err_src = 0;
+        u32 std_err_main_addr, std_err_main, err_reg;
+        u32 base, slave_addr, clear;
+        char *source_name;
+        /* Get the Type of interrupt */
+        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
+        for (i = 0; i < L3_MODULES; i++) {
+                /*
+                 * Read the regerr register of the clock domain
+                 * to determine the source
+                 */
+                base = (u32)l3->l3_base[i];
+                err_reg =  readl(base + l3_flagmux[i] + (inttype << 3));
+                /* Get the corresponding error and analyse */
+                if (err_reg) {
+                        /* Identify the source from control status register */
+                        for (j = 0; !(err_reg & (1 << j)); j++)
+                                                                        ;
+                        err_src = j;
+                        /* Read the stderrlog_main_source from clk domain */
+                        std_err_main_addr = base + *(l3_targ[i] + err_src);
+                        std_err_main = readl(std_err_main_addr);
+                        switch (std_err_main & CUSTOM_ERROR) {
+                        case STANDARD_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+                                slave_addr = std_err_main_addr +
+                                                L3_SLAVE_ADDRESS_OFFSET;
+                                WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
+                                        source_name, readl(slave_addr));
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+                        case CUSTOM_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+                                WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
+                                                        source_name);
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+                        default:
+                                /* Nothing to be handled here as of now */
+                                break;
+                        }
+                /* Error found so break the for loop */
+                break;
+                }
+        }
+        return IRQ_HANDLED;
+}
+static int __init omap4_l3_probe(struct platform_device *pdev)
+{
+        static struct omap4_l3          *l3;
+        struct resource         *res;
+        int                     ret;
+        int                     irq;
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3)
+                return -ENOMEM;
+        platform_set_drvdata(pdev, l3);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 0\n");
+                ret = -ENODEV;
+                goto err0;
+        }
+        l3->l3_base[0] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[0]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 1\n");
+                ret = -ENODEV;
+                goto err1;
+        }
+        l3->l3_base[1] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[1]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err1;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 2\n");
+                ret = -ENODEV;
+                goto err2;
+        }
+        l3->l3_base[2] = ioremap(res->start, resource_size(res));
+        if (!l3->l3_base[2]) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+        /*
+         * Setup interrupt Handlers
+         */
+        irq = platform_get_irq(pdev, 0);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-dbg-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_DBG);
+                goto err3;
+        }
+        l3->debug_irq = irq;
+        irq = platform_get_irq(pdev, 1);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-app-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_APP);
+                goto err4;
+        }
+        l3->app_irq = irq;
+        return 0;
+err4:
+        free_irq(l3->debug_irq, l3);
+err3:
+        iounmap(l3->l3_base[2]);
+err2:
+        iounmap(l3->l3_base[1]);
+err1:
+        iounmap(l3->l3_base[0]);
+err0:
+        kfree(l3);
+        return ret;
+}
+static int __exit omap4_l3_remove(struct platform_device *pdev)
+{
+        struct omap4_l3         *l3 = platform_get_drvdata(pdev);
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->l3_base[0]);
+        iounmap(l3->l3_base[1]);
+        iounmap(l3->l3_base[2]);
+        kfree(l3);
+        return 0;
+}
+static struct platform_driver omap4_l3_driver = {
+        .remove         = __exit_p(omap4_l3_remove),
+        .driver         = {
+        .name           = "omap_l3_noc",
+        },
+};
+static int __init omap4_l3_init(void)
+{
+        return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
+}
+postcore_initcall_sync(omap4_l3_init);
+static void __exit omap4_l3_exit(void)
+{
+        platform_driver_unregister(&omap4_l3_driver);
+}
+module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 00000000000..359b83348ae
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
+ /*
+  * OMAP4XXX L3 Interconnect  error handling driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+/*
+ * L3 register offsets
+ */
+#define L3_MODULES                      3
+#define CLEAR_STDERR_LOG                (1 << 31)
+#define CUSTOM_ERROR                    0x2
+#define STANDARD_ERROR                  0x0
+#define INBAND_ERROR                    0x0
+#define EMIF_KERRLOG_OFFSET             0x10
+#define L3_SLAVE_ADDRESS_OFFSET         0x14
+#define LOGICAL_ADDR_ERRORLOG           0x4
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+u32 l3_flagmux[L3_MODULES] = {
+        0x50C,
+        0x100C,
+        0X020C
+};
+/*
+ * L3 Target standard Error register offsets
+ */
+u32 l3_targ_stderrlog_main_clk1[] = {
+        0x148, /* DMM1 */
+        0x248, /* DMM2 */
+        0x348, /* ABE */
+        0x448, /* L4CFG */
+        0x648  /* CLK2 PWR DISC */
+};
+u32 l3_targ_stderrlog_main_clk2[] = {
+        0x548,          /* CORTEX M3 */
+        0x348,          /* DSS */
+        0x148,          /* GPMC */
+        0x448,          /* ISS */
+        0x748,          /* IVAHD */
+        0xD48,          /* missing in TRM  corresponds to AES1*/
+        0x948,          /* L4 PER0*/
+        0x248,          /* OCMRAM */
+        0x148,          /* missing in TRM corresponds to GPMC sERROR*/
+        0x648,          /* SGX */
+        0x848,          /* SL2 */
+        0x1648,         /* C2C */
+        0x1148,         /* missing in TRM corresponds PWR DISC CLK1*/
+        0xF48,          /* missing in TRM corrsponds to SHA1*/
+        0xE48,          /* missing in TRM corresponds to AES2*/
+        0xC48,          /* L4 PER3 */
+        0xA48,          /* L4 PER1*/
+        0xB48           /* L4 PER2*/
+};
+u32 l3_targ_stderrlog_main_clk3[] = {
+        0x0148  /* EMUSS */
+};
+char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
+        {
+        "DMM1",
+        "DMM2",
+        "ABE",
+        "L4CFG",
+        "CLK2 PWR DISC",
+        },
+        {
+        "CORTEX M3" ,
+        "DSS ",
+        "GPMC ",
+        "ISS ",
+        "IVAHD ",
+        "AES1",
+        "L4 PER0",
+        "OCMRAM ",
+        "GPMC sERROR",
+        "SGX ",
+        "SL2 ",
+        "C2C ",
+        "PWR DISC CLK1",
+        "SHA1",
+        "AES2",
+        "L4 PER3",
+        "L4 PER1",
+        "L4 PER2",
+        },
+        {
+        "EMUSS",
+        },
+};
+u32 *l3_targ[L3_MODULES] = {
+        l3_targ_stderrlog_main_clk1,
+        l3_targ_stderrlog_main_clk2,
+        l3_targ_stderrlog_main_clk3,
+};
+struct omap4_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+        /* memory base */
+        void __iomem *l3_base[4];
+        int             debug_irq;
+        int             app_irq;
+};
+#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 00000000000..873c0e33b51
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,299 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include "omap_l3_smx.h"
+static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
+{
+        return __raw_readll(base + reg);
+}
+static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
+{
+        __raw_writell(value, base + reg);
+}
+static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
+{
+        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
+}
+static inline u32 omap3_l3_decode_addr(u64 error_addr)
+{
+        return error_addr & 0xffffffff;
+}
+static inline unsigned omap3_l3_decode_cmd(u64 error)
+{
+        return (error & 0x07) >> L3_ERROR_LOG_CMD;
+}
+static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
+{
+        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
+}
+static inline unsigned omap3_l3_decode_req_info(u64 error)
+{
+        return (error >> 32) & 0xffff;
+}
+static char *omap3_l3_code_string(u8 code)
+{
+        switch (code) {
+        case OMAP_L3_CODE_NOERROR:
+                return "No Error";
+        case OMAP_L3_CODE_UNSUP_CMD:
+                return "Unsupported Command";
+        case OMAP_L3_CODE_ADDR_HOLE:
+                return "Address Hole";
+        case OMAP_L3_CODE_PROTECT_VIOLATION:
+                return "Protection Violation";
+        case OMAP_L3_CODE_IN_BAND_ERR:
+                return "In-band Error";
+        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
+                return "Request Timeout Not Accepted";
+        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
+                return "Request Timeout, no response";
+        default:
+                return "UNKNOWN error";
+        }
+}
+static char *omap3_l3_initiator_string(u8 initid)
+{
+        switch (initid) {
+        case OMAP_L3_LCD:
+                return "LCD";
+        case OMAP_L3_SAD2D:
+                return "SAD2D";
+        case OMAP_L3_IA_MPU_SS_1:
+        case OMAP_L3_IA_MPU_SS_2:
+        case OMAP_L3_IA_MPU_SS_3:
+        case OMAP_L3_IA_MPU_SS_4:
+        case OMAP_L3_IA_MPU_SS_5:
+                return "MPU";
+        case OMAP_L3_IA_IVA_SS_1:
+        case OMAP_L3_IA_IVA_SS_2:
+        case OMAP_L3_IA_IVA_SS_3:
+                return "IVA_SS";
+        case OMAP_L3_IA_IVA_SS_DMA_1:
+        case OMAP_L3_IA_IVA_SS_DMA_2:
+        case OMAP_L3_IA_IVA_SS_DMA_3:
+        case OMAP_L3_IA_IVA_SS_DMA_4:
+        case OMAP_L3_IA_IVA_SS_DMA_5:
+        case OMAP_L3_IA_IVA_SS_DMA_6:
+                return "IVA_SS_DMA";
+        case OMAP_L3_IA_SGX:
+                return "SGX";
+        case OMAP_L3_IA_CAM_1:
+        case OMAP_L3_IA_CAM_2:
+        case OMAP_L3_IA_CAM_3:
+                return "CAM";
+        case OMAP_L3_IA_DAP:
+                return "DAP";
+        case OMAP_L3_SDMA_WR_1:
+        case OMAP_L3_SDMA_WR_2:
+                return "SDMA_WR";
+        case OMAP_L3_SDMA_RD_1:
+        case OMAP_L3_SDMA_RD_2:
+        case OMAP_L3_SDMA_RD_3:
+        case OMAP_L3_SDMA_RD_4:
+                return "SDMA_RD";
+        case OMAP_L3_USBOTG:
+                return "USB_OTG";
+        case OMAP_L3_USBHOST:
+                return "USB_HOST";
+        default:
+                return "UNKNOWN Initiator";
+        }
+}
+/**
+ * omap3_l3_block_irq - handles a register block's irq
+ * @l3: struct omap3_l3 *
+ * @base: register block base address
+ * @error: L3_ERROR_LOG register of our block
+ *
+ * Called in hard-irq context. Caller should take care of locking
+ *
+ * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
+ * Analysis Sequence, we are following that sequence here, please
+ * refer to that Figure for more information on the subject.
+ */
+static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
+                                        u64 error, int error_addr)
+{
+        u8                      code = omap3_l3_decode_error_code(error);
+        u8                      initid = omap3_l3_decode_initid(error);
+        u8                      multi = error & L3_ERROR_LOG_MULTI;
+        u32                     address = omap3_l3_decode_addr(error_addr);
+        WARN(true, "%s seen by %s %s at address %x\n",
+                                 omap3_l3_code_string(code),
+                          omap3_l3_initiator_string(initid),
+                             multi ? "Multiple Errors" : "",
+                                                   address);
+        return IRQ_HANDLED;
+}
+static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
+{
+        struct omap3_l3         *l3 = _l3;
+        u64                     status, clear;
+        u64                     error;
+        u64                     error_addr;
+        u64                     err_source = 0;
+        void                    __iomem *base;
+        int                     int_type;
+        irqreturn_t             ret = IRQ_NONE;
+        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
+        if (!int_type) {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
+                /*
+                 * if we have a timeout error, there's nothing we can
+                 * do besides rebooting the board. So let's BUG on any
+                 * of such errors and handle the others. timeout error
+                 * is severe and not expected to occur.
+                 */
+                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
+        } else {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
+                /* No timeout error for debug sources */
+        }
+        /* identify the error source */
+        for (err_source = 0; !(status & (1 << err_source)); err_source++)
+                                                                        ;
+        base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
+        error = omap3_l3_readll(base, L3_ERROR_LOG);
+        if (error) {
+                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
+                ret |= omap3_l3_block_irq(l3, error, error_addr);
+        }
+        /* Clear the status register */
+        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
+                L3_AGENT_STATUS_CLEAR_TA;
+        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
+        /* clear the error log register */
+        omap3_l3_writell(base, L3_ERROR_LOG, error);
+        return ret;
+}
+static int __init omap3_l3_probe(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3;
+        struct resource         *res;
+        int                     ret;
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3)
+                return -ENOMEM;
+        platform_set_drvdata(pdev, l3);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource\n");
+                ret = -ENODEV;
+                goto err0;
+        }
+        l3->rt = ioremap(res->start, resource_size(res));
+        if (!l3->rt) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+        l3->debug_irq = platform_get_irq(pdev, 0);
+        ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-debug-irq", l3);
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request debug irq\n");
+                goto err1;
+        }
+        l3->app_irq = platform_get_irq(pdev, 1);
+        ret = request_irq(l3->app_irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-app-irq", l3);
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request app irq\n");
+                goto err2;
+        }
+        return 0;
+err2:
+        free_irq(l3->debug_irq, l3);
+err1:
+        iounmap(l3->rt);
+err0:
+        kfree(l3);
+        return ret;
+}
+static int __exit omap3_l3_remove(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->rt);
+        kfree(l3);
+        return 0;
+}
+static struct platform_driver omap3_l3_driver = {
+        .remove         = __exit_p(omap3_l3_remove),
+        .driver         = {
+        .name   = "omap_l3_smx",
+        },
+};
+static int __init omap3_l3_init(void)
+{
+        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
+}
+postcore_initcall_sync(omap3_l3_init);
+static void __exit omap3_l3_exit(void)
+{
+        platform_driver_unregister(&omap3_l3_driver);
+}
+module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 00000000000..ba2ed9a850c
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+/* Register definitions. All 64-bit wide */
+#define L3_COMPONENT                    0x000
+#define L3_CORE                         0x018
+#define L3_AGENT_CONTROL                0x020
+#define L3_AGENT_STATUS                 0x028
+#define L3_ERROR_LOG                    0x058
+#define L3_ERROR_LOG_MULTI              (1 << 31)
+#define L3_ERROR_LOG_SECONDARY          (1 << 30)
+#define L3_ERROR_LOG_ADDR               0x060
+/* Register definitions for Sideband Interconnect */
+#define L3_SI_CONTROL                   0x020
+#define L3_SI_FLAG_STATUS_0             0x510
+const u64 shift = 1;
+#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
+#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
+#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
+#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
+#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
+#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
+#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
+#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
+#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
+#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
+#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
+#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
+#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
+#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
+#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
+#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
+#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
+#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
+#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
+#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
+#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
+#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
+#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
+#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
+#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
+#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
+#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
+#define L3_STATUS_0_IVATA_REQ           (shift << 54)
+#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
+#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
+#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
+#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
+#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
+#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
+#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
+#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
+                                        | L3_STATUS_0_MPUIA_RSP         \
+                                        | L3_STATUS_0_IVAIA_BRST        \
+                                        | L3_STATUS_0_IVAIA_RSP         \
+                                        | L3_STATUS_0_SGXIA_BRST        \
+                                        | L3_STATUS_0_SGXIA_RSP         \
+                                        | L3_STATUS_0_CAMIA_BRST        \
+                                        | L3_STATUS_0_CAMIA_RSP         \
+                                        | L3_STATUS_0_DISPIA_BRST       \
+                                        | L3_STATUS_0_DISPIA_RSP        \
+                                        | L3_STATUS_0_DMARDIA_BRST      \
+                                        | L3_STATUS_0_DMARDIA_RSP       \
+                                        | L3_STATUS_0_DMAWRIA_BRST      \
+                                        | L3_STATUS_0_DMAWRIA_RSP       \
+                                        | L3_STATUS_0_USBOTGIA_BRST     \
+                                        | L3_STATUS_0_USBOTGIA_RSP      \
+                                        | L3_STATUS_0_USBHOSTIA_BRST    \
+                                        | L3_STATUS_0_SMSTA_REQ         \
+                                        | L3_STATUS_0_GPMCTA_REQ        \
+                                        | L3_STATUS_0_OCMRAMTA_REQ      \
+                                        | L3_STATUS_0_OCMROMTA_REQ      \
+                                        | L3_STATUS_0_IVATA_REQ         \
+                                        | L3_STATUS_0_SGXTA_REQ         \
+                                        | L3_STATUS_0_L4CORETA_REQ      \
+                                        | L3_STATUS_0_L4PERTA_REQ       \
+                                        | L3_STATUS_0_L4EMUTA_REQ       \
+                                        | L3_STATUS_0_MAD2DTA_REQ)
+#define L3_SI_FLAG_STATUS_1             0x530
+#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
+#define L3_STATUS_1_DAPIA0              (1 << 3)
+#define L3_STATUS_1_DAPIA1              (1 << 4)
+#define L3_STATUS_1_IVAIA               (1 << 6)
+#define L3_PM_ERROR_LOG                 0x020
+#define L3_PM_CONTROL                   0x028
+#define L3_PM_ERROR_CLEAR_SINGLE        0x030
+#define L3_PM_ERROR_CLEAR_MULTI         0x038
+#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
+#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
+#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
+#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
+/* L3 error log bit fields. Common for IA and TA */
+#define L3_ERROR_LOG_CODE               24
+#define L3_ERROR_LOG_INITID             8
+#define L3_ERROR_LOG_CMD                0
+/* L3 agent status bit fields. */
+#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
+#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
+#define OMAP34xx_IRQ_L3_APP             10
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+enum omap3_l3_initiator_id {
+        /* LCD has 1 ID */
+        OMAP_L3_LCD             = 29,
+        /* SAD2D has 1 ID */
+        OMAP_L3_SAD2D           = 28,
+        /* MPU has 5 IDs */
+        OMAP_L3_IA_MPU_SS_1     = 27,
+        OMAP_L3_IA_MPU_SS_2     = 26,
+        OMAP_L3_IA_MPU_SS_3     = 25,
+        OMAP_L3_IA_MPU_SS_4     = 24,
+        OMAP_L3_IA_MPU_SS_5     = 23,
+        /* IVA2.2 SS has 3 IDs*/
+        OMAP_L3_IA_IVA_SS_1     = 22,
+        OMAP_L3_IA_IVA_SS_2     = 21,
+        OMAP_L3_IA_IVA_SS_3     = 20,
+        /* IVA 2.2 SS DMA has 6 IDS */
+        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
+        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
+        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
+        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
+        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
+        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
+        /* SGX has 1 ID */
+        OMAP_L3_IA_SGX          = 13,
+        /* CAM has 3 ID */
+        OMAP_L3_IA_CAM_1        = 12,
+        OMAP_L3_IA_CAM_2        = 11,
+        OMAP_L3_IA_CAM_3        = 10,
+        /* DAP has 1 ID */
+        OMAP_L3_IA_DAP          = 9,
+        /* SDMA WR has 2 IDs */
+        OMAP_L3_SDMA_WR_1       = 8,
+        OMAP_L3_SDMA_WR_2       = 7,
+        /* SDMA RD has 4 IDs */
+        OMAP_L3_SDMA_RD_1       = 6,
+        OMAP_L3_SDMA_RD_2       = 5,
+        OMAP_L3_SDMA_RD_3       = 4,
+        OMAP_L3_SDMA_RD_4       = 3,
+        /* HSUSB OTG has 1 ID */
+        OMAP_L3_USBOTG          = 2,
+        /* HSUSB HOST has 1 ID */
+        OMAP_L3_USBHOST         = 1,
+};
+enum omap3_l3_code {
+        OMAP_L3_CODE_NOERROR = 0,
+        OMAP_L3_CODE_UNSUP_CMD = 1,
+        OMAP_L3_CODE_ADDR_HOLE = 2,
+        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
+        OMAP_L3_CODE_IN_BAND_ERR = 4,
+        /* codes 5 and 6 are reserved */
+        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
+        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
+        /* codes 9 - 15 are also reserved */
+};
+struct omap3_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+        /* memory base*/
+        void __iomem    *rt;
+        int             debug_irq;
+        int             app_irq;
+        /* true when and inband functional error occurs */
+        unsigned        inband:1;
+};
+/* offsets for l3 agents in order with the Flag status register */
+unsigned int __iomem omap3_l3_app_bases[] = {
+        /* MPU IA */
+        0x1400,
+        0x1400,
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        0x1800,
+        0x1800,
+        /* SGX IA */
+        0x1c00,
+        0x1c00,
+        /* RESERVED */
+        0,
+        /* CAMERA IA */
+        0x5800,
+        0x5800,
+        0x5800,
+        /* DISPLAY IA */
+        0x5400,
+        0x5400,
+        /* RESERVED */
+        0,
+        /*SDMA RD IA */
+        0x4c00,
+        0x4c00,
+        /* RESERVED */
+        0,
+        /* SDMA WR IA */
+        0x5000,
+        0x5000,
+        /* RESERVED */
+        0,
+        /* USB OTG IA */
+        0x4400,
+        0x4400,
+        0x4400,
+        /* USB HOST IA */
+        0x4000,
+        0x4000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        /* SAD2D IA */
+        0x3000,
+        0x3000,
+        0x3000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        /* SMA TA */
+        0x2000,
+        /* GPMC TA */
+        0x2400,
+        /* OCM RAM TA */
+        0x2800,
+        /* OCM ROM TA */
+        0x2C00,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* IVA 2.2 TA */
+        0x6000,
+        /* SGX TA */
+        0x6400,
+        /* L4 EMU TA */
+        0x7000,
+        /* GPMC TA */
+        0x2400,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* L4 EMU TA */
+        0x7000,
+        /* MAD2D TA */
+        0x3400,
+        /* RESERVED */
+        0,
+        0,
+};
+unsigned int __iomem omap3_l3_debug_bases[] = {
+        /* MPU DATA IA */
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        /* DAP IA */
+        0x5c00,
+        0x5c00,
+        /* RESERVED */
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        /* REST RESERVED */
+};
+u32 *omap3_l3_bases[] = {
+        omap3_l3_app_bases,
+        omap3_l3_debug_bases,
+};
+/*
+ * REVISIT define __raw_readll/__raw_writell here, but move them to
+ * <asm/io.h> at some point
+ */
+#define __raw_writell(v, a)     (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a) = (v))
+#define __raw_readll(a)         (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a))
+#endif
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
new file mode 100644
index 00000000000..cf600e22bf8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -0,0 +1,241 @@
+/*
+ * OMAP2 and OMAP3 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <plat/prcm.h>
+#include "powerdomain.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+/* Common functions across OMAP2 and OMAP3 */
+static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP_POWERSTATE_MASK);
+}
+static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP_POWERSTATEST_MASK);
+}
+static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
+                                             m);
+}
+static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL, m);
+}
+static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
+        omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
+                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+                (c++ < PWRDM_TRANSITION_BAILOUT))
+                        udelay(1);
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                        "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+        return 0;
+}
+/* Applicable only for OMAP3. Not supported on OMAP2 */
+static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
+}
+static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
+}
+static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP3430_LASTMEM1STATEENTERED_MASK;
+        case 1:
+                return OMAP3430_LASTMEM2STATEENTERED_MASK;
+        case 2:
+                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
+        case 3:
+                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+        m = omap3_get_mem_bank_lastmemst_mask(bank);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                OMAP3430_PM_PREPWSTST, m);
+}
+static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        return 0;
+}
+static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(0,
+                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+}
+static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          0, pwrdm->prcm_offs,
+                                          OMAP2_PM_PWSTCTRL);
+}
+struct pwrdm_ops omap2_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+struct pwrdm_ops omap3_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
+        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
+        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
new file mode 100644
index 00000000000..a7880af4b3d
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -0,0 +1,225 @@
+/*
+ * OMAP4 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include "powerdomain.h"
+#include <plat/prcm.h>
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-44xx.h"
+static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+                                        (pwrst << OMAP_POWERSTATE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
+        return 0;
+}
+static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LOGICSTATEST_MASK;
+        v >>= OMAP4430_LOGICSTATEST_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP4430_LOGICRETSTATE_MASK;
+        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+                                            pwrdm->prcm_offs,
+                                            OMAP4_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+               (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                       "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+        return 0;
+}
+struct pwrdm_ops omap4_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
+        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
+        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
new file mode 100644
index 00000000000..2e40a5cf016
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm.c
@@ -0,0 +1,167 @@
+/*
+ * linux/arch/arm/mach-omap2/prcm.c
+ *
+ * OMAP 24xx Power Reset and Clock Management (PRCM) functions
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
+ * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <mach/system.h>
+#include <plat/common.h>
+#include <plat/prcm.h>
+#include <plat/irqs.h>
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
+void __iomem *prm_base;
+void __iomem *cm_base;
+void __iomem *cm2_base;
+#define MAX_MODULE_ENABLE_WAIT          100000
+u32 omap_prcm_get_reset_sources(void)
+{
+        /* XXX This presumably needs modification for 34XX */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+        if (cpu_is_omap44xx())
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+        return 0;
+}
+EXPORT_SYMBOL(omap_prcm_get_reset_sources);
+/* Resets clock rates and reboots the system. Only called from system.h */
+static void omap_prcm_arch_reset(char mode, const char *cmd)
+{
+        s16 prcm_offs = 0;
+        if (cpu_is_omap24xx()) {
+                omap2xxx_clk_prepare_for_reboot();
+                prcm_offs = WKUP_MOD;
+        } else if (cpu_is_omap34xx()) {
+                prcm_offs = OMAP3430_GR_MOD;
+                omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
+        } else if (cpu_is_omap44xx()) {
+                omap4_prminst_global_warm_sw_reset(); /* never returns */
+        } else {
+                WARN_ON(1);
+        }
+        /*
+         * As per Errata i520, in some cases, user will not be able to
+         * access DDR memory after warm-reset.
+         * This situation occurs while the warm-reset happens during a read
+         * access to DDR memory. In that particular condition, DDR memory
+         * does not respond to a corrupted read command due to the warm
+         * reset occurrence but SDRC is waiting for read completion.
+         * SDRC is not sensitive to the warm reset, but the interconnect is
+         * reset on the fly, thus causing a misalignment between SDRC logic,
+         * interconnect logic and DDR memory state.
+         * WORKAROUND:
+         * Steps to perform before a Warm reset is trigged:
+         * 1. enable self-refresh on idle request
+         * 2. put SDRC in idle
+         * 3. wait until SDRC goes to idle
+         * 4. generate SW reset (Global SW reset)
+         *
+         * Steps to be performed after warm reset occurs (in bootloader):
+         * if HW warm reset is the source, apply below steps before any
+         * accesses to SDRAM:
+         * 1. Reset SMS and SDRC and wait till reset is complete
+         * 2. Re-initialize SMS, SDRC and memory
+         *
+         * NOTE: Above work around is required only if arch reset is implemented
+         * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+         * the WA since it resets SDRC as well as part of cold reset.
+         */
+        /* XXX should be moved to some OMAP2/3 specific code */
+        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+                                   OMAP2_RM_RSTCTRL);
+        omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
+}
+void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
+/**
+ * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ * @reg: physical address of module IDLEST register
+ * @mask: value to mask against to determine if the module is active
+ * @idlest: idle state indicator (0 or 1) for the clock
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the module indicated readiness in time, or 0 if it
+ * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ *
+ * XXX This function is deprecated.  It should be removed once the
+ * hwmod conversion is complete.
+ */
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+                                const char *name)
+{
+        int i = 0;
+        int ena = 0;
+        if (idlest)
+                ena = 0;
+        else
+                ena = mask;
+        /* Wait for lock */
+        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+                          MAX_MODULE_ENABLE_WAIT, i);
+        if (i < MAX_MODULE_ENABLE_WAIT)
+                pr_debug("cm: Module associated with clock %s ready after %d "
+                         "loops\n", name, i);
+        else
+                pr_err("cm: Module associated with clock %s didn't enable in "
+                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+};
+void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
+{
+        /* Static mapping, never released */
+        if (omap2_globals->prm) {
+                prm_base = ioremap(omap2_globals->prm, SZ_8K);
+                WARN_ON(!prm_base);
+        }
+        if (omap2_globals->cm) {
+                cm_base = ioremap(omap2_globals->cm, SZ_8K);
+                WARN_ON(!cm_base);
+        }
+        if (omap2_globals->cm2) {
+                cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
+                WARN_ON(!cm2_base);
+        }
+}
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 00000000000..19ff0104374
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,1046 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <plat/common.h>
+#include "pm.h"
+#include "smartreflex.h"
+#define SMARTREFLEX_NAME_LEN    16
+#define NVALUE_NAME_LEN         40
+#define SR_DISABLE_TIMEOUT      200
+struct omap_sr {
+        int                             srid;
+        int                             ip_type;
+        int                             nvalue_count;
+        bool                            autocomp_active;
+        u32                             clk_length;
+        u32                             err_weight;
+        u32                             err_minlimit;
+        u32                             err_maxlimit;
+        u32                             accum_data;
+        u32                             senn_avgweight;
+        u32                             senp_avgweight;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        unsigned int                    irq;
+        void __iomem                    *base;
+        struct platform_device          *pdev;
+        struct list_head                node;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+        struct dentry                   *dbg_dir;
+};
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+        __raw_writel(value, (sr->base + offset));
+}
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+                                        u32 value)
+{
+        u32 reg_val;
+        u32 errconfig_offs = 0, errconfig_mask = 0;
+        reg_val = __raw_readl(sr->base + offset);
+        reg_val &= ~mask;
+        /*
+         * Smartreflex error config register is special as it contains
+         * certain status bits which if written a 1 into means a clear
+         * of those bits. So in order to make sure no accidental write of
+         * 1 happens to those status bits, do a clear of them in the read
+         * value. This mean this API doesn't rewrite values in these bits
+         * if they are currently set, but does allow the caller to write
+         * those bits.
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                errconfig_offs = ERRCONFIG_V1;
+                errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                errconfig_offs = ERRCONFIG_V2;
+                errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
+        }
+        if (offset == errconfig_offs)
+                reg_val &= ~errconfig_mask;
+        reg_val |= value;
+        __raw_writel(reg_val, (sr->base + offset));
+}
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+        return __raw_readl(sr->base + offset);
+}
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr_info;
+        if (!voltdm) {
+                pr_err("%s: Null voltage domain passed!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+        list_for_each_entry(sr_info, &sr_list, node) {
+                if (voltdm == sr_info->voltdm)
+                        return sr_info;
+        }
+        return ERR_PTR(-ENODATA);
+}
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+        struct omap_sr *sr_info = (struct omap_sr *)data;
+        u32 status = 0;
+        if (sr_info->ip_type == SR_TYPE_V1) {
+                /* Read the status bits */
+                status = sr_read_reg(sr_info, ERRCONFIG_V1);
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, ERRCONFIG_V1, status);
+        } else if (sr_info->ip_type == SR_TYPE_V2) {
+                /* Read the status bits */
+                status = sr_read_reg(sr_info, IRQSTATUS);
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, IRQSTATUS, status);
+        }
+        if (sr_class->notify)
+                sr_class->notify(sr_info->voltdm, status);
+        return IRQ_HANDLED;
+}
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+        struct clk *sys_ck;
+        u32 sys_clk_speed;
+        if (cpu_is_omap34xx())
+                sys_ck = clk_get(NULL, "sys_ck");
+        else
+                sys_ck = clk_get(NULL, "sys_clkin_ck");
+        if (IS_ERR(sys_ck)) {
+                dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
+                        __func__);
+                return;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+        switch (sys_clk_speed) {
+        case 12000000:
+                sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+                break;
+        case 13000000:
+                sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+                break;
+        case 19200000:
+                sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+                break;
+        case 26000000:
+                sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+                break;
+        case 38400000:
+                sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
+                        __func__, sys_clk_speed);
+                break;
+        }
+}
+static void sr_set_regfields(struct omap_sr *sr)
+{
+        /*
+         * For time being these values are defined in smartreflex.h
+         * and populated during init. May be they can be moved to board
+         * file or pmic specific data structure. In that case these structure
+         * fields will have to be populated using the pdata or pmic structure.
+         */
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                sr->err_weight = OMAP3430_SR_ERRWEIGHT;
+                sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+                sr->accum_data = OMAP3430_SR_ACCUMDATA;
+                if (!(strcmp(sr->voltdm->name, "mpu"))) {
+                        sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+                } else {
+                        sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+                }
+        }
+}
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+        if (!sr_class->enable(sr->voltdm))
+                sr->autocomp_active = true;
+}
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+        if (sr->autocomp_active) {
+                sr_class->disable(sr->voltdm, 1);
+                sr->autocomp_active = false;
+        }
+}
+/*
+ * This function handles the intializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currently this function registers interrrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+        char *name;
+        struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+        struct resource *mem;
+        int ret = 0;
+        if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
+                name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
+                if (name == NULL) {
+                        ret = -ENOMEM;
+                        goto error;
+                }
+                ret = request_irq(sr_info->irq, sr_interrupt,
+                                0, name, (void *)sr_info);
+                if (ret)
+                        goto error;
+                disable_irq(sr_info->irq);
+        }
+        if (pdata && pdata->enable_on_init)
+                sr_start_vddautocomp(sr_info);
+        return ret;
+error:
+        iounmap(sr_info->base);
+        mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mem->start, resource_size(mem));
+        list_del(&sr_info->node);
+        dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+                "interrupt handler. Smartreflex will"
+                "not function as desired\n", __func__);
+        kfree(name);
+        kfree(sr_info);
+        return ret;
+}
+static void sr_v1_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+                        (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+                        ERRCONFIG_MCUBOUNDINTST |
+                        ERRCONFIG_VPBOUNDINTST_V1));
+        /*
+         * Wait for SR to be disabled.
+         * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+                        ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+                        timeout);
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+                        ERRCONFIG_MCUDISACKINTST);
+}
+static void sr_v2_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+                        ERRCONFIG_VPBOUNDINTST_V2);
+        sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+                        IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT));
+        sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+                        IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT));
+        /*
+         * Wait for SR to be disabled.
+         * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
+                        IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+                        timeout);
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+        sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+{
+        int i;
+        if (!sr->nvalue_table) {
+                dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+                        __func__);
+                return 0;
+        }
+        for (i = 0; i < sr->nvalue_count; i++) {
+                if (sr->nvalue_table[i].efuse_offs == efuse_offs)
+                        return sr->nvalue_table[i].nvalue;
+        }
+        return 0;
+}
+/* Public Functions */
+/**
+ * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
+ *                       error generator module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
+        u32 vpboundint_st, senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+                errconfig_offs = ERRCONFIG_V1;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+                errconfig_offs = ERRCONFIG_V2;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+                (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+                (sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
+        sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+                SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                sr_errconfig);
+        /* Enabling the interrupts if the ERROR module is used */
+        sr_modify_reg(sr, errconfig_offs,
+                vpboundint_en, (vpboundint_en | vpboundint_st));
+        return 0;
+}
+/**
+ * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
+ *                       minmaxavg module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_avgwt;
+        u32 senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE |
+                (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+                (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+        sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+        /*
+         * Enabling the interrupts if MINMAXAVG module is used.
+         * TODO: check if all the interrupts are mandatory
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN),
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+                         ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                sr_write_reg(sr, IRQSTATUS,
+                        IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+                sr_write_reg(sr, IRQENABLE_SET,
+                        IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+        }
+        return 0;
+}
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ * @volt:       The voltage at which the Voltage domain associated with
+ *              the smartreflex module is operating at.
+ *              This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+{
+        u32 nvalue_reciprocal;
+        struct omap_volt_data *volt_data;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        int ret;
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+        volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
+        if (IS_ERR(volt_data)) {
+                dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
+                        "for nominal voltage %ld\n", __func__, volt);
+                return -ENODATA;
+        }
+        nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
+        if (!nvalue_reciprocal) {
+                dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
+                        __func__, volt);
+                return -ENODATA;
+        }
+        /* errminlimit is opp dependent and hence linked to voltage */
+        sr->err_minlimit = volt_data->sr_errminlimit;
+        pm_runtime_get_sync(&sr->pdev->dev);
+        /* Check if SR is already enabled. If yes do nothing */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+                return 0;
+        /* Configure SR */
+        ret = sr_class->configure(voltdm);
+        if (ret)
+                return ret;
+        sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+        /* SRCONFIG - enable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+        return 0;
+}
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        /* Check if SR clocks are already disabled. If yes do nothing */
+        if (pm_runtime_suspended(&sr->pdev->dev))
+                return;
+        /*
+         * Disable SR if only it is indeed enabled. Else just
+         * disable the clocks.
+         */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+                if (sr->ip_type == SR_TYPE_V1)
+                        sr_v1_disable(sr);
+                else if (sr->ip_type == SR_TYPE_V2)
+                        sr_v2_disable(sr);
+        }
+        pm_runtime_put_sync_suspend(&sr->pdev->dev);
+}
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data: The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+        struct omap_sr *sr_info;
+        if (!class_data) {
+                pr_warning("%s:, Smartreflex class data passed is NULL\n",
+                        __func__);
+                return -EINVAL;
+        }
+        if (sr_class) {
+                pr_warning("%s: Smartreflex class driver already registered\n",
+                        __func__);
+                return -EBUSY;
+        }
+        sr_class = class_data;
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        list_for_each_entry(sr_info, &sr_list, node)
+                sr_late_init(sr_info);
+        return 0;
+}
+/**
+ * omap_sr_enable() -  API to enable SR clocks and to call into the
+ *                      registered smartreflex class enable API.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        if (!sr->autocomp_active)
+                return;
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+        sr_class->enable(voltdm);
+}
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ *                      processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        if (!sr->autocomp_active)
+                return;
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+        sr_class->disable(voltdm, 0);
+}
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ *                              voltage processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+        if (!sr->autocomp_active)
+                return;
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+        sr_class->disable(voltdm, 1);
+}
+/**
+ * omap_sr_register_pmic() - API to register pmic specific info.
+ * @pmic_data:  The structure containing pmic specific data.
+ *
+ * This API is to be called from the PMIC specific code to register with
+ * smartreflex driver pmic specific info. Currently the only info required
+ * is the smartreflex init on the PMIC side.
+ */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
+{
+        if (!pmic_data) {
+                pr_warning("%s: Trying to register NULL PMIC data structure"
+                        "with smartreflex\n", __func__);
+                return;
+        }
+        sr_pmic_data = pmic_data;
+}
+/* PM Debug Fs enteries to enable disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct not found\n", __func__);
+                return -EINVAL;
+        }
+        *val = sr_info->autocomp_active;
+        return 0;
+}
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct not found\n", __func__);
+                return -EINVAL;
+        }
+        /* Sanity check */
+        if (val && (val != 1)) {
+                pr_warning("%s: Invalid argument %lld\n", __func__, val);
+                return -EINVAL;
+        }
+        /* control enable/disable only if there is a delta in value */
+        if (sr_info->autocomp_active != val) {
+                if (!val)
+                        sr_stop_vddautocomp(sr_info);
+                else
+                        sr_start_vddautocomp(sr_info);
+        }
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+                omap_sr_autocomp_store, "%llu\n");
+static int __init omap_sr_probe(struct platform_device *pdev)
+{
+        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct resource *mem, *irq;
+        struct dentry *vdd_dbg_dir, *nvalue_dir;
+        struct omap_volt_data *volt_data;
+        int i, ret = 0;
+        if (!sr_info) {
+                dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+                        __func__);
+                return -ENOMEM;
+        }
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                ret = -EINVAL;
+                goto err_free_devinfo;
+        }
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+                ret = -ENODEV;
+                goto err_free_devinfo;
+        }
+        mem = request_mem_region(mem->start, resource_size(mem),
+                                        dev_name(&pdev->dev));
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem region\n", __func__);
+                ret = -EBUSY;
+                goto err_free_devinfo;
+        }
+        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_irq_safe(&pdev->dev);
+        sr_info->pdev = pdev;
+        sr_info->srid = pdev->id;
+        sr_info->voltdm = pdata->voltdm;
+        sr_info->nvalue_table = pdata->nvalue_table;
+        sr_info->nvalue_count = pdata->nvalue_count;
+        sr_info->senn_mod = pdata->senn_mod;
+        sr_info->senp_mod = pdata->senp_mod;
+        sr_info->autocomp_active = false;
+        sr_info->ip_type = pdata->ip_type;
+        sr_info->base = ioremap(mem->start, resource_size(mem));
+        if (!sr_info->base) {
+                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+                ret = -ENOMEM;
+                goto err_release_region;
+        }
+        if (irq)
+                sr_info->irq = irq->start;
+        sr_set_clk_length(sr_info);
+        sr_set_regfields(sr_info);
+        list_add(&sr_info->node, &sr_list);
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        if (sr_class) {
+                ret = sr_late_init(sr_info);
+                if (ret) {
+                        pr_warning("%s: Error in SR late init\n", __func__);
+                        return ret;
+                }
+        }
+        dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+        /*
+         * If the voltage domain debugfs directory is not created, do
+         * not try to create rest of the debugfs entries.
+         */
+        vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
+        if (!vdd_dbg_dir) {
+                ret = -EINVAL;
+                goto err_iounmap;
+        }
+        sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+        if (IS_ERR(sr_info->dbg_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+                        __func__);
+                ret = PTR_ERR(sr_info->dbg_dir);
+                goto err_iounmap;
+        }
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
+                        sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
+        (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_weight);
+        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_maxlimit);
+        (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
+                        &sr_info->err_minlimit);
+        nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+        if (IS_ERR(nvalue_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+                        "for n-values\n", __func__);
+                ret = PTR_ERR(nvalue_dir);
+                goto err_debugfs;
+        }
+        omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
+        if (!volt_data) {
+                dev_warn(&pdev->dev, "%s: No Voltage table for the"
+                        " corresponding vdd vdd_%s. Cannot create debugfs"
+                        "entries for n-values\n",
+                        __func__, sr_info->voltdm->name);
+                ret = -ENODATA;
+                goto err_debugfs;
+        }
+        for (i = 0; i < sr_info->nvalue_count; i++) {
+                char name[NVALUE_NAME_LEN + 1];
+                snprintf(name, sizeof(name), "volt_%d",
+                         volt_data[i].volt_nominal);
+                (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+                                &(sr_info->nvalue_table[i].nvalue));
+        }
+        return ret;
+err_debugfs:
+        debugfs_remove_recursive(sr_info->dbg_dir);
+err_iounmap:
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
+err_release_region:
+        release_mem_region(mem->start, resource_size(mem));
+err_free_devinfo:
+        kfree(sr_info);
+        return ret;
+}
+static int __devexit omap_sr_remove(struct platform_device *pdev)
+{
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct omap_sr *sr_info;
+        struct resource *mem;
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return -EINVAL;
+        }
+        sr_info = _sr_lookup(pdata->voltdm);
+        if (IS_ERR(sr_info)) {
+                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+                        __func__);
+                return -EINVAL;
+        }
+        if (sr_info->autocomp_active)
+                sr_stop_vddautocomp(sr_info);
+        if (sr_info->dbg_dir)
+                debugfs_remove_recursive(sr_info->dbg_dir);
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
+        kfree(sr_info);
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mem->start, resource_size(mem));
+        return 0;
+}
+static struct platform_driver smartreflex_driver = {
+        .remove         = omap_sr_remove,
+        .driver         = {
+                .name   = "smartreflex",
+        },
+};
+static int __init sr_init(void)
+{
+        int ret = 0;
+        /*
+         * sr_init is a late init. If by then a pmic specific API is not
+         * registered either there is no need for anything to be done on
+         * the PMIC side or somebody has forgotten to register a PMIC
+         * handler. Warn for the second condition.
+         */
+        if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
+                sr_pmic_data->sr_pmic_init();
+        else
+                pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
+        ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
+        if (ret) {
+                pr_err("%s: platform driver register failed for SR\n",
+                        __func__);
+                return ret;
+        }
+        return 0;
+}
+static void __exit sr_exit(void)
+{
+        platform_driver_unregister(&smartreflex_driver);
+}
+late_initcall(sr_init);
+module_exit(sr_exit);
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
new file mode 100644
index 00000000000..5f35b9e2555
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -0,0 +1,246 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+#define __ASM_ARM_OMAP_SMARTREFLEX_H
+#include <linux/platform_device.h>
+#include "voltage.h"
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1      1
+#define SR_TYPE_V2      2
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG                0x00
+#define SRSTATUS                0x04
+#define SENVAL                  0x08
+#define SENMIN                  0x0C
+#define SENMAX                  0x10
+#define SENAVG                  0x14
+#define AVGWEIGHT               0x18
+#define NVALUERECIPROCAL        0x1c
+#define SENERROR_V1             0x20
+#define ERRCONFIG_V1            0x24
+#define IRQ_EOI                 0x20
+#define IRQSTATUS_RAW           0x24
+#define IRQSTATUS               0x28
+#define IRQENABLE_SET           0x2C
+#define IRQENABLE_CLR           0x30
+#define SENERROR_V2             0x34
+#define ERRCONFIG_V2            0x38
+/* Bit/Shift Positions */
+/* SRCONFIG */
+#define SRCONFIG_ACCUMDATA_SHIFT        22
+#define SRCONFIG_SRCLKLENGTH_SHIFT      12
+#define SRCONFIG_SENNENABLE_V1_SHIFT    5
+#define SRCONFIG_SENPENABLE_V1_SHIFT    3
+#define SRCONFIG_SENNENABLE_V2_SHIFT    1
+#define SRCONFIG_SENPENABLE_V2_SHIFT    0
+#define SRCONFIG_CLKCTRL_SHIFT          0
+#define SRCONFIG_ACCUMDATA_MASK         (0x3ff << 22)
+#define SRCONFIG_SRENABLE               BIT(11)
+#define SRCONFIG_SENENABLE              BIT(10)
+#define SRCONFIG_ERRGEN_EN              BIT(9)
+#define SRCONFIG_MINMAXAVG_EN           BIT(8)
+#define SRCONFIG_DELAYCTRL              BIT(2)
+/* AVGWEIGHT */
+#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
+#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+#define NVALUERECIPROCAL_RNSENP_SHIFT   8
+#define NVALUERECIPROCAL_RNSENN_SHIFT   0
+/* ERRCONFIG */
+#define ERRCONFIG_ERRWEIGHT_SHIFT       16
+#define ERRCONFIG_ERRMAXLIMIT_SHIFT     8
+#define ERRCONFIG_ERRMINLIMIT_SHIFT     0
+#define SR_ERRWEIGHT_MASK               (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK             (0xff << 8)
+#define SR_ERRMINLIMIT_MASK             (0xff << 0)
+#define ERRCONFIG_VPBOUNDINTEN_V1       BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1       BIT(30)
+#define ERRCONFIG_MCUACCUMINTEN         BIT(29)
+#define ERRCONFIG_MCUACCUMINTST         BIT(28)
+#define ERRCONFIG_MCUVALIDINTEN         BIT(27)
+#define ERRCONFIG_MCUVALIDINTST         BIT(26)
+#define ERRCONFIG_MCUBOUNDINTEN         BIT(25)
+#define ERRCONFIG_MCUBOUNDINTST         BIT(24)
+#define ERRCONFIG_MCUDISACKINTEN        BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2       BIT(23)
+#define ERRCONFIG_MCUDISACKINTST        BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2       BIT(22)
+#define ERRCONFIG_STATUS_V1_MASK        (ERRCONFIG_VPBOUNDINTST_V1 | \
+                                        ERRCONFIG_MCUACCUMINTST | \
+                                        ERRCONFIG_MCUVALIDINTST | \
+                                        ERRCONFIG_MCUBOUNDINTST | \
+                                        ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT           BIT(3)
+#define IRQSTATUS_MCVALIDINT            BIT(2)
+#define IRQSTATUS_MCBOUNDSINT           BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT      BIT(0)
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT           BIT(3)
+#define IRQENABLE_MCUVALIDINT           BIT(2)
+#define IRQENABLE_MCUBOUNDSINT          BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT      BIT(0)
+/* Common Bit values */
+#define SRCLKLENGTH_12MHZ_SYSCLK        0x3c
+#define SRCLKLENGTH_13MHZ_SYSCLK        0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK        0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK        0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
+/*
+ * 3430 specific values. Maybe these should be passed from board file or
+ * pmic structures.
+ */
+#define OMAP3430_SR_ACCUMDATA           0x1f4
+#define OMAP3430_SR1_SENPAVGWEIGHT      0x03
+#define OMAP3430_SR1_SENNAVGWEIGHT      0x03
+#define OMAP3430_SR2_SENPAVGWEIGHT      0x01
+#define OMAP3430_SR2_SENNAVGWEIGHT      0x01
+#define OMAP3430_SR_ERRWEIGHT           0x04
+#define OMAP3430_SR_ERRMAXLIMIT         0x02
+/**
+ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ *                              pmic specific info to smartreflex driver
+ *
+ * @sr_pmic_init:       API to initialize smartreflex on the PMIC side.
+ */
+struct omap_sr_pmic_data {
+        void (*sr_pmic_init) (void);
+};
+#ifdef CONFIG_OMAP_SMARTREFLEX
+/*
+ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ * The smartreflex class driver should pass the class type.
+ * Should be used to populate the class_type field of the
+ * omap_smartreflex_class_data structure.
+ */
+#define SR_CLASS1       0x1
+#define SR_CLASS2       0x2
+#define SR_CLASS3       0x3
+/**
+ * struct omap_sr_class_data - Smartreflex class driver info
+ *
+ * @enable:             API to enable a particular class smaartreflex.
+ * @disable:            API to disable a particular class smartreflex.
+ * @configure:          API to configure a particular class smartreflex.
+ * @notify:             API to notify the class driver about an event in SR.
+ *                      Not needed for class3.
+ * @notify_flags:       specify the events to be notified to the class driver
+ * @class_type:         specify which smartreflex class.
+ *                      Can be used by the SR driver to take any class
+ *                      based decisions.
+ */
+struct omap_sr_class_data {
+        int (*enable)(struct voltagedomain *voltdm);
+        int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+        int (*configure)(struct voltagedomain *voltdm);
+        int (*notify)(struct voltagedomain *voltdm, u32 status);
+        u8 notify_flags;
+        u8 class_type;
+};
+/**
+ * struct omap_sr_nvalue_table  - Smartreflex n-target value info
+ *
+ * @efuse_offs: The offset of the efuse where n-target values are stored.
+ * @nvalue:     The n-target value.
+ */
+struct omap_sr_nvalue_table {
+        u32 efuse_offs;
+        u32 nvalue;
+};
+/**
+ * struct omap_sr_data - Smartreflex platform data.
+ *
+ * @ip_type:            Smartreflex IP type.
+ * @senp_mod:           SENPENABLE value for the sr
+ * @senn_mod:           SENNENABLE value for sr
+ * @nvalue_count:       Number of distinct nvalues in the nvalue table
+ * @enable_on_init:     whether this sr module needs to enabled at
+ *                      boot up or not.
+ * @nvalue_table:       table containing the  efuse offsets and nvalues
+ *                      corresponding to them.
+ * @voltdm:             Pointer to the voltage domain associated with the SR
+ */
+struct omap_sr_data {
+        int                             ip_type;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        int                             nvalue_count;
+        bool                            enable_on_init;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+};
+/* Smartreflex module enable/disable interface */
+void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+/* API to register the pmic specific data with the smartreflex driver. */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+/* Smartreflex driver hooks to be called from Smartreflex class driver */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+void sr_disable(struct voltagedomain *voltdm);
+int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_configure_minmax(struct voltagedomain *voltdm);
+/* API to register the smartreflex class driver with the smartreflex driver */
+int sr_register_class(struct omap_sr_class_data *class_data);
+#else
+static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable_reset_volt(
+                struct voltagedomain *voltdm) {}
+static inline void omap_sr_register_pmic(
+                struct omap_sr_pmic_data *pmic_data) {}
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
new file mode 100644
index 00000000000..31c0ac4cd66
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -0,0 +1,39 @@
+/*
+ * The MPU local timer source file. In OMAP4, both cortex-a9 cores have
+ * own timer in it's MPU domain. These timers will be driving the
+ * linux kernel SMP tick framework when active. These timers are not
+ * part of the wake up domain.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This file is based on arm realview smp platform file.
+ * Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        /* Local timers are not supprted on OMAP4430 ES1.0 */
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+        evt->irq = OMAP44XX_IRQ_LOCALTIMER;
+        twd_timer_setup(evt);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
new file mode 100644
index 00000000000..1481078763b
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -0,0 +1,359 @@
+/*
+ * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/irq.h>
+#include <plat/usb.h>
+#include <plat/board.h>
+#include "control.h"
+#include "mux.h"
+#define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
+#define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
+#define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
+#define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
+#define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
+#if defined(CONFIG_ARCH_OMAP2)
+#ifdef  CONFIG_USB_GADGET_OMAP
+static struct resource udc_resources[] = {
+        /* order is significant! */
+        {               /* registers */
+                .start          = UDC_BASE,
+                .end            = UDC_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {            /* general IRQ */
+                .start          = INT_USB_IRQ_GEN,
+                .flags          = IORESOURCE_IRQ,
+        }, {            /* PIO IRQ */
+                .start          = INT_USB_IRQ_NISO,
+                .flags          = IORESOURCE_IRQ,
+        }, {            /* SOF IRQ */
+                .start          = INT_USB_IRQ_ISO,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static u64 udc_dmamask = ~(u32)0;
+static struct platform_device udc_device = {
+        .name           = "omap_udc",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &udc_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(udc_resources),
+        .resource       = udc_resources,
+};
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+        pdata->udc_device = &udc_device;
+}
+#else
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+static struct resource ohci_resources[] = {
+        {
+                .start  = OMAP_OHCI_BASE,
+                .end    = OMAP_OHCI_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_IRQ_HGEN,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ohci_device = {
+        .name                   = "ohci",
+        .id                     = -1,
+        .dev = {
+                .dma_mask               = &ohci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(ohci_resources),
+        .resource               = ohci_resources,
+};
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+        pdata->ohci_device = &ohci_device;
+}
+#else
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+#if     defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+static struct resource otg_resources[] = {
+        /* order is significant! */
+        {
+                .start          = OTG_BASE,
+                .end            = OTG_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = INT_USB_IRQ_OTG,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device otg_device = {
+        .name           = "omap_otg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(otg_resources),
+        .resource       = otg_resources,
+};
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+        pdata->otg_device = &otg_device;
+}
+#else
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+        u32 r;
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+        u32 r;
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+static void omap2_usb2_disable_5pinbitll(void)
+{
+        u32 r;
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+static void omap2_usb2_enable_5pinunitll(void)
+{
+        u32 r;
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
+{
+        u32     syscon1 = 0;
+        omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
+        if (nwires == 0)
+                return 0;
+        if (is_device)
+                omap_mux_init_signal("usb0_puen", 0);
+        omap_mux_init_signal("usb0_dat", 0);
+        omap_mux_init_signal("usb0_txen", 0);
+        omap_mux_init_signal("usb0_se0", 0);
+        if (nwires != 3)
+                omap_mux_init_signal("usb0_rcv", 0);
+        switch (nwires) {
+        case 3:
+                syscon1 = 2;
+                omap2_usb_devconf_set(0, USB_BIDIR);
+                break;
+        case 4:
+                syscon1 = 1;
+                omap2_usb_devconf_set(0, USB_BIDIR);
+                break;
+        case 6:
+                syscon1 = 3;
+                omap_mux_init_signal("usb0_vp", 0);
+                omap_mux_init_signal("usb0_vm", 0);
+                omap2_usb_devconf_set(0, USB_UNIDIR);
+                break;
+        default:
+                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                        0, nwires);
+        }
+        return syscon1 << 16;
+}
+static u32 __init omap2_usb1_init(unsigned nwires)
+{
+        u32     syscon1 = 0;
+        omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
+        if (nwires == 0)
+                return 0;
+        /* NOTE:  board-specific code must set up pin muxing for usb1,
+         * since each signal could come out on either of two balls.
+         */
+        switch (nwires) {
+        case 2:
+                /* NOTE: board-specific code must override this setting if
+                 * this TLL link is not using DP/DM
+                 */
+                syscon1 = 1;
+                omap2_usb_devconf_set(1, USB_BIDIR_TLL);
+                break;
+        case 3:
+                syscon1 = 2;
+                omap2_usb_devconf_set(1, USB_BIDIR);
+                break;
+        case 4:
+                syscon1 = 1;
+                omap2_usb_devconf_set(1, USB_BIDIR);
+                break;
+        case 6:
+        default:
+                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                        1, nwires);
+        }
+        return syscon1 << 20;
+}
+static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+        u32     syscon1 = 0;
+        omap2_usb2_disable_5pinbitll();
+        alt_pingroup = 0;
+        /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+        if (alt_pingroup || nwires == 0)
+                return 0;
+        omap_mux_init_signal("usb2_dat", 0);
+        omap_mux_init_signal("usb2_se0", 0);
+        if (nwires > 2)
+                omap_mux_init_signal("usb2_txen", 0);
+        if (nwires > 3)
+                omap_mux_init_signal("usb2_rcv", 0);
+        switch (nwires) {
+        case 2:
+                /* NOTE: board-specific code must override this setting if
+                 * this TLL link is not using DP/DM
+                 */
+                syscon1 = 1;
+                omap2_usb_devconf_set(2, USB_BIDIR_TLL);
+                break;
+        case 3:
+                syscon1 = 2;
+                omap2_usb_devconf_set(2, USB_BIDIR);
+                break;
+        case 4:
+                syscon1 = 1;
+                omap2_usb_devconf_set(2, USB_BIDIR);
+                break;
+        case 5:
+                /* NOTE: board-specific code must mux this setting depending
+                 * on TLL link using DP/DM.  Something must also
+                 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+                 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
+                 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
+                 */
+                syscon1 = 3;
+                omap2_usb2_enable_5pinunitll();
+                break;
+        case 6:
+        default:
+                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                        2, nwires);
+        }
+        return syscon1 << 24;
+}
+void __init omap2_usbfs_init(struct omap_usb_config *pdata)
+{
+        struct clk *ick;
+        if (!cpu_is_omap24xx())
+                return;
+        ick = clk_get(NULL, "usb_l4_ick");
+        if (IS_ERR(ick))
+                return;
+        clk_enable(ick);
+        pdata->usb0_init = omap2_usb0_init;
+        pdata->usb1_init = omap2_usb1_init;
+        pdata->usb2_init = omap2_usb2_init;
+        udc_device_init(pdata);
+        ohci_device_init(pdata);
+        otg_device_init(pdata);
+        omap_otg_init(pdata);
+        clk_disable(ick);
+        clk_put(ick);
+}
+#endif