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-rw-r--r--arch/arm/mach-mx5/Kconfig244
-rw-r--r--arch/arm/mach-mx5/Makefile26
-rw-r--r--arch/arm/mach-mx5/Makefile.boot9
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c301
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c339
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c226
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c179
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c430
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c296
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c291
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c261
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c179
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c321
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c168
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c1675
-rw-r--r--arch/arm/mach-mx5/cpu.c187
-rw-r--r--arch/arm/mach-mx5/cpu_op-mx51.c29
-rw-r--r--arch/arm/mach-mx5/cpu_op-mx51.h14
-rw-r--r--arch/arm/mach-mx5/crm_regs.h600
-rw-r--r--arch/arm/mach-mx5/devices-imx50.h34
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h71
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h48
-rw-r--r--arch/arm/mach-mx5/efika.h10
-rw-r--r--arch/arm/mach-mx5/ehci.c156
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c206
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c146
-rw-r--r--arch/arm/mach-mx5/imx51-dt.c119
-rw-r--r--arch/arm/mach-mx5/imx53-dt.c129
-rw-r--r--arch/arm/mach-mx5/mm.c209
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c632
-rw-r--r--arch/arm/mach-mx5/pm-imx5.c83
-rw-r--r--arch/arm/mach-mx5/system.c82
32 files changed, 0 insertions, 7700 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
deleted file mode 100644
index af0c212e3c7..00000000000
--- a/arch/arm/mach-mx5/Kconfig
+++ /dev/null
@@ -1,244 +0,0 @@
1if ARCH_MX5
2
3# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
4# image. So for most time, SOC_IMX50/51/53 should be used.
5
6config ARCH_MX51
7 bool
8
9config ARCH_MX50
10 bool
11
12config ARCH_MX53
13 bool
14
15config SOC_IMX50
16 bool
17 select CPU_V7
18 select ARM_L1_CACHE_SHIFT_6
19 select MXC_TZIC
20 select ARCH_MXC_IOMUX_V3
21 select ARCH_MXC_AUDMUX_V2
22 select ARCH_HAS_CPUFREQ
23 select ARCH_MX50
24
25config SOC_IMX51
26 bool
27 select CPU_V7
28 select ARM_L1_CACHE_SHIFT_6
29 select MXC_TZIC
30 select ARCH_MXC_IOMUX_V3
31 select ARCH_MXC_AUDMUX_V2
32 select ARCH_HAS_CPUFREQ
33 select ARCH_MX51
34
35config SOC_IMX53
36 bool
37 select CPU_V7
38 select ARM_L1_CACHE_SHIFT_6
39 select MXC_TZIC
40 select ARCH_MXC_IOMUX_V3
41 select ARCH_MX53
42
43#comment "i.MX50 machines:"
44
45config MACH_MX50_RDP
46 bool "Support MX50 reference design platform"
47 depends on BROKEN
48 select SOC_IMX50
49 select IMX_HAVE_PLATFORM_IMX_I2C
50 select IMX_HAVE_PLATFORM_IMX_UART
51 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
52 select IMX_HAVE_PLATFORM_SPI_IMX
53 help
54 Include support for MX50 reference design platform (RDP) board. This
55 includes specific configurations for the board and its peripherals.
56
57comment "i.MX51 machines:"
58
59config MACH_IMX51_DT
60 bool "Support i.MX51 platforms from device tree"
61 select SOC_IMX51
62 select USE_OF
63 select MACH_MX51_BABBAGE
64 help
65 Include support for Freescale i.MX51 based platforms
66 using the device tree for discovery
67
68config MACH_MX51_BABBAGE
69 bool "Support MX51 BABBAGE platforms"
70 select SOC_IMX51
71 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
72 select IMX_HAVE_PLATFORM_IMX2_WDT
73 select IMX_HAVE_PLATFORM_IMX_I2C
74 select IMX_HAVE_PLATFORM_IMX_UART
75 select IMX_HAVE_PLATFORM_MXC_EHCI
76 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
77 select IMX_HAVE_PLATFORM_SPI_IMX
78 help
79 Include support for MX51 Babbage platform, also known as MX51EVK in
80 u-boot. This includes specific configurations for the board and its
81 peripherals.
82
83config MACH_MX51_3DS
84 bool "Support MX51PDK (3DS)"
85 select SOC_IMX51
86 select IMX_HAVE_PLATFORM_IMX2_WDT
87 select IMX_HAVE_PLATFORM_IMX_KEYPAD
88 select IMX_HAVE_PLATFORM_IMX_UART
89 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
90 select IMX_HAVE_PLATFORM_SPI_IMX
91 select MXC_DEBUG_BOARD
92 help
93 Include support for MX51PDK (3DS) platform. This includes specific
94 configurations for the board and its peripherals.
95
96config MACH_EUKREA_CPUIMX51
97 bool "Support Eukrea CPUIMX51 module"
98 select SOC_IMX51
99 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
100 select IMX_HAVE_PLATFORM_IMX_I2C
101 select IMX_HAVE_PLATFORM_IMX_UART
102 select IMX_HAVE_PLATFORM_MXC_EHCI
103 select IMX_HAVE_PLATFORM_MXC_NAND
104 select IMX_HAVE_PLATFORM_SPI_IMX
105 help
106 Include support for Eukrea CPUIMX51 platform. This includes
107 specific configurations for the module and its peripherals.
108
109choice
110 prompt "Baseboard"
111 depends on MACH_EUKREA_CPUIMX51
112 default MACH_EUKREA_MBIMX51_BASEBOARD
113
114config MACH_EUKREA_MBIMX51_BASEBOARD
115 prompt "Eukrea MBIMX51 development board"
116 bool
117 select IMX_HAVE_PLATFORM_IMX_KEYPAD
118 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
119 select LEDS_GPIO_REGISTER
120 help
121 This adds board specific devices that can be found on Eukrea's
122 MBIMX51 evaluation board.
123
124endchoice
125
126config MACH_EUKREA_CPUIMX51SD
127 bool "Support Eukrea CPUIMX51SD module"
128 select SOC_IMX51
129 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
130 select IMX_HAVE_PLATFORM_IMX_I2C
131 select IMX_HAVE_PLATFORM_IMX_UART
132 select IMX_HAVE_PLATFORM_MXC_EHCI
133 select IMX_HAVE_PLATFORM_MXC_NAND
134 select IMX_HAVE_PLATFORM_SPI_IMX
135 help
136 Include support for Eukrea CPUIMX51SD platform. This includes
137 specific configurations for the module and its peripherals.
138
139choice
140 prompt "Baseboard"
141 depends on MACH_EUKREA_CPUIMX51SD
142 default MACH_EUKREA_MBIMXSD51_BASEBOARD
143
144config MACH_EUKREA_MBIMXSD51_BASEBOARD
145 prompt "Eukrea MBIMXSD development board"
146 bool
147 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
148 select LEDS_GPIO_REGISTER
149 help
150 This adds board specific devices that can be found on Eukrea's
151 MBIMXSD evaluation board.
152
153endchoice
154
155config MX51_EFIKA_COMMON
156 bool
157 select SOC_IMX51
158 select IMX_HAVE_PLATFORM_IMX_UART
159 select IMX_HAVE_PLATFORM_MXC_EHCI
160 select IMX_HAVE_PLATFORM_PATA_IMX
161 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
162 select IMX_HAVE_PLATFORM_SPI_IMX
163 select MXC_ULPI if USB_ULPI
164
165config MACH_MX51_EFIKAMX
166 bool "Support MX51 Genesi Efika MX nettop"
167 select LEDS_GPIO_REGISTER
168 select MX51_EFIKA_COMMON
169 help
170 Include support for Genesi Efika MX nettop. This includes specific
171 configurations for the board and its peripherals.
172
173config MACH_MX51_EFIKASB
174 bool "Support MX51 Genesi Efika Smartbook"
175 select LEDS_GPIO_REGISTER
176 select MX51_EFIKA_COMMON
177 help
178 Include support for Genesi Efika Smartbook. This includes specific
179 configurations for the board and its peripherals.
180
181comment "i.MX53 machines:"
182
183config MACH_IMX53_DT
184 bool "Support i.MX53 platforms from device tree"
185 select SOC_IMX53
186 select USE_OF
187 select MACH_MX53_ARD
188 select MACH_MX53_EVK
189 select MACH_MX53_LOCO
190 select MACH_MX53_SMD
191 help
192 Include support for Freescale i.MX53 based platforms
193 using the device tree for discovery
194
195config MACH_MX53_EVK
196 bool "Support MX53 EVK platforms"
197 select SOC_IMX53
198 select IMX_HAVE_PLATFORM_IMX2_WDT
199 select IMX_HAVE_PLATFORM_IMX_UART
200 select IMX_HAVE_PLATFORM_IMX_I2C
201 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
202 select IMX_HAVE_PLATFORM_SPI_IMX
203 select LEDS_GPIO_REGISTER
204 help
205 Include support for MX53 EVK platform. This includes specific
206 configurations for the board and its peripherals.
207
208config MACH_MX53_SMD
209 bool "Support MX53 SMD platforms"
210 select SOC_IMX53
211 select IMX_HAVE_PLATFORM_IMX2_WDT
212 select IMX_HAVE_PLATFORM_IMX_I2C
213 select IMX_HAVE_PLATFORM_IMX_UART
214 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
215 help
216 Include support for MX53 SMD platform. This includes specific
217 configurations for the board and its peripherals.
218
219config MACH_MX53_LOCO
220 bool "Support MX53 LOCO platforms"
221 select SOC_IMX53
222 select IMX_HAVE_PLATFORM_IMX2_WDT
223 select IMX_HAVE_PLATFORM_IMX_I2C
224 select IMX_HAVE_PLATFORM_IMX_UART
225 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
226 select IMX_HAVE_PLATFORM_GPIO_KEYS
227 select LEDS_GPIO_REGISTER
228 help
229 Include support for MX53 LOCO platform. This includes specific
230 configurations for the board and its peripherals.
231
232config MACH_MX53_ARD
233 bool "Support MX53 ARD platforms"
234 select SOC_IMX53
235 select IMX_HAVE_PLATFORM_IMX2_WDT
236 select IMX_HAVE_PLATFORM_IMX_I2C
237 select IMX_HAVE_PLATFORM_IMX_UART
238 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
239 select IMX_HAVE_PLATFORM_GPIO_KEYS
240 help
241 Include support for MX53 ARD platform. This includes specific
242 configurations for the board and its peripherals.
243
244endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
deleted file mode 100644
index 0fc60807fa2..00000000000
--- a/arch/arm/mach-mx5/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
7
8obj-$(CONFIG_PM) += pm-imx5.o
9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
10obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
11obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
12obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
13obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
14obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
15obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
16obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
17obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
18obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
19obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
20obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
21obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
22obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
23obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
24
25obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
26obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
deleted file mode 100644
index ca207ca305e..00000000000
--- a/arch/arm/mach-mx5/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
1 zreladdr-$(CONFIG_ARCH_MX50) += 0x70008000
2params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
3initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
4 zreladdr-$(CONFIG_ARCH_MX51) += 0x90008000
5params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
6initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
7 zreladdr-$(CONFIG_ARCH_MX53) += 0x70008000
8params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
9initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
deleted file mode 100644
index 944025da833..00000000000
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ /dev/null
@@ -1,301 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/serial_8250.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25
26#include <mach/eukrea-baseboards.h>
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx51.h>
30
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35
36#include "devices-imx51.h"
37
38#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
39#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
40#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
41#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
42#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
43#define CPUIMX51_QUART_XTAL 14745600
44#define CPUIMX51_QUART_REGSHIFT 17
45
46/* USB_CTRL_1 */
47#define MX51_USB_CTRL_1_OFFSET 0x10
48#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
49
50#define MX51_USB_PLLDIV_12_MHZ 0x00
51#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
52#define MX51_USB_PLL_DIV_24_MHZ 0x02
53
54static struct plat_serial8250_port serial_platform_data[] = {
55 {
56 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
57 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
58 .irqflags = IRQF_TRIGGER_HIGH,
59 .uartclk = CPUIMX51_QUART_XTAL,
60 .regshift = CPUIMX51_QUART_REGSHIFT,
61 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
63 }, {
64 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
65 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
66 .irqflags = IRQF_TRIGGER_HIGH,
67 .uartclk = CPUIMX51_QUART_XTAL,
68 .regshift = CPUIMX51_QUART_REGSHIFT,
69 .iotype = UPIO_MEM,
70 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
71 }, {
72 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
73 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
74 .irqflags = IRQF_TRIGGER_HIGH,
75 .uartclk = CPUIMX51_QUART_XTAL,
76 .regshift = CPUIMX51_QUART_REGSHIFT,
77 .iotype = UPIO_MEM,
78 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
79 }, {
80 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
81 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
82 .irqflags = IRQF_TRIGGER_HIGH,
83 .uartclk = CPUIMX51_QUART_XTAL,
84 .regshift = CPUIMX51_QUART_REGSHIFT,
85 .iotype = UPIO_MEM,
86 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
87 }, {
88 }
89};
90
91static struct platform_device serial_device = {
92 .name = "serial8250",
93 .id = 0,
94 .dev = {
95 .platform_data = serial_platform_data,
96 },
97};
98
99static struct platform_device *devices[] __initdata = {
100 &serial_device,
101};
102
103static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
104 /* UART1 */
105 MX51_PAD_UART1_RXD__UART1_RXD,
106 MX51_PAD_UART1_TXD__UART1_TXD,
107 MX51_PAD_UART1_RTS__UART1_RTS,
108 MX51_PAD_UART1_CTS__UART1_CTS,
109
110 /* I2C2 */
111 MX51_PAD_GPIO1_2__I2C2_SCL,
112 MX51_PAD_GPIO1_3__I2C2_SDA,
113 MX51_PAD_NANDF_D10__GPIO3_30,
114
115 /* QUART IRQ */
116 MX51_PAD_NANDF_D15__GPIO3_25,
117 MX51_PAD_NANDF_D14__GPIO3_26,
118 MX51_PAD_NANDF_D13__GPIO3_27,
119 MX51_PAD_NANDF_D12__GPIO3_28,
120
121 /* USB HOST1 */
122 MX51_PAD_USBH1_CLK__USBH1_CLK,
123 MX51_PAD_USBH1_DIR__USBH1_DIR,
124 MX51_PAD_USBH1_NXT__USBH1_NXT,
125 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
126 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
127 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
128 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
129 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
130 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
131 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
132 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
133 MX51_PAD_USBH1_STP__USBH1_STP,
134};
135
136static const struct mxc_nand_platform_data
137 eukrea_cpuimx51_nand_board_info __initconst = {
138 .width = 1,
139 .hw_ecc = 1,
140 .flash_bbt = 1,
141};
142
143static const struct imxuart_platform_data uart_pdata __initconst = {
144 .flags = IMXUART_HAVE_RTSCTS,
145};
146
147static const
148struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
149 .bitrate = 100000,
150};
151
152static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
153 {
154 I2C_BOARD_INFO("pcf8563", 0x51),
155 },
156};
157
158/* This function is board specific as the bit mask for the plldiv will also
159be different for other Freescale SoCs, thus a common bitmask is not
160possible and cannot get place in /plat-mxc/ehci.c.*/
161static int initialize_otg_port(struct platform_device *pdev)
162{
163 u32 v;
164 void __iomem *usb_base;
165 void __iomem *usbother_base;
166
167 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
168 if (!usb_base)
169 return -ENOMEM;
170 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
171
172 /* Set the PHY clock to 19.2MHz */
173 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
174 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
175 v |= MX51_USB_PLL_DIV_19_2_MHZ;
176 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
177 iounmap(usb_base);
178
179 mdelay(10);
180
181 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
182}
183
184static int initialize_usbh1_port(struct platform_device *pdev)
185{
186 u32 v;
187 void __iomem *usb_base;
188 void __iomem *usbother_base;
189
190 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
191 if (!usb_base)
192 return -ENOMEM;
193 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
194
195 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
196 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
197 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
198 iounmap(usb_base);
199
200 mdelay(10);
201
202 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
203 MXC_EHCI_ITC_NO_THRESHOLD);
204}
205
206static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
207 .init = initialize_otg_port,
208 .portsc = MXC_EHCI_UTMI_16BIT,
209};
210
211static const struct fsl_usb2_platform_data usb_pdata __initconst = {
212 .operating_mode = FSL_USB2_DR_DEVICE,
213 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
214};
215
216static const struct mxc_usbh_platform_data usbh1_config __initconst = {
217 .init = initialize_usbh1_port,
218 .portsc = MXC_EHCI_MODE_ULPI,
219};
220
221static int otg_mode_host;
222
223static int __init eukrea_cpuimx51_otg_mode(char *options)
224{
225 if (!strcmp(options, "host"))
226 otg_mode_host = 1;
227 else if (!strcmp(options, "device"))
228 otg_mode_host = 0;
229 else
230 pr_info("otg_mode neither \"host\" nor \"device\". "
231 "Defaulting to device\n");
232 return 0;
233}
234__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
235
236/*
237 * Board specific initialization.
238 */
239static void __init eukrea_cpuimx51_init(void)
240{
241 imx51_soc_init();
242
243 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
244 ARRAY_SIZE(eukrea_cpuimx51_pads));
245
246 imx51_add_imx_uart(0, &uart_pdata);
247 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
248
249 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
250 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
251 gpio_free(CPUIMX51_QUARTA_GPIO);
252 gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
253 gpio_direction_input(CPUIMX51_QUARTB_GPIO);
254 gpio_free(CPUIMX51_QUARTB_GPIO);
255 gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
256 gpio_direction_input(CPUIMX51_QUARTC_GPIO);
257 gpio_free(CPUIMX51_QUARTC_GPIO);
258 gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
259 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
260 gpio_free(CPUIMX51_QUARTD_GPIO);
261
262 imx51_add_fec(NULL);
263 platform_add_devices(devices, ARRAY_SIZE(devices));
264
265 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
266 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
267 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
268
269 if (otg_mode_host)
270 imx51_add_mxc_ehci_otg(&dr_utmi_config);
271 else {
272 initialize_otg_port(NULL);
273 imx51_add_fsl_usb2_udc(&usb_pdata);
274 }
275 imx51_add_mxc_ehci_hs(1, &usbh1_config);
276
277#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
278 eukrea_mbimx51_baseboard_init();
279#endif
280}
281
282static void __init eukrea_cpuimx51_timer_init(void)
283{
284 mx51_clocks_init(32768, 24000000, 22579200, 0);
285}
286
287static struct sys_timer mxc_timer = {
288 .init = eukrea_cpuimx51_timer_init,
289};
290
291MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
292 /* Maintainer: Eric Bénard <eric@eukrea.com> */
293 .atag_offset = 0x100,
294 .map_io = mx51_map_io,
295 .init_early = imx51_init_early,
296 .init_irq = mx51_init_irq,
297 .handle_irq = imx51_handle_irq,
298 .timer = &mxc_timer,
299 .init_machine = eukrea_cpuimx51_init,
300 .restart = mxc_restart,
301MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
deleted file mode 100644
index 9fbe923c8b0..00000000000
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ /dev/null
@@ -1,339 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/i2c-gpio.h>
26#include <linux/spi/spi.h>
27#include <linux/can/platform/mcp251x.h>
28
29#include <mach/eukrea-baseboards.h>
30#include <mach/common.h>
31#include <mach/hardware.h>
32#include <mach/iomux-mx51.h>
33
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38
39#include "devices-imx51.h"
40#include "cpu_op-mx51.h"
41
42#define USBH1_RST IMX_GPIO_NR(2, 28)
43#define ETH_RST IMX_GPIO_NR(2, 31)
44#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
45#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
46#define CAN_RST IMX_GPIO_NR(4, 15)
47#define CAN_NCS IMX_GPIO_NR(4, 24)
48#define CAN_RXOBF IMX_GPIO_NR(1, 4)
49#define CAN_RX1BF IMX_GPIO_NR(1, 6)
50#define CAN_TXORTS IMX_GPIO_NR(1, 7)
51#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
52#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
53#define I2C_SCL IMX_GPIO_NR(4, 16)
54#define I2C_SDA IMX_GPIO_NR(4, 17)
55
56/* USB_CTRL_1 */
57#define MX51_USB_CTRL_1_OFFSET 0x10
58#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
59
60#define MX51_USB_PLLDIV_12_MHZ 0x00
61#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
62#define MX51_USB_PLL_DIV_24_MHZ 0x02
63
64static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* USB HOST1 */
72 MX51_PAD_USBH1_CLK__USBH1_CLK,
73 MX51_PAD_USBH1_DIR__USBH1_DIR,
74 MX51_PAD_USBH1_NXT__USBH1_NXT,
75 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
76 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
77 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
78 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
79 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
80 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
81 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
82 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
83 MX51_PAD_USBH1_STP__USBH1_STP,
84 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
85
86 /* FEC */
87 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
88
89 /* HSI2C */
90 MX51_PAD_I2C1_CLK__GPIO4_16,
91 MX51_PAD_I2C1_DAT__GPIO4_17,
92
93 /* CAN */
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
96 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
97 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
98 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
99 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
100 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
101 MX51_PAD_GPIO1_6__GPIO1_6,
102 MX51_PAD_GPIO1_7__GPIO1_7,
103 MX51_PAD_GPIO1_8__GPIO1_8,
104 MX51_PAD_GPIO1_9__GPIO1_9,
105
106 /* Touchscreen */
107 /* IRQ */
108 NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
109 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
110 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
111};
112
113static const struct imxuart_platform_data uart_pdata __initconst = {
114 .flags = IMXUART_HAVE_RTSCTS,
115};
116
117static struct tsc2007_platform_data tsc2007_info = {
118 .model = 2007,
119 .x_plate_ohms = 180,
120};
121
122static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
123 {
124 I2C_BOARD_INFO("pcf8563", 0x51),
125 }, {
126 I2C_BOARD_INFO("tsc2007", 0x49),
127 .type = "tsc2007",
128 .platform_data = &tsc2007_info,
129 .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
130 },
131};
132
133static const struct mxc_nand_platform_data
134 eukrea_cpuimx51sd_nand_board_info __initconst = {
135 .width = 1,
136 .hw_ecc = 1,
137 .flash_bbt = 1,
138};
139
140/* This function is board specific as the bit mask for the plldiv will also
141be different for other Freescale SoCs, thus a common bitmask is not
142possible and cannot get place in /plat-mxc/ehci.c.*/
143static int initialize_otg_port(struct platform_device *pdev)
144{
145 u32 v;
146 void __iomem *usb_base;
147 void __iomem *usbother_base;
148
149 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
150 if (!usb_base)
151 return -ENOMEM;
152 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
153
154 /* Set the PHY clock to 19.2MHz */
155 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
156 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
157 v |= MX51_USB_PLL_DIV_19_2_MHZ;
158 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
159 iounmap(usb_base);
160
161 mdelay(10);
162
163 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
164}
165
166static int initialize_usbh1_port(struct platform_device *pdev)
167{
168 u32 v;
169 void __iomem *usb_base;
170 void __iomem *usbother_base;
171
172 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
173 if (!usb_base)
174 return -ENOMEM;
175 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
176
177 /* The clock for the USBH1 ULPI port will come from the PHY. */
178 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
179 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
180 usbother_base + MX51_USB_CTRL_1_OFFSET);
181 iounmap(usb_base);
182
183 mdelay(10);
184
185 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
186 MXC_EHCI_ITC_NO_THRESHOLD);
187}
188
189static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
190 .init = initialize_otg_port,
191 .portsc = MXC_EHCI_UTMI_16BIT,
192};
193
194static const struct fsl_usb2_platform_data usb_pdata __initconst = {
195 .operating_mode = FSL_USB2_DR_DEVICE,
196 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
197};
198
199static const struct mxc_usbh_platform_data usbh1_config __initconst = {
200 .init = initialize_usbh1_port,
201 .portsc = MXC_EHCI_MODE_ULPI,
202};
203
204static int otg_mode_host;
205
206static int __init eukrea_cpuimx51sd_otg_mode(char *options)
207{
208 if (!strcmp(options, "host"))
209 otg_mode_host = 1;
210 else if (!strcmp(options, "device"))
211 otg_mode_host = 0;
212 else
213 pr_info("otg_mode neither \"host\" nor \"device\". "
214 "Defaulting to device\n");
215 return 0;
216}
217__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
218
219static struct i2c_gpio_platform_data pdata = {
220 .sda_pin = I2C_SDA,
221 .sda_is_open_drain = 0,
222 .scl_pin = I2C_SCL,
223 .scl_is_open_drain = 0,
224 .udelay = 2,
225};
226
227static struct platform_device hsi2c_gpio_device = {
228 .name = "i2c-gpio",
229 .id = 0,
230 .dev.platform_data = &pdata,
231};
232
233static struct mcp251x_platform_data mcp251x_info = {
234 .oscillator_frequency = 24E6,
235};
236
237static struct spi_board_info cpuimx51sd_spi_device[] = {
238 {
239 .modalias = "mcp2515",
240 .max_speed_hz = 10000000,
241 .bus_num = 0,
242 .mode = SPI_MODE_0,
243 .chip_select = 0,
244 .platform_data = &mcp251x_info,
245 .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
246 },
247};
248
249static int cpuimx51sd_spi1_cs[] = {
250 CAN_NCS,
251};
252
253static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
254 .chipselect = cpuimx51sd_spi1_cs,
255 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
256};
257
258static struct platform_device *platform_devices[] __initdata = {
259 &hsi2c_gpio_device,
260};
261
262static void __init eukrea_cpuimx51sd_init(void)
263{
264 imx51_soc_init();
265
266 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
267 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
268
269#if defined(CONFIG_CPU_FREQ_IMX)
270 get_cpu_op = mx51_get_cpu_op;
271#endif
272
273 imx51_add_imx_uart(0, &uart_pdata);
274 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
275
276 gpio_request(ETH_RST, "eth_rst");
277 gpio_set_value(ETH_RST, 1);
278 imx51_add_fec(NULL);
279
280 gpio_request(CAN_IRQGPIO, "can_irq");
281 gpio_direction_input(CAN_IRQGPIO);
282 gpio_free(CAN_IRQGPIO);
283 gpio_request(CAN_NCS, "can_ncs");
284 gpio_direction_output(CAN_NCS, 1);
285 gpio_free(CAN_NCS);
286 gpio_request(CAN_RST, "can_rst");
287 gpio_direction_output(CAN_RST, 0);
288 msleep(20);
289 gpio_set_value(CAN_RST, 1);
290 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
291 spi_register_board_info(cpuimx51sd_spi_device,
292 ARRAY_SIZE(cpuimx51sd_spi_device));
293
294 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
295 gpio_direction_input(TSC2007_IRQGPIO);
296 gpio_free(TSC2007_IRQGPIO);
297
298 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
299 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
300 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
301
302 if (otg_mode_host)
303 imx51_add_mxc_ehci_otg(&dr_utmi_config);
304 else {
305 initialize_otg_port(NULL);
306 imx51_add_fsl_usb2_udc(&usb_pdata);
307 }
308
309 gpio_request(USBH1_RST, "usb_rst");
310 gpio_direction_output(USBH1_RST, 0);
311 msleep(20);
312 gpio_set_value(USBH1_RST, 1);
313 imx51_add_mxc_ehci_hs(1, &usbh1_config);
314
315#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
316 eukrea_mbimxsd51_baseboard_init();
317#endif
318}
319
320static void __init eukrea_cpuimx51sd_timer_init(void)
321{
322 mx51_clocks_init(32768, 24000000, 22579200, 0);
323}
324
325static struct sys_timer mxc_timer = {
326 .init = eukrea_cpuimx51sd_timer_init,
327};
328
329MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
330 /* Maintainer: Eric Bénard <eric@eukrea.com> */
331 .atag_offset = 0x100,
332 .map_io = mx51_map_io,
333 .init_early = imx51_init_early,
334 .init_irq = mx51_init_irq,
335 .handle_irq = imx51_handle_irq,
336 .timer = &mxc_timer,
337 .init_machine = eukrea_cpuimx51sd_init,
338 .restart = mxc_restart,
339MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
deleted file mode 100644
index 42b66e8d961..00000000000
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ /dev/null
@@ -1,226 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx50.h>
30
31#include <asm/irq.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx50.h"
38
39#define FEC_EN IMX_GPIO_NR(6, 23)
40#define FEC_RESET_B IMX_GPIO_NR(4, 12)
41
42static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
43 /* SD1 */
44 MX50_PAD_ECSPI2_SS0__GPIO_4_19,
45 MX50_PAD_EIM_CRE__GPIO_1_27,
46 MX50_PAD_SD1_CMD__SD1_CMD,
47
48 MX50_PAD_SD1_CLK__SD1_CLK,
49 MX50_PAD_SD1_D0__SD1_D0,
50 MX50_PAD_SD1_D1__SD1_D1,
51 MX50_PAD_SD1_D2__SD1_D2,
52 MX50_PAD_SD1_D3__SD1_D3,
53
54 /* SD2 */
55 MX50_PAD_SD2_CD__GPIO_5_17,
56 MX50_PAD_SD2_WP__GPIO_5_16,
57 MX50_PAD_SD2_CMD__SD2_CMD,
58 MX50_PAD_SD2_CLK__SD2_CLK,
59 MX50_PAD_SD2_D0__SD2_D0,
60 MX50_PAD_SD2_D1__SD2_D1,
61 MX50_PAD_SD2_D2__SD2_D2,
62 MX50_PAD_SD2_D3__SD2_D3,
63 MX50_PAD_SD2_D4__SD2_D4,
64 MX50_PAD_SD2_D5__SD2_D5,
65 MX50_PAD_SD2_D6__SD2_D6,
66 MX50_PAD_SD2_D7__SD2_D7,
67
68 /* SD3 */
69 MX50_PAD_SD3_CMD__SD3_CMD,
70 MX50_PAD_SD3_CLK__SD3_CLK,
71 MX50_PAD_SD3_D0__SD3_D0,
72 MX50_PAD_SD3_D1__SD3_D1,
73 MX50_PAD_SD3_D2__SD3_D2,
74 MX50_PAD_SD3_D3__SD3_D3,
75 MX50_PAD_SD3_D4__SD3_D4,
76 MX50_PAD_SD3_D5__SD3_D5,
77 MX50_PAD_SD3_D6__SD3_D6,
78 MX50_PAD_SD3_D7__SD3_D7,
79
80 /* PWR_INT */
81 MX50_PAD_ECSPI2_MISO__GPIO_4_18,
82
83 /* UART pad setting */
84 MX50_PAD_UART1_TXD__UART1_TXD,
85 MX50_PAD_UART1_RXD__UART1_RXD,
86 MX50_PAD_UART1_RTS__UART1_RTS,
87 MX50_PAD_UART2_TXD__UART2_TXD,
88 MX50_PAD_UART2_RXD__UART2_RXD,
89 MX50_PAD_UART2_CTS__UART2_CTS,
90 MX50_PAD_UART2_RTS__UART2_RTS,
91
92 MX50_PAD_I2C1_SCL__I2C1_SCL,
93 MX50_PAD_I2C1_SDA__I2C1_SDA,
94 MX50_PAD_I2C2_SCL__I2C2_SCL,
95 MX50_PAD_I2C2_SDA__I2C2_SDA,
96
97 MX50_PAD_EPITO__USBH1_PWR,
98 /* Need to comment below line if
99 * one needs to debug owire.
100 */
101 MX50_PAD_OWIRE__USBH1_OC,
102 /* using gpio to control otg pwr */
103 MX50_PAD_PWM2__GPIO_6_25,
104 MX50_PAD_I2C3_SCL__USBOTG_OC,
105
106 MX50_PAD_SSI_RXC__FEC_MDIO,
107 MX50_PAD_SSI_RXFS__FEC_MDC,
108 MX50_PAD_DISP_D0__FEC_TXCLK,
109 MX50_PAD_DISP_D1__FEC_RX_ER,
110 MX50_PAD_DISP_D2__FEC_RX_DV,
111 MX50_PAD_DISP_D3__FEC_RXD1,
112 MX50_PAD_DISP_D4__FEC_RXD0,
113 MX50_PAD_DISP_D5__FEC_TX_EN,
114 MX50_PAD_DISP_D6__FEC_TXD1,
115 MX50_PAD_DISP_D7__FEC_TXD0,
116 MX50_PAD_I2C3_SDA__GPIO_6_23,
117 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
118
119 MX50_PAD_CSPI_SS0__CSPI_SS0,
120 MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
121 MX50_PAD_CSPI_MOSI__CSPI_MOSI,
122 MX50_PAD_CSPI_MISO__CSPI_MISO,
123
124 /* SGTL500_OSC_EN */
125 MX50_PAD_UART1_CTS__GPIO_6_8,
126
127 /* SGTL_AMP_SHDN */
128 MX50_PAD_UART3_RXD__GPIO_6_15,
129
130 /* Keypad */
131 MX50_PAD_KEY_COL0__KEY_COL0,
132 MX50_PAD_KEY_ROW0__KEY_ROW0,
133 MX50_PAD_KEY_COL1__KEY_COL1,
134 MX50_PAD_KEY_ROW1__KEY_ROW1,
135 MX50_PAD_KEY_COL2__KEY_COL2,
136 MX50_PAD_KEY_ROW2__KEY_ROW2,
137 MX50_PAD_KEY_COL3__KEY_COL3,
138 MX50_PAD_KEY_ROW3__KEY_ROW3,
139 MX50_PAD_EIM_DA0__KEY_COL4,
140 MX50_PAD_EIM_DA1__KEY_ROW4,
141 MX50_PAD_EIM_DA2__KEY_COL5,
142 MX50_PAD_EIM_DA3__KEY_ROW5,
143 MX50_PAD_EIM_DA4__KEY_COL6,
144 MX50_PAD_EIM_DA5__KEY_ROW6,
145 MX50_PAD_EIM_DA6__KEY_COL7,
146 MX50_PAD_EIM_DA7__KEY_ROW7,
147 /*EIM pads */
148 MX50_PAD_EIM_DA8__GPIO_1_8,
149 MX50_PAD_EIM_DA9__GPIO_1_9,
150 MX50_PAD_EIM_DA10__GPIO_1_10,
151 MX50_PAD_EIM_DA11__GPIO_1_11,
152 MX50_PAD_EIM_DA12__GPIO_1_12,
153 MX50_PAD_EIM_DA13__GPIO_1_13,
154 MX50_PAD_EIM_DA14__GPIO_1_14,
155 MX50_PAD_EIM_DA15__GPIO_1_15,
156 MX50_PAD_EIM_CS2__GPIO_1_16,
157 MX50_PAD_EIM_CS1__GPIO_1_17,
158 MX50_PAD_EIM_CS0__GPIO_1_18,
159 MX50_PAD_EIM_EB0__GPIO_1_19,
160 MX50_PAD_EIM_EB1__GPIO_1_20,
161 MX50_PAD_EIM_WAIT__GPIO_1_21,
162 MX50_PAD_EIM_BCLK__GPIO_1_22,
163 MX50_PAD_EIM_RDY__GPIO_1_23,
164 MX50_PAD_EIM_OE__GPIO_1_24,
165};
166
167/* Serial ports */
168static const struct imxuart_platform_data uart_pdata __initconst = {
169 .flags = IMXUART_HAVE_RTSCTS,
170};
171
172static const struct fec_platform_data fec_data __initconst = {
173 .phy = PHY_INTERFACE_MODE_RMII,
174};
175
176static inline void mx50_rdp_fec_reset(void)
177{
178 gpio_request(FEC_EN, "fec-en");
179 gpio_direction_output(FEC_EN, 0);
180 gpio_request(FEC_RESET_B, "fec-reset_b");
181 gpio_direction_output(FEC_RESET_B, 0);
182 msleep(1);
183 gpio_set_value(FEC_RESET_B, 1);
184}
185
186static const struct imxi2c_platform_data i2c_data __initconst = {
187 .bitrate = 100000,
188};
189
190/*
191 * Board specific initialization.
192 */
193static void __init mx50_rdp_board_init(void)
194{
195 imx50_soc_init();
196
197 mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
198 ARRAY_SIZE(mx50_rdp_pads));
199
200 imx50_add_imx_uart(0, &uart_pdata);
201 imx50_add_imx_uart(1, &uart_pdata);
202 mx50_rdp_fec_reset();
203 imx50_add_fec(&fec_data);
204 imx50_add_imx_i2c(0, &i2c_data);
205 imx50_add_imx_i2c(1, &i2c_data);
206 imx50_add_imx_i2c(2, &i2c_data);
207}
208
209static void __init mx50_rdp_timer_init(void)
210{
211 mx50_clocks_init(32768, 24000000, 22579200);
212}
213
214static struct sys_timer mx50_rdp_timer = {
215 .init = mx50_rdp_timer_init,
216};
217
218MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
219 .map_io = mx50_map_io,
220 .init_early = imx50_init_early,
221 .init_irq = mx50_init_irq,
222 .handle_irq = imx50_handle_irq,
223 .timer = &mx50_rdp_timer,
224 .init_machine = mx50_rdp_board_init,
225 .restart = mxc_restart,
226MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
deleted file mode 100644
index 83eab4176ca..00000000000
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/hardware.h>
23#include <mach/common.h>
24#include <mach/iomux-mx51.h>
25#include <mach/3ds_debugboard.h>
26
27#include "devices-imx51.h"
28
29#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
30#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
31
32static iomux_v3_cfg_t mx51_3ds_pads[] = {
33 /* UART1 */
34 MX51_PAD_UART1_RXD__UART1_RXD,
35 MX51_PAD_UART1_TXD__UART1_TXD,
36 MX51_PAD_UART1_RTS__UART1_RTS,
37 MX51_PAD_UART1_CTS__UART1_CTS,
38
39 /* UART2 */
40 MX51_PAD_UART2_RXD__UART2_RXD,
41 MX51_PAD_UART2_TXD__UART2_TXD,
42 MX51_PAD_EIM_D25__UART2_CTS,
43 MX51_PAD_EIM_D26__UART2_RTS,
44
45 /* UART3 */
46 MX51_PAD_UART3_RXD__UART3_RXD,
47 MX51_PAD_UART3_TXD__UART3_TXD,
48 MX51_PAD_EIM_D24__UART3_CTS,
49 MX51_PAD_EIM_D27__UART3_RTS,
50
51 /* CPLD PARENT IRQ PIN */
52 MX51_PAD_GPIO1_6__GPIO1_6,
53
54 /* KPP */
55 MX51_PAD_KEY_ROW0__KEY_ROW0,
56 MX51_PAD_KEY_ROW1__KEY_ROW1,
57 MX51_PAD_KEY_ROW2__KEY_ROW2,
58 MX51_PAD_KEY_ROW3__KEY_ROW3,
59 MX51_PAD_KEY_COL0__KEY_COL0,
60 MX51_PAD_KEY_COL1__KEY_COL1,
61 MX51_PAD_KEY_COL2__KEY_COL2,
62 MX51_PAD_KEY_COL3__KEY_COL3,
63 MX51_PAD_KEY_COL4__KEY_COL4,
64 MX51_PAD_KEY_COL5__KEY_COL5,
65
66 /* eCSPI2 */
67 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
68 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
69 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
70 MX51_PAD_NANDF_D12__GPIO3_28,
71};
72
73/* Serial ports */
74static const struct imxuart_platform_data uart_pdata __initconst = {
75 .flags = IMXUART_HAVE_RTSCTS,
76};
77
78static int mx51_3ds_board_keymap[] = {
79 KEY(0, 0, KEY_1),
80 KEY(0, 1, KEY_2),
81 KEY(0, 2, KEY_3),
82 KEY(0, 3, KEY_F1),
83 KEY(0, 4, KEY_UP),
84 KEY(0, 5, KEY_F2),
85
86 KEY(1, 0, KEY_4),
87 KEY(1, 1, KEY_5),
88 KEY(1, 2, KEY_6),
89 KEY(1, 3, KEY_LEFT),
90 KEY(1, 4, KEY_SELECT),
91 KEY(1, 5, KEY_RIGHT),
92
93 KEY(2, 0, KEY_7),
94 KEY(2, 1, KEY_8),
95 KEY(2, 2, KEY_9),
96 KEY(2, 3, KEY_F3),
97 KEY(2, 4, KEY_DOWN),
98 KEY(2, 5, KEY_F4),
99
100 KEY(3, 0, KEY_0),
101 KEY(3, 1, KEY_OK),
102 KEY(3, 2, KEY_ESC),
103 KEY(3, 3, KEY_ENTER),
104 KEY(3, 4, KEY_MENU),
105 KEY(3, 5, KEY_BACK)
106};
107
108static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
109 .keymap = mx51_3ds_board_keymap,
110 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
111};
112
113static int mx51_3ds_spi2_cs[] = {
114 MXC_SPI_CS(0),
115 MX51_3DS_ECSPI2_CS,
116};
117
118static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
119 .chipselect = mx51_3ds_spi2_cs,
120 .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
121};
122
123static struct spi_board_info mx51_3ds_spi_nor_device[] = {
124 {
125 .modalias = "m25p80",
126 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
127 .bus_num = 1,
128 .chip_select = 1,
129 .mode = SPI_MODE_0,
130 .platform_data = NULL,},
131};
132
133/*
134 * Board specific initialization.
135 */
136static void __init mx51_3ds_init(void)
137{
138 imx51_soc_init();
139
140 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
141 ARRAY_SIZE(mx51_3ds_pads));
142
143 imx51_add_imx_uart(0, &uart_pdata);
144 imx51_add_imx_uart(1, &uart_pdata);
145 imx51_add_imx_uart(2, &uart_pdata);
146
147 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
148 spi_register_board_info(mx51_3ds_spi_nor_device,
149 ARRAY_SIZE(mx51_3ds_spi_nor_device));
150
151 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
152 printk(KERN_WARNING "Init of the debugboard failed, all "
153 "devices on the board are unusable.\n");
154
155 imx51_add_sdhci_esdhc_imx(0, NULL);
156 imx51_add_imx_keypad(&mx51_3ds_map_data);
157 imx51_add_imx2_wdt(0, NULL);
158}
159
160static void __init mx51_3ds_timer_init(void)
161{
162 mx51_clocks_init(32768, 24000000, 22579200, 0);
163}
164
165static struct sys_timer mx51_3ds_timer = {
166 .init = mx51_3ds_timer_init,
167};
168
169MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
170 /* Maintainer: Freescale Semiconductor, Inc. */
171 .atag_offset = 0x100,
172 .map_io = mx51_map_io,
173 .init_early = imx51_init_early,
174 .init_irq = mx51_init_irq,
175 .handle_irq = imx51_handle_irq,
176 .timer = &mx51_3ds_timer,
177 .init_machine = mx51_3ds_init,
178 .restart = mxc_restart,
179MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
deleted file mode 100644
index e4b822e9f71..00000000000
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ /dev/null
@@ -1,430 +0,0 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/i2c.h>
16#include <linux/gpio.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/input.h>
20#include <linux/spi/flash.h>
21#include <linux/spi/spi.h>
22
23#include <mach/common.h>
24#include <mach/hardware.h>
25#include <mach/iomux-mx51.h>
26
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/time.h>
31
32#include "devices-imx51.h"
33#include "cpu_op-mx51.h"
34
35#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
36#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
37#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
38#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
39#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
40#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
41#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
42#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
43#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
44
45/* USB_CTRL_1 */
46#define MX51_USB_CTRL_1_OFFSET 0x10
47#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48
49#define MX51_USB_PLLDIV_12_MHZ 0x00
50#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
51#define MX51_USB_PLL_DIV_24_MHZ 0x02
52
53static struct gpio_keys_button babbage_buttons[] = {
54 {
55 .gpio = BABBAGE_POWER_KEY,
56 .code = BTN_0,
57 .desc = "PWR",
58 .active_low = 1,
59 .wakeup = 1,
60 },
61};
62
63static const struct gpio_keys_platform_data imx_button_data __initconst = {
64 .buttons = babbage_buttons,
65 .nbuttons = ARRAY_SIZE(babbage_buttons),
66};
67
68static iomux_v3_cfg_t mx51babbage_pads[] = {
69 /* UART1 */
70 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD,
72 MX51_PAD_UART1_RTS__UART1_RTS,
73 MX51_PAD_UART1_CTS__UART1_CTS,
74
75 /* UART2 */
76 MX51_PAD_UART2_RXD__UART2_RXD,
77 MX51_PAD_UART2_TXD__UART2_TXD,
78
79 /* UART3 */
80 MX51_PAD_EIM_D25__UART3_RXD,
81 MX51_PAD_EIM_D26__UART3_TXD,
82 MX51_PAD_EIM_D27__UART3_RTS,
83 MX51_PAD_EIM_D24__UART3_CTS,
84
85 /* I2C1 */
86 MX51_PAD_EIM_D16__I2C1_SDA,
87 MX51_PAD_EIM_D19__I2C1_SCL,
88
89 /* I2C2 */
90 MX51_PAD_KEY_COL4__I2C2_SCL,
91 MX51_PAD_KEY_COL5__I2C2_SDA,
92
93 /* HSI2C */
94 MX51_PAD_I2C1_CLK__I2C1_CLK,
95 MX51_PAD_I2C1_DAT__I2C1_DAT,
96
97 /* USB HOST1 */
98 MX51_PAD_USBH1_CLK__USBH1_CLK,
99 MX51_PAD_USBH1_DIR__USBH1_DIR,
100 MX51_PAD_USBH1_NXT__USBH1_NXT,
101 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
102 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
103 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
104 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
105 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
106 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
107 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
108 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109
110 /* USB HUB reset line*/
111 MX51_PAD_GPIO1_7__GPIO1_7,
112
113 /* USB PHY reset line */
114 MX51_PAD_EIM_D21__GPIO2_5,
115
116 /* FEC */
117 MX51_PAD_EIM_EB2__FEC_MDIO,
118 MX51_PAD_EIM_EB3__FEC_RDATA1,
119 MX51_PAD_EIM_CS2__FEC_RDATA2,
120 MX51_PAD_EIM_CS3__FEC_RDATA3,
121 MX51_PAD_EIM_CS4__FEC_RX_ER,
122 MX51_PAD_EIM_CS5__FEC_CRS,
123 MX51_PAD_NANDF_RB2__FEC_COL,
124 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
125 MX51_PAD_NANDF_D9__FEC_RDATA0,
126 MX51_PAD_NANDF_D8__FEC_TDATA0,
127 MX51_PAD_NANDF_CS2__FEC_TX_ER,
128 MX51_PAD_NANDF_CS3__FEC_MDC,
129 MX51_PAD_NANDF_CS4__FEC_TDATA1,
130 MX51_PAD_NANDF_CS5__FEC_TDATA2,
131 MX51_PAD_NANDF_CS6__FEC_TDATA3,
132 MX51_PAD_NANDF_CS7__FEC_TX_EN,
133 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
134
135 /* FEC PHY reset line */
136 MX51_PAD_EIM_A20__GPIO2_14,
137
138 /* SD 1 */
139 MX51_PAD_SD1_CMD__SD1_CMD,
140 MX51_PAD_SD1_CLK__SD1_CLK,
141 MX51_PAD_SD1_DATA0__SD1_DATA0,
142 MX51_PAD_SD1_DATA1__SD1_DATA1,
143 MX51_PAD_SD1_DATA2__SD1_DATA2,
144 MX51_PAD_SD1_DATA3__SD1_DATA3,
145 /* CD/WP from controller */
146 MX51_PAD_GPIO1_0__SD1_CD,
147 MX51_PAD_GPIO1_1__SD1_WP,
148
149 /* SD 2 */
150 MX51_PAD_SD2_CMD__SD2_CMD,
151 MX51_PAD_SD2_CLK__SD2_CLK,
152 MX51_PAD_SD2_DATA0__SD2_DATA0,
153 MX51_PAD_SD2_DATA1__SD2_DATA1,
154 MX51_PAD_SD2_DATA2__SD2_DATA2,
155 MX51_PAD_SD2_DATA3__SD2_DATA3,
156 /* CD/WP gpio */
157 MX51_PAD_GPIO1_6__GPIO1_6,
158 MX51_PAD_GPIO1_5__GPIO1_5,
159
160 /* eCSPI1 */
161 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
162 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
163 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
164 MX51_PAD_CSPI1_SS0__GPIO4_24,
165 MX51_PAD_CSPI1_SS1__GPIO4_25,
166};
167
168/* Serial ports */
169static const struct imxuart_platform_data uart_pdata __initconst = {
170 .flags = IMXUART_HAVE_RTSCTS,
171};
172
173static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
174 .bitrate = 100000,
175};
176
177static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
178 .bitrate = 400000,
179};
180
181static struct gpio mx51_babbage_usbh1_gpios[] = {
182 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
183 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
184};
185
186static int gpio_usbh1_active(void)
187{
188 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
189 int ret;
190
191 /* Set USBH1_STP to GPIO and toggle it */
192 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
193 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
194 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
195
196 if (ret) {
197 pr_debug("failed to get USBH1 pins: %d\n", ret);
198 return ret;
199 }
200
201 msleep(100);
202 gpio_set_value(BABBAGE_USBH1_STP, 1);
203 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
204 gpio_free_array(mx51_babbage_usbh1_gpios,
205 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
206 return 0;
207}
208
209static inline void babbage_usbhub_reset(void)
210{
211 int ret;
212
213 /* Reset USB hub */
214 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
215 GPIOF_OUT_INIT_LOW, "GPIO1_7");
216 if (ret) {
217 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
218 return;
219 }
220
221 msleep(2);
222 /* Deassert reset */
223 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
224}
225
226static inline void babbage_fec_reset(void)
227{
228 int ret;
229
230 /* reset FEC PHY */
231 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
232 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
233 if (ret) {
234 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
235 return;
236 }
237 msleep(1);
238 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
239}
240
241/* This function is board specific as the bit mask for the plldiv will also
242be different for other Freescale SoCs, thus a common bitmask is not
243possible and cannot get place in /plat-mxc/ehci.c.*/
244static int initialize_otg_port(struct platform_device *pdev)
245{
246 u32 v;
247 void __iomem *usb_base;
248 void __iomem *usbother_base;
249
250 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
251 if (!usb_base)
252 return -ENOMEM;
253 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
254
255 /* Set the PHY clock to 19.2MHz */
256 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
257 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
258 v |= MX51_USB_PLL_DIV_19_2_MHZ;
259 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
260 iounmap(usb_base);
261
262 mdelay(10);
263
264 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
265}
266
267static int initialize_usbh1_port(struct platform_device *pdev)
268{
269 u32 v;
270 void __iomem *usb_base;
271 void __iomem *usbother_base;
272
273 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
274 if (!usb_base)
275 return -ENOMEM;
276 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
277
278 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
279 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
280 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
281 iounmap(usb_base);
282
283 mdelay(10);
284
285 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
286 MXC_EHCI_ITC_NO_THRESHOLD);
287}
288
289static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
290 .init = initialize_otg_port,
291 .portsc = MXC_EHCI_UTMI_16BIT,
292};
293
294static const struct fsl_usb2_platform_data usb_pdata __initconst = {
295 .operating_mode = FSL_USB2_DR_DEVICE,
296 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
297};
298
299static const struct mxc_usbh_platform_data usbh1_config __initconst = {
300 .init = initialize_usbh1_port,
301 .portsc = MXC_EHCI_MODE_ULPI,
302};
303
304static int otg_mode_host;
305
306static int __init babbage_otg_mode(char *options)
307{
308 if (!strcmp(options, "host"))
309 otg_mode_host = 1;
310 else if (!strcmp(options, "device"))
311 otg_mode_host = 0;
312 else
313 pr_info("otg_mode neither \"host\" nor \"device\". "
314 "Defaulting to device\n");
315 return 0;
316}
317__setup("otg_mode=", babbage_otg_mode);
318
319static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
320 {
321 .modalias = "mtd_dataflash",
322 .max_speed_hz = 25000000,
323 .bus_num = 0,
324 .chip_select = 1,
325 .mode = SPI_MODE_0,
326 .platform_data = NULL,
327 },
328};
329
330static int mx51_babbage_spi_cs[] = {
331 BABBAGE_ECSPI1_CS0,
332 BABBAGE_ECSPI1_CS1,
333};
334
335static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
336 .chipselect = mx51_babbage_spi_cs,
337 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
338};
339
340static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
341 .cd_type = ESDHC_CD_CONTROLLER,
342 .wp_type = ESDHC_WP_CONTROLLER,
343};
344
345static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
346 .cd_gpio = BABBAGE_SD2_CD,
347 .wp_gpio = BABBAGE_SD2_WP,
348 .cd_type = ESDHC_CD_GPIO,
349 .wp_type = ESDHC_WP_GPIO,
350};
351
352void __init imx51_babbage_common_init(void)
353{
354 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
355 ARRAY_SIZE(mx51babbage_pads));
356}
357
358/*
359 * Board specific initialization.
360 */
361static void __init mx51_babbage_init(void)
362{
363 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
364 iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
365 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
366
367 imx51_soc_init();
368
369#if defined(CONFIG_CPU_FREQ_IMX)
370 get_cpu_op = mx51_get_cpu_op;
371#endif
372 imx51_babbage_common_init();
373
374 imx51_add_imx_uart(0, &uart_pdata);
375 imx51_add_imx_uart(1, NULL);
376 imx51_add_imx_uart(2, &uart_pdata);
377
378 babbage_fec_reset();
379 imx51_add_fec(NULL);
380
381 /* Set the PAD settings for the pwr key. */
382 mxc_iomux_v3_setup_pad(power_key);
383 imx_add_gpio_keys(&imx_button_data);
384
385 imx51_add_imx_i2c(0, &babbage_i2c_data);
386 imx51_add_imx_i2c(1, &babbage_i2c_data);
387 imx51_add_hsi2c(&babbage_hsi2c_data);
388
389 if (otg_mode_host)
390 imx51_add_mxc_ehci_otg(&dr_utmi_config);
391 else {
392 initialize_otg_port(NULL);
393 imx51_add_fsl_usb2_udc(&usb_pdata);
394 }
395
396 gpio_usbh1_active();
397 imx51_add_mxc_ehci_hs(1, &usbh1_config);
398 /* setback USBH1_STP to be function */
399 mxc_iomux_v3_setup_pad(usbh1stp);
400 babbage_usbhub_reset();
401
402 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
403 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
404
405 spi_register_board_info(mx51_babbage_spi_board_info,
406 ARRAY_SIZE(mx51_babbage_spi_board_info));
407 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
408 imx51_add_imx2_wdt(0, NULL);
409}
410
411static void __init mx51_babbage_timer_init(void)
412{
413 mx51_clocks_init(32768, 24000000, 22579200, 0);
414}
415
416static struct sys_timer mx51_babbage_timer = {
417 .init = mx51_babbage_timer_init,
418};
419
420MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
421 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
422 .atag_offset = 0x100,
423 .map_io = mx51_map_io,
424 .init_early = imx51_init_early,
425 .init_irq = mx51_init_irq,
426 .handle_irq = imx51_handle_irq,
427 .timer = &mx51_babbage_timer,
428 .init_machine = mx51_babbage_init,
429 .restart = mxc_restart,
430MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
deleted file mode 100644
index 3a5ed2dd885..00000000000
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30
31#include <mach/common.h>
32#include <mach/hardware.h>
33#include <mach/iomux-mx51.h>
34
35#include <asm/setup.h>
36#include <asm/mach-types.h>
37#include <asm/mach/arch.h>
38#include <asm/mach/time.h>
39
40#include "devices-imx51.h"
41#include "efika.h"
42
43#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
44#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
45#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
46
47#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
48#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
49#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
50
51#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
52
53/* board 1.1 doesn't have same reset gpio */
54#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
55#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
56
57#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
58
59#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
60
61/* the pci ids pin have pull up. they're driven low according to board id */
62#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
63#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
64#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
66
67static iomux_v3_cfg_t mx51efikamx_pads[] = {
68 /* board id */
69 MX51_PAD_PCBID0,
70 MX51_PAD_PCBID1,
71 MX51_PAD_PCBID2,
72
73 /* leds */
74 MX51_PAD_CSI1_D9__GPIO3_13,
75 MX51_PAD_CSI1_VSYNC__GPIO3_14,
76 MX51_PAD_CSI1_HSYNC__GPIO3_15,
77
78 /* power key */
79 MX51_PAD_PWRKEY,
80
81 /* reset */
82 MX51_PAD_DI1_PIN13__GPIO3_2,
83 MX51_PAD_GPIO1_4__GPIO1_4,
84
85 /* power off */
86 MX51_PAD_CSI2_VSYNC__GPIO4_13,
87};
88
89/* PCBID2 PCBID1 PCBID0 STATE
90 1 1 1 ER1:rev1.1
91 1 1 0 ER2:rev1.2
92 1 0 1 ER3:rev1.3
93 1 0 0 ER4:rev1.4
94*/
95static void __init mx51_efikamx_board_id(void)
96{
97 int id;
98
99 /* things are taking time to settle */
100 msleep(150);
101
102 gpio_request(EFIKAMX_PCBID0, "pcbid0");
103 gpio_direction_input(EFIKAMX_PCBID0);
104 gpio_request(EFIKAMX_PCBID1, "pcbid1");
105 gpio_direction_input(EFIKAMX_PCBID1);
106 gpio_request(EFIKAMX_PCBID2, "pcbid2");
107 gpio_direction_input(EFIKAMX_PCBID2);
108
109 id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
110 id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
111 id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
112
113 switch (id) {
114 case 7:
115 system_rev = 0x11;
116 break;
117 case 6:
118 system_rev = 0x12;
119 break;
120 case 5:
121 system_rev = 0x13;
122 break;
123 case 4:
124 system_rev = 0x14;
125 break;
126 default:
127 system_rev = 0x10;
128 break;
129 }
130
131 if ((system_rev == 0x10)
132 || (system_rev == 0x12)
133 || (system_rev == 0x14)) {
134 printk(KERN_WARNING
135 "EfikaMX: Unsupported board revision 1.%u!\n",
136 system_rev & 0xf);
137 }
138}
139
140static struct gpio_led mx51_efikamx_leds[] __initdata = {
141 {
142 .name = "efikamx:green",
143 .default_trigger = "default-on",
144 .gpio = EFIKAMX_GREEN_LED,
145 },
146 {
147 .name = "efikamx:red",
148 .default_trigger = "ide-disk",
149 .gpio = EFIKAMX_RED_LED,
150 },
151 {
152 .name = "efikamx:blue",
153 .default_trigger = "mmc0",
154 .gpio = EFIKAMX_BLUE_LED,
155 },
156};
157
158static const struct gpio_led_platform_data
159 mx51_efikamx_leds_data __initconst = {
160 .leds = mx51_efikamx_leds,
161 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
162};
163
164static struct esdhc_platform_data sd_pdata = {
165 .cd_type = ESDHC_CD_CONTROLLER,
166 .wp_type = ESDHC_WP_CONTROLLER,
167};
168
169static struct gpio_keys_button mx51_efikamx_powerkey[] = {
170 {
171 .code = KEY_POWER,
172 .gpio = EFIKAMX_POWER_KEY,
173 .type = EV_PWR,
174 .desc = "Power Button (CM)",
175 .wakeup = 1,
176 .debounce_interval = 10, /* ms */
177 },
178};
179
180static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
181 .buttons = mx51_efikamx_powerkey,
182 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
183};
184
185static void mx51_efikamx_restart(char mode, const char *cmd)
186{
187 if (system_rev == 0x11)
188 gpio_direction_output(EFIKAMX_RESET1_1, 0);
189 else
190 gpio_direction_output(EFIKAMX_RESET, 0);
191}
192
193static struct regulator *pwgt1, *pwgt2, *coincell;
194
195static void mx51_efikamx_power_off(void)
196{
197 if (!IS_ERR(coincell))
198 regulator_disable(coincell);
199
200 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
201 regulator_disable(pwgt2);
202 regulator_disable(pwgt1);
203 }
204 gpio_direction_output(EFIKAMX_POWEROFF, 1);
205}
206
207static int __init mx51_efikamx_power_init(void)
208{
209 if (machine_is_mx51_efikamx()) {
210 pwgt1 = regulator_get(NULL, "pwgt1");
211 pwgt2 = regulator_get(NULL, "pwgt2");
212 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
213 regulator_enable(pwgt1);
214 regulator_enable(pwgt2);
215 }
216 gpio_request(EFIKAMX_POWEROFF, "poweroff");
217 pm_power_off = mx51_efikamx_power_off;
218
219 /* enable coincell charger. maybe need a small power driver ? */
220 coincell = regulator_get(NULL, "coincell");
221 if (!IS_ERR(coincell)) {
222 regulator_set_voltage(coincell, 3000000, 3000000);
223 regulator_enable(coincell);
224 }
225
226 regulator_has_full_constraints();
227 }
228
229 return 0;
230}
231late_initcall(mx51_efikamx_power_init);
232
233static void __init mx51_efikamx_init(void)
234{
235 imx51_soc_init();
236
237 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
238 ARRAY_SIZE(mx51efikamx_pads));
239 efika_board_common_init();
240
241 mx51_efikamx_board_id();
242
243 /* on < 1.2 boards both SD controllers are used */
244 if (system_rev < 0x12) {
245 imx51_add_sdhci_esdhc_imx(0, NULL);
246 imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
247 mx51_efikamx_leds[2].default_trigger = "mmc1";
248 } else
249 imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
250
251 gpio_led_register_device(-1, &mx51_efikamx_leds_data);
252 imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
253
254 if (system_rev == 0x11) {
255 gpio_request(EFIKAMX_RESET1_1, "reset");
256 gpio_direction_output(EFIKAMX_RESET1_1, 1);
257 } else {
258 gpio_request(EFIKAMX_RESET, "reset");
259 gpio_direction_output(EFIKAMX_RESET, 1);
260 }
261
262 /*
263 * enable wifi by default only on mx
264 * sb and mx have same wlan pin but the value to enable it are
265 * different :/
266 */
267 gpio_request(EFIKA_WLAN_EN, "wlan_en");
268 gpio_direction_output(EFIKA_WLAN_EN, 0);
269 msleep(10);
270
271 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
272 gpio_direction_output(EFIKA_WLAN_RESET, 0);
273 msleep(10);
274 gpio_set_value(EFIKA_WLAN_RESET, 1);
275}
276
277static void __init mx51_efikamx_timer_init(void)
278{
279 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
280}
281
282static struct sys_timer mx51_efikamx_timer = {
283 .init = mx51_efikamx_timer_init,
284};
285
286MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
287 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
288 .atag_offset = 0x100,
289 .map_io = mx51_map_io,
290 .init_early = imx51_init_early,
291 .init_irq = mx51_init_irq,
292 .handle_irq = imx51_handle_irq,
293 .timer = &mx51_efikamx_timer,
294 .init_machine = mx51_efikamx_init,
295 .restart = mx51_efikamx_restart,
296MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
deleted file mode 100644
index ea5f65b0381..00000000000
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ /dev/null
@@ -1,291 +0,0 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <mach/ulpi.h>
33
34#include <mach/common.h>
35#include <mach/hardware.h>
36#include <mach/iomux-mx51.h>
37
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42
43#include "devices-imx51.h"
44#include "efika.h"
45
46#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
47#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
48#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
49#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
50#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
51#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
52#define EFIKASB_LID IMX_GPIO_NR(3, 14)
53#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
54#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
55
56#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
57#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
58
59static iomux_v3_cfg_t mx51efikasb_pads[] = {
60 /* USB HOST2 */
61 MX51_PAD_EIM_D16__USBH2_DATA0,
62 MX51_PAD_EIM_D17__USBH2_DATA1,
63 MX51_PAD_EIM_D18__USBH2_DATA2,
64 MX51_PAD_EIM_D19__USBH2_DATA3,
65 MX51_PAD_EIM_D20__USBH2_DATA4,
66 MX51_PAD_EIM_D21__USBH2_DATA5,
67 MX51_PAD_EIM_D22__USBH2_DATA6,
68 MX51_PAD_EIM_D23__USBH2_DATA7,
69 MX51_PAD_EIM_A24__USBH2_CLK,
70 MX51_PAD_EIM_A25__USBH2_DIR,
71 MX51_PAD_EIM_A26__USBH2_STP,
72 MX51_PAD_EIM_A27__USBH2_NXT,
73
74 /* leds */
75 MX51_PAD_EIM_CS0__GPIO2_25,
76 MX51_PAD_GPIO1_3__GPIO1_3,
77
78 /* pcb id */
79 MX51_PAD_EIM_CS3__GPIO2_28,
80 MX51_PAD_EIM_CS4__GPIO2_29,
81
82 /* lid */
83 MX51_PAD_CSI1_VSYNC__GPIO3_14,
84
85 /* power key*/
86 MX51_PAD_PWRKEY,
87
88 /* wifi/bt button */
89 MX51_PAD_DI1_PIN12__GPIO3_1,
90
91 /* power off */
92 MX51_PAD_CSI2_VSYNC__GPIO4_13,
93
94 /* wdog reset */
95 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
96
97 /* BT */
98 MX51_PAD_EIM_A17__GPIO2_11,
99
100 MX51_PAD_SD1_CD,
101};
102
103static int initialize_usbh2_port(struct platform_device *pdev)
104{
105 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
106 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
107
108 mxc_iomux_v3_setup_pad(usbh2gpio);
109 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
110 gpio_direction_output(EFIKASB_USBH2_STP, 0);
111 msleep(1);
112 gpio_set_value(EFIKASB_USBH2_STP, 1);
113 msleep(1);
114
115 gpio_free(EFIKASB_USBH2_STP);
116 mxc_iomux_v3_setup_pad(usbh2stp);
117
118 mdelay(10);
119
120 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
121}
122
123static struct mxc_usbh_platform_data usbh2_config __initdata = {
124 .init = initialize_usbh2_port,
125 .portsc = MXC_EHCI_MODE_ULPI,
126};
127
128static void __init mx51_efikasb_usb(void)
129{
130 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
131 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
132 if (usbh2_config.otg)
133 imx51_add_mxc_ehci_hs(2, &usbh2_config);
134}
135
136static const struct gpio_led mx51_efikasb_leds[] __initconst = {
137 {
138 .name = "efikasb:green",
139 .default_trigger = "default-on",
140 .gpio = EFIKASB_GREEN_LED,
141 .active_low = 1,
142 },
143 {
144 .name = "efikasb:white",
145 .default_trigger = "caps",
146 .gpio = EFIKASB_WHITE_LED,
147 },
148};
149
150static const struct gpio_led_platform_data
151 mx51_efikasb_leds_data __initconst = {
152 .leds = mx51_efikasb_leds,
153 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
154};
155
156static struct gpio_keys_button mx51_efikasb_keys[] = {
157 {
158 .code = KEY_POWER,
159 .gpio = EFIKASB_PWRKEY,
160 .type = EV_KEY,
161 .desc = "Power Button",
162 .wakeup = 1,
163 .active_low = 1,
164 },
165 {
166 .code = SW_LID,
167 .gpio = EFIKASB_LID,
168 .type = EV_SW,
169 .desc = "Lid Switch",
170 .active_low = 1,
171 },
172 {
173 .code = KEY_RFKILL,
174 .gpio = EFIKASB_RFKILL,
175 .type = EV_KEY,
176 .desc = "rfkill",
177 .active_low = 1,
178 },
179};
180
181static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
182 .buttons = mx51_efikasb_keys,
183 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
184};
185
186static struct esdhc_platform_data sd0_pdata = {
187#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
188 .cd_gpio = EFIKASB_SD1_CD,
189 .cd_type = ESDHC_CD_GPIO,
190 .wp_type = ESDHC_WP_CONTROLLER,
191};
192
193static struct esdhc_platform_data sd1_pdata = {
194 .cd_type = ESDHC_CD_CONTROLLER,
195 .wp_type = ESDHC_WP_CONTROLLER,
196};
197
198static struct regulator *pwgt1, *pwgt2;
199
200static void mx51_efikasb_power_off(void)
201{
202 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
203
204 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
205 regulator_disable(pwgt2);
206 regulator_disable(pwgt1);
207 }
208 gpio_direction_output(EFIKASB_POWEROFF, 1);
209}
210
211static int __init mx51_efikasb_power_init(void)
212{
213 if (machine_is_mx51_efikasb()) {
214 pwgt1 = regulator_get(NULL, "pwgt1");
215 pwgt2 = regulator_get(NULL, "pwgt2");
216 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
217 regulator_enable(pwgt1);
218 regulator_enable(pwgt2);
219 }
220 gpio_request(EFIKASB_POWEROFF, "poweroff");
221 pm_power_off = mx51_efikasb_power_off;
222
223 regulator_has_full_constraints();
224 }
225
226 return 0;
227}
228late_initcall(mx51_efikasb_power_init);
229
230/* 01 R1.3 board
231 10 R2.0 board */
232static void __init mx51_efikasb_board_id(void)
233{
234 int id;
235
236 gpio_request(EFIKASB_PCBID0, "pcb id0");
237 gpio_direction_input(EFIKASB_PCBID0);
238 gpio_request(EFIKASB_PCBID1, "pcb id1");
239 gpio_direction_input(EFIKASB_PCBID1);
240
241 id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
242 id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
243
244 switch (id) {
245 default:
246 break;
247 case 1:
248 system_rev = 0x13;
249 break;
250 case 2:
251 system_rev = 0x20;
252 break;
253 }
254}
255
256static void __init efikasb_board_init(void)
257{
258 imx51_soc_init();
259
260 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
261 ARRAY_SIZE(mx51efikasb_pads));
262 efika_board_common_init();
263
264 mx51_efikasb_board_id();
265 mx51_efikasb_usb();
266 imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
267 imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
268
269 gpio_led_register_device(-1, &mx51_efikasb_leds_data);
270 imx_add_gpio_keys(&mx51_efikasb_keys_data);
271}
272
273static void __init mx51_efikasb_timer_init(void)
274{
275 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
276}
277
278static struct sys_timer mx51_efikasb_timer = {
279 .init = mx51_efikasb_timer_init,
280};
281
282MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
283 .atag_offset = 0x100,
284 .map_io = mx51_map_io,
285 .init_early = imx51_init_early,
286 .init_irq = mx51_init_irq,
287 .handle_irq = imx51_handle_irq,
288 .init_machine = efikasb_board_init,
289 .timer = &mx51_efikasb_timer,
290 .restart = mxc_restart,
291MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
deleted file mode 100644
index 5f224f1c3eb..00000000000
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "crm_regs.h"
36#include "devices-imx53.h"
37
38#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
39#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
40#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
41#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
42#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
43#define ARD_HOME IMX_GPIO_NR(5, 10)
44#define ARD_BACK IMX_GPIO_NR(5, 11)
45#define ARD_PROG IMX_GPIO_NR(5, 12)
46#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
47
48static iomux_v3_cfg_t mx53_ard_pads[] = {
49 /* UART1 */
50 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
51 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
52 /* WEIM for CS1 */
53 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
54 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
55 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
56 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
57 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
58 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
59 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
60 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
61 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
62 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
63 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
64 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
65 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
66 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
67 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
68 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
69 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
70 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
71 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
72 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
73 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
74 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
75 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
76 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
77 MX53_PAD_EIM_OE__EMI_WEIM_OE,
78 MX53_PAD_EIM_RW__EMI_WEIM_RW,
79 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
80 /* SDHC1 */
81 MX53_PAD_SD1_CMD__ESDHC1_CMD,
82 MX53_PAD_SD1_CLK__ESDHC1_CLK,
83 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
84 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
85 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
86 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
87 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
88 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
89 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
90 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
91 MX53_PAD_GPIO_1__GPIO1_1,
92 MX53_PAD_GPIO_9__GPIO1_9,
93 /* I2C2 */
94 MX53_PAD_EIM_EB2__I2C2_SCL,
95 MX53_PAD_KEY_ROW3__I2C2_SDA,
96 /* I2C3 */
97 MX53_PAD_GPIO_3__I2C3_SCL,
98 MX53_PAD_GPIO_16__I2C3_SDA,
99 /* GPIO */
100 MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
101 MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
102 MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
103 MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
104 MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
105};
106
107#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
108{ \
109 .gpio = gpio_num, \
110 .type = EV_KEY, \
111 .code = ev_code, \
112 .active_low = act_low, \
113 .desc = "btn " descr, \
114 .wakeup = wake, \
115}
116
117static struct gpio_keys_button ard_buttons[] = {
118 GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
119 GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
120 GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
121 GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
122 GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
123};
124
125static const struct gpio_keys_platform_data ard_button_data __initconst = {
126 .buttons = ard_buttons,
127 .nbuttons = ARRAY_SIZE(ard_buttons),
128};
129
130static struct resource ard_smsc911x_resources[] = {
131 {
132 .start = MX53_CS1_64MB_BASE_ADDR,
133 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
138 .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143struct smsc911x_platform_config ard_smsc911x_config = {
144 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
145 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
146 .flags = SMSC911X_USE_32BIT,
147};
148
149static struct platform_device ard_smsc_lan9220_device = {
150 .name = "smsc911x",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
153 .resource = ard_smsc911x_resources,
154 .dev = {
155 .platform_data = &ard_smsc911x_config,
156 },
157};
158
159static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
160 .cd_gpio = ARD_SD1_CD,
161 .wp_gpio = ARD_SD1_WP,
162};
163
164static struct imxi2c_platform_data mx53_ard_i2c2_data = {
165 .bitrate = 50000,
166};
167
168static struct imxi2c_platform_data mx53_ard_i2c3_data = {
169 .bitrate = 400000,
170};
171
172static void __init mx53_ard_io_init(void)
173{
174 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
175 gpio_direction_input(ARD_ETHERNET_INT_B);
176
177 gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
178 gpio_direction_output(ARD_I2CPORTEXP_B, 1);
179}
180
181/* Config CS1 settings for ethernet controller */
182static int weim_cs_config(void)
183{
184 u32 reg;
185 void __iomem *weim_base, *iomuxc_base;
186
187 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
188 if (!weim_base)
189 return -ENOMEM;
190
191 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
192 if (!iomuxc_base)
193 return -ENOMEM;
194
195 /* CS1 timings for LAN9220 */
196 writel(0x20001, (weim_base + 0x18));
197 writel(0x0, (weim_base + 0x1C));
198 writel(0x16000202, (weim_base + 0x20));
199 writel(0x00000002, (weim_base + 0x24));
200 writel(0x16002082, (weim_base + 0x28));
201 writel(0x00000000, (weim_base + 0x2C));
202 writel(0x00000000, (weim_base + 0x90));
203
204 /* specify 64 MB on CS1 and CS0 on GPR1 */
205 reg = readl(iomuxc_base + 0x4);
206 reg &= ~0x3F;
207 reg |= 0x1B;
208 writel(reg, (iomuxc_base + 0x4));
209
210 iounmap(iomuxc_base);
211 iounmap(weim_base);
212
213 return 0;
214}
215
216void __init imx53_ard_common_init(void)
217{
218 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
219 ARRAY_SIZE(mx53_ard_pads));
220 weim_cs_config();
221}
222
223static struct platform_device *devices[] __initdata = {
224 &ard_smsc_lan9220_device,
225};
226
227static void __init mx53_ard_board_init(void)
228{
229 imx53_soc_init();
230 imx53_add_imx_uart(0, NULL);
231
232 imx53_ard_common_init();
233 mx53_ard_io_init();
234 platform_add_devices(devices, ARRAY_SIZE(devices));
235
236 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
237 imx53_add_imx2_wdt(0, NULL);
238 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
239 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
240 imx_add_gpio_keys(&ard_button_data);
241 imx53_add_ahci_imx();
242}
243
244static void __init mx53_ard_timer_init(void)
245{
246 mx53_clocks_init(32768, 24000000, 22579200, 0);
247}
248
249static struct sys_timer mx53_ard_timer = {
250 .init = mx53_ard_timer_init,
251};
252
253MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
254 .map_io = mx53_map_io,
255 .init_early = imx53_init_early,
256 .init_irq = mx53_init_irq,
257 .handle_irq = imx53_handle_irq,
258 .timer = &mx53_ard_timer,
259 .init_machine = mx53_ard_board_init,
260 .restart = mxc_restart,
261MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
deleted file mode 100644
index d6ce137896d..00000000000
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <mach/iomux-mx53.h>
34
35#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
36#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
37#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
38#define MX53EVK_LED IMX_GPIO_NR(7, 7)
39
40#include "crm_regs.h"
41#include "devices-imx53.h"
42
43static iomux_v3_cfg_t mx53_evk_pads[] = {
44 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
45 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
46
47 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
48 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
49 MX53_PAD_PATA_DIOR__UART2_RTS,
50 MX53_PAD_PATA_INTRQ__UART2_CTS,
51
52 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
53 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
54
55 MX53_PAD_EIM_D16__ECSPI1_SCLK,
56 MX53_PAD_EIM_D17__ECSPI1_MISO,
57 MX53_PAD_EIM_D18__ECSPI1_MOSI,
58
59 /* ecspi chip select lines */
60 MX53_PAD_EIM_EB2__GPIO2_30,
61 MX53_PAD_EIM_D19__GPIO3_19,
62 /* LED */
63 MX53_PAD_PATA_DA_1__GPIO7_7,
64};
65
66static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
67 .flags = IMXUART_HAVE_RTSCTS,
68};
69
70static const struct gpio_led mx53evk_leds[] __initconst = {
71 {
72 .name = "green",
73 .default_trigger = "heartbeat",
74 .gpio = MX53EVK_LED,
75 },
76};
77
78static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
79 .leds = mx53evk_leds,
80 .num_leds = ARRAY_SIZE(mx53evk_leds),
81};
82
83static inline void mx53_evk_init_uart(void)
84{
85 imx53_add_imx_uart(0, NULL);
86 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
87 imx53_add_imx_uart(2, NULL);
88}
89
90static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
91 .bitrate = 100000,
92};
93
94static inline void mx53_evk_fec_reset(void)
95{
96 int ret;
97
98 /* reset FEC PHY */
99 ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
100 "fec-phy-reset");
101 if (ret) {
102 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
103 return;
104 }
105 msleep(1);
106 gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
107}
108
109static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
110 .phy = PHY_INTERFACE_MODE_RMII,
111};
112
113static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
114 {
115 .modalias = "mtd_dataflash",
116 .max_speed_hz = 25000000,
117 .bus_num = 0,
118 .chip_select = 1,
119 .mode = SPI_MODE_0,
120 .platform_data = NULL,
121 },
122};
123
124static int mx53_evk_spi_cs[] = {
125 EVK_ECSPI1_CS0,
126 EVK_ECSPI1_CS1,
127};
128
129static const struct spi_imx_master mx53_evk_spi_data __initconst = {
130 .chipselect = mx53_evk_spi_cs,
131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
132};
133
134void __init imx53_evk_common_init(void)
135{
136 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
137 ARRAY_SIZE(mx53_evk_pads));
138}
139
140static void __init mx53_evk_board_init(void)
141{
142 imx53_soc_init();
143 imx53_evk_common_init();
144
145 mx53_evk_init_uart();
146 mx53_evk_fec_reset();
147 imx53_add_fec(&mx53_evk_fec_pdata);
148
149 imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
150 imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
151
152 imx53_add_sdhci_esdhc_imx(0, NULL);
153 imx53_add_sdhci_esdhc_imx(1, NULL);
154
155 spi_register_board_info(mx53_evk_spi_board_info,
156 ARRAY_SIZE(mx53_evk_spi_board_info));
157 imx53_add_ecspi(0, &mx53_evk_spi_data);
158 imx53_add_imx2_wdt(0, NULL);
159 gpio_led_register_device(-1, &mx53evk_leds_data);
160}
161
162static void __init mx53_evk_timer_init(void)
163{
164 mx53_clocks_init(32768, 24000000, 22579200, 0);
165}
166
167static struct sys_timer mx53_evk_timer = {
168 .init = mx53_evk_timer_init,
169};
170
171MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
172 .map_io = mx53_map_io,
173 .init_early = imx53_init_early,
174 .init_irq = mx53_init_irq,
175 .handle_irq = imx53_handle_irq,
176 .timer = &mx53_evk_timer,
177 .init_machine = mx53_evk_board_init,
178 .restart = mxc_restart,
179MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
deleted file mode 100644
index fd8b524e1c5..00000000000
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/i2c.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "crm_regs.h"
36#include "devices-imx53.h"
37
38#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
39#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
40#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
41#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
42#define LOCO_LED IMX_GPIO_NR(7, 7)
43#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
44#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
45#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
46#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
47
48static iomux_v3_cfg_t mx53_loco_pads[] = {
49 /* FEC */
50 MX53_PAD_FEC_MDC__FEC_MDC,
51 MX53_PAD_FEC_MDIO__FEC_MDIO,
52 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
53 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
54 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
55 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
56 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
57 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
58 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
59 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
60 /* FEC_nRST */
61 MX53_PAD_PATA_DA_0__GPIO7_6,
62 /* FEC_nINT */
63 MX53_PAD_PATA_DATA4__GPIO2_4,
64 /* AUDMUX5 */
65 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
66 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
67 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
68 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
69 /* I2C1 */
70 MX53_PAD_CSI0_DAT8__I2C1_SDA,
71 MX53_PAD_CSI0_DAT9__I2C1_SCL,
72 MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */
73 /* I2C2 */
74 MX53_PAD_KEY_COL3__I2C2_SCL,
75 MX53_PAD_KEY_ROW3__I2C2_SDA,
76 /* SD1 */
77 MX53_PAD_SD1_CMD__ESDHC1_CMD,
78 MX53_PAD_SD1_CLK__ESDHC1_CLK,
79 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
80 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
81 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
82 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
83 /* SD1_CD */
84 MX53_PAD_EIM_DA13__GPIO3_13,
85 /* SD3 */
86 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
87 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
88 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
89 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
90 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
91 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
92 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
93 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
94 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
95 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
96 /* SD3_CD */
97 MX53_PAD_EIM_DA11__GPIO3_11,
98 /* SD3_WP */
99 MX53_PAD_EIM_DA12__GPIO3_12,
100 /* VGA */
101 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
102 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
103 /* DISPLB */
104 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
105 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
106 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
107 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
108 /* DISP0_POWER_EN */
109 MX53_PAD_EIM_D24__GPIO3_24,
110 /* DISP0 DET INT */
111 MX53_PAD_EIM_D31__GPIO3_31,
112 /* LVDS */
113 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
114 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
115 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
116 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
117 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
118 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
119 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
120 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
121 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
122 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
123 /* I2C1 */
124 MX53_PAD_CSI0_DAT8__I2C1_SDA,
125 MX53_PAD_CSI0_DAT9__I2C1_SCL,
126 /* UART1 */
127 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
128 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
129 /* CSI0 */
130 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
131 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
132 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
133 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
134 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
135 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
136 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
137 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
138 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
139 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
140 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
141 /* DISPLAY */
142 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
143 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
144 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
145 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
146 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
147 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
148 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
149 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
150 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
151 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
152 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
153 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
154 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
155 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
156 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
157 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
158 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
159 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
160 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
161 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
162 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
163 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
164 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
165 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
166 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
167 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
168 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
169 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
170 /* Audio CLK*/
171 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
172 /* PWM */
173 MX53_PAD_GPIO_1__PWM2_PWMO,
174 /* SPDIF */
175 MX53_PAD_GPIO_7__SPDIF_PLOCK,
176 MX53_PAD_GPIO_17__SPDIF_OUT1,
177 /* GPIO */
178 MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
179 MX53_PAD_PATA_DA_2__GPIO7_8,
180 MX53_PAD_PATA_DATA5__GPIO2_5,
181 MX53_PAD_PATA_DATA6__GPIO2_6,
182 MX53_PAD_PATA_DATA14__GPIO2_14,
183 MX53_PAD_PATA_DATA15__GPIO2_15,
184 MX53_PAD_PATA_INTRQ__GPIO7_2,
185 MX53_PAD_EIM_WAIT__GPIO5_0,
186 MX53_PAD_NANDF_WP_B__GPIO6_9,
187 MX53_PAD_NANDF_RB0__GPIO6_10,
188 MX53_PAD_NANDF_CS1__GPIO6_14,
189 MX53_PAD_NANDF_CS2__GPIO6_15,
190 MX53_PAD_NANDF_CS3__GPIO6_16,
191 MX53_PAD_GPIO_5__GPIO1_5,
192 MX53_PAD_GPIO_16__GPIO7_11,
193 MX53_PAD_GPIO_8__GPIO1_8,
194};
195
196#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
197{ \
198 .gpio = gpio_num, \
199 .type = EV_KEY, \
200 .code = ev_code, \
201 .active_low = act_low, \
202 .desc = "btn " descr, \
203 .wakeup = wake, \
204}
205
206static struct gpio_keys_button loco_buttons[] = {
207 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
208 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
209 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
210};
211
212static const struct gpio_keys_platform_data loco_button_data __initconst = {
213 .buttons = loco_buttons,
214 .nbuttons = ARRAY_SIZE(loco_buttons),
215};
216
217static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
218 .cd_gpio = LOCO_SD1_CD,
219 .cd_type = ESDHC_CD_GPIO,
220 .wp_type = ESDHC_WP_NONE,
221};
222
223static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
224 .cd_gpio = LOCO_SD3_CD,
225 .wp_gpio = LOCO_SD3_WP,
226 .cd_type = ESDHC_CD_GPIO,
227 .wp_type = ESDHC_WP_GPIO,
228};
229
230static inline void mx53_loco_fec_reset(void)
231{
232 int ret;
233
234 /* reset FEC PHY */
235 ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
236 if (ret) {
237 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
238 return;
239 }
240 gpio_direction_output(LOCO_FEC_PHY_RST, 0);
241 msleep(1);
242 gpio_set_value(LOCO_FEC_PHY_RST, 1);
243}
244
245static const struct fec_platform_data mx53_loco_fec_data __initconst = {
246 .phy = PHY_INTERFACE_MODE_RMII,
247};
248
249static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
250 .bitrate = 100000,
251};
252
253static const struct gpio_led mx53loco_leds[] __initconst = {
254 {
255 .name = "green",
256 .default_trigger = "heartbeat",
257 .gpio = LOCO_LED,
258 },
259};
260
261static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
262 .leds = mx53loco_leds,
263 .num_leds = ARRAY_SIZE(mx53loco_leds),
264};
265
266void __init imx53_qsb_common_init(void)
267{
268 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
269 ARRAY_SIZE(mx53_loco_pads));
270}
271
272static struct i2c_board_info mx53loco_i2c_devices[] = {
273 {
274 I2C_BOARD_INFO("mma8450", 0x1C),
275 },
276};
277
278static void __init mx53_loco_board_init(void)
279{
280 int ret;
281 imx53_soc_init();
282 imx53_qsb_common_init();
283
284 imx53_add_imx_uart(0, NULL);
285 mx53_loco_fec_reset();
286 imx53_add_fec(&mx53_loco_fec_data);
287 imx53_add_imx2_wdt(0, NULL);
288
289 ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
290 if (ret)
291 pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
292
293 i2c_register_board_info(0, mx53loco_i2c_devices,
294 ARRAY_SIZE(mx53loco_i2c_devices));
295 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
296 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
297 imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
298 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
299 imx_add_gpio_keys(&loco_button_data);
300 gpio_led_register_device(-1, &mx53loco_leds_data);
301 imx53_add_ahci_imx();
302}
303
304static void __init mx53_loco_timer_init(void)
305{
306 mx53_clocks_init(32768, 24000000, 0, 0);
307}
308
309static struct sys_timer mx53_loco_timer = {
310 .init = mx53_loco_timer_init,
311};
312
313MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
314 .map_io = mx53_map_io,
315 .init_early = imx53_init_early,
316 .init_irq = mx53_init_irq,
317 .handle_irq = imx53_handle_irq,
318 .timer = &mx53_loco_timer,
319 .init_machine = mx53_loco_board_init,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
deleted file mode 100644
index 22c53c9b18a..00000000000
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx53.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "crm_regs.h"
35#include "devices-imx53.h"
36
37#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
38#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
39
40static iomux_v3_cfg_t mx53_smd_pads[] = {
41 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
42 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
43
44 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
45 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
46
47 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
48 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
49 MX53_PAD_PATA_DA_1__UART3_CTS,
50 MX53_PAD_PATA_DA_2__UART3_RTS,
51 /* I2C1 */
52 MX53_PAD_CSI0_DAT8__I2C1_SDA,
53 MX53_PAD_CSI0_DAT9__I2C1_SCL,
54 /* SD1 */
55 MX53_PAD_SD1_CMD__ESDHC1_CMD,
56 MX53_PAD_SD1_CLK__ESDHC1_CLK,
57 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
58 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
59 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
60 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
61 /* SD2 */
62 MX53_PAD_SD2_CMD__ESDHC2_CMD,
63 MX53_PAD_SD2_CLK__ESDHC2_CLK,
64 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
65 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
66 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
67 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
68 /* SD3 */
69 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
70 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
71 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
72 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
73 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
74 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
75 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
76 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
77 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
78 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
79};
80
81static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
82 .flags = IMXUART_HAVE_RTSCTS,
83};
84
85static inline void mx53_smd_init_uart(void)
86{
87 imx53_add_imx_uart(0, NULL);
88 imx53_add_imx_uart(1, NULL);
89 imx53_add_imx_uart(2, &mx53_smd_uart_data);
90}
91
92static inline void mx53_smd_fec_reset(void)
93{
94 int ret;
95
96 /* reset FEC PHY */
97 ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
98 if (ret) {
99 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
100 return;
101 }
102 gpio_direction_output(SMD_FEC_PHY_RST, 0);
103 msleep(1);
104 gpio_set_value(SMD_FEC_PHY_RST, 1);
105}
106
107static const struct fec_platform_data mx53_smd_fec_data __initconst = {
108 .phy = PHY_INTERFACE_MODE_RMII,
109};
110
111static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
112 .bitrate = 100000,
113};
114
115static inline void mx53_smd_ahci_pwr_on(void)
116{
117 int ret;
118
119 /* Enable SATA PWR */
120 ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
121 GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
122 if (ret) {
123 pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
124 return;
125 }
126}
127
128void __init imx53_smd_common_init(void)
129{
130 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
131 ARRAY_SIZE(mx53_smd_pads));
132}
133
134static void __init mx53_smd_board_init(void)
135{
136 imx53_soc_init();
137 imx53_smd_common_init();
138
139 mx53_smd_init_uart();
140 mx53_smd_fec_reset();
141 imx53_add_fec(&mx53_smd_fec_data);
142 imx53_add_imx2_wdt(0, NULL);
143 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
144 imx53_add_sdhci_esdhc_imx(0, NULL);
145 imx53_add_sdhci_esdhc_imx(1, NULL);
146 imx53_add_sdhci_esdhc_imx(2, NULL);
147 mx53_smd_ahci_pwr_on();
148 imx53_add_ahci_imx();
149}
150
151static void __init mx53_smd_timer_init(void)
152{
153 mx53_clocks_init(32768, 24000000, 22579200, 0);
154}
155
156static struct sys_timer mx53_smd_timer = {
157 .init = mx53_smd_timer_init,
158};
159
160MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
161 .map_io = mx53_map_io,
162 .init_early = imx53_init_early,
163 .init_irq = mx53_init_irq,
164 .handle_irq = imx53_handle_irq,
165 .timer = &mx53_smd_timer,
166 .init_machine = mx53_smd_board_init,
167 .restart = mxc_restart,
168MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
deleted file mode 100644
index 4cb27697719..00000000000
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ /dev/null
@@ -1,1675 +0,0 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
18#include <linux/of.h>
19
20#include <asm/div64.h>
21
22#include <mach/hardware.h>
23#include <mach/common.h>
24#include <mach/clock.h>
25
26#include "crm_regs.h"
27
28/* External clock values passed-in by the board code */
29static unsigned long external_high_reference, external_low_reference;
30static unsigned long oscillator_reference, ckih2_reference;
31
32static struct clk osc_clk;
33static struct clk pll1_main_clk;
34static struct clk pll1_sw_clk;
35static struct clk pll2_sw_clk;
36static struct clk pll3_sw_clk;
37static struct clk mx53_pll4_sw_clk;
38static struct clk lp_apm_clk;
39static struct clk periph_apm_clk;
40static struct clk ahb_clk;
41static struct clk ipg_clk;
42static struct clk usboh3_clk;
43static struct clk emi_fast_clk;
44static struct clk ipu_clk;
45static struct clk mipi_hsc1_clk;
46static struct clk esdhc1_clk;
47static struct clk esdhc2_clk;
48static struct clk esdhc3_mx53_clk;
49
50#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
51
52/* calculate best pre and post dividers to get the required divider */
53static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
54 u32 max_pre, u32 max_post)
55{
56 if (div >= max_pre * max_post) {
57 *pre = max_pre;
58 *post = max_post;
59 } else if (div >= max_pre) {
60 u32 min_pre, temp_pre, old_err, err;
61 min_pre = DIV_ROUND_UP(div, max_post);
62 old_err = max_pre;
63 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
64 err = div % temp_pre;
65 if (err == 0) {
66 *pre = temp_pre;
67 break;
68 }
69 err = temp_pre - err;
70 if (err < old_err) {
71 old_err = err;
72 *pre = temp_pre;
73 }
74 }
75 *post = DIV_ROUND_UP(div, *pre);
76 } else {
77 *pre = div;
78 *post = 1;
79 }
80}
81
82static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
83{
84 u32 reg = __raw_readl(clk->enable_reg);
85
86 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
87 reg |= mode << clk->enable_shift;
88
89 __raw_writel(reg, clk->enable_reg);
90}
91
92static int _clk_ccgr_enable(struct clk *clk)
93{
94 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
95 return 0;
96}
97
98static void _clk_ccgr_disable(struct clk *clk)
99{
100 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
101}
102
103static int _clk_ccgr_enable_inrun(struct clk *clk)
104{
105 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
106 return 0;
107}
108
109static void _clk_ccgr_disable_inwait(struct clk *clk)
110{
111 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
112}
113
114/*
115 * For the 4-to-1 muxed input clock
116 */
117static inline u32 _get_mux(struct clk *parent, struct clk *m0,
118 struct clk *m1, struct clk *m2, struct clk *m3)
119{
120 if (parent == m0)
121 return 0;
122 else if (parent == m1)
123 return 1;
124 else if (parent == m2)
125 return 2;
126 else if (parent == m3)
127 return 3;
128 else
129 BUG();
130
131 return -EINVAL;
132}
133
134static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
135{
136 if (pll == &pll1_main_clk)
137 return MX51_DPLL1_BASE;
138 else if (pll == &pll2_sw_clk)
139 return MX51_DPLL2_BASE;
140 else if (pll == &pll3_sw_clk)
141 return MX51_DPLL3_BASE;
142 else
143 BUG();
144
145 return NULL;
146}
147
148static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
149{
150 if (pll == &pll1_main_clk)
151 return MX53_DPLL1_BASE;
152 else if (pll == &pll2_sw_clk)
153 return MX53_DPLL2_BASE;
154 else if (pll == &pll3_sw_clk)
155 return MX53_DPLL3_BASE;
156 else if (pll == &mx53_pll4_sw_clk)
157 return MX53_DPLL4_BASE;
158 else
159 BUG();
160
161 return NULL;
162}
163
164static inline void __iomem *_get_pll_base(struct clk *pll)
165{
166 if (cpu_is_mx51())
167 return _mx51_get_pll_base(pll);
168 else
169 return _mx53_get_pll_base(pll);
170}
171
172static unsigned long clk_pll_get_rate(struct clk *clk)
173{
174 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
175 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
176 void __iomem *pllbase;
177 s64 temp;
178 unsigned long parent_rate;
179
180 parent_rate = clk_get_rate(clk->parent);
181
182 pllbase = _get_pll_base(clk);
183
184 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
185 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
186 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
187
188 if (pll_hfsm == 0) {
189 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
190 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
191 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
192 } else {
193 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
194 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
195 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
196 }
197 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
198 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
199 mfi = (mfi <= 5) ? 5 : mfi;
200 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
201 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
202 /* Sign extend to 32-bits */
203 if (mfn >= 0x04000000) {
204 mfn |= 0xFC000000;
205 mfn_abs = -mfn;
206 }
207
208 ref_clk = 2 * parent_rate;
209 if (dbl != 0)
210 ref_clk *= 2;
211
212 ref_clk /= (pdf + 1);
213 temp = (u64) ref_clk * mfn_abs;
214 do_div(temp, mfd + 1);
215 if (mfn < 0)
216 temp = -temp;
217 temp = (ref_clk * mfi) + temp;
218
219 return temp;
220}
221
222static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
223{
224 u32 reg;
225 void __iomem *pllbase;
226
227 long mfi, pdf, mfn, mfd = 999999;
228 s64 temp64;
229 unsigned long quad_parent_rate;
230 unsigned long pll_hfsm, dp_ctl;
231 unsigned long parent_rate;
232
233 parent_rate = clk_get_rate(clk->parent);
234
235 pllbase = _get_pll_base(clk);
236
237 quad_parent_rate = 4 * parent_rate;
238 pdf = mfi = -1;
239 while (++pdf < 16 && mfi < 5)
240 mfi = rate * (pdf+1) / quad_parent_rate;
241 if (mfi > 15)
242 return -EINVAL;
243 pdf--;
244
245 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
246 do_div(temp64, quad_parent_rate/1000000);
247 mfn = (long)temp64;
248
249 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
250 /* use dpdck0_2 */
251 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
252 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
253 if (pll_hfsm == 0) {
254 reg = mfi << 4 | pdf;
255 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
256 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
257 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
258 } else {
259 reg = mfi << 4 | pdf;
260 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
261 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
262 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
263 }
264
265 return 0;
266}
267
268static int _clk_pll_enable(struct clk *clk)
269{
270 u32 reg;
271 void __iomem *pllbase;
272 int i = 0;
273
274 pllbase = _get_pll_base(clk);
275 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
276 if (reg & MXC_PLL_DP_CTL_UPEN)
277 return 0;
278
279 reg |= MXC_PLL_DP_CTL_UPEN;
280 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
281
282 /* Wait for lock */
283 do {
284 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
285 if (reg & MXC_PLL_DP_CTL_LRF)
286 break;
287
288 udelay(1);
289 } while (++i < MAX_DPLL_WAIT_TRIES);
290
291 if (i == MAX_DPLL_WAIT_TRIES) {
292 pr_err("MX5: pll locking failed\n");
293 return -EINVAL;
294 }
295
296 return 0;
297}
298
299static void _clk_pll_disable(struct clk *clk)
300{
301 u32 reg;
302 void __iomem *pllbase;
303
304 pllbase = _get_pll_base(clk);
305 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
306 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
307}
308
309static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
310{
311 u32 reg, step;
312
313 reg = __raw_readl(MXC_CCM_CCSR);
314
315 /* When switching from pll_main_clk to a bypass clock, first select a
316 * multiplexed clock in 'step_sel', then shift the glitchless mux
317 * 'pll1_sw_clk_sel'.
318 *
319 * When switching back, do it in reverse order
320 */
321 if (parent == &pll1_main_clk) {
322 /* Switch to pll1_main_clk */
323 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
324 __raw_writel(reg, MXC_CCM_CCSR);
325 /* step_clk mux switched to lp_apm, to save power. */
326 reg = __raw_readl(MXC_CCM_CCSR);
327 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
328 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
329 MXC_CCM_CCSR_STEP_SEL_OFFSET);
330 } else {
331 if (parent == &lp_apm_clk) {
332 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
333 } else if (parent == &pll2_sw_clk) {
334 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
335 } else if (parent == &pll3_sw_clk) {
336 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
337 } else
338 return -EINVAL;
339
340 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
341 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
342
343 __raw_writel(reg, MXC_CCM_CCSR);
344 /* Switch to step_clk */
345 reg = __raw_readl(MXC_CCM_CCSR);
346 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
347 }
348 __raw_writel(reg, MXC_CCM_CCSR);
349 return 0;
350}
351
352static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
353{
354 u32 reg, div;
355 unsigned long parent_rate;
356
357 parent_rate = clk_get_rate(clk->parent);
358
359 reg = __raw_readl(MXC_CCM_CCSR);
360
361 if (clk->parent == &pll2_sw_clk) {
362 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
363 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
364 } else if (clk->parent == &pll3_sw_clk) {
365 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
366 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
367 } else
368 div = 1;
369 return parent_rate / div;
370}
371
372static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
373{
374 u32 reg;
375
376 reg = __raw_readl(MXC_CCM_CCSR);
377
378 if (parent == &pll2_sw_clk)
379 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
380 else
381 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
382
383 __raw_writel(reg, MXC_CCM_CCSR);
384 return 0;
385}
386
387static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
388{
389 u32 reg;
390
391 if (parent == &osc_clk)
392 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
393 else
394 return -EINVAL;
395
396 __raw_writel(reg, MXC_CCM_CCSR);
397
398 return 0;
399}
400
401static unsigned long clk_cpu_get_rate(struct clk *clk)
402{
403 u32 cacrr, div;
404 unsigned long parent_rate;
405
406 parent_rate = clk_get_rate(clk->parent);
407 cacrr = __raw_readl(MXC_CCM_CACRR);
408 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
409
410 return parent_rate / div;
411}
412
413static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
414{
415 u32 reg, cpu_podf;
416 unsigned long parent_rate;
417
418 parent_rate = clk_get_rate(clk->parent);
419 cpu_podf = parent_rate / rate - 1;
420 /* use post divider to change freq */
421 reg = __raw_readl(MXC_CCM_CACRR);
422 reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
423 reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
424 __raw_writel(reg, MXC_CCM_CACRR);
425
426 return 0;
427}
428
429static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
430{
431 u32 reg, mux;
432 int i = 0;
433
434 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
435
436 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
437 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
438 __raw_writel(reg, MXC_CCM_CBCMR);
439
440 /* Wait for lock */
441 do {
442 reg = __raw_readl(MXC_CCM_CDHIPR);
443 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
444 break;
445
446 udelay(1);
447 } while (++i < MAX_DPLL_WAIT_TRIES);
448
449 if (i == MAX_DPLL_WAIT_TRIES) {
450 pr_err("MX5: Set parent for periph_apm clock failed\n");
451 return -EINVAL;
452 }
453
454 return 0;
455}
456
457static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
458{
459 u32 reg;
460
461 reg = __raw_readl(MXC_CCM_CBCDR);
462
463 if (parent == &pll2_sw_clk)
464 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
465 else if (parent == &periph_apm_clk)
466 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
467 else
468 return -EINVAL;
469
470 __raw_writel(reg, MXC_CCM_CBCDR);
471
472 return 0;
473}
474
475static struct clk main_bus_clk = {
476 .parent = &pll2_sw_clk,
477 .set_parent = _clk_main_bus_set_parent,
478};
479
480static unsigned long clk_ahb_get_rate(struct clk *clk)
481{
482 u32 reg, div;
483 unsigned long parent_rate;
484
485 parent_rate = clk_get_rate(clk->parent);
486
487 reg = __raw_readl(MXC_CCM_CBCDR);
488 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
489 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
490 return parent_rate / div;
491}
492
493
494static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
495{
496 u32 reg, div;
497 unsigned long parent_rate;
498 int i = 0;
499
500 parent_rate = clk_get_rate(clk->parent);
501
502 div = parent_rate / rate;
503 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
504 return -EINVAL;
505
506 reg = __raw_readl(MXC_CCM_CBCDR);
507 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
508 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
509 __raw_writel(reg, MXC_CCM_CBCDR);
510
511 /* Wait for lock */
512 do {
513 reg = __raw_readl(MXC_CCM_CDHIPR);
514 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
515 break;
516
517 udelay(1);
518 } while (++i < MAX_DPLL_WAIT_TRIES);
519
520 if (i == MAX_DPLL_WAIT_TRIES) {
521 pr_err("MX5: clk_ahb_set_rate failed\n");
522 return -EINVAL;
523 }
524
525 return 0;
526}
527
528static unsigned long _clk_ahb_round_rate(struct clk *clk,
529 unsigned long rate)
530{
531 u32 div;
532 unsigned long parent_rate;
533
534 parent_rate = clk_get_rate(clk->parent);
535
536 div = parent_rate / rate;
537 if (div > 8)
538 div = 8;
539 else if (div == 0)
540 div++;
541 return parent_rate / div;
542}
543
544
545static int _clk_max_enable(struct clk *clk)
546{
547 u32 reg;
548
549 _clk_ccgr_enable(clk);
550
551 /* Handshake with MAX when LPM is entered. */
552 reg = __raw_readl(MXC_CCM_CLPCR);
553 if (cpu_is_mx51())
554 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
555 else if (cpu_is_mx53())
556 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
557 __raw_writel(reg, MXC_CCM_CLPCR);
558
559 return 0;
560}
561
562static void _clk_max_disable(struct clk *clk)
563{
564 u32 reg;
565
566 _clk_ccgr_disable_inwait(clk);
567
568 /* No Handshake with MAX when LPM is entered as its disabled. */
569 reg = __raw_readl(MXC_CCM_CLPCR);
570 if (cpu_is_mx51())
571 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
572 else if (cpu_is_mx53())
573 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
574 __raw_writel(reg, MXC_CCM_CLPCR);
575}
576
577static unsigned long clk_ipg_get_rate(struct clk *clk)
578{
579 u32 reg, div;
580 unsigned long parent_rate;
581
582 parent_rate = clk_get_rate(clk->parent);
583
584 reg = __raw_readl(MXC_CCM_CBCDR);
585 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
586 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
587
588 return parent_rate / div;
589}
590
591static unsigned long clk_ipg_per_get_rate(struct clk *clk)
592{
593 u32 reg, prediv1, prediv2, podf;
594 unsigned long parent_rate;
595
596 parent_rate = clk_get_rate(clk->parent);
597
598 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
599 /* the main_bus_clk is the one before the DVFS engine */
600 reg = __raw_readl(MXC_CCM_CBCDR);
601 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
602 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
603 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
604 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
605 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
606 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
607 return parent_rate / (prediv1 * prediv2 * podf);
608 } else if (clk->parent == &ipg_clk)
609 return parent_rate;
610 else
611 BUG();
612}
613
614static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
615{
616 u32 reg;
617
618 reg = __raw_readl(MXC_CCM_CBCMR);
619
620 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
621 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
622
623 if (parent == &ipg_clk)
624 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
625 else if (parent == &lp_apm_clk)
626 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
627 else if (parent != &main_bus_clk)
628 return -EINVAL;
629
630 __raw_writel(reg, MXC_CCM_CBCMR);
631
632 return 0;
633}
634
635#define clk_nfc_set_parent NULL
636
637static unsigned long clk_nfc_get_rate(struct clk *clk)
638{
639 unsigned long rate;
640 u32 reg, div;
641
642 reg = __raw_readl(MXC_CCM_CBCDR);
643 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
644 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
645 rate = clk_get_rate(clk->parent) / div;
646 WARN_ON(rate == 0);
647 return rate;
648}
649
650static unsigned long clk_nfc_round_rate(struct clk *clk,
651 unsigned long rate)
652{
653 u32 div;
654 unsigned long parent_rate = clk_get_rate(clk->parent);
655
656 if (!rate)
657 return -EINVAL;
658
659 div = parent_rate / rate;
660
661 if (parent_rate % rate)
662 div++;
663
664 if (div > 8)
665 return -EINVAL;
666
667 return parent_rate / div;
668
669}
670
671static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
672{
673 u32 reg, div;
674
675 div = clk_get_rate(clk->parent) / rate;
676 if (div == 0)
677 div++;
678 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
679 return -EINVAL;
680
681 reg = __raw_readl(MXC_CCM_CBCDR);
682 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
683 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
684 __raw_writel(reg, MXC_CCM_CBCDR);
685
686 while (__raw_readl(MXC_CCM_CDHIPR) &
687 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
688 }
689
690 return 0;
691}
692
693static unsigned long get_high_reference_clock_rate(struct clk *clk)
694{
695 return external_high_reference;
696}
697
698static unsigned long get_low_reference_clock_rate(struct clk *clk)
699{
700 return external_low_reference;
701}
702
703static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
704{
705 return oscillator_reference;
706}
707
708static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
709{
710 return ckih2_reference;
711}
712
713static unsigned long clk_emi_slow_get_rate(struct clk *clk)
714{
715 u32 reg, div;
716
717 reg = __raw_readl(MXC_CCM_CBCDR);
718 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
719 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
720
721 return clk_get_rate(clk->parent) / div;
722}
723
724static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
725{
726 unsigned long rate;
727 u32 reg, div;
728
729 reg = __raw_readl(MXC_CCM_CBCDR);
730 div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
731 MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
732 rate = clk_get_rate(clk->parent) / div;
733
734 return rate;
735}
736
737/* External high frequency clock */
738static struct clk ckih_clk = {
739 .get_rate = get_high_reference_clock_rate,
740};
741
742static struct clk ckih2_clk = {
743 .get_rate = get_ckih2_reference_clock_rate,
744};
745
746static struct clk osc_clk = {
747 .get_rate = get_oscillator_reference_clock_rate,
748};
749
750/* External low frequency (32kHz) clock */
751static struct clk ckil_clk = {
752 .get_rate = get_low_reference_clock_rate,
753};
754
755static struct clk pll1_main_clk = {
756 .parent = &osc_clk,
757 .get_rate = clk_pll_get_rate,
758 .enable = _clk_pll_enable,
759 .disable = _clk_pll_disable,
760};
761
762/* Clock tree block diagram (WIP):
763 * CCM: Clock Controller Module
764 *
765 * PLL output -> |
766 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
767 * PLL bypass -> |
768 *
769 */
770
771/* PLL1 SW supplies to ARM core */
772static struct clk pll1_sw_clk = {
773 .parent = &pll1_main_clk,
774 .set_parent = _clk_pll1_sw_set_parent,
775 .get_rate = clk_pll1_sw_get_rate,
776};
777
778/* PLL2 SW supplies to AXI/AHB/IP buses */
779static struct clk pll2_sw_clk = {
780 .parent = &osc_clk,
781 .get_rate = clk_pll_get_rate,
782 .set_rate = _clk_pll_set_rate,
783 .set_parent = _clk_pll2_sw_set_parent,
784 .enable = _clk_pll_enable,
785 .disable = _clk_pll_disable,
786};
787
788/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
789static struct clk pll3_sw_clk = {
790 .parent = &osc_clk,
791 .set_rate = _clk_pll_set_rate,
792 .get_rate = clk_pll_get_rate,
793 .enable = _clk_pll_enable,
794 .disable = _clk_pll_disable,
795};
796
797/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
798static struct clk mx53_pll4_sw_clk = {
799 .parent = &osc_clk,
800 .set_rate = _clk_pll_set_rate,
801 .enable = _clk_pll_enable,
802 .disable = _clk_pll_disable,
803};
804
805/* Low-power Audio Playback Mode clock */
806static struct clk lp_apm_clk = {
807 .parent = &osc_clk,
808 .set_parent = _clk_lp_apm_set_parent,
809};
810
811static struct clk periph_apm_clk = {
812 .parent = &pll1_sw_clk,
813 .set_parent = _clk_periph_apm_set_parent,
814};
815
816static struct clk cpu_clk = {
817 .parent = &pll1_sw_clk,
818 .get_rate = clk_cpu_get_rate,
819 .set_rate = clk_cpu_set_rate,
820};
821
822static struct clk ahb_clk = {
823 .parent = &main_bus_clk,
824 .get_rate = clk_ahb_get_rate,
825 .set_rate = _clk_ahb_set_rate,
826 .round_rate = _clk_ahb_round_rate,
827};
828
829static struct clk iim_clk = {
830 .parent = &ipg_clk,
831 .enable_reg = MXC_CCM_CCGR0,
832 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
833};
834
835/* Main IP interface clock for access to registers */
836static struct clk ipg_clk = {
837 .parent = &ahb_clk,
838 .get_rate = clk_ipg_get_rate,
839};
840
841static struct clk ipg_perclk = {
842 .parent = &lp_apm_clk,
843 .get_rate = clk_ipg_per_get_rate,
844 .set_parent = _clk_ipg_per_set_parent,
845};
846
847static struct clk ahb_max_clk = {
848 .parent = &ahb_clk,
849 .enable_reg = MXC_CCM_CCGR0,
850 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
851 .enable = _clk_max_enable,
852 .disable = _clk_max_disable,
853};
854
855static struct clk aips_tz1_clk = {
856 .parent = &ahb_clk,
857 .secondary = &ahb_max_clk,
858 .enable_reg = MXC_CCM_CCGR0,
859 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
860 .enable = _clk_ccgr_enable,
861 .disable = _clk_ccgr_disable_inwait,
862};
863
864static struct clk aips_tz2_clk = {
865 .parent = &ahb_clk,
866 .secondary = &ahb_max_clk,
867 .enable_reg = MXC_CCM_CCGR0,
868 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
869 .enable = _clk_ccgr_enable,
870 .disable = _clk_ccgr_disable_inwait,
871};
872
873static struct clk gpc_dvfs_clk = {
874 .enable_reg = MXC_CCM_CCGR5,
875 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
876 .enable = _clk_ccgr_enable,
877 .disable = _clk_ccgr_disable,
878};
879
880static struct clk gpt_32k_clk = {
881 .id = 0,
882 .parent = &ckil_clk,
883};
884
885static struct clk dummy_clk = {
886 .id = 0,
887};
888
889static struct clk emi_slow_clk = {
890 .parent = &pll2_sw_clk,
891 .enable_reg = MXC_CCM_CCGR5,
892 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
893 .enable = _clk_ccgr_enable,
894 .disable = _clk_ccgr_disable_inwait,
895 .get_rate = clk_emi_slow_get_rate,
896};
897
898static int clk_ipu_enable(struct clk *clk)
899{
900 u32 reg;
901
902 _clk_ccgr_enable(clk);
903
904 /* Enable handshake with IPU when certain clock rates are changed */
905 reg = __raw_readl(MXC_CCM_CCDR);
906 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
907 __raw_writel(reg, MXC_CCM_CCDR);
908
909 /* Enable handshake with IPU when LPM is entered */
910 reg = __raw_readl(MXC_CCM_CLPCR);
911 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
912 __raw_writel(reg, MXC_CCM_CLPCR);
913
914 return 0;
915}
916
917static void clk_ipu_disable(struct clk *clk)
918{
919 u32 reg;
920
921 _clk_ccgr_disable(clk);
922
923 /* Disable handshake with IPU whe dividers are changed */
924 reg = __raw_readl(MXC_CCM_CCDR);
925 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
926 __raw_writel(reg, MXC_CCM_CCDR);
927
928 /* Disable handshake with IPU when LPM is entered */
929 reg = __raw_readl(MXC_CCM_CLPCR);
930 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
931 __raw_writel(reg, MXC_CCM_CLPCR);
932}
933
934static struct clk ahbmux1_clk = {
935 .parent = &ahb_clk,
936 .secondary = &ahb_max_clk,
937 .enable_reg = MXC_CCM_CCGR0,
938 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
939 .enable = _clk_ccgr_enable,
940 .disable = _clk_ccgr_disable_inwait,
941};
942
943static struct clk ipu_sec_clk = {
944 .parent = &emi_fast_clk,
945 .secondary = &ahbmux1_clk,
946};
947
948static struct clk ddr_hf_clk = {
949 .parent = &pll1_sw_clk,
950 .get_rate = _clk_ddr_hf_get_rate,
951};
952
953static struct clk ddr_clk = {
954 .parent = &ddr_hf_clk,
955};
956
957/* clock definitions for MIPI HSC unit which has been removed
958 * from documentation, but not from hardware
959 */
960static int _clk_hsc_enable(struct clk *clk)
961{
962 u32 reg;
963
964 _clk_ccgr_enable(clk);
965 /* Handshake with IPU when certain clock rates are changed. */
966 reg = __raw_readl(MXC_CCM_CCDR);
967 reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
968 __raw_writel(reg, MXC_CCM_CCDR);
969
970 reg = __raw_readl(MXC_CCM_CLPCR);
971 reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
972 __raw_writel(reg, MXC_CCM_CLPCR);
973
974 return 0;
975}
976
977static void _clk_hsc_disable(struct clk *clk)
978{
979 u32 reg;
980
981 _clk_ccgr_disable(clk);
982 /* No handshake with HSC as its not enabled. */
983 reg = __raw_readl(MXC_CCM_CCDR);
984 reg |= MXC_CCM_CCDR_HSC_HS_MASK;
985 __raw_writel(reg, MXC_CCM_CCDR);
986
987 reg = __raw_readl(MXC_CCM_CLPCR);
988 reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
989 __raw_writel(reg, MXC_CCM_CLPCR);
990}
991
992static struct clk mipi_hsp_clk = {
993 .parent = &ipu_clk,
994 .enable_reg = MXC_CCM_CCGR4,
995 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
996 .enable = _clk_hsc_enable,
997 .disable = _clk_hsc_disable,
998 .secondary = &mipi_hsc1_clk,
999};
1000
1001#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
1002 static struct clk name = { \
1003 .id = i, \
1004 .enable_reg = er, \
1005 .enable_shift = es, \
1006 .get_rate = pfx##_get_rate, \
1007 .set_rate = pfx##_set_rate, \
1008 .round_rate = pfx##_round_rate, \
1009 .set_parent = pfx##_set_parent, \
1010 .enable = _clk_ccgr_enable, \
1011 .disable = _clk_ccgr_disable, \
1012 .parent = p, \
1013 .secondary = s, \
1014 }
1015
1016#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
1017 static struct clk name = { \
1018 .id = i, \
1019 .enable_reg = er, \
1020 .enable_shift = es, \
1021 .get_rate = pfx##_get_rate, \
1022 .set_rate = pfx##_set_rate, \
1023 .set_parent = pfx##_set_parent, \
1024 .enable = _clk_max_enable, \
1025 .disable = _clk_max_disable, \
1026 .parent = p, \
1027 .secondary = s, \
1028 }
1029
1030#define CLK_GET_RATE(name, nr, bitsname) \
1031static unsigned long clk_##name##_get_rate(struct clk *clk) \
1032{ \
1033 u32 reg, pred, podf; \
1034 \
1035 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
1036 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
1037 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1038 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
1039 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1040 \
1041 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
1042 (pred + 1) * (podf + 1)); \
1043}
1044
1045#define CLK_SET_PARENT(name, nr, bitsname) \
1046static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
1047{ \
1048 u32 reg, mux; \
1049 \
1050 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
1051 &pll3_sw_clk, &lp_apm_clk); \
1052 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
1053 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
1054 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
1055 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
1056 \
1057 return 0; \
1058}
1059
1060#define CLK_SET_RATE(name, nr, bitsname) \
1061static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
1062{ \
1063 u32 reg, div, parent_rate; \
1064 u32 pre = 0, post = 0; \
1065 \
1066 parent_rate = clk_get_rate(clk->parent); \
1067 div = parent_rate / rate; \
1068 \
1069 if ((parent_rate / div) != rate) \
1070 return -EINVAL; \
1071 \
1072 __calc_pre_post_dividers(div, &pre, &post, \
1073 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
1074 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
1075 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
1076 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
1077 \
1078 /* Set sdhc1 clock divider */ \
1079 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
1080 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
1081 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
1082 reg |= (post - 1) << \
1083 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1084 reg |= (pre - 1) << \
1085 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1086 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
1087 \
1088 return 0; \
1089}
1090
1091/* UART */
1092CLK_GET_RATE(uart, 1, UART)
1093CLK_SET_PARENT(uart, 1, UART)
1094
1095static struct clk uart_root_clk = {
1096 .parent = &pll2_sw_clk,
1097 .get_rate = clk_uart_get_rate,
1098 .set_parent = clk_uart_set_parent,
1099};
1100
1101/* USBOH3 */
1102CLK_GET_RATE(usboh3, 1, USBOH3)
1103CLK_SET_PARENT(usboh3, 1, USBOH3)
1104
1105static struct clk usboh3_clk = {
1106 .parent = &pll2_sw_clk,
1107 .get_rate = clk_usboh3_get_rate,
1108 .set_parent = clk_usboh3_set_parent,
1109 .enable = _clk_ccgr_enable,
1110 .disable = _clk_ccgr_disable,
1111 .enable_reg = MXC_CCM_CCGR2,
1112 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1113};
1114
1115static struct clk usb_ahb_clk = {
1116 .parent = &ipg_clk,
1117 .enable = _clk_ccgr_enable,
1118 .disable = _clk_ccgr_disable,
1119 .enable_reg = MXC_CCM_CCGR2,
1120 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1121};
1122
1123static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
1124{
1125 u32 reg;
1126
1127 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
1128
1129 if (parent == &pll3_sw_clk)
1130 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
1131
1132 __raw_writel(reg, MXC_CCM_CSCMR1);
1133
1134 return 0;
1135}
1136
1137static struct clk usb_phy1_clk = {
1138 .parent = &pll3_sw_clk,
1139 .set_parent = clk_usb_phy1_set_parent,
1140 .enable = _clk_ccgr_enable,
1141 .enable_reg = MXC_CCM_CCGR2,
1142 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1143 .disable = _clk_ccgr_disable,
1144};
1145
1146/* eCSPI */
1147CLK_GET_RATE(ecspi, 2, CSPI)
1148CLK_SET_PARENT(ecspi, 1, CSPI)
1149
1150static struct clk ecspi_main_clk = {
1151 .parent = &pll3_sw_clk,
1152 .get_rate = clk_ecspi_get_rate,
1153 .set_parent = clk_ecspi_set_parent,
1154};
1155
1156/* eSDHC */
1157CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1158CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1159CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1160
1161/* mx51 specific */
1162CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1163CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1164CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1165
1166static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1167{
1168 u32 reg;
1169
1170 reg = __raw_readl(MXC_CCM_CSCMR1);
1171 if (parent == &esdhc1_clk)
1172 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1173 else if (parent == &esdhc2_clk)
1174 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1175 else
1176 return -EINVAL;
1177 __raw_writel(reg, MXC_CCM_CSCMR1);
1178
1179 return 0;
1180}
1181
1182static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1183{
1184 u32 reg;
1185
1186 reg = __raw_readl(MXC_CCM_CSCMR1);
1187 if (parent == &esdhc1_clk)
1188 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1189 else if (parent == &esdhc2_clk)
1190 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1191 else
1192 return -EINVAL;
1193 __raw_writel(reg, MXC_CCM_CSCMR1);
1194
1195 return 0;
1196}
1197
1198/* mx53 specific */
1199static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1200{
1201 u32 reg;
1202
1203 reg = __raw_readl(MXC_CCM_CSCMR1);
1204 if (parent == &esdhc1_clk)
1205 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1206 else if (parent == &esdhc3_mx53_clk)
1207 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1208 else
1209 return -EINVAL;
1210 __raw_writel(reg, MXC_CCM_CSCMR1);
1211
1212 return 0;
1213}
1214
1215CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1216CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1217CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1218
1219static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1220{
1221 u32 reg;
1222
1223 reg = __raw_readl(MXC_CCM_CSCMR1);
1224 if (parent == &esdhc1_clk)
1225 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1226 else if (parent == &esdhc3_mx53_clk)
1227 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1228 else
1229 return -EINVAL;
1230 __raw_writel(reg, MXC_CCM_CSCMR1);
1231
1232 return 0;
1233}
1234
1235#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
1236 static struct clk name = { \
1237 .id = i, \
1238 .enable_reg = er, \
1239 .enable_shift = es, \
1240 .get_rate = gr, \
1241 .set_rate = sr, \
1242 .enable = e, \
1243 .disable = d, \
1244 .parent = p, \
1245 .secondary = s, \
1246 }
1247
1248#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
1249 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
1250
1251/* Shared peripheral bus arbiter */
1252DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
1253 NULL, NULL, &ipg_clk, NULL);
1254
1255/* UART */
1256DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
1257 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1258DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
1259 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1260DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1261 NULL, NULL, &ipg_clk, &spba_clk);
1262DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
1263 NULL, NULL, &ipg_clk, &spba_clk);
1264DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
1265 NULL, NULL, &ipg_clk, &spba_clk);
1266DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1267 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
1268DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1269 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
1270DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1271 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
1272DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
1273 NULL, NULL, &uart_root_clk, &uart4_ipg_clk);
1274DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
1275 NULL, NULL, &uart_root_clk, &uart5_ipg_clk);
1276
1277/* GPT */
1278DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1279 NULL, NULL, &ipg_clk, NULL);
1280DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1281 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
1282
1283DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
1284 NULL, NULL, &ipg_perclk, NULL);
1285DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
1286 NULL, NULL, &ipg_perclk, NULL);
1287
1288/* I2C */
1289DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1290 NULL, NULL, &ipg_perclk, NULL);
1291DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1292 NULL, NULL, &ipg_perclk, NULL);
1293DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1294 NULL, NULL, &ipg_clk, NULL);
1295DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1296 NULL, NULL, &ipg_perclk, NULL);
1297
1298/* FEC */
1299DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1300 NULL, NULL, &ipg_clk, NULL);
1301
1302/* NFC */
1303DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1304 clk_nfc, &emi_slow_clk, NULL);
1305
1306/* SSI */
1307DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1308 NULL, NULL, &ipg_clk, NULL);
1309DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1310 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1311DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1312 NULL, NULL, &ipg_clk, NULL);
1313DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1314 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1315DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
1316 NULL, NULL, &ipg_clk, NULL);
1317DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
1318 NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
1319
1320/* eCSPI */
1321DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1322 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1323 &ipg_clk, &spba_clk);
1324DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1325 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1326DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1327 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1328 &ipg_clk, &aips_tz2_clk);
1329DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1330 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1331
1332/* CSPI */
1333DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1334 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1335DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1336 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1337
1338/* SDMA */
1339DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1340 NULL, NULL, &ahb_clk, NULL);
1341
1342/* eSDHC */
1343DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1344 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1345DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1346 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1347DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1348 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1349DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1350 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1351DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1352 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1353
1354/* mx51 specific */
1355DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1356 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1357
1358static struct clk esdhc3_clk = {
1359 .id = 2,
1360 .parent = &esdhc1_clk,
1361 .set_parent = clk_esdhc3_set_parent,
1362 .enable_reg = MXC_CCM_CCGR3,
1363 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1364 .enable = _clk_max_enable,
1365 .disable = _clk_max_disable,
1366 .secondary = &esdhc3_ipg_clk,
1367};
1368static struct clk esdhc4_clk = {
1369 .id = 3,
1370 .parent = &esdhc1_clk,
1371 .set_parent = clk_esdhc4_set_parent,
1372 .enable_reg = MXC_CCM_CCGR3,
1373 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1374 .enable = _clk_max_enable,
1375 .disable = _clk_max_disable,
1376 .secondary = &esdhc4_ipg_clk,
1377};
1378
1379/* mx53 specific */
1380static struct clk esdhc2_mx53_clk = {
1381 .id = 2,
1382 .parent = &esdhc1_clk,
1383 .set_parent = clk_esdhc2_mx53_set_parent,
1384 .enable_reg = MXC_CCM_CCGR3,
1385 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1386 .enable = _clk_max_enable,
1387 .disable = _clk_max_disable,
1388 .secondary = &esdhc3_ipg_clk,
1389};
1390
1391DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1392 clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1393
1394static struct clk esdhc4_mx53_clk = {
1395 .id = 3,
1396 .parent = &esdhc1_clk,
1397 .set_parent = clk_esdhc4_mx53_set_parent,
1398 .enable_reg = MXC_CCM_CCGR3,
1399 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1400 .enable = _clk_max_enable,
1401 .disable = _clk_max_disable,
1402 .secondary = &esdhc4_ipg_clk,
1403};
1404
1405static struct clk sata_clk = {
1406 .parent = &ipg_clk,
1407 .enable = _clk_max_enable,
1408 .enable_reg = MXC_CCM_CCGR4,
1409 .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
1410 .disable = _clk_max_disable,
1411};
1412
1413static struct clk ahci_phy_clk = {
1414 .parent = &usb_phy1_clk,
1415};
1416
1417static struct clk ahci_dma_clk = {
1418 .parent = &ahb_clk,
1419};
1420
1421DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1422DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1423DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
1424
1425/* IPU */
1426DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
1427 NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
1428
1429DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
1430 NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
1431 &ddr_clk, NULL);
1432
1433DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1434 NULL, NULL, &pll3_sw_clk, NULL);
1435DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1436 NULL, NULL, &pll3_sw_clk, NULL);
1437
1438/* PATA */
1439DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
1440 NULL, NULL, &ipg_clk, &spba_clk);
1441
1442#define _REGISTER_CLOCK(d, n, c) \
1443 { \
1444 .dev_id = d, \
1445 .con_id = n, \
1446 .clk = &c, \
1447 },
1448
1449static struct clk_lookup mx51_lookups[] = {
1450 /* i.mx51 has the i.mx21 type uart */
1451 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1452 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1453 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1454 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1455 /* i.mx51 has the i.mx27 type fec */
1456 _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
1457 _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
1458 _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
1459 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1460 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1461 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1462 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1463 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1464 _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1465 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1466 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1467 _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1468 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1469 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1470 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1471 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1472 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1473 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1474 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1475 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1476 /* i.mx51 has the i.mx35 type sdma */
1477 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1478 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1479 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1480 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1481 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1482 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1483 /* i.mx51 has the i.mx35 type cspi */
1484 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1485 _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
1486 _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
1487 _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
1488 _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
1489 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1490 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1491 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1492 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1493 _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
1494 _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1495 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1496 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1497 _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
1498 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1499};
1500
1501static struct clk_lookup mx53_lookups[] = {
1502 /* i.mx53 has the i.mx21 type uart */
1503 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1504 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1505 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1506 _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
1507 _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
1508 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1509 /* i.mx53 has the i.mx25 type fec */
1510 _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
1511 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1512 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1513 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1514 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
1515 /* i.mx53 has the i.mx51 type ecspi */
1516 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1517 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1518 /* i.mx53 has the i.mx25 type cspi */
1519 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1520 _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
1521 _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
1522 _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
1523 _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
1524 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1525 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1526 /* i.mx53 has the i.mx35 type sdma */
1527 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1528 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1529 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1530 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1531 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1532 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1533 _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
1534 _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
1535 _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
1536};
1537
1538static void clk_tree_init(void)
1539{
1540 u32 reg;
1541
1542 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1543
1544 /*
1545 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1546 * 8MHz, its derived from lp_apm.
1547 *
1548 * FIXME: Verify if true for all boards
1549 */
1550 reg = __raw_readl(MXC_CCM_CBCDR);
1551 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1552 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1553 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1554 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1555 __raw_writel(reg, MXC_CCM_CBCDR);
1556}
1557
1558int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1559 unsigned long ckih1, unsigned long ckih2)
1560{
1561 int i;
1562
1563 external_low_reference = ckil;
1564 external_high_reference = ckih1;
1565 ckih2_reference = ckih2;
1566 oscillator_reference = osc;
1567
1568 for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1569 clkdev_add(&mx51_lookups[i]);
1570
1571 clk_tree_init();
1572
1573 clk_enable(&cpu_clk);
1574 clk_enable(&main_bus_clk);
1575
1576 clk_enable(&iim_clk);
1577 imx_print_silicon_rev("i.MX51", mx51_revision());
1578 clk_disable(&iim_clk);
1579
1580 /* move usb_phy_clk to 24MHz */
1581 clk_set_parent(&usb_phy1_clk, &osc_clk);
1582
1583 /* set the usboh3_clk parent to pll2_sw_clk */
1584 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1585
1586 /* Set SDHC parents to be PLL2 */
1587 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1588 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1589
1590 /* set SDHC root clock as 166.25MHZ*/
1591 clk_set_rate(&esdhc1_clk, 166250000);
1592 clk_set_rate(&esdhc2_clk, 166250000);
1593
1594 /* System timer */
1595 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1596 MX51_INT_GPT);
1597 return 0;
1598}
1599
1600int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1601 unsigned long ckih1, unsigned long ckih2)
1602{
1603 int i;
1604
1605 external_low_reference = ckil;
1606 external_high_reference = ckih1;
1607 ckih2_reference = ckih2;
1608 oscillator_reference = osc;
1609
1610 for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1611 clkdev_add(&mx53_lookups[i]);
1612
1613 clk_tree_init();
1614
1615 clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1616 clk_enable(&cpu_clk);
1617 clk_enable(&main_bus_clk);
1618
1619 clk_enable(&iim_clk);
1620 imx_print_silicon_rev("i.MX53", mx53_revision());
1621 clk_disable(&iim_clk);
1622
1623 /* Set SDHC parents to be PLL2 */
1624 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1625 clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1626
1627 /* set SDHC root clock as 200MHZ*/
1628 clk_set_rate(&esdhc1_clk, 200000000);
1629 clk_set_rate(&esdhc3_mx53_clk, 200000000);
1630
1631 /* System timer */
1632 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1633 MX53_INT_GPT);
1634 return 0;
1635}
1636
1637#ifdef CONFIG_OF
1638static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
1639 unsigned long *ckih1, unsigned long *ckih2)
1640{
1641 struct device_node *np;
1642
1643 /* retrieve the freqency of fixed clocks from device tree */
1644 for_each_compatible_node(np, NULL, "fixed-clock") {
1645 u32 rate;
1646 if (of_property_read_u32(np, "clock-frequency", &rate))
1647 continue;
1648
1649 if (of_device_is_compatible(np, "fsl,imx-ckil"))
1650 *ckil = rate;
1651 else if (of_device_is_compatible(np, "fsl,imx-osc"))
1652 *osc = rate;
1653 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
1654 *ckih1 = rate;
1655 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
1656 *ckih2 = rate;
1657 }
1658}
1659
1660int __init mx51_clocks_init_dt(void)
1661{
1662 unsigned long ckil, osc, ckih1, ckih2;
1663
1664 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1665 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
1666}
1667
1668int __init mx53_clocks_init_dt(void)
1669{
1670 unsigned long ckil, osc, ckih1, ckih2;
1671
1672 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1673 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
1674}
1675#endif
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
deleted file mode 100644
index 5e2e7a84386..00000000000
--- a/arch/arm/mach-mx5/cpu.c
+++ /dev/null
@@ -1,187 +0,0 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <mach/hardware.h>
19#include <linux/io.h>
20
21static int mx5_cpu_rev = -1;
22
23#define IIM_SREV 0x24
24#define MX50_HW_ADADIG_DIGPROG 0xB0
25
26static int get_mx51_srev(void)
27{
28 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
29 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
30
31 switch (rev) {
32 case 0x0:
33 return IMX_CHIP_REVISION_2_0;
34 case 0x10:
35 return IMX_CHIP_REVISION_3_0;
36 default:
37 return IMX_CHIP_REVISION_UNKNOWN;
38 }
39}
40
41/*
42 * Returns:
43 * the silicon revision of the cpu
44 * -EINVAL - not a mx51
45 */
46int mx51_revision(void)
47{
48 if (!cpu_is_mx51())
49 return -EINVAL;
50
51 if (mx5_cpu_rev == -1)
52 mx5_cpu_rev = get_mx51_srev();
53
54 return mx5_cpu_rev;
55}
56EXPORT_SYMBOL(mx51_revision);
57
58#ifdef CONFIG_NEON
59
60/*
61 * All versions of the silicon before Rev. 3 have broken NEON implementations.
62 * Dependent on link order - so the assumption is that vfp_init is called
63 * before us.
64 */
65static int __init mx51_neon_fixup(void)
66{
67 if (!cpu_is_mx51())
68 return 0;
69
70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
71 (elf_hwcap & HWCAP_NEON)) {
72 elf_hwcap &= ~HWCAP_NEON;
73 pr_info("Turning off NEON support, detected broken NEON implementation\n");
74 }
75 return 0;
76}
77
78late_initcall(mx51_neon_fixup);
79#endif
80
81static int get_mx53_srev(void)
82{
83 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
84 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
85
86 switch (rev) {
87 case 0x0:
88 return IMX_CHIP_REVISION_1_0;
89 case 0x2:
90 return IMX_CHIP_REVISION_2_0;
91 case 0x3:
92 return IMX_CHIP_REVISION_2_1;
93 default:
94 return IMX_CHIP_REVISION_UNKNOWN;
95 }
96}
97
98/*
99 * Returns:
100 * the silicon revision of the cpu
101 * -EINVAL - not a mx53
102 */
103int mx53_revision(void)
104{
105 if (!cpu_is_mx53())
106 return -EINVAL;
107
108 if (mx5_cpu_rev == -1)
109 mx5_cpu_rev = get_mx53_srev();
110
111 return mx5_cpu_rev;
112}
113EXPORT_SYMBOL(mx53_revision);
114
115static int get_mx50_srev(void)
116{
117 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
118 u32 rev;
119
120 if (!anatop) {
121 mx5_cpu_rev = -EINVAL;
122 return 0;
123 }
124
125 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
126 rev &= 0xff;
127
128 iounmap(anatop);
129 if (rev == 0x0)
130 return IMX_CHIP_REVISION_1_0;
131 else if (rev == 0x1)
132 return IMX_CHIP_REVISION_1_1;
133 return 0;
134}
135
136/*
137 * Returns:
138 * the silicon revision of the cpu
139 * -EINVAL - not a mx50
140 */
141int mx50_revision(void)
142{
143 if (!cpu_is_mx50())
144 return -EINVAL;
145
146 if (mx5_cpu_rev == -1)
147 mx5_cpu_rev = get_mx50_srev();
148
149 return mx5_cpu_rev;
150}
151EXPORT_SYMBOL(mx50_revision);
152
153static int __init post_cpu_init(void)
154{
155 unsigned int reg;
156 void __iomem *base;
157
158 if (cpu_is_mx51() || cpu_is_mx53()) {
159 if (cpu_is_mx51())
160 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
161 else
162 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
163
164 __raw_writel(0x0, base + 0x40);
165 __raw_writel(0x0, base + 0x44);
166 __raw_writel(0x0, base + 0x48);
167 __raw_writel(0x0, base + 0x4C);
168 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
169 __raw_writel(reg, base + 0x50);
170
171 if (cpu_is_mx51())
172 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
173 else
174 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
175
176 __raw_writel(0x0, base + 0x40);
177 __raw_writel(0x0, base + 0x44);
178 __raw_writel(0x0, base + 0x48);
179 __raw_writel(0x0, base + 0x4C);
180 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
181 __raw_writel(reg, base + 0x50);
182 }
183
184 return 0;
185}
186
187postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
deleted file mode 100644
index 9d34c3d4c02..00000000000
--- a/arch/arm/mach-mx5/cpu_op-mx51.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/types.h>
15#include <mach/hardware.h>
16#include <linux/kernel.h>
17
18static struct cpu_op mx51_cpu_op[] = {
19 {
20 .cpu_rate = 160000000,},
21 {
22 .cpu_rate = 800000000,},
23};
24
25struct cpu_op *mx51_get_cpu_op(int *op)
26{
27 *op = ARRAY_SIZE(mx51_cpu_op);
28 return mx51_cpu_op;
29}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
deleted file mode 100644
index 97477fecb46..00000000000
--- a/arch/arm/mach-mx5/cpu_op-mx51.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
deleted file mode 100644
index 5e11ba7daee..00000000000
--- a/arch/arm/mach-mx5/crm_regs.h
+++ /dev/null
@@ -1,600 +0,0 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
13
14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20
21/*MX53*/
22#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
23#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
24#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
25#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
26#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
27
28/* PLL Register Offsets */
29#define MXC_PLL_DP_CTL 0x00
30#define MXC_PLL_DP_CONFIG 0x04
31#define MXC_PLL_DP_OP 0x08
32#define MXC_PLL_DP_MFD 0x0C
33#define MXC_PLL_DP_MFN 0x10
34#define MXC_PLL_DP_MFNMINUS 0x14
35#define MXC_PLL_DP_MFNPLUS 0x18
36#define MXC_PLL_DP_HFS_OP 0x1C
37#define MXC_PLL_DP_HFS_MFD 0x20
38#define MXC_PLL_DP_HFS_MFN 0x24
39#define MXC_PLL_DP_MFN_TOGC 0x28
40#define MXC_PLL_DP_DESTAT 0x2c
41
42/* PLL Register Bit definitions */
43#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
44#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
45#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
46#define MXC_PLL_DP_CTL_ADE 0x800
47#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
48#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
49#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
50#define MXC_PLL_DP_CTL_HFSM 0x80
51#define MXC_PLL_DP_CTL_PRE 0x40
52#define MXC_PLL_DP_CTL_UPEN 0x20
53#define MXC_PLL_DP_CTL_RST 0x10
54#define MXC_PLL_DP_CTL_RCP 0x8
55#define MXC_PLL_DP_CTL_PLM 0x4
56#define MXC_PLL_DP_CTL_BRM0 0x2
57#define MXC_PLL_DP_CTL_LRF 0x1
58
59#define MXC_PLL_DP_CONFIG_BIST 0x8
60#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
61#define MXC_PLL_DP_CONFIG_AREN 0x2
62#define MXC_PLL_DP_CONFIG_LDREQ 0x1
63
64#define MXC_PLL_DP_OP_MFI_OFFSET 4
65#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
66#define MXC_PLL_DP_OP_PDF_OFFSET 0
67#define MXC_PLL_DP_OP_PDF_MASK 0xF
68
69#define MXC_PLL_DP_MFD_OFFSET 0
70#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
71
72#define MXC_PLL_DP_MFN_OFFSET 0x0
73#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
74
75#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
76#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
77#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
78#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
79
80#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
81#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
82
83/* Register addresses of CCM*/
84#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
85#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
86#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
87#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
88#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
89#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
90#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
91#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
92#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
93#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
94#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
95#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
96#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
97#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
98#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
99#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
100#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
101#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
102#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
103#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
104#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
105#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
106#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
107#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
108#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
109#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
110#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
111#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
112#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
113#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
114#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
115#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
116#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
117#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
118
119#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
120
121/* Define the bits in register CCR */
122#define MXC_CCM_CCR_COSC_EN (1 << 12)
123#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
124#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
125#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
126#define MXC_CCM_CCR_FPM_EN (1 << 8)
127#define MXC_CCM_CCR_OSCNT_OFFSET (0)
128#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
129
130/* Define the bits in register CCDR */
131#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
132#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
133#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
134
135/* Define the bits in register CSR */
136#define MXC_CCM_CSR_COSR_READY (1 << 5)
137#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
138#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
139#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
140#define MXC_CCM_CSR_FPM_READY (1 << 1)
141#define MXC_CCM_CSR_REF_EN_B (1 << 0)
142
143/* Define the bits in register CCSR */
144#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
145#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
146#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
147#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
148#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
149#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
150#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
151#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
152#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
153#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
154#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
155#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
156 1: step_clk */
157#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
158#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
159
160/* Define the bits in register CACRR */
161#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
162#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
163
164/* Define the bits in register CBCDR */
165#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
166#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
167#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
168#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
169#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
170#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
171#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
172#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
173#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
174#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
175#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
176#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
177#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
178#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
179#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
180#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
181#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
182#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
183#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
184#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
185#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
186#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
187#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
188#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
189
190/* Define the bits in register CBCMR */
191#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
192#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
193#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
194#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
195#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
196#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
197#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
198#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
199#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
200#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
201#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
202#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
203#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
204#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
205#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
206#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
207
208/* Define the bits in register CSCMR1 */
209#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
210#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
211#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
212#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
213#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
214#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
215#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
216#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
217#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
218#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
219#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
220#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
221#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
223#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
224#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
225#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
226#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
227#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
228#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
229#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
230#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
231#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
232#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
233#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
234#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
235#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
236#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
237#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
238#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
239#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
240#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
241#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
242#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
243#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
244
245/* Define the bits in register CSCMR2 */
246#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
247#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
248#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
249#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
250#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
251#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
252#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
253#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
254#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
255#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
256#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
257#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
258#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
259#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
260#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
261#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
262#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
263#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
264#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
265#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
266#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
267#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
268#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
269#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
270#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
271#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
272#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
273
274/* Define the bits in register CSCDR1 */
275#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
276#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
277#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
278#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
279#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
280#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
281#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
282#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
283#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
284#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
285#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
286#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
287#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
288#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
289#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
290#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
291#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
292#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
293#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
294#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
295#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
296#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
297
298/* Define the bits in register CS1CDR and CS2CDR */
299#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
300#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
301#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
302#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
303#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
304#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
305#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
306#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
307
308#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
309#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
310#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
311#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
312#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
313#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
314#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
315#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
316
317/* Define the bits in register CDCDR */
318#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
319#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
320#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
321#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
322#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
323#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
324#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
325#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
326#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
327#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
328#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
329#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
330#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
331#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
332#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
333#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
334
335/* Define the bits in register CHSCCDR */
336#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
337#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
338#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
339#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
340#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
341#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
342#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
343#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
344
345/* Define the bits in register CSCDR2 */
346#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
347#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
348#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
349#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
350#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
351#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
352#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
353#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
354#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
355#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
356#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
357#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
358
359/* Define the bits in register CSCDR3 */
360#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
361#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
362#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
363#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
364#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
365#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
366#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
367#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
368
369/* Define the bits in register CSCDR4 */
370#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
371#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
372#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
373#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
374#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
375#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
376#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
377#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
378
379/* Define the bits in register CDHIPR */
380#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
381#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
382#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
383#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
384#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
385#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
386#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
387#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
388#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
389#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
390
391/* Define the bits in register CDCR */
392#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
393#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
394#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
395
396/* Define the bits in register CLPCR */
397#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
398#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
399#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
400#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
401#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
402#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
403#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
404#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
405#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
406#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
407#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
408#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
409#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
410#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
411#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
412#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
413#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
414#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
415#define MXC_CCM_CLPCR_LPM_OFFSET (0)
416#define MXC_CCM_CLPCR_LPM_MASK (0x3)
417
418/* Define the bits in register CISR */
419#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
420#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
421#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
422#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
423#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
424#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
425#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
426#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
427#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
428#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
429#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
430#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
431#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
432#define MXC_CCM_CISR_LRF_PLL1 (0x1)
433
434/* Define the bits in register CIMR */
435#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
436#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
437#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
438#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
439#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
440#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
441#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
442#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
443#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
444#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
445#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
446#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
447#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
448
449/* Define the bits in register CCOSR */
450#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
451#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
452#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
453#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
454#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
455#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
456#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
457#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
458#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
459#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
460
461/* Define the bits in registers CGPR */
462#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
463#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
464#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
465#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
466
467/* Define the bits in registers CCGRx */
468#define MXC_CCM_CCGRx_CG_MASK 0x3
469#define MXC_CCM_CCGRx_MOD_OFF 0x0
470#define MXC_CCM_CCGRx_MOD_ON 0x3
471#define MXC_CCM_CCGRx_MOD_IDLE 0x1
472
473#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
474#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
475#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
476#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
477#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
478#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
479#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
480#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
481#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
482#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
483#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
484#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
485#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
486#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
487
488#define MXC_CCM_CCGRx_CG15_OFFSET 30
489#define MXC_CCM_CCGRx_CG14_OFFSET 28
490#define MXC_CCM_CCGRx_CG13_OFFSET 26
491#define MXC_CCM_CCGRx_CG12_OFFSET 24
492#define MXC_CCM_CCGRx_CG11_OFFSET 22
493#define MXC_CCM_CCGRx_CG10_OFFSET 20
494#define MXC_CCM_CCGRx_CG9_OFFSET 18
495#define MXC_CCM_CCGRx_CG8_OFFSET 16
496#define MXC_CCM_CCGRx_CG7_OFFSET 14
497#define MXC_CCM_CCGRx_CG6_OFFSET 12
498#define MXC_CCM_CCGRx_CG5_OFFSET 10
499#define MXC_CCM_CCGRx_CG4_OFFSET 8
500#define MXC_CCM_CCGRx_CG3_OFFSET 6
501#define MXC_CCM_CCGRx_CG2_OFFSET 4
502#define MXC_CCM_CCGRx_CG1_OFFSET 2
503#define MXC_CCM_CCGRx_CG0_OFFSET 0
504
505#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
506#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
507#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
508#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
509#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
510#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
511#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
512#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
513#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
514#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
515#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
516#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
517#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
518
519/* CORTEXA8 platform */
520#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
521#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
522#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
523#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
524#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
525#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
526#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
527#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
528#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
529
530/* DVFS CORE */
531#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
532#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
533#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
534#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
535#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
536#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
537#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
538#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
539#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
540#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
541#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
542#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
543#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
544#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
545#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
546#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
547#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
548
549/* GPC */
550#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
551#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
552#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
553#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
554#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
555#define MXC_GPC_PGR_ARMPG_OFFSET 8
556#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
557
558/* PGC */
559#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
560#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
561#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
562#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
563#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
564#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
565
566#define MXC_PGCR_PCR 1
567#define MXC_SRPGCR_PCR 1
568#define MXC_EMPGCR_PCR 1
569#define MXC_PGSR_PSR 1
570
571
572#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
573#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
574
575/* SRPG */
576#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
577#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
578#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
579
580#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
581#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
582#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
583
584#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
585#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
586#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
587
588#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
589#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
590#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
591
592#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
593#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
594#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
595
596#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
597#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
598#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
599
600#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
deleted file mode 100644
index 7216667eaaf..00000000000
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <mach/mx50.h>
22#include <mach/devices-common.h>
23
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
27
28extern const struct imx_fec_data imx50_fec_data;
29#define imx50_add_fec(pdata) \
30 imx_add_fec(&imx50_fec_data, pdata)
31
32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
33#define imx50_add_imx_i2c(id, pdata) \
34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
deleted file mode 100644
index af488bc0e22..00000000000
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx51.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fec_data imx51_fec_data;
13#define imx51_add_fec(pdata) \
14 imx_add_fec(&imx51_fec_data, pdata)
15
16extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
17#define imx51_add_fsl_usb2_udc(pdata) \
18 imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
19
20extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
21#define imx51_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
23#define imx51_add_hsi2c(pdata) \
24 imx51_add_imx_i2c(2, pdata)
25
26extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
27#define imx51_add_imx_ssi(id, pdata) \
28 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
29
30extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
31#define imx51_add_imx_uart(id, pdata) \
32 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
33
34extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
35#define imx51_add_mxc_ehci_otg(pdata) \
36 imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
37extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
38#define imx51_add_mxc_ehci_hs(id, pdata) \
39 imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
40
41extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
42#define imx51_add_mxc_nand(pdata) \
43 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
44
45extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
46#define imx51_add_sdhci_esdhc_imx(id, pdata) \
47 imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
48
49extern const struct imx_spi_imx_data imx51_cspi_data;
50#define imx51_add_cspi(pdata) \
51 imx_add_spi_imx(&imx51_cspi_data, pdata)
52
53extern const struct imx_spi_imx_data imx51_ecspi_data[];
54#define imx51_add_ecspi(id, pdata) \
55 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
56
57extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
58#define imx51_add_imx2_wdt(id, pdata) \
59 imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
60
61extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
62#define imx51_add_mxc_pwm(id) \
63 imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
64
65extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
66#define imx51_add_imx_keypad(pdata) \
67 imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
68
69extern const struct imx_pata_imx_data imx51_pata_imx_data;
70#define imx51_add_pata_imx() \
71 imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
deleted file mode 100644
index 6e1e5d1f8c3..00000000000
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <mach/mx53.h>
9#include <mach/devices-common.h>
10
11extern const struct imx_fec_data imx53_fec_data;
12#define imx53_add_fec(pdata) \
13 imx_add_fec(&imx53_fec_data, pdata)
14
15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
16#define imx53_add_imx_uart(id, pdata) \
17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
18
19
20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
21#define imx53_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
23
24extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
25#define imx53_add_sdhci_esdhc_imx(id, pdata) \
26 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
27
28extern const struct imx_spi_imx_data imx53_ecspi_data[];
29#define imx53_add_ecspi(id, pdata) \
30 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
31
32extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
33#define imx53_add_imx2_wdt(id, pdata) \
34 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
35
36extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
37#define imx53_add_imx_ssi(id, pdata) \
38 imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
39
40extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
41#define imx53_add_imx_keypad(pdata) \
42 imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
43
44extern const struct imx_pata_imx_data imx53_pata_imx_data;
45#define imx53_add_pata_imx() \
46 imx_add_pata_imx(&imx53_pata_imx_data)
47
48extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
deleted file mode 100644
index 014aa985faa..00000000000
--- a/arch/arm/mach-mx5/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
deleted file mode 100644
index c17fa131728..00000000000
--- a/arch/arm/mach-mx5/ehci.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
25
26/* USB_CTRL */
27#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
28#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
29#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
30#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
31#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
32
33/* USB_PHY_CTRL_FUNC */
34#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
35#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
36
37/* USBH2CTRL */
38#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
39#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
40#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
41
42#define MXC_USBCMD_OFFSET 0x140
43
44/* USBCMD */
45#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
46
47int mx51_initialize_usb_hw(int port, unsigned int flags)
48{
49 unsigned int v;
50 void __iomem *usb_base;
51 void __iomem *usbotg_base;
52 void __iomem *usbother_base;
53 int ret = 0;
54
55 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
56 if (!usb_base) {
57 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
58 return -ENOMEM;
59 }
60
61 switch (port) {
62 case 0: /* OTG port */
63 usbotg_base = usb_base + MXC_OTG_OFFSET;
64 break;
65 case 1: /* Host 1 port */
66 usbotg_base = usb_base + MXC_H1_OFFSET;
67 break;
68 case 2: /* Host 2 port */
69 usbotg_base = usb_base + MXC_H2_OFFSET;
70 break;
71 default:
72 printk(KERN_ERR"%s no such port %d\n", __func__, port);
73 ret = -ENOENT;
74 goto error;
75 }
76 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
77
78 switch (port) {
79 case 0: /*OTG port */
80 if (flags & MXC_EHCI_INTERNAL_PHY) {
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
82
83 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
84 /* OC/USBPWR is not used */
85 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
86 } else {
87 /* OC/USBPWR is used */
88 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
89 }
90 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
91
92 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
93 if (flags & MXC_EHCI_WAKEUP_ENABLED)
94 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
95 else
96 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
97 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
98 v |= MXC_OTG_UCTRL_OPM_BIT;
99 else
100 v &= ~MXC_OTG_UCTRL_OPM_BIT;
101 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
102 }
103 break;
104 case 1: /* Host 1 */
105 /*Host ULPI */
106 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
107 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
108 /* HOST1 wakeup/ULPI intr enable */
109 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
110 } else {
111 /* HOST1 wakeup/ULPI intr disable */
112 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
113 }
114
115 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
116 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
117 else
118 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
119 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
120
121 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
122 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
123 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
124 else
125 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
126 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
127
128 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
129 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
130 /* Interrupt Threshold Control:Immediate (no threshold) */
131 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
132 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
133 break;
134 case 2: /* Host 2 ULPI */
135 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
136 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
137 /* HOST1 wakeup/ULPI intr enable */
138 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
139 } else {
140 /* HOST1 wakeup/ULPI intr disable */
141 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
142 }
143
144 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
145 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
146 else
147 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
148 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
149 break;
150 }
151
152error:
153 iounmap(usb_base);
154 return ret;
155}
156
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
deleted file mode 100644
index a6a3ab8f1b1..00000000000
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/serial_8250.h>
16#include <linux/i2c.h>
17#include <linux/gpio.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/i2c/tsc2007.h>
22#include <linux/leds.h>
23
24#include <mach/common.h>
25#include <mach/hardware.h>
26#include <mach/iomux-mx51.h>
27
28#include <asm/mach/arch.h>
29
30#include "devices-imx51.h"
31
32#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
33#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
34#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
35#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
36#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
37
38static const struct gpio_led mbimx51_leds[] __initconst = {
39 {
40 .name = "led0",
41 .default_trigger = "heartbeat",
42 .active_low = 1,
43 .gpio = MBIMX51_LED0,
44 },
45 {
46 .name = "led1",
47 .default_trigger = "nand-disk",
48 .active_low = 1,
49 .gpio = MBIMX51_LED1,
50 },
51 {
52 .name = "led2",
53 .default_trigger = "mmc0",
54 .active_low = 1,
55 .gpio = MBIMX51_LED2,
56 },
57 {
58 .name = "led3",
59 .default_trigger = "default-on",
60 .active_low = 1,
61 .gpio = MBIMX51_LED3,
62 },
63};
64
65static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
66 .leds = mbimx51_leds,
67 .num_leds = ARRAY_SIZE(mbimx51_leds),
68};
69
70static iomux_v3_cfg_t mbimx51_pads[] = {
71 /* UART2 */
72 MX51_PAD_UART2_RXD__UART2_RXD,
73 MX51_PAD_UART2_TXD__UART2_TXD,
74
75 /* UART3 */
76 MX51_PAD_UART3_RXD__UART3_RXD,
77 MX51_PAD_UART3_TXD__UART3_TXD,
78 MX51_PAD_KEY_COL4__UART3_RTS,
79 MX51_PAD_KEY_COL5__UART3_CTS,
80
81 /* TSC2007 IRQ */
82 MX51_PAD_NANDF_D10__GPIO3_30,
83
84 /* LEDS */
85 MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
86 MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
87 MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
88 MX51_PAD_DISPB2_SER_RS__GPIO3_8,
89
90 /* KPP */
91 MX51_PAD_KEY_ROW0__KEY_ROW0,
92 MX51_PAD_KEY_ROW1__KEY_ROW1,
93 MX51_PAD_KEY_ROW2__KEY_ROW2,
94 MX51_PAD_KEY_ROW3__KEY_ROW3,
95 MX51_PAD_KEY_COL0__KEY_COL0,
96 MX51_PAD_KEY_COL1__KEY_COL1,
97 MX51_PAD_KEY_COL2__KEY_COL2,
98 MX51_PAD_KEY_COL3__KEY_COL3,
99
100 /* SD 1 */
101 MX51_PAD_SD1_CMD__SD1_CMD,
102 MX51_PAD_SD1_CLK__SD1_CLK,
103 MX51_PAD_SD1_DATA0__SD1_DATA0,
104 MX51_PAD_SD1_DATA1__SD1_DATA1,
105 MX51_PAD_SD1_DATA2__SD1_DATA2,
106 MX51_PAD_SD1_DATA3__SD1_DATA3,
107
108 /* SD 2 */
109 MX51_PAD_SD2_CMD__SD2_CMD,
110 MX51_PAD_SD2_CLK__SD2_CLK,
111 MX51_PAD_SD2_DATA0__SD2_DATA0,
112 MX51_PAD_SD2_DATA1__SD2_DATA1,
113 MX51_PAD_SD2_DATA2__SD2_DATA2,
114 MX51_PAD_SD2_DATA3__SD2_DATA3,
115};
116
117static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS,
119};
120
121static int mbimx51_keymap[] = {
122 KEY(0, 0, KEY_1),
123 KEY(0, 1, KEY_2),
124 KEY(0, 2, KEY_3),
125 KEY(0, 3, KEY_UP),
126
127 KEY(1, 0, KEY_4),
128 KEY(1, 1, KEY_5),
129 KEY(1, 2, KEY_6),
130 KEY(1, 3, KEY_LEFT),
131
132 KEY(2, 0, KEY_7),
133 KEY(2, 1, KEY_8),
134 KEY(2, 2, KEY_9),
135 KEY(2, 3, KEY_RIGHT),
136
137 KEY(3, 0, KEY_0),
138 KEY(3, 1, KEY_DOWN),
139 KEY(3, 2, KEY_ESC),
140 KEY(3, 3, KEY_ENTER),
141};
142
143static const struct matrix_keymap_data mbimx51_map_data __initconst = {
144 .keymap = mbimx51_keymap,
145 .keymap_size = ARRAY_SIZE(mbimx51_keymap),
146};
147
148static int tsc2007_get_pendown_state(void)
149{
150 return !gpio_get_value(MBIMX51_TSC2007_GPIO);
151}
152
153struct tsc2007_platform_data tsc2007_data = {
154 .model = 2007,
155 .x_plate_ohms = 180,
156 .get_pendown_state = tsc2007_get_pendown_state,
157};
158
159static struct i2c_board_info mbimx51_i2c_devices[] = {
160 {
161 I2C_BOARD_INFO("tsc2007", 0x49),
162 .irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
163 .platform_data = &tsc2007_data,
164 }, {
165 I2C_BOARD_INFO("tlv320aic23", 0x1a),
166 },
167};
168
169/*
170 * baseboard initialization.
171 */
172void __init eukrea_mbimx51_baseboard_init(void)
173{
174 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
175 ARRAY_SIZE(mbimx51_pads));
176
177 imx51_add_imx_uart(1, NULL);
178 imx51_add_imx_uart(2, &uart_pdata);
179
180 gpio_request(MBIMX51_LED0, "LED0");
181 gpio_direction_output(MBIMX51_LED0, 1);
182 gpio_free(MBIMX51_LED0);
183 gpio_request(MBIMX51_LED1, "LED1");
184 gpio_direction_output(MBIMX51_LED1, 1);
185 gpio_free(MBIMX51_LED1);
186 gpio_request(MBIMX51_LED2, "LED2");
187 gpio_direction_output(MBIMX51_LED2, 1);
188 gpio_free(MBIMX51_LED2);
189 gpio_request(MBIMX51_LED3, "LED3");
190 gpio_direction_output(MBIMX51_LED3, 1);
191 gpio_free(MBIMX51_LED3);
192
193 gpio_led_register_device(-1, &mbimx51_leds_info);
194
195 imx51_add_imx_keypad(&mbimx51_map_data);
196
197 gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
198 gpio_direction_input(MBIMX51_TSC2007_GPIO);
199 irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
200 IRQF_TRIGGER_FALLING);
201 i2c_register_board_info(1, mbimx51_i2c_devices,
202 ARRAY_SIZE(mbimx51_i2c_devices));
203
204 imx51_add_sdhci_esdhc_imx(0, NULL);
205 imx51_add_sdhci_esdhc_imx(1, NULL);
206}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
deleted file mode 100644
index d817fc80b98..00000000000
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36
37#include <mach/hardware.h>
38#include <mach/common.h>
39#include <mach/iomux-mx51.h>
40#include <mach/audmux.h>
41
42#include "devices-imx51.h"
43
44static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
45 /* LED */
46 MX51_PAD_NANDF_D10__GPIO3_30,
47 /* SWITCH */
48 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
49 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
50 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
51 /* UART2 */
52 MX51_PAD_UART2_RXD__UART2_RXD,
53 MX51_PAD_UART2_TXD__UART2_TXD,
54 /* UART 3 */
55 MX51_PAD_UART3_RXD__UART3_RXD,
56 MX51_PAD_UART3_TXD__UART3_TXD,
57 MX51_PAD_KEY_COL4__UART3_RTS,
58 MX51_PAD_KEY_COL5__UART3_CTS,
59 /* SD */
60 MX51_PAD_SD1_CMD__SD1_CMD,
61 MX51_PAD_SD1_CLK__SD1_CLK,
62 MX51_PAD_SD1_DATA0__SD1_DATA0,
63 MX51_PAD_SD1_DATA1__SD1_DATA1,
64 MX51_PAD_SD1_DATA2__SD1_DATA2,
65 MX51_PAD_SD1_DATA3__SD1_DATA3,
66 /* SD1 CD */
67 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
68 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
69 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
70};
71
72#define GPIO_LED1 IMX_GPIO_NR(3, 30)
73#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
74
75static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
76 {
77 .name = "led1",
78 .default_trigger = "heartbeat",
79 .active_low = 1,
80 .gpio = GPIO_LED1,
81 },
82};
83
84static const struct gpio_led_platform_data
85 eukrea_mbimxsd_led_info __initconst = {
86 .leds = eukrea_mbimxsd_leds,
87 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
88};
89
90static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
91 {
92 .gpio = GPIO_SWITCH1,
93 .code = BTN_0,
94 .desc = "BP1",
95 .active_low = 1,
96 .wakeup = 1,
97 },
98};
99
100static const struct gpio_keys_platform_data
101 eukrea_mbimxsd_button_data __initconst = {
102 .buttons = eukrea_mbimxsd_gpio_buttons,
103 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
104};
105
106static const struct imxuart_platform_data uart_pdata __initconst = {
107 .flags = IMXUART_HAVE_RTSCTS,
108};
109
110static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
111 {
112 I2C_BOARD_INFO("tlv320aic23", 0x1a),
113 },
114};
115
116/*
117 * system init for baseboard usage. Will be called by cpuimx51sd init.
118 *
119 * Add platform devices present on this baseboard and init
120 * them from CPU side as far as required to use them later on
121 */
122void __init eukrea_mbimxsd51_baseboard_init(void)
123{
124 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
125 ARRAY_SIZE(eukrea_mbimxsd_pads)))
126 printk(KERN_ERR "error setting mbimxsd pads !\n");
127
128 imx51_add_imx_uart(1, NULL);
129 imx51_add_imx_uart(2, &uart_pdata);
130
131 imx51_add_sdhci_esdhc_imx(0, NULL);
132
133 gpio_request(GPIO_LED1, "LED1");
134 gpio_direction_output(GPIO_LED1, 1);
135 gpio_free(GPIO_LED1);
136
137 gpio_request(GPIO_SWITCH1, "SWITCH1");
138 gpio_direction_input(GPIO_SWITCH1);
139 gpio_free(GPIO_SWITCH1);
140
141 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
142 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
143
144 gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
145 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
146}
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
deleted file mode 100644
index e6bad17b908..00000000000
--- a/arch/arm/mach-mx5/imx51-dt.c
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
19#include <mach/common.h>
20#include <mach/mx51.h>
21
22/*
23 * Lookup table for attaching a specific name and platform_data pointer to
24 * devices as they get created by of_platform_populate(). Ideally this table
25 * would not exist, but the current clock implementation depends on some devices
26 * having a specific name.
27 */
28static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
29 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
30 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
31 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
32 OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
33 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
34 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
35 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
36 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
37 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
38 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
39 OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
40 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
43 OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
44 { /* sentinel */ }
45};
46
47static int __init imx51_tzic_add_irq_domain(struct device_node *np,
48 struct device_node *interrupt_parent)
49{
50 irq_domain_add_simple(np, 0);
51 return 0;
52}
53
54static int __init imx51_gpio_add_irq_domain(struct device_node *np,
55 struct device_node *interrupt_parent)
56{
57 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
58
59 gpio_irq_base -= 32;
60 irq_domain_add_simple(np, gpio_irq_base);
61
62 return 0;
63}
64
65static const struct of_device_id imx51_irq_match[] __initconst = {
66 { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
67 { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
68 { /* sentinel */ }
69};
70
71static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
72 { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
73 { /* sentinel */ }
74};
75
76static void __init imx51_dt_init(void)
77{
78 struct device_node *node;
79 const struct of_device_id *of_id;
80 void (*func)(void);
81
82 of_irq_init(imx51_irq_match);
83
84 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
85 if (node) {
86 of_id = of_match_node(imx51_iomuxc_of_match, node);
87 func = of_id->data;
88 func();
89 of_node_put(node);
90 }
91
92 of_platform_populate(NULL, of_default_bus_match_table,
93 imx51_auxdata_lookup, NULL);
94}
95
96static void __init imx51_timer_init(void)
97{
98 mx51_clocks_init_dt();
99}
100
101static struct sys_timer imx51_timer = {
102 .init = imx51_timer_init,
103};
104
105static const char *imx51_dt_board_compat[] __initdata = {
106 "fsl,imx51-babbage",
107 NULL
108};
109
110DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
111 .map_io = mx51_map_io,
112 .init_early = imx51_init_early,
113 .init_irq = mx51_init_irq,
114 .handle_irq = imx51_handle_irq,
115 .timer = &imx51_timer,
116 .init_machine = imx51_dt_init,
117 .dt_compat = imx51_dt_board_compat,
118 .restart = mxc_restart,
119MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
deleted file mode 100644
index 05ebb3e6867..00000000000
--- a/arch/arm/mach-mx5/imx53-dt.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20#include <mach/common.h>
21#include <mach/mx53.h>
22
23/*
24 * Lookup table for attaching a specific name and platform_data pointer to
25 * devices as they get created by of_platform_populate(). Ideally this table
26 * would not exist, but the current clock implementation depends on some devices
27 * having a specific name.
28 */
29static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
30 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
31 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
32 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
33 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
34 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
35 OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
36 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
37 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
38 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
39 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
40 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
43 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
44 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
45 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
46 OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
47 OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
48 { /* sentinel */ }
49};
50
51static int __init imx53_tzic_add_irq_domain(struct device_node *np,
52 struct device_node *interrupt_parent)
53{
54 irq_domain_add_simple(np, 0);
55 return 0;
56}
57
58static int __init imx53_gpio_add_irq_domain(struct device_node *np,
59 struct device_node *interrupt_parent)
60{
61 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
62
63 gpio_irq_base -= 32;
64 irq_domain_add_simple(np, gpio_irq_base);
65
66 return 0;
67}
68
69static const struct of_device_id imx53_irq_match[] __initconst = {
70 { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
71 { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
72 { /* sentinel */ }
73};
74
75static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
76 { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
77 { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
78 { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
79 { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
80 { /* sentinel */ }
81};
82
83static void __init imx53_dt_init(void)
84{
85 struct device_node *node;
86 const struct of_device_id *of_id;
87 void (*func)(void);
88
89 of_irq_init(imx53_irq_match);
90
91 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
92 if (node) {
93 of_id = of_match_node(imx53_iomuxc_of_match, node);
94 func = of_id->data;
95 func();
96 of_node_put(node);
97 }
98
99 of_platform_populate(NULL, of_default_bus_match_table,
100 imx53_auxdata_lookup, NULL);
101}
102
103static void __init imx53_timer_init(void)
104{
105 mx53_clocks_init_dt();
106}
107
108static struct sys_timer imx53_timer = {
109 .init = imx53_timer_init,
110};
111
112static const char *imx53_dt_board_compat[] __initdata = {
113 "fsl,imx53-ard",
114 "fsl,imx53-evk",
115 "fsl,imx53-qsb",
116 "fsl,imx53-smd",
117 NULL
118};
119
120DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
121 .map_io = mx53_map_io,
122 .init_early = imx53_init_early,
123 .init_irq = mx53_init_irq,
124 .handle_irq = imx53_handle_irq,
125 .timer = &imx53_timer,
126 .init_machine = imx53_dt_init,
127 .dt_compat = imx53_dt_board_compat,
128 .restart = mxc_restart,
129MACHINE_END
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
deleted file mode 100644
index bc17dfea381..00000000000
--- a/arch/arm/mach-mx5/mm.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16#include <linux/clk.h>
17
18#include <asm/mach/map.h>
19
20#include <mach/hardware.h>
21#include <mach/common.h>
22#include <mach/devices-common.h>
23#include <mach/iomux-v3.h>
24
25static struct clk *gpc_dvfs_clk;
26
27static void imx5_idle(void)
28{
29 if (!need_resched()) {
30 /* gpc clock is needed for SRPG */
31 if (gpc_dvfs_clk == NULL) {
32 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
33 if (IS_ERR(gpc_dvfs_clk))
34 goto err0;
35 }
36 clk_enable(gpc_dvfs_clk);
37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
38 if (tzic_enable_wake())
39 goto err1;
40 cpu_do_idle();
41err1:
42 clk_disable(gpc_dvfs_clk);
43 }
44err0:
45 local_irq_enable();
46}
47
48/*
49 * Define the MX50 memory map.
50 */
51static struct map_desc mx50_io_desc[] __initdata = {
52 imx_map_entry(MX50, TZIC, MT_DEVICE),
53 imx_map_entry(MX50, SPBA0, MT_DEVICE),
54 imx_map_entry(MX50, AIPS1, MT_DEVICE),
55 imx_map_entry(MX50, AIPS2, MT_DEVICE),
56};
57
58/*
59 * Define the MX51 memory map.
60 */
61static struct map_desc mx51_io_desc[] __initdata = {
62 imx_map_entry(MX51, TZIC, MT_DEVICE),
63 imx_map_entry(MX51, IRAM, MT_DEVICE),
64 imx_map_entry(MX51, AIPS1, MT_DEVICE),
65 imx_map_entry(MX51, SPBA0, MT_DEVICE),
66 imx_map_entry(MX51, AIPS2, MT_DEVICE),
67};
68
69/*
70 * Define the MX53 memory map.
71 */
72static struct map_desc mx53_io_desc[] __initdata = {
73 imx_map_entry(MX53, TZIC, MT_DEVICE),
74 imx_map_entry(MX53, AIPS1, MT_DEVICE),
75 imx_map_entry(MX53, SPBA0, MT_DEVICE),
76 imx_map_entry(MX53, AIPS2, MT_DEVICE),
77};
78
79/*
80 * This function initializes the memory map. It is called during the
81 * system startup to create static physical to virtual memory mappings
82 * for the IO modules.
83 */
84void __init mx50_map_io(void)
85{
86 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
87}
88
89void __init mx51_map_io(void)
90{
91 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
92}
93
94void __init mx53_map_io(void)
95{
96 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
97}
98
99void __init imx50_init_early(void)
100{
101 mxc_set_cpu_type(MXC_CPU_MX50);
102 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
103 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
104}
105
106void __init imx51_init_early(void)
107{
108 mxc_set_cpu_type(MXC_CPU_MX51);
109 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
110 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
111 pm_idle = imx5_idle;
112}
113
114void __init imx53_init_early(void)
115{
116 mxc_set_cpu_type(MXC_CPU_MX53);
117 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
118 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
119}
120
121void __init mx50_init_irq(void)
122{
123 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
124}
125
126void __init mx51_init_irq(void)
127{
128 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
129}
130
131void __init mx53_init_irq(void)
132{
133 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
134}
135
136static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
137 .ap_2_ap_addr = 642,
138 .uart_2_mcu_addr = 817,
139 .mcu_2_app_addr = 747,
140 .mcu_2_shp_addr = 961,
141 .ata_2_mcu_addr = 1473,
142 .mcu_2_ata_addr = 1392,
143 .app_2_per_addr = 1033,
144 .app_2_mcu_addr = 683,
145 .shp_2_per_addr = 1251,
146 .shp_2_mcu_addr = 892,
147};
148
149static struct sdma_platform_data imx51_sdma_pdata __initdata = {
150 .fw_name = "sdma-imx51.bin",
151 .script_addrs = &imx51_sdma_script,
152};
153
154static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
155 .ap_2_ap_addr = 642,
156 .app_2_mcu_addr = 683,
157 .mcu_2_app_addr = 747,
158 .uart_2_mcu_addr = 817,
159 .shp_2_mcu_addr = 891,
160 .mcu_2_shp_addr = 960,
161 .uartsh_2_mcu_addr = 1032,
162 .spdif_2_mcu_addr = 1100,
163 .mcu_2_spdif_addr = 1134,
164 .firi_2_mcu_addr = 1193,
165 .mcu_2_firi_addr = 1290,
166};
167
168static struct sdma_platform_data imx53_sdma_pdata __initdata = {
169 .fw_name = "sdma-imx53.bin",
170 .script_addrs = &imx53_sdma_script,
171};
172
173void __init imx50_soc_init(void)
174{
175 /* i.mx50 has the i.mx31 type gpio */
176 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
177 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
178 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
179 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
180 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
181 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
182}
183
184void __init imx51_soc_init(void)
185{
186 /* i.mx51 has the i.mx31 type gpio */
187 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
188 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
189 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
190 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
191
192 /* i.mx51 has the i.mx35 type sdma */
193 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
194}
195
196void __init imx53_soc_init(void)
197{
198 /* i.mx53 has the i.mx31 type gpio */
199 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
200 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
201 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
202 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
203 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
204 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
205 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
206
207 /* i.mx53 has the i.mx35 type sdma */
208 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
209}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
deleted file mode 100644
index ec6ca91b299..00000000000
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ /dev/null
@@ -1,632 +0,0 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
25#include <linux/mfd/mc13892.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/consumer.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <mach/ulpi.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41
42#include "devices-imx51.h"
43#include "efika.h"
44#include "cpu_op-mx51.h"
45
46#define MX51_USB_CTRL_1_OFFSET 0x10
47#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
49
50#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
51#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
52
53#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
54#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
55
56#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
57
58static iomux_v3_cfg_t mx51efika_pads[] = {
59 /* UART1 */
60 MX51_PAD_UART1_RXD__UART1_RXD,
61 MX51_PAD_UART1_TXD__UART1_TXD,
62 MX51_PAD_UART1_RTS__UART1_RTS,
63 MX51_PAD_UART1_CTS__UART1_CTS,
64
65 /* SD 1 */
66 MX51_PAD_SD1_CMD__SD1_CMD,
67 MX51_PAD_SD1_CLK__SD1_CLK,
68 MX51_PAD_SD1_DATA0__SD1_DATA0,
69 MX51_PAD_SD1_DATA1__SD1_DATA1,
70 MX51_PAD_SD1_DATA2__SD1_DATA2,
71 MX51_PAD_SD1_DATA3__SD1_DATA3,
72
73 /* SD 2 */
74 MX51_PAD_SD2_CMD__SD2_CMD,
75 MX51_PAD_SD2_CLK__SD2_CLK,
76 MX51_PAD_SD2_DATA0__SD2_DATA0,
77 MX51_PAD_SD2_DATA1__SD2_DATA1,
78 MX51_PAD_SD2_DATA2__SD2_DATA2,
79 MX51_PAD_SD2_DATA3__SD2_DATA3,
80
81 /* SD/MMC WP/CD */
82 MX51_PAD_GPIO1_0__SD1_CD,
83 MX51_PAD_GPIO1_1__SD1_WP,
84 MX51_PAD_GPIO1_7__SD2_WP,
85 MX51_PAD_GPIO1_8__SD2_CD,
86
87 /* spi */
88 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
89 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
90 MX51_PAD_CSPI1_SS0__GPIO4_24,
91 MX51_PAD_CSPI1_SS1__GPIO4_25,
92 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
93 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
94 MX51_PAD_GPIO1_6__GPIO1_6,
95
96 /* USB HOST1 */
97 MX51_PAD_USBH1_CLK__USBH1_CLK,
98 MX51_PAD_USBH1_DIR__USBH1_DIR,
99 MX51_PAD_USBH1_NXT__USBH1_NXT,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
108
109 /* USB HUB RESET */
110 MX51_PAD_GPIO1_5__GPIO1_5,
111
112 /* WLAN */
113 MX51_PAD_EIM_A22__GPIO2_16,
114 MX51_PAD_EIM_A16__GPIO2_10,
115
116 /* USB PHY RESET */
117 MX51_PAD_EIM_D27__GPIO2_9,
118};
119
120/* Serial ports */
121static const struct imxuart_platform_data uart_pdata = {
122 .flags = IMXUART_HAVE_RTSCTS,
123};
124
125/* This function is board specific as the bit mask for the plldiv will also
126 * be different for other Freescale SoCs, thus a common bitmask is not
127 * possible and cannot get place in /plat-mxc/ehci.c.
128 */
129static int initialize_otg_port(struct platform_device *pdev)
130{
131 u32 v;
132 void __iomem *usb_base;
133 void __iomem *usbother_base;
134 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
135 if (!usb_base)
136 return -ENOMEM;
137 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
138
139 /* Set the PHY clock to 19.2MHz */
140 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
141 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
142 v |= MX51_USB_PLL_DIV_19_2_MHZ;
143 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
144 iounmap(usb_base);
145
146 mdelay(10);
147
148 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
149}
150
151static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
152 .init = initialize_otg_port,
153 .portsc = MXC_EHCI_UTMI_16BIT,
154};
155
156static int initialize_usbh1_port(struct platform_device *pdev)
157{
158 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
159 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
160 u32 v;
161 void __iomem *usb_base;
162 void __iomem *socregs_base;
163
164 mxc_iomux_v3_setup_pad(usbh1gpio);
165 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
166 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
167 msleep(1);
168 gpio_set_value(EFIKAMX_USBH1_STP, 1);
169 msleep(1);
170
171 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
172 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
173
174 /* The clock for the USBH1 ULPI port will come externally */
175 /* from the PHY. */
176 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
177 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
178 socregs_base + MX51_USB_CTRL_1_OFFSET);
179
180 iounmap(usb_base);
181
182 gpio_free(EFIKAMX_USBH1_STP);
183 mxc_iomux_v3_setup_pad(usbh1stp);
184
185 mdelay(10);
186
187 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
188}
189
190static struct mxc_usbh_platform_data usbh1_config __initdata = {
191 .init = initialize_usbh1_port,
192 .portsc = MXC_EHCI_MODE_ULPI,
193};
194
195static void mx51_efika_hubreset(void)
196{
197 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
198 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
199 msleep(1);
200 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
201 msleep(1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
203}
204
205static void __init mx51_efika_usb(void)
206{
207 mx51_efika_hubreset();
208
209 /* pulling it low, means no USB at all... */
210 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
211 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
212 msleep(1);
213 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
214
215 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
216 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
217
218 imx51_add_mxc_ehci_otg(&dr_utmi_config);
219 if (usbh1_config.otg)
220 imx51_add_mxc_ehci_hs(1, &usbh1_config);
221}
222
223static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
224 {
225 .name = "u-boot",
226 .offset = 0,
227 .size = SZ_256K,
228 },
229 {
230 .name = "config",
231 .offset = MTDPART_OFS_APPEND,
232 .size = SZ_64K,
233 },
234};
235
236static struct flash_platform_data mx51_efika_spi_flash_data = {
237 .name = "spi_flash",
238 .parts = mx51_efika_spi_nor_partitions,
239 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
240 .type = "sst25vf032b",
241};
242
243static struct regulator_consumer_supply sw1_consumers[] = {
244 {
245 .supply = "cpu_vcc",
246 }
247};
248
249static struct regulator_consumer_supply vdig_consumers[] = {
250 /* sgtl5000 */
251 REGULATOR_SUPPLY("VDDA", "1-000a"),
252 REGULATOR_SUPPLY("VDDD", "1-000a"),
253};
254
255static struct regulator_consumer_supply vvideo_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDIO", "1-000a"),
258};
259
260static struct regulator_consumer_supply vsd_consumers[] = {
261 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
262 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
263};
264
265static struct regulator_consumer_supply pwgt1_consumer[] = {
266 {
267 .supply = "pwgt1",
268 }
269};
270
271static struct regulator_consumer_supply pwgt2_consumer[] = {
272 {
273 .supply = "pwgt2",
274 }
275};
276
277static struct regulator_consumer_supply coincell_consumer[] = {
278 {
279 .supply = "coincell",
280 }
281};
282
283static struct regulator_init_data sw1_init = {
284 .constraints = {
285 .name = "SW1",
286 .min_uV = 600000,
287 .max_uV = 1375000,
288 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
289 .valid_modes_mask = 0,
290 .always_on = 1,
291 .boot_on = 1,
292 .state_mem = {
293 .uV = 850000,
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 1,
296 },
297 },
298 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
299 .consumer_supplies = sw1_consumers,
300};
301
302static struct regulator_init_data sw2_init = {
303 .constraints = {
304 .name = "SW2",
305 .min_uV = 900000,
306 .max_uV = 1850000,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
308 .always_on = 1,
309 .boot_on = 1,
310 .state_mem = {
311 .uV = 950000,
312 .mode = REGULATOR_MODE_NORMAL,
313 .enabled = 1,
314 },
315 }
316};
317
318static struct regulator_init_data sw3_init = {
319 .constraints = {
320 .name = "SW3",
321 .min_uV = 1100000,
322 .max_uV = 1850000,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
324 .always_on = 1,
325 .boot_on = 1,
326 }
327};
328
329static struct regulator_init_data sw4_init = {
330 .constraints = {
331 .name = "SW4",
332 .min_uV = 1100000,
333 .max_uV = 1850000,
334 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
335 .always_on = 1,
336 .boot_on = 1,
337 }
338};
339
340static struct regulator_init_data viohi_init = {
341 .constraints = {
342 .name = "VIOHI",
343 .boot_on = 1,
344 .always_on = 1,
345 }
346};
347
348static struct regulator_init_data vusb_init = {
349 .constraints = {
350 .name = "VUSB",
351 .boot_on = 1,
352 .always_on = 1,
353 }
354};
355
356static struct regulator_init_data swbst_init = {
357 .constraints = {
358 .name = "SWBST",
359 }
360};
361
362static struct regulator_init_data vdig_init = {
363 .constraints = {
364 .name = "VDIG",
365 .min_uV = 1050000,
366 .max_uV = 1800000,
367 .valid_ops_mask =
368 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
369 .boot_on = 1,
370 .always_on = 1,
371 },
372 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
373 .consumer_supplies = vdig_consumers,
374};
375
376static struct regulator_init_data vpll_init = {
377 .constraints = {
378 .name = "VPLL",
379 .min_uV = 1050000,
380 .max_uV = 1800000,
381 .valid_ops_mask =
382 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
383 .boot_on = 1,
384 .always_on = 1,
385 }
386};
387
388static struct regulator_init_data vusb2_init = {
389 .constraints = {
390 .name = "VUSB2",
391 .min_uV = 2400000,
392 .max_uV = 2775000,
393 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
394 .boot_on = 1,
395 .always_on = 1,
396 }
397};
398
399static struct regulator_init_data vvideo_init = {
400 .constraints = {
401 .name = "VVIDEO",
402 .min_uV = 2775000,
403 .max_uV = 2775000,
404 .valid_ops_mask =
405 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
406 .boot_on = 1,
407 .apply_uV = 1,
408 },
409 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
410 .consumer_supplies = vvideo_consumers,
411};
412
413static struct regulator_init_data vaudio_init = {
414 .constraints = {
415 .name = "VAUDIO",
416 .min_uV = 2300000,
417 .max_uV = 3000000,
418 .valid_ops_mask =
419 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
420 .boot_on = 1,
421 }
422};
423
424static struct regulator_init_data vsd_init = {
425 .constraints = {
426 .name = "VSD",
427 .min_uV = 1800000,
428 .max_uV = 3150000,
429 .valid_ops_mask =
430 REGULATOR_CHANGE_VOLTAGE,
431 .boot_on = 1,
432 },
433 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
434 .consumer_supplies = vsd_consumers,
435};
436
437static struct regulator_init_data vcam_init = {
438 .constraints = {
439 .name = "VCAM",
440 .min_uV = 2500000,
441 .max_uV = 3000000,
442 .valid_ops_mask =
443 REGULATOR_CHANGE_VOLTAGE |
444 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
445 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
446 .boot_on = 1,
447 }
448};
449
450static struct regulator_init_data vgen1_init = {
451 .constraints = {
452 .name = "VGEN1",
453 .min_uV = 1200000,
454 .max_uV = 3150000,
455 .valid_ops_mask =
456 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
457 .boot_on = 1,
458 .always_on = 1,
459 }
460};
461
462static struct regulator_init_data vgen2_init = {
463 .constraints = {
464 .name = "VGEN2",
465 .min_uV = 1200000,
466 .max_uV = 3150000,
467 .valid_ops_mask =
468 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
469 .boot_on = 1,
470 .always_on = 1,
471 }
472};
473
474static struct regulator_init_data vgen3_init = {
475 .constraints = {
476 .name = "VGEN3",
477 .min_uV = 1800000,
478 .max_uV = 2900000,
479 .valid_ops_mask =
480 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
481 .boot_on = 1,
482 .always_on = 1,
483 }
484};
485
486static struct regulator_init_data gpo1_init = {
487 .constraints = {
488 .name = "GPO1",
489 }
490};
491
492static struct regulator_init_data gpo2_init = {
493 .constraints = {
494 .name = "GPO2",
495 }
496};
497
498static struct regulator_init_data gpo3_init = {
499 .constraints = {
500 .name = "GPO3",
501 }
502};
503
504static struct regulator_init_data gpo4_init = {
505 .constraints = {
506 .name = "GPO4",
507 }
508};
509
510static struct regulator_init_data pwgt1_init = {
511 .constraints = {
512 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
513 .boot_on = 1,
514 },
515 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
516 .consumer_supplies = pwgt1_consumer,
517};
518
519static struct regulator_init_data pwgt2_init = {
520 .constraints = {
521 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
522 .boot_on = 1,
523 },
524 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
525 .consumer_supplies = pwgt2_consumer,
526};
527
528static struct regulator_init_data vcoincell_init = {
529 .constraints = {
530 .name = "COINCELL",
531 .min_uV = 3000000,
532 .max_uV = 3000000,
533 .valid_ops_mask =
534 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
535 },
536 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
537 .consumer_supplies = coincell_consumer,
538};
539
540static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
541 { .id = MC13892_SW1, .init_data = &sw1_init },
542 { .id = MC13892_SW2, .init_data = &sw2_init },
543 { .id = MC13892_SW3, .init_data = &sw3_init },
544 { .id = MC13892_SW4, .init_data = &sw4_init },
545 { .id = MC13892_SWBST, .init_data = &swbst_init },
546 { .id = MC13892_VIOHI, .init_data = &viohi_init },
547 { .id = MC13892_VPLL, .init_data = &vpll_init },
548 { .id = MC13892_VDIG, .init_data = &vdig_init },
549 { .id = MC13892_VSD, .init_data = &vsd_init },
550 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
551 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
552 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
553 { .id = MC13892_VCAM, .init_data = &vcam_init },
554 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
555 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
556 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
557 { .id = MC13892_VUSB, .init_data = &vusb_init },
558 { .id = MC13892_GPO1, .init_data = &gpo1_init },
559 { .id = MC13892_GPO2, .init_data = &gpo2_init },
560 { .id = MC13892_GPO3, .init_data = &gpo3_init },
561 { .id = MC13892_GPO4, .init_data = &gpo4_init },
562 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
563 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
564 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
565};
566
567static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
568 .flags = MC13XXX_USE_RTC,
569 .regulators = {
570 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
571 .regulators = mx51_efika_regulators,
572 },
573};
574
575static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
576 {
577 .modalias = "m25p80",
578 .max_speed_hz = 25000000,
579 .bus_num = 0,
580 .chip_select = 1,
581 .platform_data = &mx51_efika_spi_flash_data,
582 .irq = -1,
583 },
584 {
585 .modalias = "mc13892",
586 .max_speed_hz = 1000000,
587 .bus_num = 0,
588 .chip_select = 0,
589 .platform_data = &mx51_efika_mc13892_data,
590 .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
591 },
592};
593
594static int mx51_efika_spi_cs[] = {
595 EFIKAMX_SPI_CS0,
596 EFIKAMX_SPI_CS1,
597};
598
599static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
600 .chipselect = mx51_efika_spi_cs,
601 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
602};
603
604void __init efika_board_common_init(void)
605{
606 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
607 ARRAY_SIZE(mx51efika_pads));
608 imx51_add_imx_uart(0, &uart_pdata);
609 mx51_efika_usb();
610
611 /* FIXME: comes from original code. check this. */
612 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
613 sw2_init.constraints.state_mem.uV = 1100000;
614 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
615 sw2_init.constraints.state_mem.uV = 1250000;
616 sw1_init.constraints.state_mem.uV = 1000000;
617 }
618 if (machine_is_mx51_efikasb())
619 vgen1_init.constraints.max_uV = 1200000;
620
621 gpio_request(EFIKAMX_PMIC, "pmic irq");
622 gpio_direction_input(EFIKAMX_PMIC);
623 spi_register_board_info(mx51_efika_spi_board_info,
624 ARRAY_SIZE(mx51_efika_spi_board_info));
625 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
626
627 imx51_add_pata_imx();
628
629#if defined(CONFIG_CPU_FREQ_IMX)
630 get_cpu_op = mx51_get_cpu_op;
631#endif
632}
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
deleted file mode 100644
index 98052fc852c..00000000000
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include <linux/suspend.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <asm/cacheflush.h>
16#include <asm/tlbflush.h>
17#include <mach/common.h>
18#include <mach/hardware.h>
19#include "crm_regs.h"
20
21static struct clk *gpc_dvfs_clk;
22
23static int mx5_suspend_prepare(void)
24{
25 return clk_enable(gpc_dvfs_clk);
26}
27
28static int mx5_suspend_enter(suspend_state_t state)
29{
30 switch (state) {
31 case PM_SUSPEND_MEM:
32 mx5_cpu_lp_set(STOP_POWER_OFF);
33 break;
34 case PM_SUSPEND_STANDBY:
35 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
36 break;
37 default:
38 return -EINVAL;
39 }
40
41 if (state == PM_SUSPEND_MEM) {
42 local_flush_tlb_all();
43 flush_cache_all();
44
45 /*clear the EMPGC0/1 bits */
46 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
47 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
48 }
49 cpu_do_idle();
50 return 0;
51}
52
53static void mx5_suspend_finish(void)
54{
55 clk_disable(gpc_dvfs_clk);
56}
57
58static int mx5_pm_valid(suspend_state_t state)
59{
60 return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
61}
62
63static const struct platform_suspend_ops mx5_suspend_ops = {
64 .valid = mx5_pm_valid,
65 .prepare = mx5_suspend_prepare,
66 .enter = mx5_suspend_enter,
67 .finish = mx5_suspend_finish,
68};
69
70static int __init mx5_pm_init(void)
71{
72 if (gpc_dvfs_clk == NULL)
73 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
74
75 if (!IS_ERR(gpc_dvfs_clk)) {
76 if (cpu_is_mx51())
77 suspend_set_ops(&mx5_suspend_ops);
78 } else
79 return -EPERM;
80
81 return 0;
82}
83device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
deleted file mode 100644
index 5eebfaad122..00000000000
--- a/arch/arm/mach-mx5/system.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <mach/hardware.h>
16#include <mach/common.h>
17#include "crm_regs.h"
18
19/* set cpu low power mode before WFI instruction. This function is called
20 * mx5 because it can be used for mx50, mx51, and mx53.*/
21void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
22{
23 u32 plat_lpc, arm_srpgcr, ccm_clpcr;
24 u32 empgc0, empgc1;
25 int stop_mode = 0;
26
27 /* always allow platform to issue a deep sleep mode request */
28 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
29 ~(MXC_CORTEXA8_PLAT_LPC_DSM);
30 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
31 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
32 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
33 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
34
35 switch (mode) {
36 case WAIT_CLOCKED:
37 break;
38 case WAIT_UNCLOCKED:
39 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
40 break;
41 case WAIT_UNCLOCKED_POWER_OFF:
42 case STOP_POWER_OFF:
43 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
44 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
45 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
46 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
47 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
48 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
49 stop_mode = 0;
50 } else {
51 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
52 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
53 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
54 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
55 stop_mode = 1;
56 }
57 arm_srpgcr |= MXC_SRPGCR_PCR;
58 break;
59 case STOP_POWER_ON:
60 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
61 break;
62 default:
63 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
64 return;
65 }
66
67 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
68 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
69 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
70
71 /* Enable NEON SRPG for all but MX50TO1.0. */
72 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
73 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
74
75 if (stop_mode) {
76 empgc0 |= MXC_SRPGCR_PCR;
77 empgc1 |= MXC_SRPGCR_PCR;
78
79 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
80 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
81 }
82}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 06:36:08 -0400