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-rw-r--r--arch/arm/mach-mx5/mx51_efika.c636
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diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 00000000000..51a67fc7f0e
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+++ b/arch/arm/mach-mx5/mx51_efika.c
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1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24#include <linux/spi/flash.h>
25#include <linux/spi/spi.h>
26#include <linux/mfd/mc13892.h>
27#include <linux/regulator/machine.h>
28#include <linux/regulator/consumer.h>
29
30#include <mach/common.h>
31#include <mach/hardware.h>
32#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h>
35
36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38#include <mach/ulpi.h>
39
40#include <asm/irq.h>
41#include <asm/setup.h>
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/time.h>
45#include <asm/mach-types.h>
46
47#include "devices-imx51.h"
48#include "devices.h"
49#include "efika.h"
50#include "cpu_op-mx51.h"
51
52#define MX51_USB_CTRL_1_OFFSET 0x10
53#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
54#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55
56#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
57#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
58
59#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
60#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
61
62#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
63
64static iomux_v3_cfg_t mx51efika_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* SD 1 */
72 MX51_PAD_SD1_CMD__SD1_CMD,
73 MX51_PAD_SD1_CLK__SD1_CLK,
74 MX51_PAD_SD1_DATA0__SD1_DATA0,
75 MX51_PAD_SD1_DATA1__SD1_DATA1,
76 MX51_PAD_SD1_DATA2__SD1_DATA2,
77 MX51_PAD_SD1_DATA3__SD1_DATA3,
78
79 /* SD 2 */
80 MX51_PAD_SD2_CMD__SD2_CMD,
81 MX51_PAD_SD2_CLK__SD2_CLK,
82 MX51_PAD_SD2_DATA0__SD2_DATA0,
83 MX51_PAD_SD2_DATA1__SD2_DATA1,
84 MX51_PAD_SD2_DATA2__SD2_DATA2,
85 MX51_PAD_SD2_DATA3__SD2_DATA3,
86
87 /* SD/MMC WP/CD */
88 MX51_PAD_GPIO1_0__SD1_CD,
89 MX51_PAD_GPIO1_1__SD1_WP,
90 MX51_PAD_GPIO1_7__SD2_WP,
91 MX51_PAD_GPIO1_8__SD2_CD,
92
93 /* spi */
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
96 MX51_PAD_CSPI1_SS0__GPIO4_24,
97 MX51_PAD_CSPI1_SS1__GPIO4_25,
98 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
99 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
100 MX51_PAD_GPIO1_6__GPIO1_6,
101
102 /* USB HOST1 */
103 MX51_PAD_USBH1_CLK__USBH1_CLK,
104 MX51_PAD_USBH1_DIR__USBH1_DIR,
105 MX51_PAD_USBH1_NXT__USBH1_NXT,
106 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
107 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
108 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
109 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
110 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
111 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
112 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
113 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
114
115 /* USB HUB RESET */
116 MX51_PAD_GPIO1_5__GPIO1_5,
117
118 /* WLAN */
119 MX51_PAD_EIM_A22__GPIO2_16,
120 MX51_PAD_EIM_A16__GPIO2_10,
121
122 /* USB PHY RESET */
123 MX51_PAD_EIM_D27__GPIO2_9,
124};
125
126/* Serial ports */
127static const struct imxuart_platform_data uart_pdata = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131/* This function is board specific as the bit mask for the plldiv will also
132 * be different for other Freescale SoCs, thus a common bitmask is not
133 * possible and cannot get place in /plat-mxc/ehci.c.
134 */
135static int initialize_otg_port(struct platform_device *pdev)
136{
137 u32 v;
138 void __iomem *usb_base;
139 void __iomem *usbother_base;
140 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
141 if (!usb_base)
142 return -ENOMEM;
143 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
144
145 /* Set the PHY clock to 19.2MHz */
146 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
147 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
148 v |= MX51_USB_PLL_DIV_19_2_MHZ;
149 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
150 iounmap(usb_base);
151
152 mdelay(10);
153
154 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
155}
156
157static struct mxc_usbh_platform_data dr_utmi_config = {
158 .init = initialize_otg_port,
159 .portsc = MXC_EHCI_UTMI_16BIT,
160};
161
162static int initialize_usbh1_port(struct platform_device *pdev)
163{
164 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
165 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
166 u32 v;
167 void __iomem *usb_base;
168 void __iomem *socregs_base;
169
170 mxc_iomux_v3_setup_pad(usbh1gpio);
171 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
172 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
173 msleep(1);
174 gpio_set_value(EFIKAMX_USBH1_STP, 1);
175 msleep(1);
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
179
180 /* The clock for the USBH1 ULPI port will come externally */
181 /* from the PHY. */
182 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
183 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
184 socregs_base + MX51_USB_CTRL_1_OFFSET);
185
186 iounmap(usb_base);
187
188 gpio_free(EFIKAMX_USBH1_STP);
189 mxc_iomux_v3_setup_pad(usbh1stp);
190
191 mdelay(10);
192
193 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
194}
195
196static struct mxc_usbh_platform_data usbh1_config = {
197 .init = initialize_usbh1_port,
198 .portsc = MXC_EHCI_MODE_ULPI,
199};
200
201static void mx51_efika_hubreset(void)
202{
203 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
204 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
205 msleep(1);
206 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
207 msleep(1);
208 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
209}
210
211static void __init mx51_efika_usb(void)
212{
213 mx51_efika_hubreset();
214
215 /* pulling it low, means no USB at all... */
216 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
217 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
218 msleep(1);
219 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
220
221 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
222 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
223
224 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
225 if (usbh1_config.otg)
226 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
227}
228
229static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
230 {
231 .name = "u-boot",
232 .offset = 0,
233 .size = SZ_256K,
234 },
235 {
236 .name = "config",
237 .offset = MTDPART_OFS_APPEND,
238 .size = SZ_64K,
239 },
240};
241
242static struct flash_platform_data mx51_efika_spi_flash_data = {
243 .name = "spi_flash",
244 .parts = mx51_efika_spi_nor_partitions,
245 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
246 .type = "sst25vf032b",
247};
248
249static struct regulator_consumer_supply sw1_consumers[] = {
250 {
251 .supply = "cpu_vcc",
252 }
253};
254
255static struct regulator_consumer_supply vdig_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDA", "1-000a"),
258 REGULATOR_SUPPLY("VDDD", "1-000a"),
259};
260
261static struct regulator_consumer_supply vvideo_consumers[] = {
262 /* sgtl5000 */
263 REGULATOR_SUPPLY("VDDIO", "1-000a"),
264};
265
266static struct regulator_consumer_supply vsd_consumers[] = {
267 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
268 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
269};
270
271static struct regulator_consumer_supply pwgt1_consumer[] = {
272 {
273 .supply = "pwgt1",
274 }
275};
276
277static struct regulator_consumer_supply pwgt2_consumer[] = {
278 {
279 .supply = "pwgt2",
280 }
281};
282
283static struct regulator_consumer_supply coincell_consumer[] = {
284 {
285 .supply = "coincell",
286 }
287};
288
289static struct regulator_init_data sw1_init = {
290 .constraints = {
291 .name = "SW1",
292 .min_uV = 600000,
293 .max_uV = 1375000,
294 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
295 .valid_modes_mask = 0,
296 .always_on = 1,
297 .boot_on = 1,
298 .state_mem = {
299 .uV = 850000,
300 .mode = REGULATOR_MODE_NORMAL,
301 .enabled = 1,
302 },
303 },
304 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
305 .consumer_supplies = sw1_consumers,
306};
307
308static struct regulator_init_data sw2_init = {
309 .constraints = {
310 .name = "SW2",
311 .min_uV = 900000,
312 .max_uV = 1850000,
313 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
314 .always_on = 1,
315 .boot_on = 1,
316 .state_mem = {
317 .uV = 950000,
318 .mode = REGULATOR_MODE_NORMAL,
319 .enabled = 1,
320 },
321 }
322};
323
324static struct regulator_init_data sw3_init = {
325 .constraints = {
326 .name = "SW3",
327 .min_uV = 1100000,
328 .max_uV = 1850000,
329 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
330 .always_on = 1,
331 .boot_on = 1,
332 }
333};
334
335static struct regulator_init_data sw4_init = {
336 .constraints = {
337 .name = "SW4",
338 .min_uV = 1100000,
339 .max_uV = 1850000,
340 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
341 .always_on = 1,
342 .boot_on = 1,
343 }
344};
345
346static struct regulator_init_data viohi_init = {
347 .constraints = {
348 .name = "VIOHI",
349 .boot_on = 1,
350 .always_on = 1,
351 }
352};
353
354static struct regulator_init_data vusb_init = {
355 .constraints = {
356 .name = "VUSB",
357 .boot_on = 1,
358 .always_on = 1,
359 }
360};
361
362static struct regulator_init_data swbst_init = {
363 .constraints = {
364 .name = "SWBST",
365 }
366};
367
368static struct regulator_init_data vdig_init = {
369 .constraints = {
370 .name = "VDIG",
371 .min_uV = 1050000,
372 .max_uV = 1800000,
373 .valid_ops_mask =
374 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
375 .boot_on = 1,
376 .always_on = 1,
377 },
378 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
379 .consumer_supplies = vdig_consumers,
380};
381
382static struct regulator_init_data vpll_init = {
383 .constraints = {
384 .name = "VPLL",
385 .min_uV = 1050000,
386 .max_uV = 1800000,
387 .valid_ops_mask =
388 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
389 .boot_on = 1,
390 .always_on = 1,
391 }
392};
393
394static struct regulator_init_data vusb2_init = {
395 .constraints = {
396 .name = "VUSB2",
397 .min_uV = 2400000,
398 .max_uV = 2775000,
399 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
400 .boot_on = 1,
401 .always_on = 1,
402 }
403};
404
405static struct regulator_init_data vvideo_init = {
406 .constraints = {
407 .name = "VVIDEO",
408 .min_uV = 2775000,
409 .max_uV = 2775000,
410 .valid_ops_mask =
411 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
412 .boot_on = 1,
413 .apply_uV = 1,
414 },
415 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
416 .consumer_supplies = vvideo_consumers,
417};
418
419static struct regulator_init_data vaudio_init = {
420 .constraints = {
421 .name = "VAUDIO",
422 .min_uV = 2300000,
423 .max_uV = 3000000,
424 .valid_ops_mask =
425 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
426 .boot_on = 1,
427 }
428};
429
430static struct regulator_init_data vsd_init = {
431 .constraints = {
432 .name = "VSD",
433 .min_uV = 1800000,
434 .max_uV = 3150000,
435 .valid_ops_mask =
436 REGULATOR_CHANGE_VOLTAGE,
437 .boot_on = 1,
438 },
439 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
440 .consumer_supplies = vsd_consumers,
441};
442
443static struct regulator_init_data vcam_init = {
444 .constraints = {
445 .name = "VCAM",
446 .min_uV = 2500000,
447 .max_uV = 3000000,
448 .valid_ops_mask =
449 REGULATOR_CHANGE_VOLTAGE |
450 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
451 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
452 .boot_on = 1,
453 }
454};
455
456static struct regulator_init_data vgen1_init = {
457 .constraints = {
458 .name = "VGEN1",
459 .min_uV = 1200000,
460 .max_uV = 3150000,
461 .valid_ops_mask =
462 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
463 .boot_on = 1,
464 .always_on = 1,
465 }
466};
467
468static struct regulator_init_data vgen2_init = {
469 .constraints = {
470 .name = "VGEN2",
471 .min_uV = 1200000,
472 .max_uV = 3150000,
473 .valid_ops_mask =
474 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
475 .boot_on = 1,
476 .always_on = 1,
477 }
478};
479
480static struct regulator_init_data vgen3_init = {
481 .constraints = {
482 .name = "VGEN3",
483 .min_uV = 1800000,
484 .max_uV = 2900000,
485 .valid_ops_mask =
486 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
487 .boot_on = 1,
488 .always_on = 1,
489 }
490};
491
492static struct regulator_init_data gpo1_init = {
493 .constraints = {
494 .name = "GPO1",
495 }
496};
497
498static struct regulator_init_data gpo2_init = {
499 .constraints = {
500 .name = "GPO2",
501 }
502};
503
504static struct regulator_init_data gpo3_init = {
505 .constraints = {
506 .name = "GPO3",
507 }
508};
509
510static struct regulator_init_data gpo4_init = {
511 .constraints = {
512 .name = "GPO4",
513 }
514};
515
516static struct regulator_init_data pwgt1_init = {
517 .constraints = {
518 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
519 .boot_on = 1,
520 },
521 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
522 .consumer_supplies = pwgt1_consumer,
523};
524
525static struct regulator_init_data pwgt2_init = {
526 .constraints = {
527 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
528 .boot_on = 1,
529 },
530 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
531 .consumer_supplies = pwgt2_consumer,
532};
533
534static struct regulator_init_data vcoincell_init = {
535 .constraints = {
536 .name = "COINCELL",
537 .min_uV = 3000000,
538 .max_uV = 3000000,
539 .valid_ops_mask =
540 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
541 },
542 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
543 .consumer_supplies = coincell_consumer,
544};
545
546static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
547 { .id = MC13892_SW1, .init_data = &sw1_init },
548 { .id = MC13892_SW2, .init_data = &sw2_init },
549 { .id = MC13892_SW3, .init_data = &sw3_init },
550 { .id = MC13892_SW4, .init_data = &sw4_init },
551 { .id = MC13892_SWBST, .init_data = &swbst_init },
552 { .id = MC13892_VIOHI, .init_data = &viohi_init },
553 { .id = MC13892_VPLL, .init_data = &vpll_init },
554 { .id = MC13892_VDIG, .init_data = &vdig_init },
555 { .id = MC13892_VSD, .init_data = &vsd_init },
556 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
557 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
558 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
559 { .id = MC13892_VCAM, .init_data = &vcam_init },
560 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
561 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
562 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
563 { .id = MC13892_VUSB, .init_data = &vusb_init },
564 { .id = MC13892_GPO1, .init_data = &gpo1_init },
565 { .id = MC13892_GPO2, .init_data = &gpo2_init },
566 { .id = MC13892_GPO3, .init_data = &gpo3_init },
567 { .id = MC13892_GPO4, .init_data = &gpo4_init },
568 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
569 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
570 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
571};
572
573static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
574 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
575 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
576 .regulators = mx51_efika_regulators,
577};
578
579static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
580 {
581 .modalias = "m25p80",
582 .max_speed_hz = 25000000,
583 .bus_num = 0,
584 .chip_select = 1,
585 .platform_data = &mx51_efika_spi_flash_data,
586 .irq = -1,
587 },
588 {
589 .modalias = "mc13892",
590 .max_speed_hz = 1000000,
591 .bus_num = 0,
592 .chip_select = 0,
593 .platform_data = &mx51_efika_mc13892_data,
594 .irq = gpio_to_irq(EFIKAMX_PMIC),
595 },
596};
597
598static int mx51_efika_spi_cs[] = {
599 EFIKAMX_SPI_CS0,
600 EFIKAMX_SPI_CS1,
601};
602
603static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
604 .chipselect = mx51_efika_spi_cs,
605 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
606};
607
608void __init efika_board_common_init(void)
609{
610 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
611 ARRAY_SIZE(mx51efika_pads));
612 imx51_add_imx_uart(0, &uart_pdata);
613 mx51_efika_usb();
614 imx51_add_sdhci_esdhc_imx(0, NULL);
615
616 /* FIXME: comes from original code. check this. */
617 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
618 sw2_init.constraints.state_mem.uV = 1100000;
619 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
620 sw2_init.constraints.state_mem.uV = 1250000;
621 sw1_init.constraints.state_mem.uV = 1000000;
622 }
623 if (machine_is_mx51_efikasb())
624 vgen1_init.constraints.max_uV = 1200000;
625
626 gpio_request(EFIKAMX_PMIC, "pmic irq");
627 gpio_direction_input(EFIKAMX_PMIC);
628 spi_register_board_info(mx51_efika_spi_board_info,
629 ARRAY_SIZE(mx51_efika_spi_board_info));
630 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
631
632#if defined(CONFIG_CPU_FREQ_IMX)
633 get_cpu_op = mx51_get_cpu_op;
634#endif
635}
636
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 23:20:35 -0500