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Diffstat (limited to 'arch/arm/mach-mx5/board-mx51_babbage.c')
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c101
1 files changed, 71 insertions, 30 deletions
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index acbe30df2e6..1d231e84107 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -20,6 +20,8 @@
20#include <linux/fec.h> 20#include <linux/fec.h>
21#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
23 25
24#include <mach/common.h> 26#include <mach/common.h>
25#include <mach/hardware.h> 27#include <mach/hardware.h>
@@ -36,11 +38,13 @@
36#include "devices.h" 38#include "devices.h"
37#include "cpu_op-mx51.h" 39#include "cpu_op-mx51.h"
38 40
39#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ 41#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
40#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ 42#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
41#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ 43#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
42#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ 44#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
43#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ 45#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
46#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
47#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
44 48
45/* USB_CTRL_1 */ 49/* USB_CTRL_1 */
46#define MX51_USB_CTRL_1_OFFSET 0x10 50#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = {
65 .nbuttons = ARRAY_SIZE(babbage_buttons), 69 .nbuttons = ARRAY_SIZE(babbage_buttons),
66}; 70};
67 71
68static struct pad_desc mx51babbage_pads[] = { 72static iomux_v3_cfg_t mx51babbage_pads[] = {
69 /* UART1 */ 73 /* UART1 */
70 MX51_PAD_UART1_RXD__UART1_RXD, 74 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD, 75 MX51_PAD_UART1_TXD__UART1_TXD,
@@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = {
91 MX51_PAD_KEY_COL5__I2C2_SDA, 95 MX51_PAD_KEY_COL5__I2C2_SDA,
92 96
93 /* HSI2C */ 97 /* HSI2C */
94 MX51_PAD_I2C1_CLK__HSI2C_CLK, 98 MX51_PAD_I2C1_CLK__I2C1_CLK,
95 MX51_PAD_I2C1_DAT__HSI2C_DAT, 99 MX51_PAD_I2C1_DAT__I2C1_DAT,
96 100
97 /* USB HOST1 */ 101 /* USB HOST1 */
98 MX51_PAD_USBH1_CLK__USBH1_CLK, 102 MX51_PAD_USBH1_CLK__USBH1_CLK,
@@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = {
108 MX51_PAD_USBH1_DATA7__USBH1_DATA7, 112 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109 113
110 /* USB HUB reset line*/ 114 /* USB HUB reset line*/
111 MX51_PAD_GPIO_1_7__GPIO_1_7, 115 MX51_PAD_GPIO1_7__GPIO1_7,
112 116
113 /* FEC */ 117 /* FEC */
114 MX51_PAD_EIM_EB2__FEC_MDIO, 118 MX51_PAD_EIM_EB2__FEC_MDIO,
115 MX51_PAD_EIM_EB3__FEC_RDAT1, 119 MX51_PAD_EIM_EB3__FEC_RDATA1,
116 MX51_PAD_EIM_CS2__FEC_RDAT2, 120 MX51_PAD_EIM_CS2__FEC_RDATA2,
117 MX51_PAD_EIM_CS3__FEC_RDAT3, 121 MX51_PAD_EIM_CS3__FEC_RDATA3,
118 MX51_PAD_EIM_CS4__FEC_RX_ER, 122 MX51_PAD_EIM_CS4__FEC_RX_ER,
119 MX51_PAD_EIM_CS5__FEC_CRS, 123 MX51_PAD_EIM_CS5__FEC_CRS,
120 MX51_PAD_NANDF_RB2__FEC_COL, 124 MX51_PAD_NANDF_RB2__FEC_COL,
121 MX51_PAD_NANDF_RB3__FEC_RXCLK, 125 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
122 MX51_PAD_NANDF_RB6__FEC_RDAT0, 126 MX51_PAD_NANDF_D9__FEC_RDATA0,
123 MX51_PAD_NANDF_RB7__FEC_TDAT0, 127 MX51_PAD_NANDF_D8__FEC_TDATA0,
124 MX51_PAD_NANDF_CS2__FEC_TX_ER, 128 MX51_PAD_NANDF_CS2__FEC_TX_ER,
125 MX51_PAD_NANDF_CS3__FEC_MDC, 129 MX51_PAD_NANDF_CS3__FEC_MDC,
126 MX51_PAD_NANDF_CS4__FEC_TDAT1, 130 MX51_PAD_NANDF_CS4__FEC_TDATA1,
127 MX51_PAD_NANDF_CS5__FEC_TDAT2, 131 MX51_PAD_NANDF_CS5__FEC_TDATA2,
128 MX51_PAD_NANDF_CS6__FEC_TDAT3, 132 MX51_PAD_NANDF_CS6__FEC_TDATA3,
129 MX51_PAD_NANDF_CS7__FEC_TX_EN, 133 MX51_PAD_NANDF_CS7__FEC_TX_EN,
130 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, 134 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
131 135
132 /* FEC PHY reset line */ 136 /* FEC PHY reset line */
133 MX51_PAD_EIM_A20__GPIO_2_14, 137 MX51_PAD_EIM_A20__GPIO2_14,
134 138
135 /* SD 1 */ 139 /* SD 1 */
136 MX51_PAD_SD1_CMD__SD1_CMD, 140 MX51_PAD_SD1_CMD__SD1_CMD,
@@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = {
147 MX51_PAD_SD2_DATA1__SD2_DATA1, 151 MX51_PAD_SD2_DATA1__SD2_DATA1,
148 MX51_PAD_SD2_DATA2__SD2_DATA2, 152 MX51_PAD_SD2_DATA2__SD2_DATA2,
149 MX51_PAD_SD2_DATA3__SD2_DATA3, 153 MX51_PAD_SD2_DATA3__SD2_DATA3,
154
155 /* eCSPI1 */
156 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
157 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
158 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
159 MX51_PAD_CSPI1_SS0__GPIO4_24,
160 MX51_PAD_CSPI1_SS1__GPIO4_25,
150}; 161};
151 162
152/* Serial ports */ 163/* Serial ports */
@@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
177 188
178static int gpio_usbh1_active(void) 189static int gpio_usbh1_active(void)
179{ 190{
180 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; 191 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
181 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; 192 iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
182 int ret; 193 int ret;
183 194
184 /* Set USBH1_STP to GPIO and toggle it */ 195 /* Set USBH1_STP to GPIO and toggle it */
185 mxc_iomux_v3_setup_pad(&usbh1stp_gpio); 196 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
186 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); 197 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
187 198
188 if (ret) { 199 if (ret) {
@@ -195,7 +206,7 @@ static int gpio_usbh1_active(void)
195 gpio_free(BABBAGE_USBH1_STP); 206 gpio_free(BABBAGE_USBH1_STP);
196 207
197 /* De-assert USB PHY RESETB */ 208 /* De-assert USB PHY RESETB */
198 mxc_iomux_v3_setup_pad(&phyreset_gpio); 209 mxc_iomux_v3_setup_pad(phyreset_gpio);
199 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); 210 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
200 211
201 if (ret) { 212 if (ret) {
@@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev)
251 void __iomem *usbother_base; 262 void __iomem *usbother_base;
252 263
253 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 264 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
265 if (!usb_base)
266 return -ENOMEM;
254 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 267 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
255 268
256 /* Set the PHY clock to 19.2MHz */ 269 /* Set the PHY clock to 19.2MHz */
@@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
269 void __iomem *usbother_base; 282 void __iomem *usbother_base;
270 283
271 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 284 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
285 if (!usb_base)
286 return -ENOMEM;
272 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 287 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
273 288
274 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ 289 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
@@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options)
310} 325}
311__setup("otg_mode=", babbage_otg_mode); 326__setup("otg_mode=", babbage_otg_mode);
312 327
328static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
329 {
330 .modalias = "mtd_dataflash",
331 .max_speed_hz = 25000000,
332 .bus_num = 0,
333 .chip_select = 1,
334 .mode = SPI_MODE_0,
335 .platform_data = NULL,
336 },
337};
338
339static int mx51_babbage_spi_cs[] = {
340 BABBAGE_ECSPI1_CS0,
341 BABBAGE_ECSPI1_CS1,
342};
343
344static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
345 .chipselect = mx51_babbage_spi_cs,
346 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
347};
348
313/* 349/*
314 * Board specific initialization. 350 * Board specific initialization.
315 */ 351 */
316static void __init mxc_board_init(void) 352static void __init mxc_board_init(void)
317{ 353{
318 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; 354 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
319 struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21; 355 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
356 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
320 357
321#if defined(CONFIG_CPU_FREQ_IMX) 358#if defined(CONFIG_CPU_FREQ_IMX)
322 get_cpu_op = mx51_get_cpu_op; 359 get_cpu_op = mx51_get_cpu_op;
@@ -328,8 +365,7 @@ static void __init mxc_board_init(void)
328 imx51_add_fec(NULL); 365 imx51_add_fec(NULL);
329 366
330 /* Set the PAD settings for the pwr key. */ 367 /* Set the PAD settings for the pwr key. */
331 power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2; 368 mxc_iomux_v3_setup_pad(power_key);
332 mxc_iomux_v3_setup_pad(&power_key);
333 imx51_add_gpio_keys(&imx_button_data); 369 imx51_add_gpio_keys(&imx_button_data);
334 370
335 imx51_add_imx_i2c(0, &babbage_i2c_data); 371 imx51_add_imx_i2c(0, &babbage_i2c_data);
@@ -346,11 +382,16 @@ static void __init mxc_board_init(void)
346 gpio_usbh1_active(); 382 gpio_usbh1_active();
347 mxc_register_device(&mxc_usbh1_device, &usbh1_config); 383 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
348 /* setback USBH1_STP to be function */ 384 /* setback USBH1_STP to be function */
349 mxc_iomux_v3_setup_pad(&usbh1stp); 385 mxc_iomux_v3_setup_pad(usbh1stp);
350 babbage_usbhub_reset(); 386 babbage_usbhub_reset();
351 387
352 imx51_add_esdhc(0, NULL); 388 imx51_add_sdhci_esdhc_imx(0, NULL);
353 imx51_add_esdhc(1, NULL); 389 imx51_add_sdhci_esdhc_imx(1, NULL);
390
391 spi_register_board_info(mx51_babbage_spi_board_info,
392 ARRAY_SIZE(mx51_babbage_spi_board_info));
393 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
394 imx51_add_imx2_wdt(0, NULL);
354} 395}
355 396
356static void __init mx51_babbage_timer_init(void) 397static void __init mx51_babbage_timer_init(void)