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-rw-r--r--arch/arm/mach-mx5/Kconfig226
-rw-r--r--arch/arm/mach-mx5/Makefile24
-rw-r--r--arch/arm/mach-mx5/Makefile.boot9
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c302
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c340
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c224
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c178
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c425
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c289
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c275
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c254
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c172
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c293
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c145
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c1611
-rw-r--r--arch/arm/mach-mx5/cpu.c226
-rw-r--r--arch/arm/mach-mx5/cpu_op-mx51.c29
-rw-r--r--arch/arm/mach-mx5/cpu_op-mx51.h14
-rw-r--r--arch/arm/mach-mx5/crm_regs.h600
-rw-r--r--arch/arm/mach-mx5/devices-imx50.h34
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h54
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h42
-rw-r--r--arch/arm/mach-mx5/devices.c120
-rw-r--r--arch/arm/mach-mx5/devices.h5
-rw-r--r--arch/arm/mach-mx5/efika.h10
-rw-r--r--arch/arm/mach-mx5/ehci.c156
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c207
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c148
-rw-r--r--arch/arm/mach-mx5/mm-mx50.c72
-rw-r--r--arch/arm/mach-mx5/mm.c166
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c634
-rw-r--r--arch/arm/mach-mx5/pm-imx5.c73
-rw-r--r--arch/arm/mach-mx5/system.c84
33 files changed, 7441 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
new file mode 100644
index 00000000000..b4e7c58bbb3
--- /dev/null
+++ b/arch/arm/mach-mx5/Kconfig
@@ -0,0 +1,226 @@
1if ARCH_MX503 || ARCH_MX51
2# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
3# image. So for most time, SOC_IMX50/51/53 should be used.
4
5config ARCH_MX5
6 bool
7
8config ARCH_MX50
9 bool
10
11config ARCH_MX53
12 bool
13
14config SOC_IMX50
15 bool
16 select CPU_V7
17 select ARM_L1_CACHE_SHIFT_6
18 select MXC_TZIC
19 select ARCH_MXC_IOMUX_V3
20 select ARCH_MXC_AUDMUX_V2
21 select ARCH_HAS_CPUFREQ
22 select ARCH_MX5
23 select ARCH_MX50
24
25config SOC_IMX51
26 bool
27 select CPU_V7
28 select ARM_L1_CACHE_SHIFT_6
29 select MXC_TZIC
30 select ARCH_MXC_IOMUX_V3
31 select ARCH_MXC_AUDMUX_V2
32 select ARCH_HAS_CPUFREQ
33 select ARCH_MX5
34
35config SOC_IMX53
36 bool
37 select CPU_V7
38 select ARM_L1_CACHE_SHIFT_6
39 select MXC_TZIC
40 select ARCH_MXC_IOMUX_V3
41 select ARCH_MX5
42 select ARCH_MX53
43
44if ARCH_MX50_SUPPORTED
45#comment "i.MX50 machines:"
46
47config MACH_MX50_RDP
48 bool "Support MX50 reference design platform"
49 depends on BROKEN
50 select SOC_IMX50
51 select IMX_HAVE_PLATFORM_IMX_I2C
52 select IMX_HAVE_PLATFORM_IMX_UART
53 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
54 select IMX_HAVE_PLATFORM_SPI_IMX
55 select IMX_HAVE_PLATFORM_FEC
56 help
57 Include support for MX50 reference design platform (RDP) board. This
58 includes specific configurations for the board and its peripherals.
59
60endif # ARCH_MX50_SUPPORTED
61
62if ARCH_MX51
63comment "i.MX51 machines:"
64
65config MACH_MX51_BABBAGE
66 bool "Support MX51 BABBAGE platforms"
67 select SOC_IMX51
68 select IMX_HAVE_PLATFORM_IMX2_WDT
69 select IMX_HAVE_PLATFORM_IMX_I2C
70 select IMX_HAVE_PLATFORM_IMX_UART
71 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
72 select IMX_HAVE_PLATFORM_SPI_IMX
73 help
74 Include support for MX51 Babbage platform, also known as MX51EVK in
75 u-boot. This includes specific configurations for the board and its
76 peripherals.
77
78config MACH_MX51_3DS
79 bool "Support MX51PDK (3DS)"
80 select SOC_IMX51
81 select IMX_HAVE_PLATFORM_IMX2_WDT
82 select IMX_HAVE_PLATFORM_IMX_KEYPAD
83 select IMX_HAVE_PLATFORM_IMX_UART
84 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
85 select IMX_HAVE_PLATFORM_SPI_IMX
86 select MXC_DEBUG_BOARD
87 help
88 Include support for MX51PDK (3DS) platform. This includes specific
89 configurations for the board and its peripherals.
90
91config MACH_EUKREA_CPUIMX51
92 bool "Support Eukrea CPUIMX51 module"
93 select SOC_IMX51
94 select IMX_HAVE_PLATFORM_IMX_I2C
95 select IMX_HAVE_PLATFORM_IMX_UART
96 select IMX_HAVE_PLATFORM_MXC_NAND
97 select IMX_HAVE_PLATFORM_SPI_IMX
98 help
99 Include support for Eukrea CPUIMX51 platform. This includes
100 specific configurations for the module and its peripherals.
101
102choice
103 prompt "Baseboard"
104 depends on MACH_EUKREA_CPUIMX51
105 default MACH_EUKREA_MBIMX51_BASEBOARD
106
107config MACH_EUKREA_MBIMX51_BASEBOARD
108 prompt "Eukrea MBIMX51 development board"
109 bool
110 select IMX_HAVE_PLATFORM_IMX_KEYPAD
111 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
112 select LEDS_GPIO_REGISTER
113 help
114 This adds board specific devices that can be found on Eukrea's
115 MBIMX51 evaluation board.
116
117endchoice
118
119config MACH_EUKREA_CPUIMX51SD
120 bool "Support Eukrea CPUIMX51SD module"
121 select SOC_IMX51
122 select IMX_HAVE_PLATFORM_IMX_I2C
123 select IMX_HAVE_PLATFORM_SPI_IMX
124 select IMX_HAVE_PLATFORM_IMX_UART
125 select IMX_HAVE_PLATFORM_MXC_NAND
126 help
127 Include support for Eukrea CPUIMX51SD platform. This includes
128 specific configurations for the module and its peripherals.
129
130choice
131 prompt "Baseboard"
132 depends on MACH_EUKREA_CPUIMX51SD
133 default MACH_EUKREA_MBIMXSD51_BASEBOARD
134
135config MACH_EUKREA_MBIMXSD51_BASEBOARD
136 prompt "Eukrea MBIMXSD development board"
137 bool
138 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
139 select LEDS_GPIO_REGISTER
140 help
141 This adds board specific devices that can be found on Eukrea's
142 MBIMXSD evaluation board.
143
144endchoice
145
146config MX51_EFIKA_COMMON
147 bool
148 select SOC_IMX51
149 select IMX_HAVE_PLATFORM_IMX_UART
150 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
151 select IMX_HAVE_PLATFORM_SPI_IMX
152 select MXC_ULPI if USB_ULPI
153
154config MACH_MX51_EFIKAMX
155 bool "Support MX51 Genesi Efika MX nettop"
156 select LEDS_GPIO_REGISTER
157 select MX51_EFIKA_COMMON
158 help
159 Include support for Genesi Efika MX nettop. This includes specific
160 configurations for the board and its peripherals.
161
162config MACH_MX51_EFIKASB
163 bool "Support MX51 Genesi Efika Smartbook"
164 select LEDS_GPIO_REGISTER
165 select MX51_EFIKA_COMMON
166 help
167 Include support for Genesi Efika Smartbook. This includes specific
168 configurations for the board and its peripherals.
169
170endif # ARCH_MX51
171
172if ARCH_MX53_SUPPORTED
173comment "i.MX53 machines:"
174
175config MACH_MX53_EVK
176 bool "Support MX53 EVK platforms"
177 select SOC_IMX53
178 select IMX_HAVE_PLATFORM_IMX2_WDT
179 select IMX_HAVE_PLATFORM_IMX_UART
180 select IMX_HAVE_PLATFORM_IMX_I2C
181 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
182 select IMX_HAVE_PLATFORM_SPI_IMX
183 select LEDS_GPIO_REGISTER
184 help
185 Include support for MX53 EVK platform. This includes specific
186 configurations for the board and its peripherals.
187
188config MACH_MX53_SMD
189 bool "Support MX53 SMD platforms"
190 select SOC_IMX53
191 select IMX_HAVE_PLATFORM_IMX2_WDT
192 select IMX_HAVE_PLATFORM_IMX_I2C
193 select IMX_HAVE_PLATFORM_IMX_UART
194 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
195 help
196 Include support for MX53 SMD platform. This includes specific
197 configurations for the board and its peripherals.
198
199config MACH_MX53_LOCO
200 bool "Support MX53 LOCO platforms"
201 select SOC_IMX53
202 select IMX_HAVE_PLATFORM_IMX2_WDT
203 select IMX_HAVE_PLATFORM_IMX_I2C
204 select IMX_HAVE_PLATFORM_IMX_UART
205 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
206 select IMX_HAVE_PLATFORM_GPIO_KEYS
207 select LEDS_GPIO_REGISTER
208 help
209 Include support for MX53 LOCO platform. This includes specific
210 configurations for the board and its peripherals.
211
212config MACH_MX53_ARD
213 bool "Support MX53 ARD platforms"
214 select SOC_IMX53
215 select IMX_HAVE_PLATFORM_IMX2_WDT
216 select IMX_HAVE_PLATFORM_IMX_I2C
217 select IMX_HAVE_PLATFORM_IMX_UART
218 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
219 select IMX_HAVE_PLATFORM_GPIO_KEYS
220 help
221 Include support for MX53 ARD platform. This includes specific
222 configurations for the board and its peripherals.
223
224endif # ARCH_MX53_SUPPORTED
225
226endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
new file mode 100644
index 00000000000..383e7cd3fbc
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile
@@ -0,0 +1,24 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
8
9obj-$(CONFIG_PM) += pm-imx5.o
10obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
11obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
12obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
13obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
14obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
15obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
16obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
17obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
18obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
19obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
20obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
21obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
22obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
23obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
24obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
new file mode 100644
index 00000000000..e928be1b675
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile.boot
@@ -0,0 +1,9 @@
1 zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000
2params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
3initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
4 zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000
5params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
6initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
7 zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000
8params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
9initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
new file mode 100644
index 00000000000..68934ea8725
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -0,0 +1,302 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/serial_8250.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26
27#include <mach/eukrea-baseboards.h>
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-mx51.h>
31
32#include <asm/irq.h>
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37
38#include "devices-imx51.h"
39#include "devices.h"
40
41#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
42#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
43#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
44#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
45#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
46#define CPUIMX51_QUART_XTAL 14745600
47#define CPUIMX51_QUART_REGSHIFT 17
48
49/* USB_CTRL_1 */
50#define MX51_USB_CTRL_1_OFFSET 0x10
51#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
52
53#define MX51_USB_PLLDIV_12_MHZ 0x00
54#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55#define MX51_USB_PLL_DIV_24_MHZ 0x02
56
57static struct plat_serial8250_port serial_platform_data[] = {
58 {
59 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
60 .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
61 .irqflags = IRQF_TRIGGER_HIGH,
62 .uartclk = CPUIMX51_QUART_XTAL,
63 .regshift = CPUIMX51_QUART_REGSHIFT,
64 .iotype = UPIO_MEM,
65 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
66 }, {
67 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
68 .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
69 .irqflags = IRQF_TRIGGER_HIGH,
70 .uartclk = CPUIMX51_QUART_XTAL,
71 .regshift = CPUIMX51_QUART_REGSHIFT,
72 .iotype = UPIO_MEM,
73 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
74 }, {
75 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
76 .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
77 .irqflags = IRQF_TRIGGER_HIGH,
78 .uartclk = CPUIMX51_QUART_XTAL,
79 .regshift = CPUIMX51_QUART_REGSHIFT,
80 .iotype = UPIO_MEM,
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
82 }, {
83 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
84 .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
85 .irqflags = IRQF_TRIGGER_HIGH,
86 .uartclk = CPUIMX51_QUART_XTAL,
87 .regshift = CPUIMX51_QUART_REGSHIFT,
88 .iotype = UPIO_MEM,
89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
90 }, {
91 }
92};
93
94static struct platform_device serial_device = {
95 .name = "serial8250",
96 .id = 0,
97 .dev = {
98 .platform_data = serial_platform_data,
99 },
100};
101
102static struct platform_device *devices[] __initdata = {
103 &serial_device,
104};
105
106static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
107 /* UART1 */
108 MX51_PAD_UART1_RXD__UART1_RXD,
109 MX51_PAD_UART1_TXD__UART1_TXD,
110 MX51_PAD_UART1_RTS__UART1_RTS,
111 MX51_PAD_UART1_CTS__UART1_CTS,
112
113 /* I2C2 */
114 MX51_PAD_GPIO1_2__I2C2_SCL,
115 MX51_PAD_GPIO1_3__I2C2_SDA,
116 MX51_PAD_NANDF_D10__GPIO3_30,
117
118 /* QUART IRQ */
119 MX51_PAD_NANDF_D15__GPIO3_25,
120 MX51_PAD_NANDF_D14__GPIO3_26,
121 MX51_PAD_NANDF_D13__GPIO3_27,
122 MX51_PAD_NANDF_D12__GPIO3_28,
123
124 /* USB HOST1 */
125 MX51_PAD_USBH1_CLK__USBH1_CLK,
126 MX51_PAD_USBH1_DIR__USBH1_DIR,
127 MX51_PAD_USBH1_NXT__USBH1_NXT,
128 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
129 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
130 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
131 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
132 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
133 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
134 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
135 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
136 MX51_PAD_USBH1_STP__USBH1_STP,
137};
138
139static const struct mxc_nand_platform_data
140 eukrea_cpuimx51_nand_board_info __initconst = {
141 .width = 1,
142 .hw_ecc = 1,
143 .flash_bbt = 1,
144};
145
146static const struct imxuart_platform_data uart_pdata __initconst = {
147 .flags = IMXUART_HAVE_RTSCTS,
148};
149
150static const
151struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
152 .bitrate = 100000,
153};
154
155static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
156 {
157 I2C_BOARD_INFO("pcf8563", 0x51),
158 },
159};
160
161/* This function is board specific as the bit mask for the plldiv will also
162be different for other Freescale SoCs, thus a common bitmask is not
163possible and cannot get place in /plat-mxc/ehci.c.*/
164static int initialize_otg_port(struct platform_device *pdev)
165{
166 u32 v;
167 void __iomem *usb_base;
168 void __iomem *usbother_base;
169
170 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
171 if (!usb_base)
172 return -ENOMEM;
173 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
174
175 /* Set the PHY clock to 19.2MHz */
176 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
177 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
178 v |= MX51_USB_PLL_DIV_19_2_MHZ;
179 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
180 iounmap(usb_base);
181
182 mdelay(10);
183
184 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
185}
186
187static int initialize_usbh1_port(struct platform_device *pdev)
188{
189 u32 v;
190 void __iomem *usb_base;
191 void __iomem *usbother_base;
192
193 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
194 if (!usb_base)
195 return -ENOMEM;
196 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
197
198 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
199 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
200 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
201 iounmap(usb_base);
202
203 mdelay(10);
204
205 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
206 MXC_EHCI_ITC_NO_THRESHOLD);
207}
208
209static struct mxc_usbh_platform_data dr_utmi_config = {
210 .init = initialize_otg_port,
211 .portsc = MXC_EHCI_UTMI_16BIT,
212};
213
214static struct fsl_usb2_platform_data usb_pdata = {
215 .operating_mode = FSL_USB2_DR_DEVICE,
216 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
217};
218
219static struct mxc_usbh_platform_data usbh1_config = {
220 .init = initialize_usbh1_port,
221 .portsc = MXC_EHCI_MODE_ULPI,
222};
223
224static int otg_mode_host;
225
226static int __init eukrea_cpuimx51_otg_mode(char *options)
227{
228 if (!strcmp(options, "host"))
229 otg_mode_host = 1;
230 else if (!strcmp(options, "device"))
231 otg_mode_host = 0;
232 else
233 pr_info("otg_mode neither \"host\" nor \"device\". "
234 "Defaulting to device\n");
235 return 0;
236}
237__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
238
239/*
240 * Board specific initialization.
241 */
242static void __init eukrea_cpuimx51_init(void)
243{
244 imx51_soc_init();
245
246 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
247 ARRAY_SIZE(eukrea_cpuimx51_pads));
248
249 imx51_add_imx_uart(0, &uart_pdata);
250 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
251
252 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
253 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
254 gpio_free(CPUIMX51_QUARTA_GPIO);
255 gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
256 gpio_direction_input(CPUIMX51_QUARTB_GPIO);
257 gpio_free(CPUIMX51_QUARTB_GPIO);
258 gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
259 gpio_direction_input(CPUIMX51_QUARTC_GPIO);
260 gpio_free(CPUIMX51_QUARTC_GPIO);
261 gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
262 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
263 gpio_free(CPUIMX51_QUARTD_GPIO);
264
265 imx51_add_fec(NULL);
266 platform_add_devices(devices, ARRAY_SIZE(devices));
267
268 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
269 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
270 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
271
272 if (otg_mode_host)
273 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
274 else {
275 initialize_otg_port(NULL);
276 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
277 }
278 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
279
280#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
281 eukrea_mbimx51_baseboard_init();
282#endif
283}
284
285static void __init eukrea_cpuimx51_timer_init(void)
286{
287 mx51_clocks_init(32768, 24000000, 22579200, 0);
288}
289
290static struct sys_timer mxc_timer = {
291 .init = eukrea_cpuimx51_timer_init,
292};
293
294MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
295 /* Maintainer: Eric Bénard <eric@eukrea.com> */
296 .boot_params = MX51_PHYS_OFFSET + 0x100,
297 .map_io = mx51_map_io,
298 .init_early = imx51_init_early,
299 .init_irq = mx51_init_irq,
300 .timer = &mxc_timer,
301 .init_machine = eukrea_cpuimx51_init,
302MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
new file mode 100644
index 00000000000..ff096d58729
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -0,0 +1,340 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/i2c-gpio.h>
27#include <linux/spi/spi.h>
28#include <linux/can/platform/mcp251x.h>
29
30#include <mach/eukrea-baseboards.h>
31#include <mach/common.h>
32#include <mach/hardware.h>
33#include <mach/iomux-mx51.h>
34
35#include <asm/irq.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41#include "devices-imx51.h"
42#include "devices.h"
43#include "cpu_op-mx51.h"
44
45#define USBH1_RST IMX_GPIO_NR(2, 28)
46#define ETH_RST IMX_GPIO_NR(2, 31)
47#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
48#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
49#define CAN_RST IMX_GPIO_NR(4, 15)
50#define CAN_NCS IMX_GPIO_NR(4, 24)
51#define CAN_RXOBF IMX_GPIO_NR(1, 4)
52#define CAN_RX1BF IMX_GPIO_NR(1, 6)
53#define CAN_TXORTS IMX_GPIO_NR(1, 7)
54#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
55#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
56#define I2C_SCL IMX_GPIO_NR(4, 16)
57#define I2C_SDA IMX_GPIO_NR(4, 17)
58
59/* USB_CTRL_1 */
60#define MX51_USB_CTRL_1_OFFSET 0x10
61#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
62
63#define MX51_USB_PLLDIV_12_MHZ 0x00
64#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
65#define MX51_USB_PLL_DIV_24_MHZ 0x02
66
67static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
68 /* UART1 */
69 MX51_PAD_UART1_RXD__UART1_RXD,
70 MX51_PAD_UART1_TXD__UART1_TXD,
71 MX51_PAD_UART1_RTS__UART1_RTS,
72 MX51_PAD_UART1_CTS__UART1_CTS,
73
74 /* USB HOST1 */
75 MX51_PAD_USBH1_CLK__USBH1_CLK,
76 MX51_PAD_USBH1_DIR__USBH1_DIR,
77 MX51_PAD_USBH1_NXT__USBH1_NXT,
78 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
79 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
80 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
81 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
82 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
83 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
84 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
85 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
86 MX51_PAD_USBH1_STP__USBH1_STP,
87 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
88
89 /* FEC */
90 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
91
92 /* HSI2C */
93 MX51_PAD_I2C1_CLK__GPIO4_16,
94 MX51_PAD_I2C1_DAT__GPIO4_17,
95
96 /* CAN */
97 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
98 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
99 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
100 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
101 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
102 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
103 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
104 MX51_PAD_GPIO1_6__GPIO1_6,
105 MX51_PAD_GPIO1_7__GPIO1_7,
106 MX51_PAD_GPIO1_8__GPIO1_8,
107 MX51_PAD_GPIO1_9__GPIO1_9,
108
109 /* Touchscreen */
110 /* IRQ */
111 _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
112 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
113 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
114};
115
116static const struct imxuart_platform_data uart_pdata __initconst = {
117 .flags = IMXUART_HAVE_RTSCTS,
118};
119
120static struct tsc2007_platform_data tsc2007_info = {
121 .model = 2007,
122 .x_plate_ohms = 180,
123};
124
125static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
126 {
127 I2C_BOARD_INFO("pcf8563", 0x51),
128 }, {
129 I2C_BOARD_INFO("tsc2007", 0x49),
130 .type = "tsc2007",
131 .platform_data = &tsc2007_info,
132 .irq = gpio_to_irq(TSC2007_IRQGPIO),
133 },
134};
135
136static const struct mxc_nand_platform_data
137 eukrea_cpuimx51sd_nand_board_info __initconst = {
138 .width = 1,
139 .hw_ecc = 1,
140 .flash_bbt = 1,
141};
142
143/* This function is board specific as the bit mask for the plldiv will also
144be different for other Freescale SoCs, thus a common bitmask is not
145possible and cannot get place in /plat-mxc/ehci.c.*/
146static int initialize_otg_port(struct platform_device *pdev)
147{
148 u32 v;
149 void __iomem *usb_base;
150 void __iomem *usbother_base;
151
152 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
153 if (!usb_base)
154 return -ENOMEM;
155 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
156
157 /* Set the PHY clock to 19.2MHz */
158 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
159 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
160 v |= MX51_USB_PLL_DIV_19_2_MHZ;
161 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
162 iounmap(usb_base);
163
164 mdelay(10);
165
166 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
167}
168
169static int initialize_usbh1_port(struct platform_device *pdev)
170{
171 u32 v;
172 void __iomem *usb_base;
173 void __iomem *usbother_base;
174
175 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
176 if (!usb_base)
177 return -ENOMEM;
178 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179
180 /* The clock for the USBH1 ULPI port will come from the PHY. */
181 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
182 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
183 usbother_base + MX51_USB_CTRL_1_OFFSET);
184 iounmap(usb_base);
185
186 mdelay(10);
187
188 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
189 MXC_EHCI_ITC_NO_THRESHOLD);
190}
191
192static struct mxc_usbh_platform_data dr_utmi_config = {
193 .init = initialize_otg_port,
194 .portsc = MXC_EHCI_UTMI_16BIT,
195};
196
197static struct fsl_usb2_platform_data usb_pdata = {
198 .operating_mode = FSL_USB2_DR_DEVICE,
199 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
200};
201
202static struct mxc_usbh_platform_data usbh1_config = {
203 .init = initialize_usbh1_port,
204 .portsc = MXC_EHCI_MODE_ULPI,
205};
206
207static int otg_mode_host;
208
209static int __init eukrea_cpuimx51sd_otg_mode(char *options)
210{
211 if (!strcmp(options, "host"))
212 otg_mode_host = 1;
213 else if (!strcmp(options, "device"))
214 otg_mode_host = 0;
215 else
216 pr_info("otg_mode neither \"host\" nor \"device\". "
217 "Defaulting to device\n");
218 return 0;
219}
220__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
221
222static struct i2c_gpio_platform_data pdata = {
223 .sda_pin = I2C_SDA,
224 .sda_is_open_drain = 0,
225 .scl_pin = I2C_SCL,
226 .scl_is_open_drain = 0,
227 .udelay = 2,
228};
229
230static struct platform_device hsi2c_gpio_device = {
231 .name = "i2c-gpio",
232 .id = 0,
233 .dev.platform_data = &pdata,
234};
235
236static struct mcp251x_platform_data mcp251x_info = {
237 .oscillator_frequency = 24E6,
238};
239
240static struct spi_board_info cpuimx51sd_spi_device[] = {
241 {
242 .modalias = "mcp2515",
243 .max_speed_hz = 10000000,
244 .bus_num = 0,
245 .mode = SPI_MODE_0,
246 .chip_select = 0,
247 .platform_data = &mcp251x_info,
248 .irq = gpio_to_irq(CAN_IRQGPIO)
249 },
250};
251
252static int cpuimx51sd_spi1_cs[] = {
253 CAN_NCS,
254};
255
256static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
257 .chipselect = cpuimx51sd_spi1_cs,
258 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
259};
260
261static struct platform_device *platform_devices[] __initdata = {
262 &hsi2c_gpio_device,
263};
264
265static void __init eukrea_cpuimx51sd_init(void)
266{
267 imx51_soc_init();
268
269 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
270 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
271
272#if defined(CONFIG_CPU_FREQ_IMX)
273 get_cpu_op = mx51_get_cpu_op;
274#endif
275
276 imx51_add_imx_uart(0, &uart_pdata);
277 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
278
279 gpio_request(ETH_RST, "eth_rst");
280 gpio_set_value(ETH_RST, 1);
281 imx51_add_fec(NULL);
282
283 gpio_request(CAN_IRQGPIO, "can_irq");
284 gpio_direction_input(CAN_IRQGPIO);
285 gpio_free(CAN_IRQGPIO);
286 gpio_request(CAN_NCS, "can_ncs");
287 gpio_direction_output(CAN_NCS, 1);
288 gpio_free(CAN_NCS);
289 gpio_request(CAN_RST, "can_rst");
290 gpio_direction_output(CAN_RST, 0);
291 msleep(20);
292 gpio_set_value(CAN_RST, 1);
293 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
294 spi_register_board_info(cpuimx51sd_spi_device,
295 ARRAY_SIZE(cpuimx51sd_spi_device));
296
297 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
298 gpio_direction_input(TSC2007_IRQGPIO);
299 gpio_free(TSC2007_IRQGPIO);
300
301 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
302 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
303 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
304
305 if (otg_mode_host)
306 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
307 else {
308 initialize_otg_port(NULL);
309 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
310 }
311
312 gpio_request(USBH1_RST, "usb_rst");
313 gpio_direction_output(USBH1_RST, 0);
314 msleep(20);
315 gpio_set_value(USBH1_RST, 1);
316 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
317
318#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
319 eukrea_mbimxsd51_baseboard_init();
320#endif
321}
322
323static void __init eukrea_cpuimx51sd_timer_init(void)
324{
325 mx51_clocks_init(32768, 24000000, 22579200, 0);
326}
327
328static struct sys_timer mxc_timer = {
329 .init = eukrea_cpuimx51sd_timer_init,
330};
331
332MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
333 /* Maintainer: Eric Bénard <eric@eukrea.com> */
334 .boot_params = MX51_PHYS_OFFSET + 0x100,
335 .map_io = mx51_map_io,
336 .init_early = imx51_init_early,
337 .init_irq = mx51_init_irq,
338 .timer = &mxc_timer,
339 .init_machine = eukrea_cpuimx51sd_init,
340MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
new file mode 100644
index 00000000000..7de25c6712e
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -0,0 +1,224 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx50.h>
30
31#include <asm/irq.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx50.h"
38
39#define FEC_EN IMX_GPIO_NR(6, 23)
40#define FEC_RESET_B IMX_GPIO_NR(4, 12)
41
42static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
43 /* SD1 */
44 MX50_PAD_ECSPI2_SS0__GPIO_4_19,
45 MX50_PAD_EIM_CRE__GPIO_1_27,
46 MX50_PAD_SD1_CMD__SD1_CMD,
47
48 MX50_PAD_SD1_CLK__SD1_CLK,
49 MX50_PAD_SD1_D0__SD1_D0,
50 MX50_PAD_SD1_D1__SD1_D1,
51 MX50_PAD_SD1_D2__SD1_D2,
52 MX50_PAD_SD1_D3__SD1_D3,
53
54 /* SD2 */
55 MX50_PAD_SD2_CD__GPIO_5_17,
56 MX50_PAD_SD2_WP__GPIO_5_16,
57 MX50_PAD_SD2_CMD__SD2_CMD,
58 MX50_PAD_SD2_CLK__SD2_CLK,
59 MX50_PAD_SD2_D0__SD2_D0,
60 MX50_PAD_SD2_D1__SD2_D1,
61 MX50_PAD_SD2_D2__SD2_D2,
62 MX50_PAD_SD2_D3__SD2_D3,
63 MX50_PAD_SD2_D4__SD2_D4,
64 MX50_PAD_SD2_D5__SD2_D5,
65 MX50_PAD_SD2_D6__SD2_D6,
66 MX50_PAD_SD2_D7__SD2_D7,
67
68 /* SD3 */
69 MX50_PAD_SD3_CMD__SD3_CMD,
70 MX50_PAD_SD3_CLK__SD3_CLK,
71 MX50_PAD_SD3_D0__SD3_D0,
72 MX50_PAD_SD3_D1__SD3_D1,
73 MX50_PAD_SD3_D2__SD3_D2,
74 MX50_PAD_SD3_D3__SD3_D3,
75 MX50_PAD_SD3_D4__SD3_D4,
76 MX50_PAD_SD3_D5__SD3_D5,
77 MX50_PAD_SD3_D6__SD3_D6,
78 MX50_PAD_SD3_D7__SD3_D7,
79
80 /* PWR_INT */
81 MX50_PAD_ECSPI2_MISO__GPIO_4_18,
82
83 /* UART pad setting */
84 MX50_PAD_UART1_TXD__UART1_TXD,
85 MX50_PAD_UART1_RXD__UART1_RXD,
86 MX50_PAD_UART1_RTS__UART1_RTS,
87 MX50_PAD_UART2_TXD__UART2_TXD,
88 MX50_PAD_UART2_RXD__UART2_RXD,
89 MX50_PAD_UART2_CTS__UART2_CTS,
90 MX50_PAD_UART2_RTS__UART2_RTS,
91
92 MX50_PAD_I2C1_SCL__I2C1_SCL,
93 MX50_PAD_I2C1_SDA__I2C1_SDA,
94 MX50_PAD_I2C2_SCL__I2C2_SCL,
95 MX50_PAD_I2C2_SDA__I2C2_SDA,
96
97 MX50_PAD_EPITO__USBH1_PWR,
98 /* Need to comment below line if
99 * one needs to debug owire.
100 */
101 MX50_PAD_OWIRE__USBH1_OC,
102 /* using gpio to control otg pwr */
103 MX50_PAD_PWM2__GPIO_6_25,
104 MX50_PAD_I2C3_SCL__USBOTG_OC,
105
106 MX50_PAD_SSI_RXC__FEC_MDIO,
107 MX50_PAD_SSI_RXFS__FEC_MDC,
108 MX50_PAD_DISP_D0__FEC_TXCLK,
109 MX50_PAD_DISP_D1__FEC_RX_ER,
110 MX50_PAD_DISP_D2__FEC_RX_DV,
111 MX50_PAD_DISP_D3__FEC_RXD1,
112 MX50_PAD_DISP_D4__FEC_RXD0,
113 MX50_PAD_DISP_D5__FEC_TX_EN,
114 MX50_PAD_DISP_D6__FEC_TXD1,
115 MX50_PAD_DISP_D7__FEC_TXD0,
116 MX50_PAD_I2C3_SDA__GPIO_6_23,
117 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
118
119 MX50_PAD_CSPI_SS0__CSPI_SS0,
120 MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
121 MX50_PAD_CSPI_MOSI__CSPI_MOSI,
122 MX50_PAD_CSPI_MISO__CSPI_MISO,
123
124 /* SGTL500_OSC_EN */
125 MX50_PAD_UART1_CTS__GPIO_6_8,
126
127 /* SGTL_AMP_SHDN */
128 MX50_PAD_UART3_RXD__GPIO_6_15,
129
130 /* Keypad */
131 MX50_PAD_KEY_COL0__KEY_COL0,
132 MX50_PAD_KEY_ROW0__KEY_ROW0,
133 MX50_PAD_KEY_COL1__KEY_COL1,
134 MX50_PAD_KEY_ROW1__KEY_ROW1,
135 MX50_PAD_KEY_COL2__KEY_COL2,
136 MX50_PAD_KEY_ROW2__KEY_ROW2,
137 MX50_PAD_KEY_COL3__KEY_COL3,
138 MX50_PAD_KEY_ROW3__KEY_ROW3,
139 MX50_PAD_EIM_DA0__KEY_COL4,
140 MX50_PAD_EIM_DA1__KEY_ROW4,
141 MX50_PAD_EIM_DA2__KEY_COL5,
142 MX50_PAD_EIM_DA3__KEY_ROW5,
143 MX50_PAD_EIM_DA4__KEY_COL6,
144 MX50_PAD_EIM_DA5__KEY_ROW6,
145 MX50_PAD_EIM_DA6__KEY_COL7,
146 MX50_PAD_EIM_DA7__KEY_ROW7,
147 /*EIM pads */
148 MX50_PAD_EIM_DA8__GPIO_1_8,
149 MX50_PAD_EIM_DA9__GPIO_1_9,
150 MX50_PAD_EIM_DA10__GPIO_1_10,
151 MX50_PAD_EIM_DA11__GPIO_1_11,
152 MX50_PAD_EIM_DA12__GPIO_1_12,
153 MX50_PAD_EIM_DA13__GPIO_1_13,
154 MX50_PAD_EIM_DA14__GPIO_1_14,
155 MX50_PAD_EIM_DA15__GPIO_1_15,
156 MX50_PAD_EIM_CS2__GPIO_1_16,
157 MX50_PAD_EIM_CS1__GPIO_1_17,
158 MX50_PAD_EIM_CS0__GPIO_1_18,
159 MX50_PAD_EIM_EB0__GPIO_1_19,
160 MX50_PAD_EIM_EB1__GPIO_1_20,
161 MX50_PAD_EIM_WAIT__GPIO_1_21,
162 MX50_PAD_EIM_BCLK__GPIO_1_22,
163 MX50_PAD_EIM_RDY__GPIO_1_23,
164 MX50_PAD_EIM_OE__GPIO_1_24,
165};
166
167/* Serial ports */
168static const struct imxuart_platform_data uart_pdata __initconst = {
169 .flags = IMXUART_HAVE_RTSCTS,
170};
171
172static const struct fec_platform_data fec_data __initconst = {
173 .phy = PHY_INTERFACE_MODE_RMII,
174};
175
176static inline void mx50_rdp_fec_reset(void)
177{
178 gpio_request(FEC_EN, "fec-en");
179 gpio_direction_output(FEC_EN, 0);
180 gpio_request(FEC_RESET_B, "fec-reset_b");
181 gpio_direction_output(FEC_RESET_B, 0);
182 msleep(1);
183 gpio_set_value(FEC_RESET_B, 1);
184}
185
186static const struct imxi2c_platform_data i2c_data __initconst = {
187 .bitrate = 100000,
188};
189
190/*
191 * Board specific initialization.
192 */
193static void __init mx50_rdp_board_init(void)
194{
195 imx50_soc_init();
196
197 mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
198 ARRAY_SIZE(mx50_rdp_pads));
199
200 imx50_add_imx_uart(0, &uart_pdata);
201 imx50_add_imx_uart(1, &uart_pdata);
202 mx50_rdp_fec_reset();
203 imx50_add_fec(&fec_data);
204 imx50_add_imx_i2c(0, &i2c_data);
205 imx50_add_imx_i2c(1, &i2c_data);
206 imx50_add_imx_i2c(2, &i2c_data);
207}
208
209static void __init mx50_rdp_timer_init(void)
210{
211 mx50_clocks_init(32768, 24000000, 22579200);
212}
213
214static struct sys_timer mx50_rdp_timer = {
215 .init = mx50_rdp_timer_init,
216};
217
218MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
219 .map_io = mx50_map_io,
220 .init_early = imx50_init_early,
221 .init_irq = mx50_init_irq,
222 .timer = &mx50_rdp_timer,
223 .init_machine = mx50_rdp_board_init,
224MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 00000000000..07a38154da2
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,178 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/hardware.h>
23#include <mach/common.h>
24#include <mach/iomux-mx51.h>
25#include <mach/3ds_debugboard.h>
26
27#include "devices-imx51.h"
28#include "devices.h"
29
30#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
31#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
32
33static iomux_v3_cfg_t mx51_3ds_pads[] = {
34 /* UART1 */
35 MX51_PAD_UART1_RXD__UART1_RXD,
36 MX51_PAD_UART1_TXD__UART1_TXD,
37 MX51_PAD_UART1_RTS__UART1_RTS,
38 MX51_PAD_UART1_CTS__UART1_CTS,
39
40 /* UART2 */
41 MX51_PAD_UART2_RXD__UART2_RXD,
42 MX51_PAD_UART2_TXD__UART2_TXD,
43 MX51_PAD_EIM_D25__UART2_CTS,
44 MX51_PAD_EIM_D26__UART2_RTS,
45
46 /* UART3 */
47 MX51_PAD_UART3_RXD__UART3_RXD,
48 MX51_PAD_UART3_TXD__UART3_TXD,
49 MX51_PAD_EIM_D24__UART3_CTS,
50 MX51_PAD_EIM_D27__UART3_RTS,
51
52 /* CPLD PARENT IRQ PIN */
53 MX51_PAD_GPIO1_6__GPIO1_6,
54
55 /* KPP */
56 MX51_PAD_KEY_ROW0__KEY_ROW0,
57 MX51_PAD_KEY_ROW1__KEY_ROW1,
58 MX51_PAD_KEY_ROW2__KEY_ROW2,
59 MX51_PAD_KEY_ROW3__KEY_ROW3,
60 MX51_PAD_KEY_COL0__KEY_COL0,
61 MX51_PAD_KEY_COL1__KEY_COL1,
62 MX51_PAD_KEY_COL2__KEY_COL2,
63 MX51_PAD_KEY_COL3__KEY_COL3,
64 MX51_PAD_KEY_COL4__KEY_COL4,
65 MX51_PAD_KEY_COL5__KEY_COL5,
66
67 /* eCSPI2 */
68 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
69 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
70 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
71 MX51_PAD_NANDF_D12__GPIO3_28,
72};
73
74/* Serial ports */
75static const struct imxuart_platform_data uart_pdata __initconst = {
76 .flags = IMXUART_HAVE_RTSCTS,
77};
78
79static int mx51_3ds_board_keymap[] = {
80 KEY(0, 0, KEY_1),
81 KEY(0, 1, KEY_2),
82 KEY(0, 2, KEY_3),
83 KEY(0, 3, KEY_F1),
84 KEY(0, 4, KEY_UP),
85 KEY(0, 5, KEY_F2),
86
87 KEY(1, 0, KEY_4),
88 KEY(1, 1, KEY_5),
89 KEY(1, 2, KEY_6),
90 KEY(1, 3, KEY_LEFT),
91 KEY(1, 4, KEY_SELECT),
92 KEY(1, 5, KEY_RIGHT),
93
94 KEY(2, 0, KEY_7),
95 KEY(2, 1, KEY_8),
96 KEY(2, 2, KEY_9),
97 KEY(2, 3, KEY_F3),
98 KEY(2, 4, KEY_DOWN),
99 KEY(2, 5, KEY_F4),
100
101 KEY(3, 0, KEY_0),
102 KEY(3, 1, KEY_OK),
103 KEY(3, 2, KEY_ESC),
104 KEY(3, 3, KEY_ENTER),
105 KEY(3, 4, KEY_MENU),
106 KEY(3, 5, KEY_BACK)
107};
108
109static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
110 .keymap = mx51_3ds_board_keymap,
111 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
112};
113
114static int mx51_3ds_spi2_cs[] = {
115 MXC_SPI_CS(0),
116 MX51_3DS_ECSPI2_CS,
117};
118
119static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
120 .chipselect = mx51_3ds_spi2_cs,
121 .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
122};
123
124static struct spi_board_info mx51_3ds_spi_nor_device[] = {
125 {
126 .modalias = "m25p80",
127 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
128 .bus_num = 1,
129 .chip_select = 1,
130 .mode = SPI_MODE_0,
131 .platform_data = NULL,},
132};
133
134/*
135 * Board specific initialization.
136 */
137static void __init mx51_3ds_init(void)
138{
139 imx51_soc_init();
140
141 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
142 ARRAY_SIZE(mx51_3ds_pads));
143
144 imx51_add_imx_uart(0, &uart_pdata);
145 imx51_add_imx_uart(1, &uart_pdata);
146 imx51_add_imx_uart(2, &uart_pdata);
147
148 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
149 spi_register_board_info(mx51_3ds_spi_nor_device,
150 ARRAY_SIZE(mx51_3ds_spi_nor_device));
151
152 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
153 printk(KERN_WARNING "Init of the debugboard failed, all "
154 "devices on the board are unusable.\n");
155
156 imx51_add_sdhci_esdhc_imx(0, NULL);
157 imx51_add_imx_keypad(&mx51_3ds_map_data);
158 imx51_add_imx2_wdt(0, NULL);
159}
160
161static void __init mx51_3ds_timer_init(void)
162{
163 mx51_clocks_init(32768, 24000000, 22579200, 0);
164}
165
166static struct sys_timer mx51_3ds_timer = {
167 .init = mx51_3ds_timer_init,
168};
169
170MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
171 /* Maintainer: Freescale Semiconductor, Inc. */
172 .boot_params = MX51_PHYS_OFFSET + 0x100,
173 .map_io = mx51_map_io,
174 .init_early = imx51_init_early,
175 .init_irq = mx51_init_irq,
176 .timer = &mx51_3ds_timer,
177 .init_machine = mx51_3ds_init,
178MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
new file mode 100644
index 00000000000..11b0ff67f89
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -0,0 +1,425 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/i2c.h>
16#include <linux/gpio.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/input.h>
20#include <linux/spi/flash.h>
21#include <linux/spi/spi.h>
22
23#include <mach/common.h>
24#include <mach/hardware.h>
25#include <mach/iomux-mx51.h>
26
27#include <asm/irq.h>
28#include <asm/setup.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/time.h>
32
33#include "devices-imx51.h"
34#include "devices.h"
35#include "cpu_op-mx51.h"
36
37#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
38#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
39#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
40#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
41#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
42#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
43#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
44#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
45#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
46
47/* USB_CTRL_1 */
48#define MX51_USB_CTRL_1_OFFSET 0x10
49#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
50
51#define MX51_USB_PLLDIV_12_MHZ 0x00
52#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
53#define MX51_USB_PLL_DIV_24_MHZ 0x02
54
55static struct gpio_keys_button babbage_buttons[] = {
56 {
57 .gpio = BABBAGE_POWER_KEY,
58 .code = BTN_0,
59 .desc = "PWR",
60 .active_low = 1,
61 .wakeup = 1,
62 },
63};
64
65static const struct gpio_keys_platform_data imx_button_data __initconst = {
66 .buttons = babbage_buttons,
67 .nbuttons = ARRAY_SIZE(babbage_buttons),
68};
69
70static iomux_v3_cfg_t mx51babbage_pads[] = {
71 /* UART1 */
72 MX51_PAD_UART1_RXD__UART1_RXD,
73 MX51_PAD_UART1_TXD__UART1_TXD,
74 MX51_PAD_UART1_RTS__UART1_RTS,
75 MX51_PAD_UART1_CTS__UART1_CTS,
76
77 /* UART2 */
78 MX51_PAD_UART2_RXD__UART2_RXD,
79 MX51_PAD_UART2_TXD__UART2_TXD,
80
81 /* UART3 */
82 MX51_PAD_EIM_D25__UART3_RXD,
83 MX51_PAD_EIM_D26__UART3_TXD,
84 MX51_PAD_EIM_D27__UART3_RTS,
85 MX51_PAD_EIM_D24__UART3_CTS,
86
87 /* I2C1 */
88 MX51_PAD_EIM_D16__I2C1_SDA,
89 MX51_PAD_EIM_D19__I2C1_SCL,
90
91 /* I2C2 */
92 MX51_PAD_KEY_COL4__I2C2_SCL,
93 MX51_PAD_KEY_COL5__I2C2_SDA,
94
95 /* HSI2C */
96 MX51_PAD_I2C1_CLK__I2C1_CLK,
97 MX51_PAD_I2C1_DAT__I2C1_DAT,
98
99 /* USB HOST1 */
100 MX51_PAD_USBH1_CLK__USBH1_CLK,
101 MX51_PAD_USBH1_DIR__USBH1_DIR,
102 MX51_PAD_USBH1_NXT__USBH1_NXT,
103 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
104 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
105 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
106 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
107 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
108 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
109 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
110 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
111
112 /* USB HUB reset line*/
113 MX51_PAD_GPIO1_7__GPIO1_7,
114
115 /* USB PHY reset line */
116 MX51_PAD_EIM_D21__GPIO2_5,
117
118 /* FEC */
119 MX51_PAD_EIM_EB2__FEC_MDIO,
120 MX51_PAD_EIM_EB3__FEC_RDATA1,
121 MX51_PAD_EIM_CS2__FEC_RDATA2,
122 MX51_PAD_EIM_CS3__FEC_RDATA3,
123 MX51_PAD_EIM_CS4__FEC_RX_ER,
124 MX51_PAD_EIM_CS5__FEC_CRS,
125 MX51_PAD_NANDF_RB2__FEC_COL,
126 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
127 MX51_PAD_NANDF_D9__FEC_RDATA0,
128 MX51_PAD_NANDF_D8__FEC_TDATA0,
129 MX51_PAD_NANDF_CS2__FEC_TX_ER,
130 MX51_PAD_NANDF_CS3__FEC_MDC,
131 MX51_PAD_NANDF_CS4__FEC_TDATA1,
132 MX51_PAD_NANDF_CS5__FEC_TDATA2,
133 MX51_PAD_NANDF_CS6__FEC_TDATA3,
134 MX51_PAD_NANDF_CS7__FEC_TX_EN,
135 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
136
137 /* FEC PHY reset line */
138 MX51_PAD_EIM_A20__GPIO2_14,
139
140 /* SD 1 */
141 MX51_PAD_SD1_CMD__SD1_CMD,
142 MX51_PAD_SD1_CLK__SD1_CLK,
143 MX51_PAD_SD1_DATA0__SD1_DATA0,
144 MX51_PAD_SD1_DATA1__SD1_DATA1,
145 MX51_PAD_SD1_DATA2__SD1_DATA2,
146 MX51_PAD_SD1_DATA3__SD1_DATA3,
147 /* CD/WP from controller */
148 MX51_PAD_GPIO1_0__SD1_CD,
149 MX51_PAD_GPIO1_1__SD1_WP,
150
151 /* SD 2 */
152 MX51_PAD_SD2_CMD__SD2_CMD,
153 MX51_PAD_SD2_CLK__SD2_CLK,
154 MX51_PAD_SD2_DATA0__SD2_DATA0,
155 MX51_PAD_SD2_DATA1__SD2_DATA1,
156 MX51_PAD_SD2_DATA2__SD2_DATA2,
157 MX51_PAD_SD2_DATA3__SD2_DATA3,
158 /* CD/WP gpio */
159 MX51_PAD_GPIO1_6__GPIO1_6,
160 MX51_PAD_GPIO1_5__GPIO1_5,
161
162 /* eCSPI1 */
163 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
164 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
165 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
166 MX51_PAD_CSPI1_SS0__GPIO4_24,
167 MX51_PAD_CSPI1_SS1__GPIO4_25,
168};
169
170/* Serial ports */
171static const struct imxuart_platform_data uart_pdata __initconst = {
172 .flags = IMXUART_HAVE_RTSCTS,
173};
174
175static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
176 .bitrate = 100000,
177};
178
179static struct imxi2c_platform_data babbage_hsi2c_data = {
180 .bitrate = 400000,
181};
182
183static struct gpio mx51_babbage_usbh1_gpios[] = {
184 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
185 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
186};
187
188static int gpio_usbh1_active(void)
189{
190 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
191 int ret;
192
193 /* Set USBH1_STP to GPIO and toggle it */
194 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
195 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
196 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
197
198 if (ret) {
199 pr_debug("failed to get USBH1 pins: %d\n", ret);
200 return ret;
201 }
202
203 msleep(100);
204 gpio_set_value(BABBAGE_USBH1_STP, 1);
205 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
206 gpio_free_array(mx51_babbage_usbh1_gpios,
207 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
208 return 0;
209}
210
211static inline void babbage_usbhub_reset(void)
212{
213 int ret;
214
215 /* Reset USB hub */
216 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
217 GPIOF_OUT_INIT_LOW, "GPIO1_7");
218 if (ret) {
219 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
220 return;
221 }
222
223 msleep(2);
224 /* Deassert reset */
225 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
226}
227
228static inline void babbage_fec_reset(void)
229{
230 int ret;
231
232 /* reset FEC PHY */
233 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
234 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
235 if (ret) {
236 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
237 return;
238 }
239 msleep(1);
240 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
241}
242
243/* This function is board specific as the bit mask for the plldiv will also
244be different for other Freescale SoCs, thus a common bitmask is not
245possible and cannot get place in /plat-mxc/ehci.c.*/
246static int initialize_otg_port(struct platform_device *pdev)
247{
248 u32 v;
249 void __iomem *usb_base;
250 void __iomem *usbother_base;
251
252 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
253 if (!usb_base)
254 return -ENOMEM;
255 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
256
257 /* Set the PHY clock to 19.2MHz */
258 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
259 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
260 v |= MX51_USB_PLL_DIV_19_2_MHZ;
261 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
262 iounmap(usb_base);
263
264 mdelay(10);
265
266 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
267}
268
269static int initialize_usbh1_port(struct platform_device *pdev)
270{
271 u32 v;
272 void __iomem *usb_base;
273 void __iomem *usbother_base;
274
275 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
276 if (!usb_base)
277 return -ENOMEM;
278 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
279
280 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
281 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
282 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
283 iounmap(usb_base);
284
285 mdelay(10);
286
287 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
288 MXC_EHCI_ITC_NO_THRESHOLD);
289}
290
291static struct mxc_usbh_platform_data dr_utmi_config = {
292 .init = initialize_otg_port,
293 .portsc = MXC_EHCI_UTMI_16BIT,
294};
295
296static struct fsl_usb2_platform_data usb_pdata = {
297 .operating_mode = FSL_USB2_DR_DEVICE,
298 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
299};
300
301static struct mxc_usbh_platform_data usbh1_config = {
302 .init = initialize_usbh1_port,
303 .portsc = MXC_EHCI_MODE_ULPI,
304};
305
306static int otg_mode_host;
307
308static int __init babbage_otg_mode(char *options)
309{
310 if (!strcmp(options, "host"))
311 otg_mode_host = 1;
312 else if (!strcmp(options, "device"))
313 otg_mode_host = 0;
314 else
315 pr_info("otg_mode neither \"host\" nor \"device\". "
316 "Defaulting to device\n");
317 return 0;
318}
319__setup("otg_mode=", babbage_otg_mode);
320
321static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
322 {
323 .modalias = "mtd_dataflash",
324 .max_speed_hz = 25000000,
325 .bus_num = 0,
326 .chip_select = 1,
327 .mode = SPI_MODE_0,
328 .platform_data = NULL,
329 },
330};
331
332static int mx51_babbage_spi_cs[] = {
333 BABBAGE_ECSPI1_CS0,
334 BABBAGE_ECSPI1_CS1,
335};
336
337static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
338 .chipselect = mx51_babbage_spi_cs,
339 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
340};
341
342static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
343 .cd_type = ESDHC_CD_CONTROLLER,
344 .wp_type = ESDHC_WP_CONTROLLER,
345};
346
347static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
348 .cd_gpio = BABBAGE_SD2_CD,
349 .wp_gpio = BABBAGE_SD2_WP,
350 .cd_type = ESDHC_CD_GPIO,
351 .wp_type = ESDHC_WP_GPIO,
352};
353
354/*
355 * Board specific initialization.
356 */
357static void __init mx51_babbage_init(void)
358{
359 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
360 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
361 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
362
363 imx51_soc_init();
364
365#if defined(CONFIG_CPU_FREQ_IMX)
366 get_cpu_op = mx51_get_cpu_op;
367#endif
368 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
369 ARRAY_SIZE(mx51babbage_pads));
370
371 imx51_add_imx_uart(0, &uart_pdata);
372 imx51_add_imx_uart(1, NULL);
373 imx51_add_imx_uart(2, &uart_pdata);
374
375 babbage_fec_reset();
376 imx51_add_fec(NULL);
377
378 /* Set the PAD settings for the pwr key. */
379 mxc_iomux_v3_setup_pad(power_key);
380 imx_add_gpio_keys(&imx_button_data);
381
382 imx51_add_imx_i2c(0, &babbage_i2c_data);
383 imx51_add_imx_i2c(1, &babbage_i2c_data);
384 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
385
386 if (otg_mode_host)
387 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
388 else {
389 initialize_otg_port(NULL);
390 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
391 }
392
393 gpio_usbh1_active();
394 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
395 /* setback USBH1_STP to be function */
396 mxc_iomux_v3_setup_pad(usbh1stp);
397 babbage_usbhub_reset();
398
399 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
400 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
401
402 spi_register_board_info(mx51_babbage_spi_board_info,
403 ARRAY_SIZE(mx51_babbage_spi_board_info));
404 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
405 imx51_add_imx2_wdt(0, NULL);
406}
407
408static void __init mx51_babbage_timer_init(void)
409{
410 mx51_clocks_init(32768, 24000000, 22579200, 0);
411}
412
413static struct sys_timer mx51_babbage_timer = {
414 .init = mx51_babbage_timer_init,
415};
416
417MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
418 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
419 .boot_params = MX51_PHYS_OFFSET + 0x100,
420 .map_io = mx51_map_io,
421 .init_early = imx51_init_early,
422 .init_irq = mx51_init_irq,
423 .timer = &mx51_babbage_timer,
424 .init_machine = mx51_babbage_init,
425MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 00000000000..551daf85ff8
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,289 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30
31#include <mach/common.h>
32#include <mach/hardware.h>
33#include <mach/iomux-mx51.h>
34
35#include <asm/irq.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41#include "devices-imx51.h"
42#include "devices.h"
43#include "efika.h"
44
45#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
46#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
47#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
48
49#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
50#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
51#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
52
53#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
54
55/* board 1.1 doesn't have same reset gpio */
56#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
57#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
58
59#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
60
61#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
62
63/* the pci ids pin have pull up. they're driven low according to board id */
64#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
66#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
67#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
68
69static iomux_v3_cfg_t mx51efikamx_pads[] = {
70 /* board id */
71 MX51_PAD_PCBID0,
72 MX51_PAD_PCBID1,
73 MX51_PAD_PCBID2,
74
75 /* leds */
76 MX51_PAD_CSI1_D9__GPIO3_13,
77 MX51_PAD_CSI1_VSYNC__GPIO3_14,
78 MX51_PAD_CSI1_HSYNC__GPIO3_15,
79
80 /* power key */
81 MX51_PAD_PWRKEY,
82
83 /* reset */
84 MX51_PAD_DI1_PIN13__GPIO3_2,
85 MX51_PAD_GPIO1_4__GPIO1_4,
86
87 /* power off */
88 MX51_PAD_CSI2_VSYNC__GPIO4_13,
89};
90
91/* PCBID2 PCBID1 PCBID0 STATE
92 1 1 1 ER1:rev1.1
93 1 1 0 ER2:rev1.2
94 1 0 1 ER3:rev1.3
95 1 0 0 ER4:rev1.4
96*/
97static void __init mx51_efikamx_board_id(void)
98{
99 int id;
100
101 /* things are taking time to settle */
102 msleep(150);
103
104 gpio_request(EFIKAMX_PCBID0, "pcbid0");
105 gpio_direction_input(EFIKAMX_PCBID0);
106 gpio_request(EFIKAMX_PCBID1, "pcbid1");
107 gpio_direction_input(EFIKAMX_PCBID1);
108 gpio_request(EFIKAMX_PCBID2, "pcbid2");
109 gpio_direction_input(EFIKAMX_PCBID2);
110
111 id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
112 id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
113 id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
114
115 switch (id) {
116 case 7:
117 system_rev = 0x11;
118 break;
119 case 6:
120 system_rev = 0x12;
121 break;
122 case 5:
123 system_rev = 0x13;
124 break;
125 case 4:
126 system_rev = 0x14;
127 break;
128 default:
129 system_rev = 0x10;
130 break;
131 }
132
133 if ((system_rev == 0x10)
134 || (system_rev == 0x12)
135 || (system_rev == 0x14)) {
136 printk(KERN_WARNING
137 "EfikaMX: Unsupported board revision 1.%u!\n",
138 system_rev & 0xf);
139 }
140}
141
142static struct gpio_led mx51_efikamx_leds[] __initdata = {
143 {
144 .name = "efikamx:green",
145 .default_trigger = "default-on",
146 .gpio = EFIKAMX_GREEN_LED,
147 },
148 {
149 .name = "efikamx:red",
150 .default_trigger = "ide-disk",
151 .gpio = EFIKAMX_RED_LED,
152 },
153 {
154 .name = "efikamx:blue",
155 .default_trigger = "mmc0",
156 .gpio = EFIKAMX_BLUE_LED,
157 },
158};
159
160static const struct gpio_led_platform_data
161 mx51_efikamx_leds_data __initconst = {
162 .leds = mx51_efikamx_leds,
163 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
164};
165
166static struct gpio_keys_button mx51_efikamx_powerkey[] = {
167 {
168 .code = KEY_POWER,
169 .gpio = EFIKAMX_POWER_KEY,
170 .type = EV_PWR,
171 .desc = "Power Button (CM)",
172 .wakeup = 1,
173 .debounce_interval = 10, /* ms */
174 },
175};
176
177static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
178 .buttons = mx51_efikamx_powerkey,
179 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
180};
181
182void mx51_efikamx_reset(void)
183{
184 if (system_rev == 0x11)
185 gpio_direction_output(EFIKAMX_RESET1_1, 0);
186 else
187 gpio_direction_output(EFIKAMX_RESET, 0);
188}
189
190static struct regulator *pwgt1, *pwgt2, *coincell;
191
192static void mx51_efikamx_power_off(void)
193{
194 if (!IS_ERR(coincell))
195 regulator_disable(coincell);
196
197 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
198 regulator_disable(pwgt2);
199 regulator_disable(pwgt1);
200 }
201 gpio_direction_output(EFIKAMX_POWEROFF, 1);
202}
203
204static int __init mx51_efikamx_power_init(void)
205{
206 if (machine_is_mx51_efikamx()) {
207 pwgt1 = regulator_get(NULL, "pwgt1");
208 pwgt2 = regulator_get(NULL, "pwgt2");
209 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
210 regulator_enable(pwgt1);
211 regulator_enable(pwgt2);
212 }
213 gpio_request(EFIKAMX_POWEROFF, "poweroff");
214 pm_power_off = mx51_efikamx_power_off;
215
216 /* enable coincell charger. maybe need a small power driver ? */
217 coincell = regulator_get(NULL, "coincell");
218 if (!IS_ERR(coincell)) {
219 regulator_set_voltage(coincell, 3000000, 3000000);
220 regulator_enable(coincell);
221 }
222
223 regulator_has_full_constraints();
224 }
225
226 return 0;
227}
228late_initcall(mx51_efikamx_power_init);
229
230static void __init mx51_efikamx_init(void)
231{
232 imx51_soc_init();
233
234 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
235 ARRAY_SIZE(mx51efikamx_pads));
236 efika_board_common_init();
237
238 mx51_efikamx_board_id();
239
240 /* on < 1.2 boards both SD controllers are used */
241 if (system_rev < 0x12) {
242 imx51_add_sdhci_esdhc_imx(1, NULL);
243 mx51_efikamx_leds[2].default_trigger = "mmc1";
244 }
245
246 gpio_led_register_device(-1, &mx51_efikamx_leds_data);
247 imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
248
249 if (system_rev == 0x11) {
250 gpio_request(EFIKAMX_RESET1_1, "reset");
251 gpio_direction_output(EFIKAMX_RESET1_1, 1);
252 } else {
253 gpio_request(EFIKAMX_RESET, "reset");
254 gpio_direction_output(EFIKAMX_RESET, 1);
255 }
256
257 /*
258 * enable wifi by default only on mx
259 * sb and mx have same wlan pin but the value to enable it are
260 * different :/
261 */
262 gpio_request(EFIKA_WLAN_EN, "wlan_en");
263 gpio_direction_output(EFIKA_WLAN_EN, 0);
264 msleep(10);
265
266 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
267 gpio_direction_output(EFIKA_WLAN_RESET, 0);
268 msleep(10);
269 gpio_set_value(EFIKA_WLAN_RESET, 1);
270}
271
272static void __init mx51_efikamx_timer_init(void)
273{
274 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
275}
276
277static struct sys_timer mx51_efikamx_timer = {
278 .init = mx51_efikamx_timer_init,
279};
280
281MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
282 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
283 .boot_params = MX51_PHYS_OFFSET + 0x100,
284 .map_io = mx51_map_io,
285 .init_early = imx51_init_early,
286 .init_irq = mx51_init_irq,
287 .timer = &mx51_efikamx_timer,
288 .init_machine = mx51_efikamx_init,
289MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 00000000000..8a9bca22beb
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,275 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <mach/ulpi.h>
33
34#include <mach/common.h>
35#include <mach/hardware.h>
36#include <mach/iomux-mx51.h>
37
38#include <asm/irq.h>
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/time.h>
43
44#include "devices-imx51.h"
45#include "devices.h"
46#include "efika.h"
47
48#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
49#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
50#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
51#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
52#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
53#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
54#define EFIKASB_LID IMX_GPIO_NR(3, 14)
55#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
56#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
57
58#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
59
60static iomux_v3_cfg_t mx51efikasb_pads[] = {
61 /* USB HOST2 */
62 MX51_PAD_EIM_D16__USBH2_DATA0,
63 MX51_PAD_EIM_D17__USBH2_DATA1,
64 MX51_PAD_EIM_D18__USBH2_DATA2,
65 MX51_PAD_EIM_D19__USBH2_DATA3,
66 MX51_PAD_EIM_D20__USBH2_DATA4,
67 MX51_PAD_EIM_D21__USBH2_DATA5,
68 MX51_PAD_EIM_D22__USBH2_DATA6,
69 MX51_PAD_EIM_D23__USBH2_DATA7,
70 MX51_PAD_EIM_A24__USBH2_CLK,
71 MX51_PAD_EIM_A25__USBH2_DIR,
72 MX51_PAD_EIM_A26__USBH2_STP,
73 MX51_PAD_EIM_A27__USBH2_NXT,
74
75 /* leds */
76 MX51_PAD_EIM_CS0__GPIO2_25,
77 MX51_PAD_GPIO1_3__GPIO1_3,
78
79 /* pcb id */
80 MX51_PAD_EIM_CS3__GPIO2_28,
81 MX51_PAD_EIM_CS4__GPIO2_29,
82
83 /* lid */
84 MX51_PAD_CSI1_VSYNC__GPIO3_14,
85
86 /* power key*/
87 MX51_PAD_PWRKEY,
88
89 /* wifi/bt button */
90 MX51_PAD_DI1_PIN12__GPIO3_1,
91
92 /* power off */
93 MX51_PAD_CSI2_VSYNC__GPIO4_13,
94
95 /* wdog reset */
96 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
97
98 /* BT */
99 MX51_PAD_EIM_A17__GPIO2_11,
100};
101
102static int initialize_usbh2_port(struct platform_device *pdev)
103{
104 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
105 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
106
107 mxc_iomux_v3_setup_pad(usbh2gpio);
108 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
109 gpio_direction_output(EFIKASB_USBH2_STP, 0);
110 msleep(1);
111 gpio_set_value(EFIKASB_USBH2_STP, 1);
112 msleep(1);
113
114 gpio_free(EFIKASB_USBH2_STP);
115 mxc_iomux_v3_setup_pad(usbh2stp);
116
117 mdelay(10);
118
119 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
120}
121
122static struct mxc_usbh_platform_data usbh2_config = {
123 .init = initialize_usbh2_port,
124 .portsc = MXC_EHCI_MODE_ULPI,
125};
126
127static void __init mx51_efikasb_usb(void)
128{
129 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
130 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
131 if (usbh2_config.otg)
132 mxc_register_device(&mxc_usbh2_device, &usbh2_config);
133}
134
135static const struct gpio_led mx51_efikasb_leds[] __initconst = {
136 {
137 .name = "efikasb:green",
138 .default_trigger = "default-on",
139 .gpio = EFIKASB_GREEN_LED,
140 .active_low = 1,
141 },
142 {
143 .name = "efikasb:white",
144 .default_trigger = "caps",
145 .gpio = EFIKASB_WHITE_LED,
146 },
147};
148
149static const struct gpio_led_platform_data
150 mx51_efikasb_leds_data __initconst = {
151 .leds = mx51_efikasb_leds,
152 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
153};
154
155static struct gpio_keys_button mx51_efikasb_keys[] = {
156 {
157 .code = KEY_POWER,
158 .gpio = EFIKASB_PWRKEY,
159 .type = EV_KEY,
160 .desc = "Power Button",
161 .wakeup = 1,
162 .active_low = 1,
163 },
164 {
165 .code = SW_LID,
166 .gpio = EFIKASB_LID,
167 .type = EV_SW,
168 .desc = "Lid Switch",
169 .active_low = 1,
170 },
171 {
172 .code = KEY_RFKILL,
173 .gpio = EFIKASB_RFKILL,
174 .type = EV_KEY,
175 .desc = "rfkill",
176 .active_low = 1,
177 },
178};
179
180static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
181 .buttons = mx51_efikasb_keys,
182 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
183};
184
185static struct regulator *pwgt1, *pwgt2;
186
187static void mx51_efikasb_power_off(void)
188{
189 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
190
191 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
192 regulator_disable(pwgt2);
193 regulator_disable(pwgt1);
194 }
195 gpio_direction_output(EFIKASB_POWEROFF, 1);
196}
197
198static int __init mx51_efikasb_power_init(void)
199{
200 if (machine_is_mx51_efikasb()) {
201 pwgt1 = regulator_get(NULL, "pwgt1");
202 pwgt2 = regulator_get(NULL, "pwgt2");
203 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
204 regulator_enable(pwgt1);
205 regulator_enable(pwgt2);
206 }
207 gpio_request(EFIKASB_POWEROFF, "poweroff");
208 pm_power_off = mx51_efikasb_power_off;
209
210 regulator_has_full_constraints();
211 }
212
213 return 0;
214}
215late_initcall(mx51_efikasb_power_init);
216
217/* 01 R1.3 board
218 10 R2.0 board */
219static void __init mx51_efikasb_board_id(void)
220{
221 int id;
222
223 gpio_request(EFIKASB_PCBID0, "pcb id0");
224 gpio_direction_input(EFIKASB_PCBID0);
225 gpio_request(EFIKASB_PCBID1, "pcb id1");
226 gpio_direction_input(EFIKASB_PCBID1);
227
228 id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
229 id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
230
231 switch (id) {
232 default:
233 break;
234 case 1:
235 system_rev = 0x13;
236 break;
237 case 2:
238 system_rev = 0x20;
239 break;
240 }
241}
242
243static void __init efikasb_board_init(void)
244{
245 imx51_soc_init();
246
247 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
248 ARRAY_SIZE(mx51efikasb_pads));
249 efika_board_common_init();
250
251 mx51_efikasb_board_id();
252 mx51_efikasb_usb();
253 imx51_add_sdhci_esdhc_imx(1, NULL);
254
255 gpio_led_register_device(-1, &mx51_efikasb_leds_data);
256 imx_add_gpio_keys(&mx51_efikasb_keys_data);
257}
258
259static void __init mx51_efikasb_timer_init(void)
260{
261 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
262}
263
264static struct sys_timer mx51_efikasb_timer = {
265 .init = mx51_efikasb_timer_init,
266};
267
268MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
269 .boot_params = MX51_PHYS_OFFSET + 0x100,
270 .map_io = mx51_map_io,
271 .init_early = imx51_init_early,
272 .init_irq = mx51_init_irq,
273 .init_machine = efikasb_board_init,
274 .timer = &mx51_efikasb_timer,
275MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
new file mode 100644
index 00000000000..76a67c4a2a0
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -0,0 +1,254 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "crm_regs.h"
36#include "devices-imx53.h"
37
38#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
39#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
40#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
41#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
42#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
43#define ARD_HOME IMX_GPIO_NR(5, 10)
44#define ARD_BACK IMX_GPIO_NR(5, 11)
45#define ARD_PROG IMX_GPIO_NR(5, 12)
46#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
47
48static iomux_v3_cfg_t mx53_ard_pads[] = {
49 /* UART1 */
50 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
51 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
52 /* WEIM for CS1 */
53 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
54 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
55 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
56 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
57 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
58 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
59 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
60 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
61 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
62 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
63 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
64 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
65 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
66 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
67 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
68 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
69 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
70 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
71 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
72 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
73 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
74 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
75 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
76 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
77 MX53_PAD_EIM_OE__EMI_WEIM_OE,
78 MX53_PAD_EIM_RW__EMI_WEIM_RW,
79 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
80 /* SDHC1 */
81 MX53_PAD_SD1_CMD__ESDHC1_CMD,
82 MX53_PAD_SD1_CLK__ESDHC1_CLK,
83 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
84 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
85 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
86 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
87 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
88 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
89 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
90 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
91 MX53_PAD_GPIO_1__GPIO1_1,
92 MX53_PAD_GPIO_9__GPIO1_9,
93 /* I2C2 */
94 MX53_PAD_EIM_EB2__I2C2_SCL,
95 MX53_PAD_KEY_ROW3__I2C2_SDA,
96 /* I2C3 */
97 MX53_PAD_GPIO_3__I2C3_SCL,
98 MX53_PAD_GPIO_16__I2C3_SDA,
99 /* GPIO */
100 MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
101 MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
102 MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
103 MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
104 MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
105};
106
107#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
108{ \
109 .gpio = gpio_num, \
110 .type = EV_KEY, \
111 .code = ev_code, \
112 .active_low = act_low, \
113 .desc = "btn " descr, \
114 .wakeup = wake, \
115}
116
117static struct gpio_keys_button ard_buttons[] = {
118 GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
119 GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
120 GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
121 GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
122 GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
123};
124
125static const struct gpio_keys_platform_data ard_button_data __initconst = {
126 .buttons = ard_buttons,
127 .nbuttons = ARRAY_SIZE(ard_buttons),
128};
129
130static struct resource ard_smsc911x_resources[] = {
131 {
132 .start = MX53_CS1_64MB_BASE_ADDR,
133 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = gpio_to_irq(ARD_ETHERNET_INT_B),
138 .end = gpio_to_irq(ARD_ETHERNET_INT_B),
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143struct smsc911x_platform_config ard_smsc911x_config = {
144 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
145 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
146 .flags = SMSC911X_USE_32BIT,
147};
148
149static struct platform_device ard_smsc_lan9220_device = {
150 .name = "smsc911x",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
153 .resource = ard_smsc911x_resources,
154 .dev = {
155 .platform_data = &ard_smsc911x_config,
156 },
157};
158
159static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
160 .cd_gpio = ARD_SD1_CD,
161 .wp_gpio = ARD_SD1_WP,
162};
163
164static struct imxi2c_platform_data mx53_ard_i2c2_data = {
165 .bitrate = 50000,
166};
167
168static struct imxi2c_platform_data mx53_ard_i2c3_data = {
169 .bitrate = 400000,
170};
171
172static void __init mx53_ard_io_init(void)
173{
174 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
175 ARRAY_SIZE(mx53_ard_pads));
176
177 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
178 gpio_direction_input(ARD_ETHERNET_INT_B);
179
180 gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
181 gpio_direction_output(ARD_I2CPORTEXP_B, 1);
182}
183
184/* Config CS1 settings for ethernet controller */
185static int weim_cs_config(void)
186{
187 u32 reg;
188 void __iomem *weim_base, *iomuxc_base;
189
190 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
191 if (!weim_base)
192 return -ENOMEM;
193
194 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
195 if (!iomuxc_base)
196 return -ENOMEM;
197
198 /* CS1 timings for LAN9220 */
199 writel(0x20001, (weim_base + 0x18));
200 writel(0x0, (weim_base + 0x1C));
201 writel(0x16000202, (weim_base + 0x20));
202 writel(0x00000002, (weim_base + 0x24));
203 writel(0x16002082, (weim_base + 0x28));
204 writel(0x00000000, (weim_base + 0x2C));
205 writel(0x00000000, (weim_base + 0x90));
206
207 /* specify 64 MB on CS1 and CS0 on GPR1 */
208 reg = readl(iomuxc_base + 0x4);
209 reg &= ~0x3F;
210 reg |= 0x1B;
211 writel(reg, (iomuxc_base + 0x4));
212
213 iounmap(iomuxc_base);
214 iounmap(weim_base);
215
216 return 0;
217}
218
219static struct platform_device *devices[] __initdata = {
220 &ard_smsc_lan9220_device,
221};
222
223static void __init mx53_ard_board_init(void)
224{
225 imx53_soc_init();
226 imx53_add_imx_uart(0, NULL);
227
228 mx53_ard_io_init();
229 weim_cs_config();
230 platform_add_devices(devices, ARRAY_SIZE(devices));
231
232 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
233 imx53_add_imx2_wdt(0, NULL);
234 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
235 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
236 imx_add_gpio_keys(&ard_button_data);
237}
238
239static void __init mx53_ard_timer_init(void)
240{
241 mx53_clocks_init(32768, 24000000, 22579200, 0);
242}
243
244static struct sys_timer mx53_ard_timer = {
245 .init = mx53_ard_timer_init,
246};
247
248MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
249 .map_io = mx53_map_io,
250 .init_early = imx53_init_early,
251 .init_irq = mx53_init_irq,
252 .timer = &mx53_ard_timer,
253 .init_machine = mx53_ard_board_init,
254MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
new file mode 100644
index 00000000000..1b417b06b73
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -0,0 +1,172 @@
1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <mach/iomux-mx53.h>
34
35#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
36#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
37#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
38#define MX53EVK_LED IMX_GPIO_NR(7, 7)
39
40#include "crm_regs.h"
41#include "devices-imx53.h"
42
43static iomux_v3_cfg_t mx53_evk_pads[] = {
44 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
45 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
46
47 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
48 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
49 MX53_PAD_PATA_DIOR__UART2_RTS,
50 MX53_PAD_PATA_INTRQ__UART2_CTS,
51
52 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
53 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
54
55 MX53_PAD_EIM_D16__ECSPI1_SCLK,
56 MX53_PAD_EIM_D17__ECSPI1_MISO,
57 MX53_PAD_EIM_D18__ECSPI1_MOSI,
58
59 /* ecspi chip select lines */
60 MX53_PAD_EIM_EB2__GPIO2_30,
61 MX53_PAD_EIM_D19__GPIO3_19,
62 /* LED */
63 MX53_PAD_PATA_DA_1__GPIO7_7,
64};
65
66static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
67 .flags = IMXUART_HAVE_RTSCTS,
68};
69
70static const struct gpio_led mx53evk_leds[] __initconst = {
71 {
72 .name = "green",
73 .default_trigger = "heartbeat",
74 .gpio = MX53EVK_LED,
75 },
76};
77
78static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
79 .leds = mx53evk_leds,
80 .num_leds = ARRAY_SIZE(mx53evk_leds),
81};
82
83static inline void mx53_evk_init_uart(void)
84{
85 imx53_add_imx_uart(0, NULL);
86 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
87 imx53_add_imx_uart(2, NULL);
88}
89
90static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
91 .bitrate = 100000,
92};
93
94static inline void mx53_evk_fec_reset(void)
95{
96 int ret;
97
98 /* reset FEC PHY */
99 ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
100 "fec-phy-reset");
101 if (ret) {
102 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
103 return;
104 }
105 msleep(1);
106 gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
107}
108
109static struct fec_platform_data mx53_evk_fec_pdata = {
110 .phy = PHY_INTERFACE_MODE_RMII,
111};
112
113static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
114 {
115 .modalias = "mtd_dataflash",
116 .max_speed_hz = 25000000,
117 .bus_num = 0,
118 .chip_select = 1,
119 .mode = SPI_MODE_0,
120 .platform_data = NULL,
121 },
122};
123
124static int mx53_evk_spi_cs[] = {
125 EVK_ECSPI1_CS0,
126 EVK_ECSPI1_CS1,
127};
128
129static const struct spi_imx_master mx53_evk_spi_data __initconst = {
130 .chipselect = mx53_evk_spi_cs,
131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
132};
133
134static void __init mx53_evk_board_init(void)
135{
136 imx53_soc_init();
137
138 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
139 ARRAY_SIZE(mx53_evk_pads));
140 mx53_evk_init_uart();
141 mx53_evk_fec_reset();
142 imx53_add_fec(&mx53_evk_fec_pdata);
143
144 imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
145 imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
146
147 imx53_add_sdhci_esdhc_imx(0, NULL);
148 imx53_add_sdhci_esdhc_imx(1, NULL);
149
150 spi_register_board_info(mx53_evk_spi_board_info,
151 ARRAY_SIZE(mx53_evk_spi_board_info));
152 imx53_add_ecspi(0, &mx53_evk_spi_data);
153 imx53_add_imx2_wdt(0, NULL);
154 gpio_led_register_device(-1, &mx53evk_leds_data);
155}
156
157static void __init mx53_evk_timer_init(void)
158{
159 mx53_clocks_init(32768, 24000000, 22579200, 0);
160}
161
162static struct sys_timer mx53_evk_timer = {
163 .init = mx53_evk_timer_init,
164};
165
166MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
167 .map_io = mx53_map_io,
168 .init_early = imx53_init_early,
169 .init_irq = mx53_init_irq,
170 .timer = &mx53_evk_timer,
171 .init_machine = mx53_evk_board_init,
172MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
new file mode 100644
index 00000000000..4e1d51d252d
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -0,0 +1,293 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx53.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "crm_regs.h"
35#include "devices-imx53.h"
36
37#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
38#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
39#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
40#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
41#define LOCO_LED IMX_GPIO_NR(7, 7)
42#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
43#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
44#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
45
46static iomux_v3_cfg_t mx53_loco_pads[] = {
47 /* FEC */
48 MX53_PAD_FEC_MDC__FEC_MDC,
49 MX53_PAD_FEC_MDIO__FEC_MDIO,
50 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
51 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
52 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
53 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
54 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
55 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
56 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
57 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
58 /* FEC_nRST */
59 MX53_PAD_PATA_DA_0__GPIO7_6,
60 /* FEC_nINT */
61 MX53_PAD_PATA_DATA4__GPIO2_4,
62 /* AUDMUX5 */
63 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
64 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
65 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
66 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
67 /* I2C2 */
68 MX53_PAD_KEY_COL3__I2C2_SCL,
69 MX53_PAD_KEY_ROW3__I2C2_SDA,
70 /* SD1 */
71 MX53_PAD_SD1_CMD__ESDHC1_CMD,
72 MX53_PAD_SD1_CLK__ESDHC1_CLK,
73 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
74 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
75 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
76 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
77 /* SD1_CD */
78 MX53_PAD_EIM_DA13__GPIO3_13,
79 /* SD3 */
80 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
81 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
82 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
83 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
84 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
85 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
86 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
87 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
88 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
89 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
90 /* SD3_CD */
91 MX53_PAD_EIM_DA11__GPIO3_11,
92 /* SD3_WP */
93 MX53_PAD_EIM_DA12__GPIO3_12,
94 /* VGA */
95 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
96 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
97 /* DISPLB */
98 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
99 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
100 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
101 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
102 /* DISP0_POWER_EN */
103 MX53_PAD_EIM_D24__GPIO3_24,
104 /* DISP0 DET INT */
105 MX53_PAD_EIM_D31__GPIO3_31,
106 /* LVDS */
107 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
108 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
109 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
110 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
111 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
112 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
113 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
114 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
115 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
116 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
117 /* I2C1 */
118 MX53_PAD_CSI0_DAT8__I2C1_SDA,
119 MX53_PAD_CSI0_DAT9__I2C1_SCL,
120 /* UART1 */
121 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
122 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
123 /* CSI0 */
124 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
125 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
126 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
127 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
128 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
129 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
130 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
131 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
132 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
133 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
134 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
135 /* DISPLAY */
136 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
137 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
138 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
139 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
140 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
141 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
142 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
143 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
144 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
145 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
146 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
147 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
148 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
149 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
150 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
151 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
152 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
153 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
154 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
155 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
156 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
157 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
158 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
159 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
160 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
161 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
162 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
163 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
164 /* Audio CLK*/
165 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
166 /* PWM */
167 MX53_PAD_GPIO_1__PWM2_PWMO,
168 /* SPDIF */
169 MX53_PAD_GPIO_7__SPDIF_PLOCK,
170 MX53_PAD_GPIO_17__SPDIF_OUT1,
171 /* GPIO */
172 MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
173 MX53_PAD_PATA_DA_2__GPIO7_8,
174 MX53_PAD_PATA_DATA5__GPIO2_5,
175 MX53_PAD_PATA_DATA6__GPIO2_6,
176 MX53_PAD_PATA_DATA14__GPIO2_14,
177 MX53_PAD_PATA_DATA15__GPIO2_15,
178 MX53_PAD_PATA_INTRQ__GPIO7_2,
179 MX53_PAD_EIM_WAIT__GPIO5_0,
180 MX53_PAD_NANDF_WP_B__GPIO6_9,
181 MX53_PAD_NANDF_RB0__GPIO6_10,
182 MX53_PAD_NANDF_CS1__GPIO6_14,
183 MX53_PAD_NANDF_CS2__GPIO6_15,
184 MX53_PAD_NANDF_CS3__GPIO6_16,
185 MX53_PAD_GPIO_5__GPIO1_5,
186 MX53_PAD_GPIO_16__GPIO7_11,
187 MX53_PAD_GPIO_8__GPIO1_8,
188};
189
190#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
191{ \
192 .gpio = gpio_num, \
193 .type = EV_KEY, \
194 .code = ev_code, \
195 .active_low = act_low, \
196 .desc = "btn " descr, \
197 .wakeup = wake, \
198}
199
200static struct gpio_keys_button loco_buttons[] = {
201 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
202 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
203 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
204};
205
206static const struct gpio_keys_platform_data loco_button_data __initconst = {
207 .buttons = loco_buttons,
208 .nbuttons = ARRAY_SIZE(loco_buttons),
209};
210
211static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
212 .cd_gpio = LOCO_SD1_CD,
213 .cd_type = ESDHC_CD_GPIO,
214 .wp_type = ESDHC_WP_NONE,
215};
216
217static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
218 .cd_gpio = LOCO_SD3_CD,
219 .wp_gpio = LOCO_SD3_WP,
220 .cd_type = ESDHC_CD_GPIO,
221 .wp_type = ESDHC_WP_GPIO,
222};
223
224static inline void mx53_loco_fec_reset(void)
225{
226 int ret;
227
228 /* reset FEC PHY */
229 ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
230 if (ret) {
231 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
232 return;
233 }
234 gpio_direction_output(LOCO_FEC_PHY_RST, 0);
235 msleep(1);
236 gpio_set_value(LOCO_FEC_PHY_RST, 1);
237}
238
239static struct fec_platform_data mx53_loco_fec_data = {
240 .phy = PHY_INTERFACE_MODE_RMII,
241};
242
243static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
244 .bitrate = 100000,
245};
246
247static const struct gpio_led mx53loco_leds[] __initconst = {
248 {
249 .name = "green",
250 .default_trigger = "heartbeat",
251 .gpio = LOCO_LED,
252 },
253};
254
255static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
256 .leds = mx53loco_leds,
257 .num_leds = ARRAY_SIZE(mx53loco_leds),
258};
259
260static void __init mx53_loco_board_init(void)
261{
262 imx53_soc_init();
263
264 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
265 ARRAY_SIZE(mx53_loco_pads));
266 imx53_add_imx_uart(0, NULL);
267 mx53_loco_fec_reset();
268 imx53_add_fec(&mx53_loco_fec_data);
269 imx53_add_imx2_wdt(0, NULL);
270 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
271 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
272 imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
273 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
274 imx_add_gpio_keys(&loco_button_data);
275 gpio_led_register_device(-1, &mx53loco_leds_data);
276}
277
278static void __init mx53_loco_timer_init(void)
279{
280 mx53_clocks_init(32768, 24000000, 0, 0);
281}
282
283static struct sys_timer mx53_loco_timer = {
284 .init = mx53_loco_timer_init,
285};
286
287MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
288 .map_io = mx53_map_io,
289 .init_early = imx53_init_early,
290 .init_irq = mx53_init_irq,
291 .timer = &mx53_loco_timer,
292 .init_machine = mx53_loco_board_init,
293MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
new file mode 100644
index 00000000000..bc02894eafe
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx53.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "crm_regs.h"
35#include "devices-imx53.h"
36
37#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
38
39static iomux_v3_cfg_t mx53_smd_pads[] = {
40 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
41 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
42
43 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
44 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
45
46 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
47 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
48 MX53_PAD_PATA_DA_1__UART3_CTS,
49 MX53_PAD_PATA_DA_2__UART3_RTS,
50 /* I2C1 */
51 MX53_PAD_CSI0_DAT8__I2C1_SDA,
52 MX53_PAD_CSI0_DAT9__I2C1_SCL,
53 /* SD1 */
54 MX53_PAD_SD1_CMD__ESDHC1_CMD,
55 MX53_PAD_SD1_CLK__ESDHC1_CLK,
56 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
57 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
58 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
59 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
60 /* SD2 */
61 MX53_PAD_SD2_CMD__ESDHC2_CMD,
62 MX53_PAD_SD2_CLK__ESDHC2_CLK,
63 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
64 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
65 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
66 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
67 /* SD3 */
68 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
69 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
70 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
71 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
72 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
73 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
74 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
75 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
76 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
77 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
78};
79
80static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
81 .flags = IMXUART_HAVE_RTSCTS,
82};
83
84static inline void mx53_smd_init_uart(void)
85{
86 imx53_add_imx_uart(0, NULL);
87 imx53_add_imx_uart(1, NULL);
88 imx53_add_imx_uart(2, &mx53_smd_uart_data);
89}
90
91static inline void mx53_smd_fec_reset(void)
92{
93 int ret;
94
95 /* reset FEC PHY */
96 ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
97 if (ret) {
98 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
99 return;
100 }
101 gpio_direction_output(SMD_FEC_PHY_RST, 0);
102 msleep(1);
103 gpio_set_value(SMD_FEC_PHY_RST, 1);
104}
105
106static struct fec_platform_data mx53_smd_fec_data = {
107 .phy = PHY_INTERFACE_MODE_RMII,
108};
109
110static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
111 .bitrate = 100000,
112};
113
114static void __init mx53_smd_board_init(void)
115{
116 imx53_soc_init();
117
118 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
119 ARRAY_SIZE(mx53_smd_pads));
120 mx53_smd_init_uart();
121 mx53_smd_fec_reset();
122 imx53_add_fec(&mx53_smd_fec_data);
123 imx53_add_imx2_wdt(0, NULL);
124 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
125 imx53_add_sdhci_esdhc_imx(0, NULL);
126 imx53_add_sdhci_esdhc_imx(1, NULL);
127 imx53_add_sdhci_esdhc_imx(2, NULL);
128}
129
130static void __init mx53_smd_timer_init(void)
131{
132 mx53_clocks_init(32768, 24000000, 22579200, 0);
133}
134
135static struct sys_timer mx53_smd_timer = {
136 .init = mx53_smd_timer_init,
137};
138
139MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
140 .map_io = mx53_map_io,
141 .init_early = imx53_init_early,
142 .init_irq = mx53_init_irq,
143 .timer = &mx53_smd_timer,
144 .init_machine = mx53_smd_board_init,
145MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
new file mode 100644
index 00000000000..f7bf996f463
--- /dev/null
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -0,0 +1,1611 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
18
19#include <asm/div64.h>
20
21#include <mach/hardware.h>
22#include <mach/common.h>
23#include <mach/clock.h>
24
25#include "crm_regs.h"
26
27/* External clock values passed-in by the board code */
28static unsigned long external_high_reference, external_low_reference;
29static unsigned long oscillator_reference, ckih2_reference;
30
31static struct clk osc_clk;
32static struct clk pll1_main_clk;
33static struct clk pll1_sw_clk;
34static struct clk pll2_sw_clk;
35static struct clk pll3_sw_clk;
36static struct clk mx53_pll4_sw_clk;
37static struct clk lp_apm_clk;
38static struct clk periph_apm_clk;
39static struct clk ahb_clk;
40static struct clk ipg_clk;
41static struct clk usboh3_clk;
42static struct clk emi_fast_clk;
43static struct clk ipu_clk;
44static struct clk mipi_hsc1_clk;
45static struct clk esdhc1_clk;
46static struct clk esdhc2_clk;
47static struct clk esdhc3_mx53_clk;
48
49#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
50
51/* calculate best pre and post dividers to get the required divider */
52static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
53 u32 max_pre, u32 max_post)
54{
55 if (div >= max_pre * max_post) {
56 *pre = max_pre;
57 *post = max_post;
58 } else if (div >= max_pre) {
59 u32 min_pre, temp_pre, old_err, err;
60 min_pre = DIV_ROUND_UP(div, max_post);
61 old_err = max_pre;
62 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
63 err = div % temp_pre;
64 if (err == 0) {
65 *pre = temp_pre;
66 break;
67 }
68 err = temp_pre - err;
69 if (err < old_err) {
70 old_err = err;
71 *pre = temp_pre;
72 }
73 }
74 *post = DIV_ROUND_UP(div, *pre);
75 } else {
76 *pre = div;
77 *post = 1;
78 }
79}
80
81static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
82{
83 u32 reg = __raw_readl(clk->enable_reg);
84
85 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
86 reg |= mode << clk->enable_shift;
87
88 __raw_writel(reg, clk->enable_reg);
89}
90
91static int _clk_ccgr_enable(struct clk *clk)
92{
93 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
94 return 0;
95}
96
97static void _clk_ccgr_disable(struct clk *clk)
98{
99 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
100}
101
102static int _clk_ccgr_enable_inrun(struct clk *clk)
103{
104 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
105 return 0;
106}
107
108static void _clk_ccgr_disable_inwait(struct clk *clk)
109{
110 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
111}
112
113/*
114 * For the 4-to-1 muxed input clock
115 */
116static inline u32 _get_mux(struct clk *parent, struct clk *m0,
117 struct clk *m1, struct clk *m2, struct clk *m3)
118{
119 if (parent == m0)
120 return 0;
121 else if (parent == m1)
122 return 1;
123 else if (parent == m2)
124 return 2;
125 else if (parent == m3)
126 return 3;
127 else
128 BUG();
129
130 return -EINVAL;
131}
132
133static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
134{
135 if (pll == &pll1_main_clk)
136 return MX51_DPLL1_BASE;
137 else if (pll == &pll2_sw_clk)
138 return MX51_DPLL2_BASE;
139 else if (pll == &pll3_sw_clk)
140 return MX51_DPLL3_BASE;
141 else
142 BUG();
143
144 return NULL;
145}
146
147static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
148{
149 if (pll == &pll1_main_clk)
150 return MX53_DPLL1_BASE;
151 else if (pll == &pll2_sw_clk)
152 return MX53_DPLL2_BASE;
153 else if (pll == &pll3_sw_clk)
154 return MX53_DPLL3_BASE;
155 else if (pll == &mx53_pll4_sw_clk)
156 return MX53_DPLL4_BASE;
157 else
158 BUG();
159
160 return NULL;
161}
162
163static inline void __iomem *_get_pll_base(struct clk *pll)
164{
165 if (cpu_is_mx51())
166 return _mx51_get_pll_base(pll);
167 else
168 return _mx53_get_pll_base(pll);
169}
170
171static unsigned long clk_pll_get_rate(struct clk *clk)
172{
173 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
174 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
175 void __iomem *pllbase;
176 s64 temp;
177 unsigned long parent_rate;
178
179 parent_rate = clk_get_rate(clk->parent);
180
181 pllbase = _get_pll_base(clk);
182
183 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
184 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
185 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
186
187 if (pll_hfsm == 0) {
188 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
189 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
190 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
191 } else {
192 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
193 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
194 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
195 }
196 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
197 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
198 mfi = (mfi <= 5) ? 5 : mfi;
199 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
200 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
201 /* Sign extend to 32-bits */
202 if (mfn >= 0x04000000) {
203 mfn |= 0xFC000000;
204 mfn_abs = -mfn;
205 }
206
207 ref_clk = 2 * parent_rate;
208 if (dbl != 0)
209 ref_clk *= 2;
210
211 ref_clk /= (pdf + 1);
212 temp = (u64) ref_clk * mfn_abs;
213 do_div(temp, mfd + 1);
214 if (mfn < 0)
215 temp = -temp;
216 temp = (ref_clk * mfi) + temp;
217
218 return temp;
219}
220
221static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
222{
223 u32 reg;
224 void __iomem *pllbase;
225
226 long mfi, pdf, mfn, mfd = 999999;
227 s64 temp64;
228 unsigned long quad_parent_rate;
229 unsigned long pll_hfsm, dp_ctl;
230 unsigned long parent_rate;
231
232 parent_rate = clk_get_rate(clk->parent);
233
234 pllbase = _get_pll_base(clk);
235
236 quad_parent_rate = 4 * parent_rate;
237 pdf = mfi = -1;
238 while (++pdf < 16 && mfi < 5)
239 mfi = rate * (pdf+1) / quad_parent_rate;
240 if (mfi > 15)
241 return -EINVAL;
242 pdf--;
243
244 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
245 do_div(temp64, quad_parent_rate/1000000);
246 mfn = (long)temp64;
247
248 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
249 /* use dpdck0_2 */
250 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
251 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
252 if (pll_hfsm == 0) {
253 reg = mfi << 4 | pdf;
254 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
255 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
256 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
257 } else {
258 reg = mfi << 4 | pdf;
259 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
260 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
261 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
262 }
263
264 return 0;
265}
266
267static int _clk_pll_enable(struct clk *clk)
268{
269 u32 reg;
270 void __iomem *pllbase;
271 int i = 0;
272
273 pllbase = _get_pll_base(clk);
274 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
275 if (reg & MXC_PLL_DP_CTL_UPEN)
276 return 0;
277
278 reg |= MXC_PLL_DP_CTL_UPEN;
279 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
280
281 /* Wait for lock */
282 do {
283 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
284 if (reg & MXC_PLL_DP_CTL_LRF)
285 break;
286
287 udelay(1);
288 } while (++i < MAX_DPLL_WAIT_TRIES);
289
290 if (i == MAX_DPLL_WAIT_TRIES) {
291 pr_err("MX5: pll locking failed\n");
292 return -EINVAL;
293 }
294
295 return 0;
296}
297
298static void _clk_pll_disable(struct clk *clk)
299{
300 u32 reg;
301 void __iomem *pllbase;
302
303 pllbase = _get_pll_base(clk);
304 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
305 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
306}
307
308static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
309{
310 u32 reg, step;
311
312 reg = __raw_readl(MXC_CCM_CCSR);
313
314 /* When switching from pll_main_clk to a bypass clock, first select a
315 * multiplexed clock in 'step_sel', then shift the glitchless mux
316 * 'pll1_sw_clk_sel'.
317 *
318 * When switching back, do it in reverse order
319 */
320 if (parent == &pll1_main_clk) {
321 /* Switch to pll1_main_clk */
322 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
323 __raw_writel(reg, MXC_CCM_CCSR);
324 /* step_clk mux switched to lp_apm, to save power. */
325 reg = __raw_readl(MXC_CCM_CCSR);
326 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
327 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
328 MXC_CCM_CCSR_STEP_SEL_OFFSET);
329 } else {
330 if (parent == &lp_apm_clk) {
331 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
332 } else if (parent == &pll2_sw_clk) {
333 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
334 } else if (parent == &pll3_sw_clk) {
335 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
336 } else
337 return -EINVAL;
338
339 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
340 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
341
342 __raw_writel(reg, MXC_CCM_CCSR);
343 /* Switch to step_clk */
344 reg = __raw_readl(MXC_CCM_CCSR);
345 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
346 }
347 __raw_writel(reg, MXC_CCM_CCSR);
348 return 0;
349}
350
351static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
352{
353 u32 reg, div;
354 unsigned long parent_rate;
355
356 parent_rate = clk_get_rate(clk->parent);
357
358 reg = __raw_readl(MXC_CCM_CCSR);
359
360 if (clk->parent == &pll2_sw_clk) {
361 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
362 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
363 } else if (clk->parent == &pll3_sw_clk) {
364 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
365 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
366 } else
367 div = 1;
368 return parent_rate / div;
369}
370
371static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
372{
373 u32 reg;
374
375 reg = __raw_readl(MXC_CCM_CCSR);
376
377 if (parent == &pll2_sw_clk)
378 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
379 else
380 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
381
382 __raw_writel(reg, MXC_CCM_CCSR);
383 return 0;
384}
385
386static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
387{
388 u32 reg;
389
390 if (parent == &osc_clk)
391 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
392 else
393 return -EINVAL;
394
395 __raw_writel(reg, MXC_CCM_CCSR);
396
397 return 0;
398}
399
400static unsigned long clk_cpu_get_rate(struct clk *clk)
401{
402 u32 cacrr, div;
403 unsigned long parent_rate;
404
405 parent_rate = clk_get_rate(clk->parent);
406 cacrr = __raw_readl(MXC_CCM_CACRR);
407 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
408
409 return parent_rate / div;
410}
411
412static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
413{
414 u32 reg, cpu_podf;
415 unsigned long parent_rate;
416
417 parent_rate = clk_get_rate(clk->parent);
418 cpu_podf = parent_rate / rate - 1;
419 /* use post divider to change freq */
420 reg = __raw_readl(MXC_CCM_CACRR);
421 reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
422 reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
423 __raw_writel(reg, MXC_CCM_CACRR);
424
425 return 0;
426}
427
428static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
429{
430 u32 reg, mux;
431 int i = 0;
432
433 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
434
435 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
436 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
437 __raw_writel(reg, MXC_CCM_CBCMR);
438
439 /* Wait for lock */
440 do {
441 reg = __raw_readl(MXC_CCM_CDHIPR);
442 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
443 break;
444
445 udelay(1);
446 } while (++i < MAX_DPLL_WAIT_TRIES);
447
448 if (i == MAX_DPLL_WAIT_TRIES) {
449 pr_err("MX5: Set parent for periph_apm clock failed\n");
450 return -EINVAL;
451 }
452
453 return 0;
454}
455
456static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
457{
458 u32 reg;
459
460 reg = __raw_readl(MXC_CCM_CBCDR);
461
462 if (parent == &pll2_sw_clk)
463 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
464 else if (parent == &periph_apm_clk)
465 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
466 else
467 return -EINVAL;
468
469 __raw_writel(reg, MXC_CCM_CBCDR);
470
471 return 0;
472}
473
474static struct clk main_bus_clk = {
475 .parent = &pll2_sw_clk,
476 .set_parent = _clk_main_bus_set_parent,
477};
478
479static unsigned long clk_ahb_get_rate(struct clk *clk)
480{
481 u32 reg, div;
482 unsigned long parent_rate;
483
484 parent_rate = clk_get_rate(clk->parent);
485
486 reg = __raw_readl(MXC_CCM_CBCDR);
487 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
488 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
489 return parent_rate / div;
490}
491
492
493static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
494{
495 u32 reg, div;
496 unsigned long parent_rate;
497 int i = 0;
498
499 parent_rate = clk_get_rate(clk->parent);
500
501 div = parent_rate / rate;
502 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
503 return -EINVAL;
504
505 reg = __raw_readl(MXC_CCM_CBCDR);
506 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
507 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
508 __raw_writel(reg, MXC_CCM_CBCDR);
509
510 /* Wait for lock */
511 do {
512 reg = __raw_readl(MXC_CCM_CDHIPR);
513 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
514 break;
515
516 udelay(1);
517 } while (++i < MAX_DPLL_WAIT_TRIES);
518
519 if (i == MAX_DPLL_WAIT_TRIES) {
520 pr_err("MX5: clk_ahb_set_rate failed\n");
521 return -EINVAL;
522 }
523
524 return 0;
525}
526
527static unsigned long _clk_ahb_round_rate(struct clk *clk,
528 unsigned long rate)
529{
530 u32 div;
531 unsigned long parent_rate;
532
533 parent_rate = clk_get_rate(clk->parent);
534
535 div = parent_rate / rate;
536 if (div > 8)
537 div = 8;
538 else if (div == 0)
539 div++;
540 return parent_rate / div;
541}
542
543
544static int _clk_max_enable(struct clk *clk)
545{
546 u32 reg;
547
548 _clk_ccgr_enable(clk);
549
550 /* Handshake with MAX when LPM is entered. */
551 reg = __raw_readl(MXC_CCM_CLPCR);
552 if (cpu_is_mx51())
553 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
554 else if (cpu_is_mx53())
555 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
556 __raw_writel(reg, MXC_CCM_CLPCR);
557
558 return 0;
559}
560
561static void _clk_max_disable(struct clk *clk)
562{
563 u32 reg;
564
565 _clk_ccgr_disable_inwait(clk);
566
567 /* No Handshake with MAX when LPM is entered as its disabled. */
568 reg = __raw_readl(MXC_CCM_CLPCR);
569 if (cpu_is_mx51())
570 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
571 else if (cpu_is_mx53())
572 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
573 __raw_writel(reg, MXC_CCM_CLPCR);
574}
575
576static unsigned long clk_ipg_get_rate(struct clk *clk)
577{
578 u32 reg, div;
579 unsigned long parent_rate;
580
581 parent_rate = clk_get_rate(clk->parent);
582
583 reg = __raw_readl(MXC_CCM_CBCDR);
584 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
585 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
586
587 return parent_rate / div;
588}
589
590static unsigned long clk_ipg_per_get_rate(struct clk *clk)
591{
592 u32 reg, prediv1, prediv2, podf;
593 unsigned long parent_rate;
594
595 parent_rate = clk_get_rate(clk->parent);
596
597 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
598 /* the main_bus_clk is the one before the DVFS engine */
599 reg = __raw_readl(MXC_CCM_CBCDR);
600 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
601 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
602 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
603 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
604 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
605 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
606 return parent_rate / (prediv1 * prediv2 * podf);
607 } else if (clk->parent == &ipg_clk)
608 return parent_rate;
609 else
610 BUG();
611}
612
613static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
614{
615 u32 reg;
616
617 reg = __raw_readl(MXC_CCM_CBCMR);
618
619 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
620 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
621
622 if (parent == &ipg_clk)
623 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
624 else if (parent == &lp_apm_clk)
625 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
626 else if (parent != &main_bus_clk)
627 return -EINVAL;
628
629 __raw_writel(reg, MXC_CCM_CBCMR);
630
631 return 0;
632}
633
634#define clk_nfc_set_parent NULL
635
636static unsigned long clk_nfc_get_rate(struct clk *clk)
637{
638 unsigned long rate;
639 u32 reg, div;
640
641 reg = __raw_readl(MXC_CCM_CBCDR);
642 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
643 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
644 rate = clk_get_rate(clk->parent) / div;
645 WARN_ON(rate == 0);
646 return rate;
647}
648
649static unsigned long clk_nfc_round_rate(struct clk *clk,
650 unsigned long rate)
651{
652 u32 div;
653 unsigned long parent_rate = clk_get_rate(clk->parent);
654
655 if (!rate)
656 return -EINVAL;
657
658 div = parent_rate / rate;
659
660 if (parent_rate % rate)
661 div++;
662
663 if (div > 8)
664 return -EINVAL;
665
666 return parent_rate / div;
667
668}
669
670static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
671{
672 u32 reg, div;
673
674 div = clk_get_rate(clk->parent) / rate;
675 if (div == 0)
676 div++;
677 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
678 return -EINVAL;
679
680 reg = __raw_readl(MXC_CCM_CBCDR);
681 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
682 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
683 __raw_writel(reg, MXC_CCM_CBCDR);
684
685 while (__raw_readl(MXC_CCM_CDHIPR) &
686 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
687 }
688
689 return 0;
690}
691
692static unsigned long get_high_reference_clock_rate(struct clk *clk)
693{
694 return external_high_reference;
695}
696
697static unsigned long get_low_reference_clock_rate(struct clk *clk)
698{
699 return external_low_reference;
700}
701
702static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
703{
704 return oscillator_reference;
705}
706
707static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
708{
709 return ckih2_reference;
710}
711
712static unsigned long clk_emi_slow_get_rate(struct clk *clk)
713{
714 u32 reg, div;
715
716 reg = __raw_readl(MXC_CCM_CBCDR);
717 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
718 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
719
720 return clk_get_rate(clk->parent) / div;
721}
722
723static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
724{
725 unsigned long rate;
726 u32 reg, div;
727
728 reg = __raw_readl(MXC_CCM_CBCDR);
729 div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
730 MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
731 rate = clk_get_rate(clk->parent) / div;
732
733 return rate;
734}
735
736/* External high frequency clock */
737static struct clk ckih_clk = {
738 .get_rate = get_high_reference_clock_rate,
739};
740
741static struct clk ckih2_clk = {
742 .get_rate = get_ckih2_reference_clock_rate,
743};
744
745static struct clk osc_clk = {
746 .get_rate = get_oscillator_reference_clock_rate,
747};
748
749/* External low frequency (32kHz) clock */
750static struct clk ckil_clk = {
751 .get_rate = get_low_reference_clock_rate,
752};
753
754static struct clk pll1_main_clk = {
755 .parent = &osc_clk,
756 .get_rate = clk_pll_get_rate,
757 .enable = _clk_pll_enable,
758 .disable = _clk_pll_disable,
759};
760
761/* Clock tree block diagram (WIP):
762 * CCM: Clock Controller Module
763 *
764 * PLL output -> |
765 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
766 * PLL bypass -> |
767 *
768 */
769
770/* PLL1 SW supplies to ARM core */
771static struct clk pll1_sw_clk = {
772 .parent = &pll1_main_clk,
773 .set_parent = _clk_pll1_sw_set_parent,
774 .get_rate = clk_pll1_sw_get_rate,
775};
776
777/* PLL2 SW supplies to AXI/AHB/IP buses */
778static struct clk pll2_sw_clk = {
779 .parent = &osc_clk,
780 .get_rate = clk_pll_get_rate,
781 .set_rate = _clk_pll_set_rate,
782 .set_parent = _clk_pll2_sw_set_parent,
783 .enable = _clk_pll_enable,
784 .disable = _clk_pll_disable,
785};
786
787/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
788static struct clk pll3_sw_clk = {
789 .parent = &osc_clk,
790 .set_rate = _clk_pll_set_rate,
791 .get_rate = clk_pll_get_rate,
792 .enable = _clk_pll_enable,
793 .disable = _clk_pll_disable,
794};
795
796/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
797static struct clk mx53_pll4_sw_clk = {
798 .parent = &osc_clk,
799 .set_rate = _clk_pll_set_rate,
800 .enable = _clk_pll_enable,
801 .disable = _clk_pll_disable,
802};
803
804/* Low-power Audio Playback Mode clock */
805static struct clk lp_apm_clk = {
806 .parent = &osc_clk,
807 .set_parent = _clk_lp_apm_set_parent,
808};
809
810static struct clk periph_apm_clk = {
811 .parent = &pll1_sw_clk,
812 .set_parent = _clk_periph_apm_set_parent,
813};
814
815static struct clk cpu_clk = {
816 .parent = &pll1_sw_clk,
817 .get_rate = clk_cpu_get_rate,
818 .set_rate = clk_cpu_set_rate,
819};
820
821static struct clk ahb_clk = {
822 .parent = &main_bus_clk,
823 .get_rate = clk_ahb_get_rate,
824 .set_rate = _clk_ahb_set_rate,
825 .round_rate = _clk_ahb_round_rate,
826};
827
828static struct clk iim_clk = {
829 .parent = &ipg_clk,
830 .enable_reg = MXC_CCM_CCGR0,
831 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
832};
833
834/* Main IP interface clock for access to registers */
835static struct clk ipg_clk = {
836 .parent = &ahb_clk,
837 .get_rate = clk_ipg_get_rate,
838};
839
840static struct clk ipg_perclk = {
841 .parent = &lp_apm_clk,
842 .get_rate = clk_ipg_per_get_rate,
843 .set_parent = _clk_ipg_per_set_parent,
844};
845
846static struct clk ahb_max_clk = {
847 .parent = &ahb_clk,
848 .enable_reg = MXC_CCM_CCGR0,
849 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
850 .enable = _clk_max_enable,
851 .disable = _clk_max_disable,
852};
853
854static struct clk aips_tz1_clk = {
855 .parent = &ahb_clk,
856 .secondary = &ahb_max_clk,
857 .enable_reg = MXC_CCM_CCGR0,
858 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
859 .enable = _clk_ccgr_enable,
860 .disable = _clk_ccgr_disable_inwait,
861};
862
863static struct clk aips_tz2_clk = {
864 .parent = &ahb_clk,
865 .secondary = &ahb_max_clk,
866 .enable_reg = MXC_CCM_CCGR0,
867 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
868 .enable = _clk_ccgr_enable,
869 .disable = _clk_ccgr_disable_inwait,
870};
871
872static struct clk gpc_dvfs_clk = {
873 .enable_reg = MXC_CCM_CCGR5,
874 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
875 .enable = _clk_ccgr_enable,
876 .disable = _clk_ccgr_disable,
877};
878
879static struct clk gpt_32k_clk = {
880 .id = 0,
881 .parent = &ckil_clk,
882};
883
884static struct clk dummy_clk = {
885 .id = 0,
886};
887
888static struct clk emi_slow_clk = {
889 .parent = &pll2_sw_clk,
890 .enable_reg = MXC_CCM_CCGR5,
891 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
892 .enable = _clk_ccgr_enable,
893 .disable = _clk_ccgr_disable_inwait,
894 .get_rate = clk_emi_slow_get_rate,
895};
896
897static int clk_ipu_enable(struct clk *clk)
898{
899 u32 reg;
900
901 _clk_ccgr_enable(clk);
902
903 /* Enable handshake with IPU when certain clock rates are changed */
904 reg = __raw_readl(MXC_CCM_CCDR);
905 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
906 __raw_writel(reg, MXC_CCM_CCDR);
907
908 /* Enable handshake with IPU when LPM is entered */
909 reg = __raw_readl(MXC_CCM_CLPCR);
910 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
911 __raw_writel(reg, MXC_CCM_CLPCR);
912
913 return 0;
914}
915
916static void clk_ipu_disable(struct clk *clk)
917{
918 u32 reg;
919
920 _clk_ccgr_disable(clk);
921
922 /* Disable handshake with IPU whe dividers are changed */
923 reg = __raw_readl(MXC_CCM_CCDR);
924 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
925 __raw_writel(reg, MXC_CCM_CCDR);
926
927 /* Disable handshake with IPU when LPM is entered */
928 reg = __raw_readl(MXC_CCM_CLPCR);
929 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
930 __raw_writel(reg, MXC_CCM_CLPCR);
931}
932
933static struct clk ahbmux1_clk = {
934 .parent = &ahb_clk,
935 .secondary = &ahb_max_clk,
936 .enable_reg = MXC_CCM_CCGR0,
937 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
938 .enable = _clk_ccgr_enable,
939 .disable = _clk_ccgr_disable_inwait,
940};
941
942static struct clk ipu_sec_clk = {
943 .parent = &emi_fast_clk,
944 .secondary = &ahbmux1_clk,
945};
946
947static struct clk ddr_hf_clk = {
948 .parent = &pll1_sw_clk,
949 .get_rate = _clk_ddr_hf_get_rate,
950};
951
952static struct clk ddr_clk = {
953 .parent = &ddr_hf_clk,
954};
955
956/* clock definitions for MIPI HSC unit which has been removed
957 * from documentation, but not from hardware
958 */
959static int _clk_hsc_enable(struct clk *clk)
960{
961 u32 reg;
962
963 _clk_ccgr_enable(clk);
964 /* Handshake with IPU when certain clock rates are changed. */
965 reg = __raw_readl(MXC_CCM_CCDR);
966 reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
967 __raw_writel(reg, MXC_CCM_CCDR);
968
969 reg = __raw_readl(MXC_CCM_CLPCR);
970 reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
971 __raw_writel(reg, MXC_CCM_CLPCR);
972
973 return 0;
974}
975
976static void _clk_hsc_disable(struct clk *clk)
977{
978 u32 reg;
979
980 _clk_ccgr_disable(clk);
981 /* No handshake with HSC as its not enabled. */
982 reg = __raw_readl(MXC_CCM_CCDR);
983 reg |= MXC_CCM_CCDR_HSC_HS_MASK;
984 __raw_writel(reg, MXC_CCM_CCDR);
985
986 reg = __raw_readl(MXC_CCM_CLPCR);
987 reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
988 __raw_writel(reg, MXC_CCM_CLPCR);
989}
990
991static struct clk mipi_hsp_clk = {
992 .parent = &ipu_clk,
993 .enable_reg = MXC_CCM_CCGR4,
994 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
995 .enable = _clk_hsc_enable,
996 .disable = _clk_hsc_disable,
997 .secondary = &mipi_hsc1_clk,
998};
999
1000#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
1001 static struct clk name = { \
1002 .id = i, \
1003 .enable_reg = er, \
1004 .enable_shift = es, \
1005 .get_rate = pfx##_get_rate, \
1006 .set_rate = pfx##_set_rate, \
1007 .round_rate = pfx##_round_rate, \
1008 .set_parent = pfx##_set_parent, \
1009 .enable = _clk_ccgr_enable, \
1010 .disable = _clk_ccgr_disable, \
1011 .parent = p, \
1012 .secondary = s, \
1013 }
1014
1015#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
1016 static struct clk name = { \
1017 .id = i, \
1018 .enable_reg = er, \
1019 .enable_shift = es, \
1020 .get_rate = pfx##_get_rate, \
1021 .set_rate = pfx##_set_rate, \
1022 .set_parent = pfx##_set_parent, \
1023 .enable = _clk_max_enable, \
1024 .disable = _clk_max_disable, \
1025 .parent = p, \
1026 .secondary = s, \
1027 }
1028
1029#define CLK_GET_RATE(name, nr, bitsname) \
1030static unsigned long clk_##name##_get_rate(struct clk *clk) \
1031{ \
1032 u32 reg, pred, podf; \
1033 \
1034 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
1035 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
1036 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1037 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
1038 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1039 \
1040 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
1041 (pred + 1) * (podf + 1)); \
1042}
1043
1044#define CLK_SET_PARENT(name, nr, bitsname) \
1045static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
1046{ \
1047 u32 reg, mux; \
1048 \
1049 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
1050 &pll3_sw_clk, &lp_apm_clk); \
1051 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
1052 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
1053 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
1054 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
1055 \
1056 return 0; \
1057}
1058
1059#define CLK_SET_RATE(name, nr, bitsname) \
1060static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
1061{ \
1062 u32 reg, div, parent_rate; \
1063 u32 pre = 0, post = 0; \
1064 \
1065 parent_rate = clk_get_rate(clk->parent); \
1066 div = parent_rate / rate; \
1067 \
1068 if ((parent_rate / div) != rate) \
1069 return -EINVAL; \
1070 \
1071 __calc_pre_post_dividers(div, &pre, &post, \
1072 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
1073 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
1074 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
1075 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
1076 \
1077 /* Set sdhc1 clock divider */ \
1078 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
1079 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
1080 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
1081 reg |= (post - 1) << \
1082 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1083 reg |= (pre - 1) << \
1084 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1085 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
1086 \
1087 return 0; \
1088}
1089
1090/* UART */
1091CLK_GET_RATE(uart, 1, UART)
1092CLK_SET_PARENT(uart, 1, UART)
1093
1094static struct clk uart_root_clk = {
1095 .parent = &pll2_sw_clk,
1096 .get_rate = clk_uart_get_rate,
1097 .set_parent = clk_uart_set_parent,
1098};
1099
1100/* USBOH3 */
1101CLK_GET_RATE(usboh3, 1, USBOH3)
1102CLK_SET_PARENT(usboh3, 1, USBOH3)
1103
1104static struct clk usboh3_clk = {
1105 .parent = &pll2_sw_clk,
1106 .get_rate = clk_usboh3_get_rate,
1107 .set_parent = clk_usboh3_set_parent,
1108 .enable = _clk_ccgr_enable,
1109 .disable = _clk_ccgr_disable,
1110 .enable_reg = MXC_CCM_CCGR2,
1111 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1112};
1113
1114static struct clk usb_ahb_clk = {
1115 .parent = &ipg_clk,
1116 .enable = _clk_ccgr_enable,
1117 .disable = _clk_ccgr_disable,
1118 .enable_reg = MXC_CCM_CCGR2,
1119 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1120};
1121
1122static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
1123{
1124 u32 reg;
1125
1126 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
1127
1128 if (parent == &pll3_sw_clk)
1129 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
1130
1131 __raw_writel(reg, MXC_CCM_CSCMR1);
1132
1133 return 0;
1134}
1135
1136static struct clk usb_phy1_clk = {
1137 .parent = &pll3_sw_clk,
1138 .set_parent = clk_usb_phy1_set_parent,
1139 .enable = _clk_ccgr_enable,
1140 .enable_reg = MXC_CCM_CCGR2,
1141 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1142 .disable = _clk_ccgr_disable,
1143};
1144
1145/* eCSPI */
1146CLK_GET_RATE(ecspi, 2, CSPI)
1147CLK_SET_PARENT(ecspi, 1, CSPI)
1148
1149static struct clk ecspi_main_clk = {
1150 .parent = &pll3_sw_clk,
1151 .get_rate = clk_ecspi_get_rate,
1152 .set_parent = clk_ecspi_set_parent,
1153};
1154
1155/* eSDHC */
1156CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1157CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1158CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1159
1160/* mx51 specific */
1161CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1162CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1163CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1164
1165static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1166{
1167 u32 reg;
1168
1169 reg = __raw_readl(MXC_CCM_CSCMR1);
1170 if (parent == &esdhc1_clk)
1171 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1172 else if (parent == &esdhc2_clk)
1173 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1174 else
1175 return -EINVAL;
1176 __raw_writel(reg, MXC_CCM_CSCMR1);
1177
1178 return 0;
1179}
1180
1181static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1182{
1183 u32 reg;
1184
1185 reg = __raw_readl(MXC_CCM_CSCMR1);
1186 if (parent == &esdhc1_clk)
1187 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1188 else if (parent == &esdhc2_clk)
1189 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1190 else
1191 return -EINVAL;
1192 __raw_writel(reg, MXC_CCM_CSCMR1);
1193
1194 return 0;
1195}
1196
1197/* mx53 specific */
1198static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1199{
1200 u32 reg;
1201
1202 reg = __raw_readl(MXC_CCM_CSCMR1);
1203 if (parent == &esdhc1_clk)
1204 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1205 else if (parent == &esdhc3_mx53_clk)
1206 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1207 else
1208 return -EINVAL;
1209 __raw_writel(reg, MXC_CCM_CSCMR1);
1210
1211 return 0;
1212}
1213
1214CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1215CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1216CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1217
1218static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1219{
1220 u32 reg;
1221
1222 reg = __raw_readl(MXC_CCM_CSCMR1);
1223 if (parent == &esdhc1_clk)
1224 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1225 else if (parent == &esdhc3_mx53_clk)
1226 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1227 else
1228 return -EINVAL;
1229 __raw_writel(reg, MXC_CCM_CSCMR1);
1230
1231 return 0;
1232}
1233
1234#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
1235 static struct clk name = { \
1236 .id = i, \
1237 .enable_reg = er, \
1238 .enable_shift = es, \
1239 .get_rate = gr, \
1240 .set_rate = sr, \
1241 .enable = e, \
1242 .disable = d, \
1243 .parent = p, \
1244 .secondary = s, \
1245 }
1246
1247#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
1248 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
1249
1250/* Shared peripheral bus arbiter */
1251DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
1252 NULL, NULL, &ipg_clk, NULL);
1253
1254/* UART */
1255DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
1256 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1257DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
1258 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1259DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1260 NULL, NULL, &ipg_clk, &spba_clk);
1261DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
1262 NULL, NULL, &ipg_clk, &spba_clk);
1263DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
1264 NULL, NULL, &ipg_clk, &spba_clk);
1265DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1266 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
1267DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1268 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
1269DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1270 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
1271DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
1272 NULL, NULL, &uart_root_clk, &uart4_ipg_clk);
1273DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
1274 NULL, NULL, &uart_root_clk, &uart5_ipg_clk);
1275
1276/* GPT */
1277DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1278 NULL, NULL, &ipg_clk, NULL);
1279DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1280 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
1281
1282DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
1283 NULL, NULL, &ipg_clk, NULL);
1284DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
1285 NULL, NULL, &ipg_clk, NULL);
1286
1287/* I2C */
1288DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1289 NULL, NULL, &ipg_perclk, NULL);
1290DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1291 NULL, NULL, &ipg_perclk, NULL);
1292DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1293 NULL, NULL, &ipg_clk, NULL);
1294DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1295 NULL, NULL, &ipg_perclk, NULL);
1296
1297/* FEC */
1298DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1299 NULL, NULL, &ipg_clk, NULL);
1300
1301/* NFC */
1302DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1303 clk_nfc, &emi_slow_clk, NULL);
1304
1305/* SSI */
1306DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1307 NULL, NULL, &ipg_clk, NULL);
1308DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1309 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1310DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1311 NULL, NULL, &ipg_clk, NULL);
1312DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1313 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1314DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
1315 NULL, NULL, &ipg_clk, NULL);
1316DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
1317 NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
1318
1319/* eCSPI */
1320DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1321 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1322 &ipg_clk, &spba_clk);
1323DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1324 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1325DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1326 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1327 &ipg_clk, &aips_tz2_clk);
1328DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1329 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1330
1331/* CSPI */
1332DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1333 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1334DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1335 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1336
1337/* SDMA */
1338DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1339 NULL, NULL, &ahb_clk, NULL);
1340
1341/* eSDHC */
1342DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1343 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1344DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1345 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1346DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1347 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1348DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1349 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1350DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1351 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1352
1353/* mx51 specific */
1354DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1355 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1356
1357static struct clk esdhc3_clk = {
1358 .id = 2,
1359 .parent = &esdhc1_clk,
1360 .set_parent = clk_esdhc3_set_parent,
1361 .enable_reg = MXC_CCM_CCGR3,
1362 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1363 .enable = _clk_max_enable,
1364 .disable = _clk_max_disable,
1365 .secondary = &esdhc3_ipg_clk,
1366};
1367static struct clk esdhc4_clk = {
1368 .id = 3,
1369 .parent = &esdhc1_clk,
1370 .set_parent = clk_esdhc4_set_parent,
1371 .enable_reg = MXC_CCM_CCGR3,
1372 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1373 .enable = _clk_max_enable,
1374 .disable = _clk_max_disable,
1375 .secondary = &esdhc4_ipg_clk,
1376};
1377
1378/* mx53 specific */
1379static struct clk esdhc2_mx53_clk = {
1380 .id = 2,
1381 .parent = &esdhc1_clk,
1382 .set_parent = clk_esdhc2_mx53_set_parent,
1383 .enable_reg = MXC_CCM_CCGR3,
1384 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1385 .enable = _clk_max_enable,
1386 .disable = _clk_max_disable,
1387 .secondary = &esdhc3_ipg_clk,
1388};
1389
1390DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1391 clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1392
1393static struct clk esdhc4_mx53_clk = {
1394 .id = 3,
1395 .parent = &esdhc1_clk,
1396 .set_parent = clk_esdhc4_mx53_set_parent,
1397 .enable_reg = MXC_CCM_CCGR3,
1398 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1399 .enable = _clk_max_enable,
1400 .disable = _clk_max_disable,
1401 .secondary = &esdhc4_ipg_clk,
1402};
1403
1404DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1405DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1406DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
1407
1408/* IPU */
1409DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
1410 NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
1411
1412DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
1413 NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
1414 &ddr_clk, NULL);
1415
1416DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1417 NULL, NULL, &pll3_sw_clk, NULL);
1418DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1419 NULL, NULL, &pll3_sw_clk, NULL);
1420
1421#define _REGISTER_CLOCK(d, n, c) \
1422 { \
1423 .dev_id = d, \
1424 .con_id = n, \
1425 .clk = &c, \
1426 },
1427
1428static struct clk_lookup mx51_lookups[] = {
1429 /* i.mx51 has the i.mx21 type uart */
1430 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1431 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1432 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1433 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1434 /* i.mx51 has the i.mx27 type fec */
1435 _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
1436 _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
1437 _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
1438 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1439 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1440 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1441 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1442 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1443 _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1444 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1445 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1446 _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1447 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1448 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1449 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1450 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1451 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1452 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1453 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1454 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1455 /* i.mx51 has the i.mx35 type sdma */
1456 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1457 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1458 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1459 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1460 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1461 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1462 /* i.mx51 has the i.mx35 type cspi */
1463 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1464 _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
1465 _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
1466 _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
1467 _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
1468 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1469 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1470 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1471 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1472 _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
1473 _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1474 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1475 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1476 _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
1477};
1478
1479static struct clk_lookup mx53_lookups[] = {
1480 /* i.mx53 has the i.mx21 type uart */
1481 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1482 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1483 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1484 _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
1485 _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
1486 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1487 /* i.mx53 has the i.mx25 type fec */
1488 _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
1489 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1490 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1491 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1492 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
1493 /* i.mx53 has the i.mx51 type ecspi */
1494 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1495 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1496 /* i.mx53 has the i.mx25 type cspi */
1497 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1498 _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
1499 _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
1500 _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
1501 _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
1502 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1503 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1504 /* i.mx53 has the i.mx35 type sdma */
1505 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1506 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1507 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1508 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1509 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1510};
1511
1512static void clk_tree_init(void)
1513{
1514 u32 reg;
1515
1516 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1517
1518 /*
1519 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1520 * 8MHz, its derived from lp_apm.
1521 *
1522 * FIXME: Verify if true for all boards
1523 */
1524 reg = __raw_readl(MXC_CCM_CBCDR);
1525 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1526 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1527 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1528 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1529 __raw_writel(reg, MXC_CCM_CBCDR);
1530}
1531
1532int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1533 unsigned long ckih1, unsigned long ckih2)
1534{
1535 int i;
1536
1537 external_low_reference = ckil;
1538 external_high_reference = ckih1;
1539 ckih2_reference = ckih2;
1540 oscillator_reference = osc;
1541
1542 for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1543 clkdev_add(&mx51_lookups[i]);
1544
1545 clk_tree_init();
1546
1547 clk_enable(&cpu_clk);
1548 clk_enable(&main_bus_clk);
1549
1550 clk_enable(&iim_clk);
1551 mx51_revision();
1552 clk_disable(&iim_clk);
1553 mx51_display_revision();
1554
1555 /* move usb_phy_clk to 24MHz */
1556 clk_set_parent(&usb_phy1_clk, &osc_clk);
1557
1558 /* set the usboh3_clk parent to pll2_sw_clk */
1559 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1560
1561 /* Set SDHC parents to be PLL2 */
1562 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1563 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1564
1565 /* set SDHC root clock as 166.25MHZ*/
1566 clk_set_rate(&esdhc1_clk, 166250000);
1567 clk_set_rate(&esdhc2_clk, 166250000);
1568
1569 /* System timer */
1570 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1571 MX51_MXC_INT_GPT);
1572 return 0;
1573}
1574
1575int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1576 unsigned long ckih1, unsigned long ckih2)
1577{
1578 int i;
1579
1580 external_low_reference = ckil;
1581 external_high_reference = ckih1;
1582 ckih2_reference = ckih2;
1583 oscillator_reference = osc;
1584
1585 for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1586 clkdev_add(&mx53_lookups[i]);
1587
1588 clk_tree_init();
1589
1590 clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1591 clk_enable(&cpu_clk);
1592 clk_enable(&main_bus_clk);
1593
1594 clk_enable(&iim_clk);
1595 mx53_revision();
1596 clk_disable(&iim_clk);
1597 mx53_display_revision();
1598
1599 /* Set SDHC parents to be PLL2 */
1600 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1601 clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1602
1603 /* set SDHC root clock as 200MHZ*/
1604 clk_set_rate(&esdhc1_clk, 200000000);
1605 clk_set_rate(&esdhc3_mx53_clk, 200000000);
1606
1607 /* System timer */
1608 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1609 MX53_INT_GPT);
1610 return 0;
1611}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
new file mode 100644
index 00000000000..86f87da59c6
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu.c
@@ -0,0 +1,226 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <mach/hardware.h>
19#include <asm/io.h>
20
21static int cpu_silicon_rev = -1;
22
23#define IIM_SREV 0x24
24#define MX50_HW_ADADIG_DIGPROG 0xB0
25
26static int get_mx51_srev(void)
27{
28 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
29 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
30
31 if (rev == 0x0)
32 return IMX_CHIP_REVISION_2_0;
33 else if (rev == 0x10)
34 return IMX_CHIP_REVISION_3_0;
35 return 0;
36}
37
38/*
39 * Returns:
40 * the silicon revision of the cpu
41 * -EINVAL - not a mx51
42 */
43int mx51_revision(void)
44{
45 if (!cpu_is_mx51())
46 return -EINVAL;
47
48 if (cpu_silicon_rev == -1)
49 cpu_silicon_rev = get_mx51_srev();
50
51 return cpu_silicon_rev;
52}
53EXPORT_SYMBOL(mx51_revision);
54
55void mx51_display_revision(void)
56{
57 int rev;
58 char *srev;
59 rev = mx51_revision();
60
61 switch (rev) {
62 case IMX_CHIP_REVISION_2_0:
63 srev = IMX_CHIP_REVISION_2_0_STRING;
64 break;
65 case IMX_CHIP_REVISION_3_0:
66 srev = IMX_CHIP_REVISION_3_0_STRING;
67 break;
68 default:
69 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
70 }
71 printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
72}
73EXPORT_SYMBOL(mx51_display_revision);
74
75#ifdef CONFIG_NEON
76
77/*
78 * All versions of the silicon before Rev. 3 have broken NEON implementations.
79 * Dependent on link order - so the assumption is that vfp_init is called
80 * before us.
81 */
82static int __init mx51_neon_fixup(void)
83{
84 if (!cpu_is_mx51())
85 return 0;
86
87 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
88 elf_hwcap &= ~HWCAP_NEON;
89 pr_info("Turning off NEON support, detected broken NEON implementation\n");
90 }
91 return 0;
92}
93
94late_initcall(mx51_neon_fixup);
95#endif
96
97static int get_mx53_srev(void)
98{
99 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
100 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
101
102 switch (rev) {
103 case 0x0:
104 return IMX_CHIP_REVISION_1_0;
105 case 0x2:
106 return IMX_CHIP_REVISION_2_0;
107 case 0x3:
108 return IMX_CHIP_REVISION_2_1;
109 default:
110 return IMX_CHIP_REVISION_UNKNOWN;
111 }
112}
113
114/*
115 * Returns:
116 * the silicon revision of the cpu
117 * -EINVAL - not a mx53
118 */
119int mx53_revision(void)
120{
121 if (!cpu_is_mx53())
122 return -EINVAL;
123
124 if (cpu_silicon_rev == -1)
125 cpu_silicon_rev = get_mx53_srev();
126
127 return cpu_silicon_rev;
128}
129EXPORT_SYMBOL(mx53_revision);
130
131static int get_mx50_srev(void)
132{
133 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
134 u32 rev;
135
136 if (!anatop) {
137 cpu_silicon_rev = -EINVAL;
138 return 0;
139 }
140
141 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
142 rev &= 0xff;
143
144 iounmap(anatop);
145 if (rev == 0x0)
146 return IMX_CHIP_REVISION_1_0;
147 else if (rev == 0x1)
148 return IMX_CHIP_REVISION_1_1;
149 return 0;
150}
151
152/*
153 * Returns:
154 * the silicon revision of the cpu
155 * -EINVAL - not a mx50
156 */
157int mx50_revision(void)
158{
159 if (!cpu_is_mx50())
160 return -EINVAL;
161
162 if (cpu_silicon_rev == -1)
163 cpu_silicon_rev = get_mx50_srev();
164
165 return cpu_silicon_rev;
166}
167EXPORT_SYMBOL(mx50_revision);
168
169void mx53_display_revision(void)
170{
171 int rev;
172 char *srev;
173 rev = mx53_revision();
174
175 switch (rev) {
176 case IMX_CHIP_REVISION_1_0:
177 srev = IMX_CHIP_REVISION_1_0_STRING;
178 break;
179 case IMX_CHIP_REVISION_2_0:
180 srev = IMX_CHIP_REVISION_2_0_STRING;
181 break;
182 case IMX_CHIP_REVISION_2_1:
183 srev = IMX_CHIP_REVISION_2_1_STRING;
184 break;
185 default:
186 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
187 }
188 printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
189}
190EXPORT_SYMBOL(mx53_display_revision);
191
192static int __init post_cpu_init(void)
193{
194 unsigned int reg;
195 void __iomem *base;
196
197 if (cpu_is_mx51() || cpu_is_mx53()) {
198 if (cpu_is_mx51())
199 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
200 else
201 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
202
203 __raw_writel(0x0, base + 0x40);
204 __raw_writel(0x0, base + 0x44);
205 __raw_writel(0x0, base + 0x48);
206 __raw_writel(0x0, base + 0x4C);
207 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
208 __raw_writel(reg, base + 0x50);
209
210 if (cpu_is_mx51())
211 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
212 else
213 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
214
215 __raw_writel(0x0, base + 0x40);
216 __raw_writel(0x0, base + 0x44);
217 __raw_writel(0x0, base + 0x48);
218 __raw_writel(0x0, base + 0x4C);
219 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
220 __raw_writel(reg, base + 0x50);
221 }
222
223 return 0;
224}
225
226postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
new file mode 100644
index 00000000000..9d34c3d4c02
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx51.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/types.h>
15#include <mach/hardware.h>
16#include <linux/kernel.h>
17
18static struct cpu_op mx51_cpu_op[] = {
19 {
20 .cpu_rate = 160000000,},
21 {
22 .cpu_rate = 800000000,},
23};
24
25struct cpu_op *mx51_get_cpu_op(int *op)
26{
27 *op = ARRAY_SIZE(mx51_cpu_op);
28 return mx51_cpu_op;
29}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
new file mode 100644
index 00000000000..97477fecb46
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx51.h
@@ -0,0 +1,14 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
new file mode 100644
index 00000000000..5e11ba7daee
--- /dev/null
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -0,0 +1,600 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
13
14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20
21/*MX53*/
22#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
23#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
24#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
25#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
26#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
27
28/* PLL Register Offsets */
29#define MXC_PLL_DP_CTL 0x00
30#define MXC_PLL_DP_CONFIG 0x04
31#define MXC_PLL_DP_OP 0x08
32#define MXC_PLL_DP_MFD 0x0C
33#define MXC_PLL_DP_MFN 0x10
34#define MXC_PLL_DP_MFNMINUS 0x14
35#define MXC_PLL_DP_MFNPLUS 0x18
36#define MXC_PLL_DP_HFS_OP 0x1C
37#define MXC_PLL_DP_HFS_MFD 0x20
38#define MXC_PLL_DP_HFS_MFN 0x24
39#define MXC_PLL_DP_MFN_TOGC 0x28
40#define MXC_PLL_DP_DESTAT 0x2c
41
42/* PLL Register Bit definitions */
43#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
44#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
45#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
46#define MXC_PLL_DP_CTL_ADE 0x800
47#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
48#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
49#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
50#define MXC_PLL_DP_CTL_HFSM 0x80
51#define MXC_PLL_DP_CTL_PRE 0x40
52#define MXC_PLL_DP_CTL_UPEN 0x20
53#define MXC_PLL_DP_CTL_RST 0x10
54#define MXC_PLL_DP_CTL_RCP 0x8
55#define MXC_PLL_DP_CTL_PLM 0x4
56#define MXC_PLL_DP_CTL_BRM0 0x2
57#define MXC_PLL_DP_CTL_LRF 0x1
58
59#define MXC_PLL_DP_CONFIG_BIST 0x8
60#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
61#define MXC_PLL_DP_CONFIG_AREN 0x2
62#define MXC_PLL_DP_CONFIG_LDREQ 0x1
63
64#define MXC_PLL_DP_OP_MFI_OFFSET 4
65#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
66#define MXC_PLL_DP_OP_PDF_OFFSET 0
67#define MXC_PLL_DP_OP_PDF_MASK 0xF
68
69#define MXC_PLL_DP_MFD_OFFSET 0
70#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
71
72#define MXC_PLL_DP_MFN_OFFSET 0x0
73#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
74
75#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
76#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
77#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
78#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
79
80#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
81#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
82
83/* Register addresses of CCM*/
84#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
85#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
86#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
87#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
88#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
89#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
90#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
91#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
92#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
93#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
94#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
95#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
96#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
97#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
98#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
99#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
100#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
101#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
102#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
103#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
104#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
105#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
106#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
107#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
108#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
109#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
110#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
111#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
112#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
113#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
114#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
115#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
116#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
117#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
118
119#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
120
121/* Define the bits in register CCR */
122#define MXC_CCM_CCR_COSC_EN (1 << 12)
123#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
124#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
125#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
126#define MXC_CCM_CCR_FPM_EN (1 << 8)
127#define MXC_CCM_CCR_OSCNT_OFFSET (0)
128#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
129
130/* Define the bits in register CCDR */
131#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
132#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
133#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
134
135/* Define the bits in register CSR */
136#define MXC_CCM_CSR_COSR_READY (1 << 5)
137#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
138#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
139#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
140#define MXC_CCM_CSR_FPM_READY (1 << 1)
141#define MXC_CCM_CSR_REF_EN_B (1 << 0)
142
143/* Define the bits in register CCSR */
144#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
145#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
146#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
147#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
148#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
149#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
150#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
151#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
152#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
153#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
154#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
155#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
156 1: step_clk */
157#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
158#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
159
160/* Define the bits in register CACRR */
161#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
162#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
163
164/* Define the bits in register CBCDR */
165#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
166#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
167#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
168#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
169#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
170#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
171#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
172#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
173#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
174#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
175#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
176#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
177#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
178#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
179#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
180#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
181#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
182#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
183#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
184#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
185#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
186#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
187#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
188#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
189
190/* Define the bits in register CBCMR */
191#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
192#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
193#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
194#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
195#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
196#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
197#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
198#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
199#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
200#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
201#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
202#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
203#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
204#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
205#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
206#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
207
208/* Define the bits in register CSCMR1 */
209#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
210#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
211#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
212#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
213#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
214#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
215#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
216#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
217#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
218#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
219#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
220#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
221#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
223#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
224#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
225#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
226#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
227#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
228#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
229#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
230#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
231#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
232#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
233#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
234#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
235#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
236#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
237#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
238#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
239#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
240#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
241#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
242#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
243#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
244
245/* Define the bits in register CSCMR2 */
246#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
247#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
248#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
249#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
250#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
251#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
252#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
253#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
254#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
255#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
256#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
257#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
258#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
259#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
260#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
261#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
262#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
263#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
264#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
265#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
266#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
267#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
268#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
269#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
270#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
271#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
272#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
273
274/* Define the bits in register CSCDR1 */
275#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
276#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
277#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
278#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
279#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
280#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
281#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
282#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
283#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
284#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
285#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
286#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
287#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
288#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
289#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
290#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
291#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
292#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
293#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
294#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
295#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
296#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
297
298/* Define the bits in register CS1CDR and CS2CDR */
299#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
300#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
301#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
302#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
303#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
304#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
305#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
306#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
307
308#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
309#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
310#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
311#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
312#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
313#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
314#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
315#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
316
317/* Define the bits in register CDCDR */
318#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
319#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
320#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
321#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
322#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
323#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
324#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
325#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
326#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
327#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
328#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
329#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
330#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
331#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
332#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
333#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
334
335/* Define the bits in register CHSCCDR */
336#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
337#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
338#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
339#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
340#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
341#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
342#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
343#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
344
345/* Define the bits in register CSCDR2 */
346#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
347#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
348#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
349#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
350#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
351#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
352#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
353#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
354#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
355#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
356#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
357#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
358
359/* Define the bits in register CSCDR3 */
360#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
361#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
362#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
363#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
364#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
365#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
366#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
367#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
368
369/* Define the bits in register CSCDR4 */
370#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
371#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
372#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
373#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
374#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
375#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
376#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
377#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
378
379/* Define the bits in register CDHIPR */
380#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
381#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
382#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
383#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
384#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
385#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
386#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
387#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
388#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
389#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
390
391/* Define the bits in register CDCR */
392#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
393#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
394#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
395
396/* Define the bits in register CLPCR */
397#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
398#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
399#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
400#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
401#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
402#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
403#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
404#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
405#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
406#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
407#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
408#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
409#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
410#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
411#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
412#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
413#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
414#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
415#define MXC_CCM_CLPCR_LPM_OFFSET (0)
416#define MXC_CCM_CLPCR_LPM_MASK (0x3)
417
418/* Define the bits in register CISR */
419#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
420#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
421#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
422#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
423#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
424#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
425#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
426#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
427#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
428#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
429#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
430#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
431#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
432#define MXC_CCM_CISR_LRF_PLL1 (0x1)
433
434/* Define the bits in register CIMR */
435#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
436#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
437#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
438#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
439#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
440#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
441#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
442#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
443#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
444#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
445#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
446#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
447#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
448
449/* Define the bits in register CCOSR */
450#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
451#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
452#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
453#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
454#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
455#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
456#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
457#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
458#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
459#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
460
461/* Define the bits in registers CGPR */
462#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
463#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
464#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
465#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
466
467/* Define the bits in registers CCGRx */
468#define MXC_CCM_CCGRx_CG_MASK 0x3
469#define MXC_CCM_CCGRx_MOD_OFF 0x0
470#define MXC_CCM_CCGRx_MOD_ON 0x3
471#define MXC_CCM_CCGRx_MOD_IDLE 0x1
472
473#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
474#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
475#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
476#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
477#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
478#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
479#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
480#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
481#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
482#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
483#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
484#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
485#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
486#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
487
488#define MXC_CCM_CCGRx_CG15_OFFSET 30
489#define MXC_CCM_CCGRx_CG14_OFFSET 28
490#define MXC_CCM_CCGRx_CG13_OFFSET 26
491#define MXC_CCM_CCGRx_CG12_OFFSET 24
492#define MXC_CCM_CCGRx_CG11_OFFSET 22
493#define MXC_CCM_CCGRx_CG10_OFFSET 20
494#define MXC_CCM_CCGRx_CG9_OFFSET 18
495#define MXC_CCM_CCGRx_CG8_OFFSET 16
496#define MXC_CCM_CCGRx_CG7_OFFSET 14
497#define MXC_CCM_CCGRx_CG6_OFFSET 12
498#define MXC_CCM_CCGRx_CG5_OFFSET 10
499#define MXC_CCM_CCGRx_CG4_OFFSET 8
500#define MXC_CCM_CCGRx_CG3_OFFSET 6
501#define MXC_CCM_CCGRx_CG2_OFFSET 4
502#define MXC_CCM_CCGRx_CG1_OFFSET 2
503#define MXC_CCM_CCGRx_CG0_OFFSET 0
504
505#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
506#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
507#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
508#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
509#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
510#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
511#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
512#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
513#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
514#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
515#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
516#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
517#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
518
519/* CORTEXA8 platform */
520#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
521#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
522#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
523#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
524#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
525#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
526#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
527#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
528#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
529
530/* DVFS CORE */
531#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
532#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
533#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
534#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
535#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
536#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
537#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
538#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
539#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
540#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
541#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
542#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
543#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
544#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
545#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
546#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
547#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
548
549/* GPC */
550#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
551#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
552#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
553#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
554#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
555#define MXC_GPC_PGR_ARMPG_OFFSET 8
556#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
557
558/* PGC */
559#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
560#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
561#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
562#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
563#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
564#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
565
566#define MXC_PGCR_PCR 1
567#define MXC_SRPGCR_PCR 1
568#define MXC_EMPGCR_PCR 1
569#define MXC_PGSR_PSR 1
570
571
572#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
573#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
574
575/* SRPG */
576#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
577#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
578#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
579
580#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
581#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
582#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
583
584#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
585#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
586#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
587
588#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
589#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
590#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
591
592#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
593#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
594#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
595
596#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
597#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
598#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
599
600#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
new file mode 100644
index 00000000000..7216667eaaf
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <mach/mx50.h>
22#include <mach/devices-common.h>
23
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
27
28extern const struct imx_fec_data imx50_fec_data;
29#define imx50_add_fec(pdata) \
30 imx_add_fec(&imx50_fec_data, pdata)
31
32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
33#define imx50_add_imx_i2c(id, pdata) \
34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 00000000000..e11bc0e0ec4
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx51.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fec_data imx51_fec_data;
13#define imx51_add_fec(pdata) \
14 imx_add_fec(&imx51_fec_data, pdata)
15
16extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
17#define imx51_add_imx_i2c(id, pdata) \
18 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
19
20extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
21#define imx51_add_imx_ssi(id, pdata) \
22 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
23
24extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
25#define imx51_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
27
28extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
29#define imx51_add_mxc_nand(pdata) \
30 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
31
32extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
33#define imx51_add_sdhci_esdhc_imx(id, pdata) \
34 imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
35
36extern const struct imx_spi_imx_data imx51_cspi_data;
37#define imx51_add_cspi(pdata) \
38 imx_add_spi_imx(&imx51_cspi_data, pdata)
39
40extern const struct imx_spi_imx_data imx51_ecspi_data[];
41#define imx51_add_ecspi(id, pdata) \
42 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
43
44extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
45#define imx51_add_imx2_wdt(id, pdata) \
46 imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
47
48extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
49#define imx51_add_mxc_pwm(id) \
50 imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
51
52extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
53#define imx51_add_imx_keypad(pdata) \
54 imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
new file mode 100644
index 00000000000..c27fe8bb476
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <mach/mx53.h>
9#include <mach/devices-common.h>
10
11extern const struct imx_fec_data imx53_fec_data;
12#define imx53_add_fec(pdata) \
13 imx_add_fec(&imx53_fec_data, pdata)
14
15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
16#define imx53_add_imx_uart(id, pdata) \
17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
18
19
20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
21#define imx53_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
23
24extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
25#define imx53_add_sdhci_esdhc_imx(id, pdata) \
26 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
27
28extern const struct imx_spi_imx_data imx53_ecspi_data[];
29#define imx53_add_ecspi(id, pdata) \
30 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
31
32extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
33#define imx53_add_imx2_wdt(id, pdata) \
34 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
35
36extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
37#define imx53_add_imx_ssi(id, pdata) \
38 imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
39
40extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
41#define imx53_add_imx_keypad(pdata) \
42 imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 00000000000..371ca8c8414
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,120 @@
1/*
2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <mach/hardware.h>
16#include <mach/imx-uart.h>
17#include <mach/irqs.h>
18
19static struct resource mxc_hsi2c_resources[] = {
20 {
21 .start = MX51_HSI2C_DMA_BASE_ADDR,
22 .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
23 .flags = IORESOURCE_MEM,
24 },
25 {
26 .start = MX51_MXC_INT_HS_I2C,
27 .end = MX51_MXC_INT_HS_I2C,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32struct platform_device mxc_hsi2c_device = {
33 .name = "imx-i2c",
34 .id = 2,
35 .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
36 .resource = mxc_hsi2c_resources
37};
38
39static u64 usb_dma_mask = DMA_BIT_MASK(32);
40
41static struct resource usbotg_resources[] = {
42 {
43 .start = MX51_OTG_BASE_ADDR,
44 .end = MX51_OTG_BASE_ADDR + 0x1ff,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .start = MX51_MXC_INT_USB_OTG,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53/* OTG gadget device */
54struct platform_device mxc_usbdr_udc_device = {
55 .name = "fsl-usb2-udc",
56 .id = -1,
57 .num_resources = ARRAY_SIZE(usbotg_resources),
58 .resource = usbotg_resources,
59 .dev = {
60 .dma_mask = &usb_dma_mask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 },
63};
64
65struct platform_device mxc_usbdr_host_device = {
66 .name = "mxc-ehci",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(usbotg_resources),
69 .resource = usbotg_resources,
70 .dev = {
71 .dma_mask = &usb_dma_mask,
72 .coherent_dma_mask = DMA_BIT_MASK(32),
73 },
74};
75
76static struct resource usbh1_resources[] = {
77 {
78 .start = MX51_OTG_BASE_ADDR + 0x200,
79 .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
80 .flags = IORESOURCE_MEM,
81 },
82 {
83 .start = MX51_MXC_INT_USB_H1,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88struct platform_device mxc_usbh1_device = {
89 .name = "mxc-ehci",
90 .id = 1,
91 .num_resources = ARRAY_SIZE(usbh1_resources),
92 .resource = usbh1_resources,
93 .dev = {
94 .dma_mask = &usb_dma_mask,
95 .coherent_dma_mask = DMA_BIT_MASK(32),
96 },
97};
98
99static struct resource usbh2_resources[] = {
100 {
101 .start = MX51_OTG_BASE_ADDR + 0x400,
102 .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
103 .flags = IORESOURCE_MEM,
104 },
105 {
106 .start = MX51_MXC_INT_USB_H2,
107 .flags = IORESOURCE_IRQ,
108 },
109};
110
111struct platform_device mxc_usbh2_device = {
112 .name = "mxc-ehci",
113 .id = 2,
114 .num_resources = ARRAY_SIZE(usbh2_resources),
115 .resource = usbh2_resources,
116 .dev = {
117 .dma_mask = &usb_dma_mask,
118 .coherent_dma_mask = DMA_BIT_MASK(32),
119 },
120};
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 00000000000..55a5129bc29
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,5 @@
1extern struct platform_device mxc_usbdr_host_device;
2extern struct platform_device mxc_usbh1_device;
3extern struct platform_device mxc_usbh2_device;
4extern struct platform_device mxc_usbdr_udc_device;
5extern struct platform_device mxc_hsi2c_device;
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 00000000000..014aa985faa
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 00000000000..7ce12c804a3
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
25
26/* USB_CTRL */
27#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
28#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
29#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
30#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
31#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
32
33/* USB_PHY_CTRL_FUNC */
34#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
35#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
36
37/* USBH2CTRL */
38#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
39#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
40#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
41
42#define MXC_USBCMD_OFFSET 0x140
43
44/* USBCMD */
45#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
46
47int mx51_initialize_usb_hw(int port, unsigned int flags)
48{
49 unsigned int v;
50 void __iomem *usb_base;
51 void __iomem *usbotg_base;
52 void __iomem *usbother_base;
53 int ret = 0;
54
55 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
56 if (!usb_base) {
57 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
58 return -ENOMEM;
59 }
60
61 switch (port) {
62 case 0: /* OTG port */
63 usbotg_base = usb_base + MXC_OTG_OFFSET;
64 break;
65 case 1: /* Host 1 port */
66 usbotg_base = usb_base + MXC_H1_OFFSET;
67 break;
68 case 2: /* Host 2 port */
69 usbotg_base = usb_base + MXC_H2_OFFSET;
70 break;
71 default:
72 printk(KERN_ERR"%s no such port %d\n", __func__, port);
73 ret = -ENOENT;
74 goto error;
75 }
76 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
77
78 switch (port) {
79 case 0: /*OTG port */
80 if (flags & MXC_EHCI_INTERNAL_PHY) {
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
82
83 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
84 /* OC/USBPWR is not used */
85 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
86 } else {
87 /* OC/USBPWR is used */
88 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
89 }
90 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
91
92 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
93 if (flags & MXC_EHCI_WAKEUP_ENABLED)
94 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
95 else
96 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
97 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
98 v |= MXC_OTG_UCTRL_OPM_BIT;
99 else
100 v &= ~MXC_OTG_UCTRL_OPM_BIT;
101 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
102 }
103 break;
104 case 1: /* Host 1 */
105 /*Host ULPI */
106 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
107 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
108 /* HOST1 wakeup/ULPI intr enable */
109 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
110 } else {
111 /* HOST1 wakeup/ULPI intr disable */
112 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
113 }
114
115 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
116 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
117 else
118 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
119 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
120
121 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
122 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
123 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
124 else
125 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
126 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
127
128 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
129 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
130 /* Interrupt Threshold Control:Immediate (no threshold) */
131 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
132 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
133 break;
134 case 2: /* Host 2 ULPI */
135 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
136 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
137 /* HOST1 wakeup/ULPI intr enable */
138 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
139 } else {
140 /* HOST1 wakeup/ULPI intr disable */
141 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
142 }
143
144 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
145 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
146 else
147 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
148 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
149 break;
150 }
151
152error:
153 iounmap(usb_base);
154 return ret;
155}
156
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
new file mode 100644
index 00000000000..bbf4564bd05
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -0,0 +1,207 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/serial_8250.h>
16#include <linux/i2c.h>
17#include <linux/gpio.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/i2c/tsc2007.h>
22#include <linux/leds.h>
23
24#include <mach/common.h>
25#include <mach/hardware.h>
26#include <mach/iomux-mx51.h>
27
28#include <asm/mach/arch.h>
29
30#include "devices-imx51.h"
31#include "devices.h"
32
33#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
34#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
35#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
36#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
37#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
38
39static const struct gpio_led mbimx51_leds[] __initconst = {
40 {
41 .name = "led0",
42 .default_trigger = "heartbeat",
43 .active_low = 1,
44 .gpio = MBIMX51_LED0,
45 },
46 {
47 .name = "led1",
48 .default_trigger = "nand-disk",
49 .active_low = 1,
50 .gpio = MBIMX51_LED1,
51 },
52 {
53 .name = "led2",
54 .default_trigger = "mmc0",
55 .active_low = 1,
56 .gpio = MBIMX51_LED2,
57 },
58 {
59 .name = "led3",
60 .default_trigger = "default-on",
61 .active_low = 1,
62 .gpio = MBIMX51_LED3,
63 },
64};
65
66static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
67 .leds = mbimx51_leds,
68 .num_leds = ARRAY_SIZE(mbimx51_leds),
69};
70
71static iomux_v3_cfg_t mbimx51_pads[] = {
72 /* UART2 */
73 MX51_PAD_UART2_RXD__UART2_RXD,
74 MX51_PAD_UART2_TXD__UART2_TXD,
75
76 /* UART3 */
77 MX51_PAD_UART3_RXD__UART3_RXD,
78 MX51_PAD_UART3_TXD__UART3_TXD,
79 MX51_PAD_KEY_COL4__UART3_RTS,
80 MX51_PAD_KEY_COL5__UART3_CTS,
81
82 /* TSC2007 IRQ */
83 MX51_PAD_NANDF_D10__GPIO3_30,
84
85 /* LEDS */
86 MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
87 MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
88 MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
89 MX51_PAD_DISPB2_SER_RS__GPIO3_8,
90
91 /* KPP */
92 MX51_PAD_KEY_ROW0__KEY_ROW0,
93 MX51_PAD_KEY_ROW1__KEY_ROW1,
94 MX51_PAD_KEY_ROW2__KEY_ROW2,
95 MX51_PAD_KEY_ROW3__KEY_ROW3,
96 MX51_PAD_KEY_COL0__KEY_COL0,
97 MX51_PAD_KEY_COL1__KEY_COL1,
98 MX51_PAD_KEY_COL2__KEY_COL2,
99 MX51_PAD_KEY_COL3__KEY_COL3,
100
101 /* SD 1 */
102 MX51_PAD_SD1_CMD__SD1_CMD,
103 MX51_PAD_SD1_CLK__SD1_CLK,
104 MX51_PAD_SD1_DATA0__SD1_DATA0,
105 MX51_PAD_SD1_DATA1__SD1_DATA1,
106 MX51_PAD_SD1_DATA2__SD1_DATA2,
107 MX51_PAD_SD1_DATA3__SD1_DATA3,
108
109 /* SD 2 */
110 MX51_PAD_SD2_CMD__SD2_CMD,
111 MX51_PAD_SD2_CLK__SD2_CLK,
112 MX51_PAD_SD2_DATA0__SD2_DATA0,
113 MX51_PAD_SD2_DATA1__SD2_DATA1,
114 MX51_PAD_SD2_DATA2__SD2_DATA2,
115 MX51_PAD_SD2_DATA3__SD2_DATA3,
116};
117
118static const struct imxuart_platform_data uart_pdata __initconst = {
119 .flags = IMXUART_HAVE_RTSCTS,
120};
121
122static int mbimx51_keymap[] = {
123 KEY(0, 0, KEY_1),
124 KEY(0, 1, KEY_2),
125 KEY(0, 2, KEY_3),
126 KEY(0, 3, KEY_UP),
127
128 KEY(1, 0, KEY_4),
129 KEY(1, 1, KEY_5),
130 KEY(1, 2, KEY_6),
131 KEY(1, 3, KEY_LEFT),
132
133 KEY(2, 0, KEY_7),
134 KEY(2, 1, KEY_8),
135 KEY(2, 2, KEY_9),
136 KEY(2, 3, KEY_RIGHT),
137
138 KEY(3, 0, KEY_0),
139 KEY(3, 1, KEY_DOWN),
140 KEY(3, 2, KEY_ESC),
141 KEY(3, 3, KEY_ENTER),
142};
143
144static const struct matrix_keymap_data mbimx51_map_data __initconst = {
145 .keymap = mbimx51_keymap,
146 .keymap_size = ARRAY_SIZE(mbimx51_keymap),
147};
148
149static int tsc2007_get_pendown_state(void)
150{
151 return !gpio_get_value(MBIMX51_TSC2007_GPIO);
152}
153
154struct tsc2007_platform_data tsc2007_data = {
155 .model = 2007,
156 .x_plate_ohms = 180,
157 .get_pendown_state = tsc2007_get_pendown_state,
158};
159
160static struct i2c_board_info mbimx51_i2c_devices[] = {
161 {
162 I2C_BOARD_INFO("tsc2007", 0x49),
163 .irq = gpio_to_irq(MBIMX51_TSC2007_GPIO),
164 .platform_data = &tsc2007_data,
165 }, {
166 I2C_BOARD_INFO("tlv320aic23", 0x1a),
167 },
168};
169
170/*
171 * baseboard initialization.
172 */
173void __init eukrea_mbimx51_baseboard_init(void)
174{
175 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
176 ARRAY_SIZE(mbimx51_pads));
177
178 imx51_add_imx_uart(1, NULL);
179 imx51_add_imx_uart(2, &uart_pdata);
180
181 gpio_request(MBIMX51_LED0, "LED0");
182 gpio_direction_output(MBIMX51_LED0, 1);
183 gpio_free(MBIMX51_LED0);
184 gpio_request(MBIMX51_LED1, "LED1");
185 gpio_direction_output(MBIMX51_LED1, 1);
186 gpio_free(MBIMX51_LED1);
187 gpio_request(MBIMX51_LED2, "LED2");
188 gpio_direction_output(MBIMX51_LED2, 1);
189 gpio_free(MBIMX51_LED2);
190 gpio_request(MBIMX51_LED3, "LED3");
191 gpio_direction_output(MBIMX51_LED3, 1);
192 gpio_free(MBIMX51_LED3);
193
194 gpio_led_register_device(-1, &mbimx51_leds_info);
195
196 imx51_add_imx_keypad(&mbimx51_map_data);
197
198 gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
199 gpio_direction_input(MBIMX51_TSC2007_GPIO);
200 irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
201 IRQF_TRIGGER_FALLING);
202 i2c_register_board_info(1, mbimx51_i2c_devices,
203 ARRAY_SIZE(mbimx51_i2c_devices));
204
205 imx51_add_sdhci_esdhc_imx(0, NULL);
206 imx51_add_sdhci_esdhc_imx(1, NULL);
207}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 00000000000..26192399764
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/leds.h>
29#include <linux/platform_device.h>
30#include <linux/input.h>
31#include <linux/i2c.h>
32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39#include <mach/common.h>
40#include <mach/iomux-mx51.h>
41#include <mach/audmux.h>
42
43#include "devices-imx51.h"
44#include "devices.h"
45
46static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
47 /* LED */
48 MX51_PAD_NANDF_D10__GPIO3_30,
49 /* SWITCH */
50 _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
51 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
52 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
53 /* UART2 */
54 MX51_PAD_UART2_RXD__UART2_RXD,
55 MX51_PAD_UART2_TXD__UART2_TXD,
56 /* UART 3 */
57 MX51_PAD_UART3_RXD__UART3_RXD,
58 MX51_PAD_UART3_TXD__UART3_TXD,
59 MX51_PAD_KEY_COL4__UART3_RTS,
60 MX51_PAD_KEY_COL5__UART3_CTS,
61 /* SD */
62 MX51_PAD_SD1_CMD__SD1_CMD,
63 MX51_PAD_SD1_CLK__SD1_CLK,
64 MX51_PAD_SD1_DATA0__SD1_DATA0,
65 MX51_PAD_SD1_DATA1__SD1_DATA1,
66 MX51_PAD_SD1_DATA2__SD1_DATA2,
67 MX51_PAD_SD1_DATA3__SD1_DATA3,
68 /* SD1 CD */
69 _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
70 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
71 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
72};
73
74#define GPIO_LED1 IMX_GPIO_NR(3, 30)
75#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
76
77static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
78 {
79 .name = "led1",
80 .default_trigger = "heartbeat",
81 .active_low = 1,
82 .gpio = GPIO_LED1,
83 },
84};
85
86static const struct gpio_led_platform_data
87 eukrea_mbimxsd_led_info __initconst = {
88 .leds = eukrea_mbimxsd_leds,
89 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
90};
91
92static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
93 {
94 .gpio = GPIO_SWITCH1,
95 .code = BTN_0,
96 .desc = "BP1",
97 .active_low = 1,
98 .wakeup = 1,
99 },
100};
101
102static const struct gpio_keys_platform_data
103 eukrea_mbimxsd_button_data __initconst = {
104 .buttons = eukrea_mbimxsd_gpio_buttons,
105 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
106};
107
108static const struct imxuart_platform_data uart_pdata __initconst = {
109 .flags = IMXUART_HAVE_RTSCTS,
110};
111
112static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
113 {
114 I2C_BOARD_INFO("tlv320aic23", 0x1a),
115 },
116};
117
118/*
119 * system init for baseboard usage. Will be called by cpuimx51sd init.
120 *
121 * Add platform devices present on this baseboard and init
122 * them from CPU side as far as required to use them later on
123 */
124void __init eukrea_mbimxsd51_baseboard_init(void)
125{
126 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
127 ARRAY_SIZE(eukrea_mbimxsd_pads)))
128 printk(KERN_ERR "error setting mbimxsd pads !\n");
129
130 imx51_add_imx_uart(1, NULL);
131 imx51_add_imx_uart(2, &uart_pdata);
132
133 imx51_add_sdhci_esdhc_imx(0, NULL);
134
135 gpio_request(GPIO_LED1, "LED1");
136 gpio_direction_output(GPIO_LED1, 1);
137 gpio_free(GPIO_LED1);
138
139 gpio_request(GPIO_SWITCH1, "SWITCH1");
140 gpio_direction_input(GPIO_SWITCH1);
141 gpio_free(GPIO_SWITCH1);
142
143 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
144 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
145
146 gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
147 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
148}
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
new file mode 100644
index 00000000000..77e374c726f
--- /dev/null
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * Create static mapping between physical to virtual memory.
19 */
20
21#include <linux/mm.h>
22#include <linux/init.h>
23
24#include <asm/mach/map.h>
25
26#include <mach/hardware.h>
27#include <mach/common.h>
28#include <mach/iomux-v3.h>
29#include <mach/irqs.h>
30
31/*
32 * Define the MX50 memory map.
33 */
34static struct map_desc mx50_io_desc[] __initdata = {
35 imx_map_entry(MX50, TZIC, MT_DEVICE),
36 imx_map_entry(MX50, SPBA0, MT_DEVICE),
37 imx_map_entry(MX50, AIPS1, MT_DEVICE),
38 imx_map_entry(MX50, AIPS2, MT_DEVICE),
39};
40
41/*
42 * This function initializes the memory map. It is called during the
43 * system startup to create static physical to virtual memory mappings
44 * for the IO modules.
45 */
46void __init mx50_map_io(void)
47{
48 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
49}
50
51void __init imx50_init_early(void)
52{
53 mxc_set_cpu_type(MXC_CPU_MX50);
54 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
55 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
56}
57
58void __init mx50_init_irq(void)
59{
60 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
61}
62
63void __init imx50_soc_init(void)
64{
65 /* i.mx50 has the i.mx31 type gpio */
66 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
67 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
68 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
69 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
70 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
71 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
72}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
new file mode 100644
index 00000000000..baea6e5cddd
--- /dev/null
+++ b/arch/arm/mach-mx5/mm.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/hardware.h>
20#include <mach/common.h>
21#include <mach/devices-common.h>
22#include <mach/iomux-v3.h>
23
24/*
25 * Define the MX51 memory map.
26 */
27static struct map_desc mx51_io_desc[] __initdata = {
28 imx_map_entry(MX51, IRAM, MT_DEVICE),
29 imx_map_entry(MX51, DEBUG, MT_DEVICE),
30 imx_map_entry(MX51, AIPS1, MT_DEVICE),
31 imx_map_entry(MX51, SPBA0, MT_DEVICE),
32 imx_map_entry(MX51, AIPS2, MT_DEVICE),
33};
34
35/*
36 * Define the MX53 memory map.
37 */
38static struct map_desc mx53_io_desc[] __initdata = {
39 imx_map_entry(MX53, AIPS1, MT_DEVICE),
40 imx_map_entry(MX53, SPBA0, MT_DEVICE),
41 imx_map_entry(MX53, AIPS2, MT_DEVICE),
42};
43
44/*
45 * This function initializes the memory map. It is called during the
46 * system startup to create static physical to virtual memory mappings
47 * for the IO modules.
48 */
49void __init mx51_map_io(void)
50{
51 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
52}
53
54void __init imx51_init_early(void)
55{
56 mxc_set_cpu_type(MXC_CPU_MX51);
57 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
58 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
59}
60
61void __init mx53_map_io(void)
62{
63 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
64}
65
66void __init imx53_init_early(void)
67{
68 mxc_set_cpu_type(MXC_CPU_MX53);
69 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
70 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
71}
72
73void __init mx51_init_irq(void)
74{
75 unsigned long tzic_addr;
76 void __iomem *tzic_virt;
77
78 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
79 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
80 else
81 tzic_addr = MX51_TZIC_BASE_ADDR;
82
83 tzic_virt = ioremap(tzic_addr, SZ_16K);
84 if (!tzic_virt)
85 panic("unable to map TZIC interrupt controller\n");
86
87 tzic_init_irq(tzic_virt);
88}
89
90void __init mx53_init_irq(void)
91{
92 unsigned long tzic_addr;
93 void __iomem *tzic_virt;
94
95 tzic_addr = MX53_TZIC_BASE_ADDR;
96
97 tzic_virt = ioremap(tzic_addr, SZ_16K);
98 if (!tzic_virt)
99 panic("unable to map TZIC interrupt controller\n");
100
101 tzic_init_irq(tzic_virt);
102}
103
104static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
105 .ap_2_ap_addr = 642,
106 .uart_2_mcu_addr = 817,
107 .mcu_2_app_addr = 747,
108 .mcu_2_shp_addr = 961,
109 .ata_2_mcu_addr = 1473,
110 .mcu_2_ata_addr = 1392,
111 .app_2_per_addr = 1033,
112 .app_2_mcu_addr = 683,
113 .shp_2_per_addr = 1251,
114 .shp_2_mcu_addr = 892,
115};
116
117static struct sdma_platform_data imx51_sdma_pdata __initdata = {
118 .fw_name = "sdma-imx51.bin",
119 .script_addrs = &imx51_sdma_script,
120};
121
122static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
123 .ap_2_ap_addr = 642,
124 .app_2_mcu_addr = 683,
125 .mcu_2_app_addr = 747,
126 .uart_2_mcu_addr = 817,
127 .shp_2_mcu_addr = 891,
128 .mcu_2_shp_addr = 960,
129 .uartsh_2_mcu_addr = 1032,
130 .spdif_2_mcu_addr = 1100,
131 .mcu_2_spdif_addr = 1134,
132 .firi_2_mcu_addr = 1193,
133 .mcu_2_firi_addr = 1290,
134};
135
136static struct sdma_platform_data imx53_sdma_pdata __initdata = {
137 .fw_name = "sdma-imx53.bin",
138 .script_addrs = &imx53_sdma_script,
139};
140
141void __init imx51_soc_init(void)
142{
143 /* i.mx51 has the i.mx31 type gpio */
144 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
145 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
146 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
147 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
148
149 /* i.mx51 has the i.mx35 type sdma */
150 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
151}
152
153void __init imx53_soc_init(void)
154{
155 /* i.mx53 has the i.mx31 type gpio */
156 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
157 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
158 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
159 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
160 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
161 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
162 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
163
164 /* i.mx53 has the i.mx35 type sdma */
165 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
166}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 00000000000..c9209454807
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,634 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
25#include <linux/mfd/mc13892.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/consumer.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <mach/ulpi.h>
36
37#include <asm/irq.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42
43#include "devices-imx51.h"
44#include "devices.h"
45#include "efika.h"
46#include "cpu_op-mx51.h"
47
48#define MX51_USB_CTRL_1_OFFSET 0x10
49#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
50#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
51
52#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
53#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
54
55#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
56#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
57
58#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
59
60static iomux_v3_cfg_t mx51efika_pads[] = {
61 /* UART1 */
62 MX51_PAD_UART1_RXD__UART1_RXD,
63 MX51_PAD_UART1_TXD__UART1_TXD,
64 MX51_PAD_UART1_RTS__UART1_RTS,
65 MX51_PAD_UART1_CTS__UART1_CTS,
66
67 /* SD 1 */
68 MX51_PAD_SD1_CMD__SD1_CMD,
69 MX51_PAD_SD1_CLK__SD1_CLK,
70 MX51_PAD_SD1_DATA0__SD1_DATA0,
71 MX51_PAD_SD1_DATA1__SD1_DATA1,
72 MX51_PAD_SD1_DATA2__SD1_DATA2,
73 MX51_PAD_SD1_DATA3__SD1_DATA3,
74
75 /* SD 2 */
76 MX51_PAD_SD2_CMD__SD2_CMD,
77 MX51_PAD_SD2_CLK__SD2_CLK,
78 MX51_PAD_SD2_DATA0__SD2_DATA0,
79 MX51_PAD_SD2_DATA1__SD2_DATA1,
80 MX51_PAD_SD2_DATA2__SD2_DATA2,
81 MX51_PAD_SD2_DATA3__SD2_DATA3,
82
83 /* SD/MMC WP/CD */
84 MX51_PAD_GPIO1_0__SD1_CD,
85 MX51_PAD_GPIO1_1__SD1_WP,
86 MX51_PAD_GPIO1_7__SD2_WP,
87 MX51_PAD_GPIO1_8__SD2_CD,
88
89 /* spi */
90 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
91 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
92 MX51_PAD_CSPI1_SS0__GPIO4_24,
93 MX51_PAD_CSPI1_SS1__GPIO4_25,
94 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
95 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
96 MX51_PAD_GPIO1_6__GPIO1_6,
97
98 /* USB HOST1 */
99 MX51_PAD_USBH1_CLK__USBH1_CLK,
100 MX51_PAD_USBH1_DIR__USBH1_DIR,
101 MX51_PAD_USBH1_NXT__USBH1_NXT,
102 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
103 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
104 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
105 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
106 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
107 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
108 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
109 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
110
111 /* USB HUB RESET */
112 MX51_PAD_GPIO1_5__GPIO1_5,
113
114 /* WLAN */
115 MX51_PAD_EIM_A22__GPIO2_16,
116 MX51_PAD_EIM_A16__GPIO2_10,
117
118 /* USB PHY RESET */
119 MX51_PAD_EIM_D27__GPIO2_9,
120};
121
122/* Serial ports */
123static const struct imxuart_platform_data uart_pdata = {
124 .flags = IMXUART_HAVE_RTSCTS,
125};
126
127/* This function is board specific as the bit mask for the plldiv will also
128 * be different for other Freescale SoCs, thus a common bitmask is not
129 * possible and cannot get place in /plat-mxc/ehci.c.
130 */
131static int initialize_otg_port(struct platform_device *pdev)
132{
133 u32 v;
134 void __iomem *usb_base;
135 void __iomem *usbother_base;
136 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
137 if (!usb_base)
138 return -ENOMEM;
139 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
140
141 /* Set the PHY clock to 19.2MHz */
142 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
143 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
144 v |= MX51_USB_PLL_DIV_19_2_MHZ;
145 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
146 iounmap(usb_base);
147
148 mdelay(10);
149
150 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
151}
152
153static struct mxc_usbh_platform_data dr_utmi_config = {
154 .init = initialize_otg_port,
155 .portsc = MXC_EHCI_UTMI_16BIT,
156};
157
158static int initialize_usbh1_port(struct platform_device *pdev)
159{
160 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
161 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
162 u32 v;
163 void __iomem *usb_base;
164 void __iomem *socregs_base;
165
166 mxc_iomux_v3_setup_pad(usbh1gpio);
167 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
168 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
169 msleep(1);
170 gpio_set_value(EFIKAMX_USBH1_STP, 1);
171 msleep(1);
172
173 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
174 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
175
176 /* The clock for the USBH1 ULPI port will come externally */
177 /* from the PHY. */
178 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
179 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
180 socregs_base + MX51_USB_CTRL_1_OFFSET);
181
182 iounmap(usb_base);
183
184 gpio_free(EFIKAMX_USBH1_STP);
185 mxc_iomux_v3_setup_pad(usbh1stp);
186
187 mdelay(10);
188
189 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
190}
191
192static struct mxc_usbh_platform_data usbh1_config = {
193 .init = initialize_usbh1_port,
194 .portsc = MXC_EHCI_MODE_ULPI,
195};
196
197static void mx51_efika_hubreset(void)
198{
199 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
200 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
201 msleep(1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
203 msleep(1);
204 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
205}
206
207static void __init mx51_efika_usb(void)
208{
209 mx51_efika_hubreset();
210
211 /* pulling it low, means no USB at all... */
212 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
213 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
214 msleep(1);
215 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
216
217 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
218 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
219
220 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
221 if (usbh1_config.otg)
222 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
223}
224
225static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
226 {
227 .name = "u-boot",
228 .offset = 0,
229 .size = SZ_256K,
230 },
231 {
232 .name = "config",
233 .offset = MTDPART_OFS_APPEND,
234 .size = SZ_64K,
235 },
236};
237
238static struct flash_platform_data mx51_efika_spi_flash_data = {
239 .name = "spi_flash",
240 .parts = mx51_efika_spi_nor_partitions,
241 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
242 .type = "sst25vf032b",
243};
244
245static struct regulator_consumer_supply sw1_consumers[] = {
246 {
247 .supply = "cpu_vcc",
248 }
249};
250
251static struct regulator_consumer_supply vdig_consumers[] = {
252 /* sgtl5000 */
253 REGULATOR_SUPPLY("VDDA", "1-000a"),
254 REGULATOR_SUPPLY("VDDD", "1-000a"),
255};
256
257static struct regulator_consumer_supply vvideo_consumers[] = {
258 /* sgtl5000 */
259 REGULATOR_SUPPLY("VDDIO", "1-000a"),
260};
261
262static struct regulator_consumer_supply vsd_consumers[] = {
263 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
264 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
265};
266
267static struct regulator_consumer_supply pwgt1_consumer[] = {
268 {
269 .supply = "pwgt1",
270 }
271};
272
273static struct regulator_consumer_supply pwgt2_consumer[] = {
274 {
275 .supply = "pwgt2",
276 }
277};
278
279static struct regulator_consumer_supply coincell_consumer[] = {
280 {
281 .supply = "coincell",
282 }
283};
284
285static struct regulator_init_data sw1_init = {
286 .constraints = {
287 .name = "SW1",
288 .min_uV = 600000,
289 .max_uV = 1375000,
290 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
291 .valid_modes_mask = 0,
292 .always_on = 1,
293 .boot_on = 1,
294 .state_mem = {
295 .uV = 850000,
296 .mode = REGULATOR_MODE_NORMAL,
297 .enabled = 1,
298 },
299 },
300 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
301 .consumer_supplies = sw1_consumers,
302};
303
304static struct regulator_init_data sw2_init = {
305 .constraints = {
306 .name = "SW2",
307 .min_uV = 900000,
308 .max_uV = 1850000,
309 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
310 .always_on = 1,
311 .boot_on = 1,
312 .state_mem = {
313 .uV = 950000,
314 .mode = REGULATOR_MODE_NORMAL,
315 .enabled = 1,
316 },
317 }
318};
319
320static struct regulator_init_data sw3_init = {
321 .constraints = {
322 .name = "SW3",
323 .min_uV = 1100000,
324 .max_uV = 1850000,
325 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
326 .always_on = 1,
327 .boot_on = 1,
328 }
329};
330
331static struct regulator_init_data sw4_init = {
332 .constraints = {
333 .name = "SW4",
334 .min_uV = 1100000,
335 .max_uV = 1850000,
336 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
337 .always_on = 1,
338 .boot_on = 1,
339 }
340};
341
342static struct regulator_init_data viohi_init = {
343 .constraints = {
344 .name = "VIOHI",
345 .boot_on = 1,
346 .always_on = 1,
347 }
348};
349
350static struct regulator_init_data vusb_init = {
351 .constraints = {
352 .name = "VUSB",
353 .boot_on = 1,
354 .always_on = 1,
355 }
356};
357
358static struct regulator_init_data swbst_init = {
359 .constraints = {
360 .name = "SWBST",
361 }
362};
363
364static struct regulator_init_data vdig_init = {
365 .constraints = {
366 .name = "VDIG",
367 .min_uV = 1050000,
368 .max_uV = 1800000,
369 .valid_ops_mask =
370 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
371 .boot_on = 1,
372 .always_on = 1,
373 },
374 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
375 .consumer_supplies = vdig_consumers,
376};
377
378static struct regulator_init_data vpll_init = {
379 .constraints = {
380 .name = "VPLL",
381 .min_uV = 1050000,
382 .max_uV = 1800000,
383 .valid_ops_mask =
384 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
385 .boot_on = 1,
386 .always_on = 1,
387 }
388};
389
390static struct regulator_init_data vusb2_init = {
391 .constraints = {
392 .name = "VUSB2",
393 .min_uV = 2400000,
394 .max_uV = 2775000,
395 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
396 .boot_on = 1,
397 .always_on = 1,
398 }
399};
400
401static struct regulator_init_data vvideo_init = {
402 .constraints = {
403 .name = "VVIDEO",
404 .min_uV = 2775000,
405 .max_uV = 2775000,
406 .valid_ops_mask =
407 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
408 .boot_on = 1,
409 .apply_uV = 1,
410 },
411 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
412 .consumer_supplies = vvideo_consumers,
413};
414
415static struct regulator_init_data vaudio_init = {
416 .constraints = {
417 .name = "VAUDIO",
418 .min_uV = 2300000,
419 .max_uV = 3000000,
420 .valid_ops_mask =
421 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
422 .boot_on = 1,
423 }
424};
425
426static struct regulator_init_data vsd_init = {
427 .constraints = {
428 .name = "VSD",
429 .min_uV = 1800000,
430 .max_uV = 3150000,
431 .valid_ops_mask =
432 REGULATOR_CHANGE_VOLTAGE,
433 .boot_on = 1,
434 },
435 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
436 .consumer_supplies = vsd_consumers,
437};
438
439static struct regulator_init_data vcam_init = {
440 .constraints = {
441 .name = "VCAM",
442 .min_uV = 2500000,
443 .max_uV = 3000000,
444 .valid_ops_mask =
445 REGULATOR_CHANGE_VOLTAGE |
446 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
447 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
448 .boot_on = 1,
449 }
450};
451
452static struct regulator_init_data vgen1_init = {
453 .constraints = {
454 .name = "VGEN1",
455 .min_uV = 1200000,
456 .max_uV = 3150000,
457 .valid_ops_mask =
458 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
459 .boot_on = 1,
460 .always_on = 1,
461 }
462};
463
464static struct regulator_init_data vgen2_init = {
465 .constraints = {
466 .name = "VGEN2",
467 .min_uV = 1200000,
468 .max_uV = 3150000,
469 .valid_ops_mask =
470 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
471 .boot_on = 1,
472 .always_on = 1,
473 }
474};
475
476static struct regulator_init_data vgen3_init = {
477 .constraints = {
478 .name = "VGEN3",
479 .min_uV = 1800000,
480 .max_uV = 2900000,
481 .valid_ops_mask =
482 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
483 .boot_on = 1,
484 .always_on = 1,
485 }
486};
487
488static struct regulator_init_data gpo1_init = {
489 .constraints = {
490 .name = "GPO1",
491 }
492};
493
494static struct regulator_init_data gpo2_init = {
495 .constraints = {
496 .name = "GPO2",
497 }
498};
499
500static struct regulator_init_data gpo3_init = {
501 .constraints = {
502 .name = "GPO3",
503 }
504};
505
506static struct regulator_init_data gpo4_init = {
507 .constraints = {
508 .name = "GPO4",
509 }
510};
511
512static struct regulator_init_data pwgt1_init = {
513 .constraints = {
514 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
515 .boot_on = 1,
516 },
517 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
518 .consumer_supplies = pwgt1_consumer,
519};
520
521static struct regulator_init_data pwgt2_init = {
522 .constraints = {
523 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
524 .boot_on = 1,
525 },
526 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
527 .consumer_supplies = pwgt2_consumer,
528};
529
530static struct regulator_init_data vcoincell_init = {
531 .constraints = {
532 .name = "COINCELL",
533 .min_uV = 3000000,
534 .max_uV = 3000000,
535 .valid_ops_mask =
536 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
537 },
538 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
539 .consumer_supplies = coincell_consumer,
540};
541
542static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
543 { .id = MC13892_SW1, .init_data = &sw1_init },
544 { .id = MC13892_SW2, .init_data = &sw2_init },
545 { .id = MC13892_SW3, .init_data = &sw3_init },
546 { .id = MC13892_SW4, .init_data = &sw4_init },
547 { .id = MC13892_SWBST, .init_data = &swbst_init },
548 { .id = MC13892_VIOHI, .init_data = &viohi_init },
549 { .id = MC13892_VPLL, .init_data = &vpll_init },
550 { .id = MC13892_VDIG, .init_data = &vdig_init },
551 { .id = MC13892_VSD, .init_data = &vsd_init },
552 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
553 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
554 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
555 { .id = MC13892_VCAM, .init_data = &vcam_init },
556 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
557 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
558 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
559 { .id = MC13892_VUSB, .init_data = &vusb_init },
560 { .id = MC13892_GPO1, .init_data = &gpo1_init },
561 { .id = MC13892_GPO2, .init_data = &gpo2_init },
562 { .id = MC13892_GPO3, .init_data = &gpo3_init },
563 { .id = MC13892_GPO4, .init_data = &gpo4_init },
564 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
565 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
566 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
567};
568
569static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
570 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
571 .regulators = {
572 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
573 .regulators = mx51_efika_regulators,
574 },
575};
576
577static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
578 {
579 .modalias = "m25p80",
580 .max_speed_hz = 25000000,
581 .bus_num = 0,
582 .chip_select = 1,
583 .platform_data = &mx51_efika_spi_flash_data,
584 .irq = -1,
585 },
586 {
587 .modalias = "mc13892",
588 .max_speed_hz = 1000000,
589 .bus_num = 0,
590 .chip_select = 0,
591 .platform_data = &mx51_efika_mc13892_data,
592 .irq = gpio_to_irq(EFIKAMX_PMIC),
593 },
594};
595
596static int mx51_efika_spi_cs[] = {
597 EFIKAMX_SPI_CS0,
598 EFIKAMX_SPI_CS1,
599};
600
601static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
602 .chipselect = mx51_efika_spi_cs,
603 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
604};
605
606void __init efika_board_common_init(void)
607{
608 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
609 ARRAY_SIZE(mx51efika_pads));
610 imx51_add_imx_uart(0, &uart_pdata);
611 mx51_efika_usb();
612 imx51_add_sdhci_esdhc_imx(0, NULL);
613
614 /* FIXME: comes from original code. check this. */
615 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
616 sw2_init.constraints.state_mem.uV = 1100000;
617 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
618 sw2_init.constraints.state_mem.uV = 1250000;
619 sw1_init.constraints.state_mem.uV = 1000000;
620 }
621 if (machine_is_mx51_efikasb())
622 vgen1_init.constraints.max_uV = 1200000;
623
624 gpio_request(EFIKAMX_PMIC, "pmic irq");
625 gpio_direction_input(EFIKAMX_PMIC);
626 spi_register_board_info(mx51_efika_spi_board_info,
627 ARRAY_SIZE(mx51_efika_spi_board_info));
628 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
629
630#if defined(CONFIG_CPU_FREQ_IMX)
631 get_cpu_op = mx51_get_cpu_op;
632#endif
633}
634
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
new file mode 100644
index 00000000000..e4529af0da7
--- /dev/null
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include <linux/suspend.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <asm/cacheflush.h>
16#include <asm/tlbflush.h>
17#include <mach/system.h>
18#include "crm_regs.h"
19
20static struct clk *gpc_dvfs_clk;
21
22static int mx5_suspend_enter(suspend_state_t state)
23{
24 clk_enable(gpc_dvfs_clk);
25 switch (state) {
26 case PM_SUSPEND_MEM:
27 mx5_cpu_lp_set(STOP_POWER_OFF);
28 break;
29 case PM_SUSPEND_STANDBY:
30 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
31 break;
32 default:
33 return -EINVAL;
34 }
35
36 if (state == PM_SUSPEND_MEM) {
37 local_flush_tlb_all();
38 flush_cache_all();
39
40 /*clear the EMPGC0/1 bits */
41 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
42 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
43 }
44 cpu_do_idle();
45 clk_disable(gpc_dvfs_clk);
46
47 return 0;
48}
49
50static int mx5_pm_valid(suspend_state_t state)
51{
52 return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
53}
54
55static const struct platform_suspend_ops mx5_suspend_ops = {
56 .valid = mx5_pm_valid,
57 .enter = mx5_suspend_enter,
58};
59
60static int __init mx5_pm_init(void)
61{
62 if (gpc_dvfs_clk == NULL)
63 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
64
65 if (!IS_ERR(gpc_dvfs_clk)) {
66 if (cpu_is_mx51())
67 suspend_set_ops(&mx5_suspend_ops);
68 } else
69 return -EPERM;
70
71 return 0;
72}
73device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
new file mode 100644
index 00000000000..76ae8dc33e0
--- /dev/null
+++ b/arch/arm/mach-mx5/system.c
@@ -0,0 +1,84 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <mach/hardware.h>
16#include "crm_regs.h"
17
18/* set cpu low power mode before WFI instruction. This function is called
19 * mx5 because it can be used for mx50, mx51, and mx53.*/
20void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
21{
22 u32 plat_lpc, arm_srpgcr, ccm_clpcr;
23 u32 empgc0, empgc1;
24 int stop_mode = 0;
25
26 /* always allow platform to issue a deep sleep mode request */
27 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
28 ~(MXC_CORTEXA8_PLAT_LPC_DSM);
29 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
30 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
31 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
32 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
33
34 switch (mode) {
35 case WAIT_CLOCKED:
36 break;
37 case WAIT_UNCLOCKED:
38 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
39 break;
40 case WAIT_UNCLOCKED_POWER_OFF:
41 case STOP_POWER_OFF:
42 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
43 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
44 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
45 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
46 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
47 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
48 stop_mode = 0;
49 } else {
50 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
51 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
52 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
53 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
54 stop_mode = 1;
55 }
56 arm_srpgcr |= MXC_SRPGCR_PCR;
57
58 if (tzic_enable_wake(1) != 0)
59 return;
60 break;
61 case STOP_POWER_ON:
62 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
63 break;
64 default:
65 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
66 return;
67 }
68
69 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
70 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
71 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
72
73 /* Enable NEON SRPG for all but MX50TO1.0. */
74 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
75 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
76
77 if (stop_mode) {
78 empgc0 |= MXC_SRPGCR_PCR;
79 empgc1 |= MXC_SRPGCR_PCR;
80
81 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
82 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
83 }
84}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-20 10:56:33 -0400